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Split RIVA 128 aand RIVA 128 ZX

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This commit is contained in:
starfrost013
2025-04-17 21:40:41 +01:00
parent db536f521d
commit 0a579c0775
6 changed files with 223 additions and 125 deletions
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3
src/include/86box/nv/vid_nv3.h
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@@ -26,7 +26,8 @@
#include <86box/nv/render/vid_nv3_render.h>
// The GPU base structure
extern const device_config_t nv3_config[];
extern const device_config_t nv3_config[]; // Config for RIVA 128 (revision A/B)
extern const device_config_t nv3t_config[]; // Config for RIVA 128 ZX (revision C)
#define NV3_MMIO_SIZE 0x1000000 // Max MMIO size

2
src/include/86box/video.h
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@@ -599,6 +599,8 @@ extern const device_t velocity_100_agp_device;
extern const device_t velocity_200_agp_device;
extern const device_t nv3_device_pci;
extern const device_t nv3_device_agp;
extern const device_t nv3t_device_pci;
extern const device_t nv3t_device_agp;
/* Wyse 700 */
extern const device_t wy700_device;

151
src/video/nv/nv3/nv3_core.c
View File

@@ -1089,10 +1089,22 @@ void nv3_update_mappings(void)
//
void* nv3_init(const device_t *info)
{
// set the vram amount and gpu revision
/* We don't bother looking these up if they are nonzero. On Riva 128 ZX, they are already set by the init function (always 8 MB VRAM + Revision C0) */
if (!nv3->nvbase.vram_amount)
nv3->nvbase.vram_amount = device_get_config_int("vram_size");
if (!nv3->nvbase.gpu_revision)
nv3->nvbase.gpu_revision = device_get_config_int("chip_revision");
/* Set log device name based on card model */
const char* log_device_name = (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00) ? "NV3T" : "NV3";
if (device_get_config_int("nv_debug_fulllog"))
nv3->nvbase.log = log_open("NV3");
nv3->nvbase.log = log_open(log_device_name);
else
nv3->nvbase.log = log_open_cyclic("NV3");
nv3->nvbase.log = log_open_cyclic(log_device_name);
#ifdef ENABLE_NV_LOG
// Allows nv_log to be used for multiple nvidia devices
@@ -1103,16 +1115,26 @@ void* nv3_init(const device_t *info)
// this will only be logged if ENABLE_NV_LOG_ULTRA is defined
nv_log_verbose_only("ULTRA LOGGING enabled");
// Figure out which vbios the user selected
// This depends on the bus we are using and if the gpu is rev a/b or rev c
const char* vbios_id = device_get_config_bios("vbios");
const char* vbios_file = "";
// depends on the bus we are using
if (nv3->nvbase.bus_generation == nv_bus_pci)
vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0);
else
vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0);
if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00)
{
if (nv3->nvbase.bus_generation == nv_bus_pci)
vbios_file = device_get_bios_file(&nv3t_device_pci, vbios_id, 0);
else
vbios_file = device_get_bios_file(&nv3t_device_agp, vbios_id, 0);
}
else
{
if (nv3->nvbase.bus_generation == nv_bus_pci)
vbios_file = device_get_bios_file(&nv3_device_pci, vbios_id, 0);
else
vbios_file = device_get_bios_file(&nv3_device_agp, vbios_id, 0);
}
int32_t err = rom_init(&nv3->nvbase.vbios, vbios_file, 0xC0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
@@ -1125,39 +1147,52 @@ void* nv3_init(const device_t *info)
else
nv_log("Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file);
// set the vram amount and gpu revision
nv3->nvbase.vram_amount = device_get_config_int("vram_size");
nv3->nvbase.gpu_revision = device_get_config_int("chip_revision");
// set up the bus and start setting up SVGA core
if (nv3->nvbase.bus_generation == nv_bus_pci)
{
nv_log("using PCI bus\n");
nv_log("Using PCI bus\n");
pci_add_card(PCI_ADD_NORMAL, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot);
svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
/* Initialise the right revision of the card */
if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00)
{
svga_init(&nv3t_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_pci);
else
}
else
{
svga_init(&nv3_device_pci, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_pci);
}
}
else if (nv3->nvbase.bus_generation == nv_bus_agp_1x)
else if (nv3->nvbase.bus_generation == nv_bus_agp_1x
|| nv3->nvbase.bus_generation == nv_bus_agp_2x)
{
nv_log("using AGP 1X bus\n");
nv_log("Using AGP 1X/2X bus\n");
pci_add_card(PCI_ADD_AGP, nv3_pci_read, nv3_pci_write, NULL, &nv3->nvbase.pci_slot);
svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
/* Initialise the right revision of the card */
if (nv3->nvbase.gpu_revision == NV3_PCI_CFG_REVISION_C00)
{
svga_init(&nv3t_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3t_agp);
else
}
else
{
svga_init(&nv3_device_agp, &nv3->nvbase.svga, nv3, nv3->nvbase.vram_amount,
nv3_recalc_timings, nv3_svga_read, nv3_svga_write, nv3_draw_cursor, NULL);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_nv3_agp);
}
}
// set vram
@@ -1191,7 +1226,7 @@ void* nv3_init(const device_t *info)
return nv3;
}
// This function simply allocates ram and sets the bus to pci before initialising.
// RIVA 128 PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising.
void* nv3_init_pci(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
@@ -1200,7 +1235,7 @@ void* nv3_init_pci(const device_t* info)
return nv3;
}
// This function simply allocates ram and sets the bus to agp before initialising.
// RIVA 128 AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising.
void* nv3_init_agp(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
@@ -1209,6 +1244,32 @@ void* nv3_init_agp(const device_t* info)
return nv3;
}
// RIVA 128 ZX PCI initialisation function: This function simply allocates the device struct, and sets the bus to PCI before initialising.
// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant),
// and sets RAM to 8 MB (the only supported config on ZX cards)
void* nv3t_init_pci(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
nv3->nvbase.bus_generation = nv_bus_pci;
nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00;
nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB;
nv3_init(info);
return nv3;
}
// RIVA 128 ZX AGP initialisation function: This function simply allocates the device struct, and sets the bus to AGP before initialising.
// It also sets the GPU revision to C0 because NV3T config doesn't let you configure the rev (there were multiple steppings, but it's basically irrelevant)
// and sets RAM to 8 MB (the only supported config on ZX cards)
void* nv3t_init_agp(const device_t* info)
{
nv3 = (nv3_t*)calloc(1, sizeof(nv3_t));
nv3->nvbase.bus_generation = nv_bus_agp_2x; // Riva 128 ZX is AGP2X
nv3->nvbase.gpu_revision = NV3_PCI_CFG_REVISION_C00;
nv3->nvbase.vram_amount = NV3_VRAM_SIZE_8MB;
nv3_init(info);
return nv3;
}
void nv3_close(void* priv)
{
// Shut down logging
@@ -1252,8 +1313,8 @@ int32_t nv3_available(void)
// 2MB or 4MB VRAM
const device_t nv3_device_pci =
{
.name = "NVidia RIVA 128 (NV3) PCI",
.internal_name = "nv3",
.name = "nVIDIA RIVA 128 (NV3) PCI",
.internal_name = "nv3_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = nv3_init_pci,
@@ -1269,7 +1330,7 @@ const device_t nv3_device_pci =
// 2MB or 4MB VRAM
const device_t nv3_device_agp =
{
.name = "NVidia RIVA 128 (NV3) AGP",
.name = "nVIDIA RIVA 128 (NV3) AGP",
.internal_name = "nv3_agp",
.flags = DEVICE_AGP,
.local = 0,
@@ -1279,4 +1340,38 @@ const device_t nv3_device_agp =
.force_redraw = nv3_force_redraw,
.available = nv3_available,
.config = nv3_config,
};
// NV3T (RIVA 128 ZX)
// PCI
// 8MB VRAM
const device_t nv3t_device_pci =
{
.name = "nVIDIA RIVA 128 ZX (NV3T) PCI",
.internal_name = "nv3t_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = nv3t_init_pci,
.close = nv3_close,
.speed_changed = nv3_speed_changed,
.force_redraw = nv3_force_redraw,
.available = nv3_available,
.config = nv3t_config,
};
// NV3T (RIVA 128)
// AGP
// 2MB or 4MB VRAM
const device_t nv3t_device_agp =
{
.name = "nVIDIA RIVA 128 ZX (NV3T) AGP",
.internal_name = "nv3t_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = nv3t_init_agp,
.close = nv3_close,
.speed_changed = nv3_speed_changed,
.force_redraw = nv3_force_redraw,
.available = nv3_available,
.config = nv3t_config,
};

182
src/video/nv/nv3/nv3_core_config.c
View File

@@ -32,107 +32,42 @@ const device_config_t nv3_config[] =
// VBIOS type configuration
{
.name = "vbios",
#ifndef RELEASE_BUILD
.description = "VBIOS",
#else
.description = "Model",
#endif
.type = CONFIG_BIOS,
.default_string = "NV3_VBIOS_ERAZOR_V15403",
.default_int = 0,
.bios =
{
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-09-30] ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00)", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.47.01", .files_no = 1,
#endif
.name = "ELSA VICTORY Erazor - Version 1.47.00", .files_no = 1,
.internal_name = "NV3_VBIOS_ERAZOR_V14700",
.files = {NV3_VBIOS_ERAZOR_V14700, ""}
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-02-06] ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.54.03", .files_no = 1,
#endif
.name = "ELSA VICTORY Erazor - Version 1.54.03", .files_no = 1,
.internal_name = "NV3_VBIOS_ERAZOR_V15403",
.files = {NV3_VBIOS_ERAZOR_V15403, ""}
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.55.00", .files_no = 1,
#endif
.name = "ELSA VICTORY Erazor - Version 1.55.00", .files_no = 1,
.internal_name = "NV3_VBIOS_ERAZOR_V15500",
.files = {NV3_VBIOS_ERAZOR_V15500, ""}
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-01-14] Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO", .files_no = 1,
#else
.name = "[RIVA 128] Diamond Viper V330", .files_no = 1,
#endif
.name = "Diamond Viper V330 - Version 1.62-CO", .files_no = 1,
.internal_name = "NV3_VBIOS_DIAMOND_V330_V162",
.files = {NV3_VBIOS_DIAMOND_V330_V162, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-09-06] ASUS AGP/3DP-V3000 BIOS 1.51B", .files_no = 1,
#else
.name = "[RIVA 128] ASUS AGP/3DP-V3000", .files_no = 1,
#endif
.name = "ASUS AGP/3DP-V3000 - Version 1.51B", .files_no = 1,
.internal_name = "NV3_VBIOS_ASUS_V3000_V151",
.files = {NV3_VBIOS_ASUS_V3000_V151, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-12-17] STB Velocity 128 (RIVA 128) Ver.1.82", .files_no = 1,
#else
.name = "[RIVA 128] STB Velocity 128", .files_no = 1,
#endif
.name = "STB Velocity 128 - Version 1.82", .files_no = 1,
.internal_name = "NV3_VBIOS_STB_V128_V182",
.files = {NV3_VBIOS_STB_V128_V182, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-09-15] Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Diamond Multimedia Viper V330 8MB", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B",
.files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-08-04] ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1,
#else
.name = "[RIVA 128 ZX] ASUS AGP-V3000 ZXTV", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_ASUS_V170",
.files = {NV3T_VBIOS_ASUS_V170, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-07-30] RIVA 128 ZX BIOS - V1.71B-N", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.71", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171",
.files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T+SGRAM - 1998-08-15] RIVA 128 ZX BIOS - V1.72B", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.72", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172",
.files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""},
},
}
},
// Memory configuration
@@ -143,22 +78,17 @@ const device_config_t nv3_config[] =
.default_int = NV3_VRAM_SIZE_4MB,
.selection =
{
#ifndef RELEASE_BUILD
// I thought this was never released, but it seems that at least one was released:
// The card was called the "NEC G7AGK"
{
.description = "2 MB",
.value = NV3_VRAM_SIZE_2MB,
},
#endif
{
.description = "4 MB",
.value = NV3_VRAM_SIZE_4MB,
},
{
.description = "8 MB",
.value = NV3_VRAM_SIZE_8MB,
},
}
},
@@ -169,30 +99,94 @@ const device_config_t nv3_config[] =
.default_int = NV3_PCI_CFG_REVISION_B00,
.selection =
{
#ifndef RELEASE_BUILD
{
.description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997) with integrated PAUDIO sound card",
#else
.description = "RIVA 128 Prototype (Revision A)",
#endif
.description = "RIVA 128 Prototype (Revision A; January 1997)",
.value = NV3_PCI_CFG_REVISION_A00,
},
#ifndef RELEASE_BUILD
{
.description = "RIVA 128 / Stepping B0 (October 1997)",
#else
.description = "RIVA 128 (Revision B)",
#endif
.value = NV3_PCI_CFG_REVISION_B00,
},
#ifndef RELEASE_BUILD
{
.description = "NV3T - RIVA 128 ZX / Stepping C0 (March 1998)",
#else
.description = "RIVA 128 ZX (Revision C)",
#endif
.value = NV3_PCI_CFG_REVISION_C00,
},
}
},
// Multithreading configuration
{
.name = "pgraph_threads",
#ifndef RELEASE_BUILD
.description = "PFIFO/PGRAPH - Number of threads to split large object method execution into",
#else
.description = "Render threads",
#endif
.type = CONFIG_SELECTION,
.default_int = 1, // todo: change later
.selection =
{
{
.description = "1 thread (Only use if issues appear with more threads)",
.value = 1,
},
{
.description = "2 threads",
.value = 2,
},
{
.description = "4 threads",
.value = 4,
},
{
.description = "8 threads",
.value = 8,
},
},
},
#ifndef RELEASE_BUILD
{
.name = "nv_debug_fulllog",
.description = "Disable Cyclical Lines Detection for nv_log (Use for getting full context at cost of VERY large log files)",
.type = CONFIG_BINARY,
.default_int = 0,
},
#endif
{
.type = CONFIG_END
}
};
const device_config_t nv3t_config[] =
{
// VBIOS type configuration
{
.name = "vbios",
.description = "Model",
.type = CONFIG_BIOS,
.default_string = "NV3T_VBIOS_DIAMOND_V330_V182B",
.default_int = 0,
.bios =
{
{
.name = "Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1,
.internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B",
.files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""},
},
{
.name = "ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1,
.internal_name = "NV3T_VBIOS_ASUS_V170",
.files = {NV3T_VBIOS_ASUS_V170, ""},
},
{
.name = "NVidia Reference BIOS - V1.71B-N", .files_no = 1,
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171",
.files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""},
},
{
.name = "NVidia Reference BIOS - V1.72B", .files_no = 1,
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172",
.files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""},
},
}
},
// Multithreading configuration

8
src/video/nv/nv3/subsystems/nv3_pextdev.c
View File

@@ -134,8 +134,12 @@ void nv3_pextdev_write(uint32_t address, uint32_t value)
// special consideration for straps
if (address == NV3_PSTRAPS)
{
warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps);
return;
/* For some reason, all RIVA 128 ZX VBIOSes try to write to the straps. So only indicate this as a problem and return on Rev A/B */
if (nv3->nvbase.gpu_revision != NV3_PCI_CFG_REVISION_C00)
{
warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps);
return;
}
}
// if the register actually exists

2
src/video/vid_table.c
View File

@@ -253,6 +253,8 @@ video_cards[] = {
{ .device = &voodoo_3_3500_si_agp_device, .flags = VIDEO_FLAG_TYPE_NONE },
{ .device = &nv3_device_agp, .flags = VIDEO_FLAG_TYPE_NONE },
{ .device = &nv3_device_pci, .flags = VIDEO_FLAG_TYPE_NONE },
{ .device = &nv3t_device_agp, .flags = VIDEO_FLAG_TYPE_NONE },
{ .device = &nv3t_device_pci, .flags = VIDEO_FLAG_TYPE_NONE },
{ .device = NULL, .flags = VIDEO_FLAG_TYPE_NONE }
// clang-format on
};