mirror of
https://github.com/86Box/86Box.git
synced 2026-02-24 02:18:20 -07:00
Add PC-98x1 specific CPU/A20 reset ports
See above and more stuff TBD (WIP too).
This commit is contained in:
TC1995
35
src/include/86box/port_pc98_cpu.h
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35
src/include/86box/port_pc98_cpu.h
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Header for the implementation of CPU I/O ports used
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* by NEC PC-98x1 machines.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2019 Miran Grca.
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*/
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#ifndef EMU_PORT_PC98_CPU_H
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#define EMU_PORT_PC98_CPU_H
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#ifdef _TIMER_H_
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typedef struct port_pc98_cpu_t {
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pc_timer_t pulse_timer;
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uint64_t pulse_period;
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} port_92_t;
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#endif
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extern void port_pc98_cpu_add(void *priv);
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extern void port_pc98_cpu_remove(void *priv);
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extern const device_t port_pc98_cpu_device;
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#endif /*EMU_PORT_PC98_CPU_H*/
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203
src/port_pc98_cpu.c
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src/port_pc98_cpu.c
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/*
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* 86Box A hypervisor and IBM PC system emulator that specializes in
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* running old operating systems and software designed for IBM
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* PC systems and compatibles from 1981 through fairly recent
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* system designs based on the PCI bus.
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*
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* This file is part of the 86Box distribution.
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*
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* Implementation of CPU I/O ports used by NEC PC-98x1 machines.
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*
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*
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*
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* Authors: Miran Grca, <mgrca8@gmail.com>
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*
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* Copyright 2019 Miran Grca.
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*/
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <wchar.h>
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#include <86box/86box.h>
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#include <86box/device.h>
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#include "cpu.h"
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#include <86box/timer.h>
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#include <86box/io.h>
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#include <86box/keyboard.h>
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#include <86box/nmi.h>
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#include <86box/mem.h>
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#include <86box/pit.h>
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#include <86box/port_pc98_cpu.h>
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#include <86box/plat_unused.h>
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static uint8_t
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port_pc98_cpu_f2_readb(UNUSED(uint16_t port), UNUSED(void *priv))
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{
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uint8_t ret = 0xff;
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ret -= ((rammask >> 20) & 0x01);
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return ret;
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}
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static uint8_t
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port_pc98_cpu_f6_readb(UNUSED(uint16_t port), UNUSED(void *priv))
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{
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uint8_t ret = 0x00;
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if (!(rammask & (1 << 20)))
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ret |= 0x01;
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if (nmi_enable)
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ret |= 0x02;
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return ret;
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}
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static uint8_t
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port_pc98_cpu_534_readb(UNUSED(uint16_t port), UNUSED(void *priv))
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{
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return 0xec; /*CPU mode*/
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}
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static uint8_t
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port_pc98_cpu_9894_readb(UNUSED(uint16_t port), UNUSED(void *priv))
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{
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return 0x90; /*CPU wait*/
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}
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static void
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port_pc98_cpu_pulse(UNUSED(void *priv))
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{
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softresetx86(); /* Pulse reset! */
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cpu_set_edx();
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flushmmucache();
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cpu_alt_reset = 1;
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}
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static void
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port_pc98_cpu_f2_writeb(UNUSED(uint16_t port), UNUSED(uint8_t val), UNUSED(void *priv))
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{
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mem_a20_alt = 1;
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mem_a20_recalc();
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}
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static void
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port_pc98_cpu_f6_writeb(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
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{
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switch (val) {
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case 0x02:
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mem_a20_alt = 1;
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mem_a20_recalc();
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break;
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case 0x03:
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mem_a20_alt = 0;
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mem_a20_recalc();
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break;
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default:
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break;
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}
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}
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static void
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port_pc98_cpu_534_writeb(UNUSED(uint16_t port), uint8_t val, void *priv)
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{
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port_pc98_cpu_t *dev = (port_pc98_cpu_t *) priv;
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if ((~cpu_alt_reset & val) & 1)
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timer_set_delay_u64(&dev->pulse_timer, dev->pulse_period);
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else if (!(val & 1))
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timer_disable(&dev->pulse_timer);
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cpu_alt_reset = (val & 1);
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}
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void
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port_pc98_cpu_add(void *priv)
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{
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port_92_t *dev = (port_92_t *) priv;
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io_sethandler(0x00f2, 1,
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port_pc98_cpu_f2_readb, NULL, NULL, port_pc98_cpu_f2_writeb, NULL, NULL, dev);
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io_sethandler(0x00f6, 1,
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port_pc98_cpu_f6_readb, NULL, NULL, port_pc98_cpu_f6_writeb, NULL, NULL, dev);
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io_sethandler(0x0534, 1,
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port_pc98_cpu_534_readb, NULL, NULL, port_pc98_cpu_534_writeb, NULL, NULL, dev);
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io_sethandler(0x9894, 1,
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port_pc98_cpu_9894_readb, NULL, NULL, NULL, NULL, NULL, dev);
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}
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void
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port_pc98_cpu_remove(void *priv)
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{
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port_92_t *dev = (port_92_t *) priv;
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io_removehandler(0x00f2, 1,
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port_pc98_cpu_f2_readb, NULL, NULL, port_pc98_cpu_f2_writeb, NULL, NULL, dev);
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io_removehandler(0x00f6, 1,
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port_pc98_cpu_f6_readb, NULL, NULL, port_pc98_cpu_f6_writeb, NULL, NULL, dev);
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io_removehandler(0x0534, 1,
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port_pc98_cpu_534_readb, NULL, NULL, port_pc98_cpu_534_writeb, NULL, NULL, dev);
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io_removehandler(0x9894, 1,
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port_pc98_cpu_9894_readb, NULL, NULL, NULL, NULL, NULL, dev);
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}
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static void
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port_pc98_cpu_reset(UNUSED(void *priv))
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{
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cpu_alt_reset = 0;
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mem_a20_alt = 0x00;
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mem_a20_recalc();
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}
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static void
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port_pc98_cpu_close(void *priv)
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{
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port_pc98_cpu_t *dev = (port_pc98_cpu_t *) priv;
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timer_disable(&dev->pulse_timer);
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free(dev);
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}
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void *
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port_pc98_cpu_init(const device_t *info)
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{
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port_pc98_cpu_t *dev = (port_pc98_cpu_t *) malloc(sizeof(port_pc98_cpu_t));
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memset(dev, 0, sizeof(port_pc98_cpu_t));
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dev->flags = info->local & 0xff;
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timer_add(&dev->pulse_timer, port_pc98_cpu_pulse, dev, 0);
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dev->reg = 0;
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mem_a20_alt = 0;
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mem_a20_recalc();
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cpu_alt_reset = 0;
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flushmmucache();
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port_pc98_cpu_add(dev);
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dev->pulse_period = (uint64_t) (4.0 * SYSCLK * (double) (1ULL << 32ULL));
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return dev;
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}
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const device_t port_pc98_cpu_device = {
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.name = "NEC PC-98x1 CPU Ports",
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.internal_name = "port_pc98_cpu",
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.flags = 0,
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.local = 0,
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.init = port_pc98_cpu_init,
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.close = port_pc98_cpu_close,
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.reset = port_pc98_cpu_reset,
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{ .available = NULL },
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.speed_changed = NULL,
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.force_redraw = NULL,
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.config = NULL
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};
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