mirror/86Box
1
0
Fork 0
mirror of https://github.com/86Box/86Box.git synced 2026-02-24 10:28:19 -07:00
Code Issues Packages Projects Releases Activity

fix SetNotifyCtxDma

Browse Source
This commit is contained in:
starfrost013
2025-02-11 23:25:06 +00:00
parent 51a24dacb0
commit 13597fc39e
4 changed files with 17 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/include/86box/nv/classes/vid_nv3_classes.h
View File

@@ -1096,8 +1096,10 @@ typedef struct nv3_grobj_s
// TODO: PATCHCORDS!!!! TO LINK ALL OF THIS TOGETHER!!!
#pragma pack(pop) // return packing to whatever it was before this disaster
// Method IDs
#define NV3_GENERIC_METHOD_IS_PFIFO_FREE 0x0010
// PIO Subchannel info
#define NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE 0x0010
#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START 0x0012
#define NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END 0x0017
// Class methods
void nv3_generic_method(uint32_t method_id, nv3_grobj_t grobj);
@@ -1109,7 +1111,6 @@ void nv3_class_005_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_006_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_007_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_008_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_009_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_00a_method(uint32_t method_id, nv3_grobj_t grobj);
void nv3_class_00b_method(uint32_t method_id, nv3_grobj_t grobj);

2
src/video/CMakeLists.txt
View File

@@ -80,6 +80,7 @@ add_library(vid OBJECT
vid_att2xc498_ramdac.c
vid_xga.c
vid_bochs_vbe.c
nv/nv_base.c nv/nv_rivatimer.c
nv/nv3/nv3_core.c
@@ -123,6 +124,7 @@ add_library(vid OBJECT
nv/nv3/classes/nv3_class_017_d3d5_tri_zeta_buffer.c
nv/nv3/classes/nv3_class_018_point_zeta_buffer.c
nv/nv3/classes/nv3_class_01c_image_in_memory.c
)
if(G100)

5
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -612,7 +612,8 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val)
new_address |= (nv3_runout_reason_free_count_overrun << NV3_PFIFO_RUNOUT_RAMIN_ERR);
}
if (method_offset > 0 && method_offset <= 0x100)
// 0x0 is used for the context
if (method_offset > 0 && method_offset < 0x100)
{
// Reserved NVIDIA Objects
oh_shit = true;
@@ -651,7 +652,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val)
nv3->pfifo.cache1_entries[current_put_address].data = val;
// now we have to recalculate the cache1 put address
uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address);
uint32_t next_put_address = nv3_pfifo_cache1_gray2normal(current_put_address) + 1;
if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX#
next_put_address &= NV3_PFIFO_CACHE1_SIZE_REV_C;

10
src/video/nv/nv3/subsystems/nv3_user.c
View File

@@ -28,19 +28,25 @@
#include <86Box/nv/vid_nv.h>
#include <86Box/nv/vid_nv3.h>
// PIO Method Submission
// 128 channels conceptually supported - a hangover from nv1 where multiple windows all directly programming the gpu were supported? total lunacy.
uint32_t nv3_user_read(uint32_t address)
{
// Get the address within the subchannel
//todo: print out the subchannel
uint8_t method_offset = (address & 0x1FFC);
nv_log("User Submission Area method_offset=0x%04x\n", method_offset);
nv_log("User Submission Area PIO Subchannel method_offset=0x%04x\n (Trying to read...)", method_offset);
// 0x10 is free CACHE1 object
// TODO: THERE ARE OTHER STUFF!
switch (method_offset)
{
case NV3_GENERIC_METHOD_IS_PFIFO_FREE:
case NV3_SUBCHANNEL_PIO_IS_PFIFO_FREE:
return nv3_pfifo_cache1_num_free_spaces();
case NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_START ... NV3_SUBCHANNEL_PIO_ALWAYS_ZERO_END:
return 0x00;
}