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Merge branch 'master' into net-add-tap-backend

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This commit is contained in:
Jasmine Iwanek
2025-06-26 22:11:10 -04:00
committed by GitHub
parent b28bed16fc 37dfa93c47
commit 32313eb92d
1154 changed files with 93967 additions and 44063 deletions
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2
.ci/Jenkinsfile vendored
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@@ -20,7 +20,7 @@ def repository = ['https://github.com/86Box/86Box.git', scm.userRemoteConfigs[0]
def commitBrowser = ['https://github.com/86Box/86Box/commit/%s', null]
def branch = ['master', scm.branches[0].name]
def buildType = ['beta', 'alpha']
def tarballFlags = ['', '-s']
def tarballFlags = ['', '-t']
def buildBranch = env.JOB_BASE_NAME.contains('-') ? 1 : 0
def osArchs = [

5
.ci/build.sh
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@@ -542,11 +542,12 @@ then
sudo sed -i -e 's/configure.env-append MAKE=/configure.env-append VULKAN_SDK=${prefix} MAKE=/g' "$qt5_portfile"
fi
# Patch openal-soft to use 1.23.1 on all targets instead of 1.24.1 on >=10.15 only,
# Patch openal-soft to use 1.23.1 on all targets instead of 1.24.2 on >=10.13 only,
# to prevent a symlink mismatch from having different versions on x86_64 and arm64.
# See: https://github.com/macports/macports-ports/commit/9b4903fc9c76769d476079e404c9a3b8a225f8aa
# https://github.com/macports/macports-ports/commit/788deb64dc0695e8d04afb32ed904947f2a7591b
openal_portfile="$macports/var/macports/sources/rsync.macports.org/macports/release/tarballs/ports/audio/openal-soft/Portfile"
sudo sed -i -e 's/if {${os.platform} ne "darwin" || ${os.major} >= 19}/if {0}/g' "$openal_portfile"
sudo sed -i -e 's/if {${os.platform} ne "darwin" ||/if {0 \&\&/g' "$openal_portfile"
# Patch wget to remove libproxy support, as it depends on shared-mime-info which
# fails to build for a 10.13 target, which we have to do despite wget only being

18
.github/workflows/cmake_macos.yml vendored
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@@ -56,22 +56,13 @@ jobs:
- name: SDL GUI
qt: off
static: on
src-packages: >-
libsndfile
- name: Qt GUI
qt: on
slug: -Qt
packages: >-
qt@5
src-packages: >-
libsndfile
steps:
- name: Install source dependencies
run: >-
brew reinstall -s
${{ matrix.ui.src-packages }}
- name: Install dependencies
run: >-
brew install
@@ -158,22 +149,13 @@ jobs:
- name: SDL GUI
qt: off
static: on
src-packages: >-
libsndfile
- name: Qt GUI
qt: on
slug: -Qt
packages: >-
qt@5
src-packages: >-
libsndfile
steps:
- name: Install source dependencies
run: >-
brew reinstall -s
${{ matrix.ui.src-packages }}
- name: Install dependencies
run: >-
brew install

74
.github/workflows/cmake_windows_msys2.yml vendored
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@@ -18,7 +18,6 @@ on:
- cmake/**
- "**/CMakeLists.txt"
- "CMakePresets.json"
- .github/workflows/**
- .github/workflows/cmake_windows_msys2.yml
- vcpkg.json
- "!**/Makefile*"
@@ -26,9 +25,9 @@ on:
jobs:
msys2:
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }}"
name: "${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }}"
runs-on: windows-2022
runs-on: ${{ matrix.environment.runner }}
env:
BUILD_WRAPPER_OUT_DIR: build_wrapper_output_directory # Directory where build-wrapper output will be placed
@@ -41,47 +40,38 @@ jobs:
fail-fast: true
matrix:
build:
# - name: Regular
# preset: regular
- name: Debug
- name: Dev Debug
preset: dev_debug
slug: -Debug
slug: -Dev-Debug
- name: Dev
preset: development
slug: -Dev
dynarec:
- name: ODR
new: off
slug: -ODR
- name: NDR
new: on
slug: -NDR
ui:
- name: Qt GUI
qt: on
static: on
slug: -Qt
packages: >-
qt5-static:p
vulkan-headers:p
environment:
# - msystem: MSYS
# toolchain: ./cmake/flags-gcc-x86_64.cmake
- msystem: MINGW64
prefix: mingw-w64-x86_64
toolchain: ./cmake/flags-gcc-x86_64.cmake
# - msystem: CLANG64
# prefix: mingw-w64-clang-x86_64
# toolchain: ./cmake/llvm-win32-x86_64.cmake
# - msystem: UCRT64
# prefix: mingw-w64-ucrt-x86_64
# toolchain: ./cmake/flags-gcc-x86_64.cmake
slug: "-64"
runner: windows-2022
- msystem: CLANGARM64
toolchain: ./cmake/flags-gcc-aarch64.cmake
slug: -arm64
runner: windows-11-arm
exclude:
- dynarec:
new: off
environment:
msystem: CLANGARM64
steps:
- name: Prepare MSYS2 environment
uses: msys2/setup-msys2@v2
with:
release: false
release: true
update: true
msystem: ${{ matrix.environment.msystem }}
pacboy: >-
@@ -98,15 +88,17 @@ jobs:
libslirp:p
fluidsynth:p
libserialport:p
${{ matrix.ui.packages }}
qt5-static:p
vulkan-headers:p
openmp:p
- name: Checkout repository
uses: actions/checkout@v4
with:
fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis
- name: Install sonar-scanner and build-wrapper
uses: SonarSource/sonarcloud-github-c-cpp@v3
# - name: Install sonar-scanner and build-wrapper
# uses: SonarSource/sonarcloud-github-c-cpp@v3
- name: Configure CMake
run: >-
@@ -114,20 +106,20 @@ jobs:
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D STATIC_BUILD=${{ matrix.ui.static }}
# - name: Build
# run: |
# .sonar/build-wrapper-win-x86/build-wrapper-win-x86-64.exe --out-dir ${{ env.BUILD_WRAPPER_OUT_DIR }} cmake --build build
- name: Build
run: |
.sonar/build-wrapper-win-x86/build-wrapper-win-x86-64.exe --out-dir ${{ env.BUILD_WRAPPER_OUT_DIR }} cmake --build build
run: cmake --build build
- name: Run sonar-scanner
if: 0
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }}
run: |
.sonar/sonar-scanner-5.0.1.3006-windows/bin/sonar-scanner.bat --define sonar.cfamily.build-wrapper-output="${{ env.BUILD_WRAPPER_OUT_DIR }}"
# - name: Run sonar-scanner
# env:
# GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
# SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }}
# run: |
# .sonar/sonar-scanner-5.0.1.3006-windows/bin/sonar-scanner.bat --define sonar.cfamily.build-wrapper-output="${{ env.BUILD_WRAPPER_OUT_DIR }}"
- name: Generate package
run: cmake --install build
@@ -135,5 +127,5 @@ jobs:
- name: Upload artifact
uses: actions/upload-artifact@v4
with:
name: '86Box${{ matrix.ui.slug }}${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-Windows-${{ matrix.environment.msystem }}-gha${{ github.run_number }}'
name: '86Box${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-Windows${{ matrix.environment.slug }}-gha${{ github.run_number }}'
path: build/artifacts/**

29
CMakeLists.txt
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@@ -11,7 +11,7 @@
# Authors: David Hrdlička, <hrdlickadavid@outlook.com>
#
# Copyright 2020-2021 David Hrdlička.
# Copyright 2021-2024 Jasmine Iwanek.
# Copyright 2021-2025 Jasmine Iwanek.
#
cmake_minimum_required(VERSION 3.16)
@@ -36,7 +36,7 @@ if(MUNT_EXTERNAL)
endif()
project(86Box
VERSION 4.3
VERSION 5.0
DESCRIPTION "Emulator of x86-based systems"
HOMEPAGE_URL "https://86box.net"
LANGUAGES C CXX)
@@ -132,7 +132,6 @@ option(RTMIDI "RtMidi"
option(FLUIDSYNTH "FluidSynth" ON)
option(MUNT "MUNT" ON)
option(VNC "VNC renderer" OFF)
option(NEW_DYNAREC "Use the PCem v15 (\"new\") dynamic recompiler" OFF)
option(MINITRACE "Enable Chrome tracing using the modified minitrace library" OFF)
option(GDBSTUB "Enable GDB stub server for debugging" OFF)
option(DEV_BRANCH "Development branch" OFF)
@@ -140,6 +139,24 @@ option(DISCORD "Discord Rich Presence support"
option(DEBUGREGS486 "Enable debug register opeartion on 486+ CPUs" OFF)
option(LIBASAN "Enable compilation with the addresss sanitizer" OFF)
if((ARCH STREQUAL "arm64") OR (ARCH STREQUAL "arm"))
set(NEW_DYNAREC ON)
else()
option(NEW_DYNAREC "Use the PCem v15 (\"new\") dynamic recompiler" OFF)
endif()
if(CMAKE_SYSTEM_NAME STREQUAL "NetBSD")
option(AUDIO4 "Use audio(4) as sound backend" ON)
else()
set(AUDIO4 OFF)
endif()
if(CMAKE_SYSTEM_NAME STREQUAL "OpenBSD")
option(SNDIO "Use sndio as sound backend" ON)
else()
set(SNDIO OFF)
endif()
if(WIN32)
set(QT ON)
option(CPPTHREADS "C++11 threads" OFF)
@@ -157,17 +174,11 @@ endif()
# Option Description Def. Condition Otherwise
# ------ ----------- ---- ------------ ---------
cmake_dependent_option(AMD_K5 "AMD K5" ON "DEV_BRANCH" OFF)
cmake_dependent_option(AN430TX "Intel AN430TX" ON "DEV_BRANCH" OFF)
cmake_dependent_option(CDROM_MITSUMI "Mitsumi CDROM" ON "DEV_BRANCH" OFF)
cmake_dependent_option(CYRIX_6X86 "Cyrix 6x86" ON "DEV_BRANCH" OFF)
cmake_dependent_option(G100 "Matrox Productiva G100" ON "DEV_BRANCH" OFF)
cmake_dependent_option(GUSMAX "Gravis UltraSound MAX" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_RAMPAGE "AST Rampage" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_IAB "Intel Above Board" ON "DEV_BRANCH" OFF)
cmake_dependent_option(ISAMEM_BRAT "BocaRAM/AT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(LASERXT "VTech Laser XT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(OLIVETTI "Olivetti M290" ON "DEV_BRANCH" OFF)
cmake_dependent_option(OPEN_AT "OpenAT" ON "DEV_BRANCH" OFF)
cmake_dependent_option(OPL4ML "OPL4-ML daughterboard" ON "DEV_BRANCH" OFF)
cmake_dependent_option(PCL "Generic PCL5e Printer" ON "DEV_BRANCH" OFF)
cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper" ON "DEV_BRANCH" OFF)

8
CMakePresets.json
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@@ -55,6 +55,14 @@
},
"inherits": "base"
},
{
"name": "ultra_debug",
"cacheVariables": {
"CMAKE_BUILD_TYPE": "UltraDebug",
"DEV_BRANCH": "ON"
},
"inherits": "base"
},
{
"name": "llvm-macos-aarch64.cmake",
"displayName": "MacOS clang regular",

9
README.md
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@@ -26,17 +26,18 @@ Minimum system requirements and recommendations
* macOS version: macOS High Sierra 10.13 or newer
* 4 GB of RAM or higher
Performance may vary depending on both host and guest configuration. Most emulation logic is executed in a single thread; therefore, systems with better IPC (instructions per clock) generally should be able to emulate higher clock speeds.
Performance may vary depending on host and guest configuration. Most emulation logic is executed in a single thread. Therefore, systems with greater IPC (instructions per clock) capacity should be able to emulate higher clock speeds.
It is also recommended to use a manager application with 86Box for easier handling of multiple virtual machines.
For easier handling of multiple virtual machines, use a manager application:
* [Avalonia 86](https://github.com/notBald/Avalonia86) by [notBald](https://github.com/notBald) (Windows and Linux)
* [86Box Manager](https://github.com/86Box/86BoxManager) by [Overdoze](https://github.com/daviunic) (Windows only)
* [86Box Manager X](https://github.com/RetBox/86BoxManagerX) by [xafero](https://github.com/xafero) (Cross platform Port of 86Box Manager using Avalonia)
* [sl86](https://github.com/DDXofficial/sl86) by [DDX](https://github.com/DDXofficial) (Command-line 86Box machine manager written in Python)
* [Linbox-qt5](https://github.com/Dungeonseeker/linbox-qt5) by [Dungeonseeker](https://github.com/Dungeonseeker/) (Linux focused, should work on Windows though untested)
* [MacBox for 86Box](https://github.com/Moonif/MacBox) by [Moonif](https://github.com/Moonif) (MacOS only)
It is also possible to use 86Box on its own with the `--vmpath`/`-P` command line option.
To use 86Box on its own, use the `--vmpath`/`-P` command line option.
Getting started
---------------
@@ -46,7 +47,7 @@ See [our documentation](https://86box.readthedocs.io/en/latest/index.html) for a
Community
---------
We operate an IRC channel and a Discord server for discussing 86Box, its development and anything related to retro computing. We look forward to hearing from you!
We operate an IRC channel and a Discord server for discussing 86Box, its development, and anything related to retro computing. We look forward to hearing from you!
[![Visit our IRC channel](https://kiwiirc.com/buttons/irc.ringoflightning.net/86Box.png)](https://kiwiirc.com/client/irc.ringoflightning.net/?nick=86box|?#86Box)

4
cmake/flags-gcc.cmake
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@@ -20,6 +20,8 @@ string(APPEND CMAKE_C_FLAGS_RELEASE_INIT " -g0 -O3")
string(APPEND CMAKE_CXX_FLAGS_RELEASE_INIT " -g0 -O3")
string(APPEND CMAKE_C_FLAGS_DEBUG_INIT " -ggdb -Og")
string(APPEND CMAKE_CXX_FLAGS_DEBUG_INIT " -ggdb -Og")
string(APPEND CMAKE_C_FLAGS_ULTRADEBUG_INIT " -O0 -ggdb -g3")
string(APPEND CMAKE_CXX_FLAGS_ULTRADEBUG_INIT " -O0 -ggdb -g3")
string(APPEND CMAKE_C_FLAGS_OPTIMIZED_INIT " -march=native -mtune=native -O3 -ffp-contract=fast -flto")
string(APPEND CMAKE_CXX_FLAGS_OPTIMIZED_INIT " -march=native -mtune=native -O3 -ffp-contract=fast -flto")
@@ -28,7 +30,7 @@ foreach(LANG C;CXX)
set(CMAKE_${LANG}_FLAGS "$ENV{${LANG}FLAGS} ${CMAKE_${LANG}_FLAGS_INIT}" CACHE STRING "Flags used by the ${LANG} compiler during all build types.")
mark_as_advanced(CMAKE_${LANG}_FLAGS)
foreach(CONFIG RELEASE;DEBUG;OPTIMIZED)
foreach(CONFIG RELEASE;DEBUG;ULTRADEBUG;OPTIMIZED)
set(CMAKE_${LANG}_FLAGS_${CONFIG} "${CMAKE_${LANG}_FLAGS_${CONFIG}_INIT}" CACHE STRING "Flags used by the ${LANG} compiler during ${CONFIG} builds.")
mark_as_advanced(CMAKE_${LANG}_FLAGS_${CONFIG})
endforeach()

20
cmake/intel-linux-x86_64.cmake Normal file
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@@ -0,0 +1,20 @@
#
# 86Box A hypervisor and IBM PC system emulator that specializes in
# running old operating systems and software designed for IBM
# PC systems and compatibles from 1981 through fairly recent
# system designs based on the PCI bus.
#
# This file is part of the 86Box distribution.
#
# CMake toolchain file defining GCC compiler flags
# for 64-bit x86 targets.
#
# Authors: David Hrdlička, <hrdlickadavid@outlook.com>
#
# Copyright 2021 David Hrdlička.
#
include(${CMAKE_CURRENT_LIST_DIR}/flags-gcc-x86_64.cmake)
set(CMAKE_C_COMPILER icx)
set(CMAKE_CXX_COMPILER icpx)

23
cmake/llvm-linux-x86_64.cmake Normal file
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@@ -0,0 +1,23 @@
#
# 86Box A hypervisor and IBM PC system emulator that specializes in
# running old operating systems and software designed for IBM
# PC systems and compatibles from 1981 through fairly recent
# system designs based on the PCI bus.
#
# This file is part of the 86Box distribution.
#
# CMake toolchain file defining Clang compiler flags
# for 64-bit x86 targets.
#
# Authors: David Hrdlička, <hrdlickadavid@outlook.com>
# dob205
#
# Copyright 2021 David Hrdlička.
# Copyright 2022 dob205.
#
include(${CMAKE_CURRENT_LIST_DIR}/flags-gcc-x86_64.cmake)
# Use the GCC-compatible Clang executables in order to use our flags
set(CMAKE_C_COMPILER clang)
set(CMAKE_CXX_COMPILER clang++)

4
debian/changelog vendored
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@@ -1,5 +1,5 @@
86box (4.3) UNRELEASED; urgency=medium
86box (5.0) UNRELEASED; urgency=medium
* Bump release.
-- Jasmine Iwanek <jriwanek@gmail.com> Wed, 13 Nov 2024 06:31:46 +0100
-- Jasmine Iwanek <jriwanek@gmail.com> Wed, 16 Apr 2025 22:08:04 +0200

444
src/86box.c
View File

@@ -11,6 +11,7 @@
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Jasmine Iwanek, <jriwanek@gmail.com>
*
* Copyright 2008-2020 Sarah Walker.
* Copyright 2016-2020 Miran Grca.
@@ -18,7 +19,7 @@
* Copyright 2021 Laci bá'
* Copyright 2021 dob205
* Copyright 2021 Andreas J. Reichel.
* Copyright 2021-2022 Jasmine Iwanek.
* Copyright 2021-2025 Jasmine Iwanek.
*/
#include <inttypes.h>
#include <stdarg.h>
@@ -31,6 +32,7 @@
#include <wchar.h>
#include <stdatomic.h>
#include <unistd.h>
#include <math.h>
#ifndef _WIN32
# include <pwd.h>
@@ -68,6 +70,7 @@
#include <86box/unittester.h>
#include <86box/novell_cardkey.h>
#include <86box/isamem.h>
#include <86box/isarom.h>
#include <86box/isartc.h>
#include <86box/lpt.h>
#include <86box/serial.h>
@@ -103,6 +106,7 @@
#include <86box/machine_status.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/nv/vid_nv_rivatimer.h>
// Disable c99-designator to avoid the warnings about int ng
#ifdef __clang__
@@ -157,6 +161,7 @@ int window_remember;
int vid_resize; /* (C) allow resizing */
int invert_display = 0; /* (C) invert the display */
int suppress_overscan = 0; /* (C) suppress overscans */
int lang_id = 0; /* (C) language id */
int scale = 0; /* (C) screen scale factor */
int dpi_scale = 0; /* (C) DPI scaling of the emulated
screen */
@@ -164,20 +169,20 @@ int vid_api = 0; /* (C) video r
int vid_cga_contrast = 0; /* (C) video */
int video_fullscreen = 0; /* (C) video */
int video_fullscreen_scale = 0; /* (C) video */
int video_fullscreen_first = 0; /* (C) video */
int enable_overscan = 0; /* (C) video */
int force_43 = 0; /* (C) video */
int video_filter_method = 1; /* (C) video */
int video_vsync = 0; /* (C) video */
int video_framerate = -1; /* (C) video */
char video_shader[512] = { '\0' }; /* (C) video */
bool serial_passthrough_enabled[SERIAL_MAX] = { 0, 0, 0, 0, 0, 0, 0 }; /* (C) activation and kind of
bool serial_passthrough_enabled[SERIAL_MAX - 1] = { 0, 0, 0, 0, 0, 0, 0 }; /* (C) activation and kind of
pass-through for serial ports */
int bugger_enabled = 0; /* (C) enable ISAbugger */
int novell_keycard_enabled = 0; /* (C) enable Novell NetWare 2.x key card emulation. */
int postcard_enabled = 0; /* (C) enable POST card */
int unittester_enabled = 0; /* (C) enable unit tester device */
int gameport_type[GAMEPORT_MAX] = { 0, 0 }; /* (C) enable gameports */
int isamem_type[ISAMEM_MAX] = { 0, 0, 0, 0 }; /* (C) enable ISA mem cards */
int isarom_type[ISAROM_MAX] = { 0, 0, 0, 0 }; /* (C) enable ISA ROM cards */
int isartc_type = 0; /* (C) enable ISA RTC card */
int gfxcard[GFXCARD_MAX] = { 0, 0 }; /* (C) graphics/video card */
int show_second_monitors = 1; /* (C) show non-primary monitors */
@@ -186,6 +191,7 @@ int voodoo_enabled = 0; /* (C) video o
int lba_enhancer_enabled = 0; /* (C) enable Vision Systems LBA Enhancer */
int ibm8514_standalone_enabled = 0; /* (C) video option */
int xga_standalone_enabled = 0; /* (C) video option */
int da2_standalone_enabled = 0; /* (C) video option */
uint32_t mem_size = 0; /* (C) memory size (Installed on
system board)*/
uint32_t isa_mem_size = 0; /* (C) memory size (ISA Memory Cards) */
@@ -207,13 +213,49 @@ int video_fullscreen_scale_maximized = 0; /* (C) Whether
int do_auto_pause = 0; /* (C) Auto-pause the emulator on focus
loss */
int hook_enabled = 1; /* (C) Keyboard hook is enabled */
int test_mode = 0; /* (C) Test mode */
char uuid[MAX_UUID_LEN] = { '\0' }; /* (C) UUID or machine identifier */
int sound_muted = 0; /* (C) Is sound muted? */
int inhibit_multimedia_keys; /* (C) Inhibit multimedia keys on Windows. */
int other_ide_present = 0; /* IDE controllers from non-IDE cards are
present */
int other_scsi_present = 0; /* SCSI controllers from non-SCSI cards are
present */
// Accelerator key array
struct accelKey acc_keys[NUM_ACCELS];
// Default accelerator key values
struct accelKey def_acc_keys[NUM_ACCELS] = {
{ .name="send_ctrl_alt_del", .desc="Send Control+Alt+Del",
.seq="Ctrl+F12" },
{ .name="send_ctrl_alt_esc", .desc="Send Control+Alt+Escape",
.seq="Ctrl+F10" },
{ .name="fullscreen", .desc="Toggle fullscreen",
.seq="Ctrl+Alt+PgUp" },
{ .name="screenshot", .desc="Screenshot",
.seq="Ctrl+F11" },
{ .name="release_mouse", .desc="Release mouse pointer",
.seq="Ctrl+End" },
{ .name="hard_reset", .desc="Hard reset",
.seq="Ctrl+Alt+F12" },
{ .name="pause", .desc="Toggle pause",
.seq="Ctrl+Alt+F1" },
{ .name="mute", .desc="Toggle mute",
.seq="Ctrl+Alt+M" }
};
char vmm_path[1024] = { '\0'}; /* TEMPORARY - VM manager path to scan for VMs */
int vmm_enabled = 0;
/* Statistics. */
extern int mmuflush;
extern int readlnum;
@@ -227,6 +269,8 @@ extern int CPUID;
extern int output;
int atfullspeed;
extern double exp_pow_table[0x800];
char exe_path[2048]; /* path (dir) of executable */
char usr_path[1024]; /* path (dir) of user data */
char cfg_path[1024]; /* full path of config file */
@@ -246,18 +290,44 @@ int unscaled_size_y = SCREEN_RES_Y; /* current unscaled size Y */
int efscrnsz_y = SCREEN_RES_Y;
#endif
__thread int is_cpu_thread = 0;
static wchar_t mouse_msg[3][200];
static volatile atomic_int do_pause_ack = 0;
static volatile atomic_int pause_ack = 0;
#ifndef RELEASE_BUILD
static char buff[1024];
static int seen = 0;
#define LOG_SIZE_BUFFER 1024 /* Log size buffer */
static char buff[LOG_SIZE_BUFFER];
static int seen = 0;
static int suppr_seen = 1;
// Functions only used in this translation unit
void pclog_ensure_stdlog_open(void);
#endif
/*
Ensures STDLOG is open for pclog_ex and pclog_ex_cyclic
*/
void pclog_ensure_stdlog_open(void)
{
#ifndef RELEASE_BUILD
if (stdlog == NULL) {
if (log_path[0] != '\0') {
stdlog = plat_fopen(log_path, "w");
if (stdlog == NULL)
stdlog = stdout;
} else
stdlog = stdout;
}
#endif
}
/*
* Log something to the logfile or stdout.
*
@@ -266,22 +336,15 @@ static int suppr_seen = 1;
* being logged, and catch repeating entries.
*/
void
pclog_ex(const char *fmt, va_list ap)
pclog_ex(UNUSED(const char *fmt), UNUSED(va_list ap))
{
#ifndef RELEASE_BUILD
char temp[1024];
char temp[LOG_SIZE_BUFFER];
if (strcmp(fmt, "") == 0)
return;
if (stdlog == NULL) {
if (log_path[0] != '\0') {
stdlog = plat_fopen(log_path, "w");
if (stdlog == NULL)
stdlog = stdout;
} else
stdlog = stdout;
}
pclog_ensure_stdlog_open();
vsprintf(temp, fmt, ap);
if (suppr_seen && !strcmp(buff, temp))
@@ -298,6 +361,8 @@ pclog_ex(const char *fmt, va_list ap)
#endif
}
void
pclog_toggle_suppr(void)
{
@@ -308,7 +373,7 @@ pclog_toggle_suppr(void)
/* Log something. We only do this in non-release builds. */
void
pclog(const char *fmt, ...)
pclog(UNUSED(const char *fmt), ...)
{
#ifndef RELEASE_BUILD
va_list ap;
@@ -410,6 +475,75 @@ fatal_ex(const char *fmt, va_list ap)
fflush(stdlog);
}
/* Log a warning error, and display a UI message without exiting. */
void
warning(const char *fmt, ...)
{
char temp[1024];
va_list ap;
char *sp;
va_start(ap, fmt);
if (stdlog == NULL) {
if (log_path[0] != '\0') {
stdlog = plat_fopen(log_path, "w");
if (stdlog == NULL)
stdlog = stdout;
} else
stdlog = stdout;
}
vsprintf(temp, fmt, ap);
fprintf(stdlog, "%s", temp);
fflush(stdlog);
va_end(ap);
/* Make sure the message does not have a trailing newline. */
if ((sp = strchr(temp, '\n')) != NULL)
*sp = '\0';
do_pause(2);
ui_msgbox(MBX_ERROR | MBX_ANSI, temp);
fflush(stdlog);
do_pause(0);
}
void
warning_ex(const char *fmt, va_list ap)
{
char temp[1024];
char *sp;
if (stdlog == NULL) {
if (log_path[0] != '\0') {
stdlog = plat_fopen(log_path, "w");
if (stdlog == NULL)
stdlog = stdout;
} else
stdlog = stdout;
}
vsprintf(temp, fmt, ap);
fprintf(stdlog, "%s", temp);
fflush(stdlog);
/* Make sure the message does not have a trailing newline. */
if ((sp = strchr(temp, '\n')) != NULL)
*sp = '\0';
do_pause(2);
ui_msgbox(MBX_ERROR | MBX_ANSI, temp);
fflush(stdlog);
do_pause(0);
}
#ifdef ENABLE_PC_LOG
int pc_do_log = ENABLE_PC_LOG;
@@ -435,7 +569,7 @@ delete_nvr_file(uint8_t flash)
int c;
/* Set up the NVR file's name. */
c = strlen(machine_get_internal_name()) + 5;
c = strlen(machine_get_nvr_name()) + 5;
fn = (char *) malloc(c + 1);
if (fn == NULL)
@@ -443,9 +577,9 @@ delete_nvr_file(uint8_t flash)
flash ? "BIOS flash" : "CMOS");
if (flash)
sprintf(fn, "%s.bin", machine_get_internal_name());
sprintf(fn, "%s.bin", machine_get_nvr_name());
else
sprintf(fn, "%s.nvr", machine_get_internal_name());
sprintf(fn, "%s.nvr", machine_get_nvr_name());
remove(nvr_path(fn));
@@ -455,6 +589,62 @@ delete_nvr_file(uint8_t flash)
extern void device_find_all_descs(void);
static void
pc_show_usage(char *s)
{
char p[4096] = { 0 };
sprintf(p,
"\n%sUsage: 86box [options] [cfg-file]\n\n"
"Valid options are:\n\n"
"-? or --help\t\t\t- show this information\n"
"-C or --config path\t\t- set 'path' to be config file\n"
#ifdef _WIN32
"-D or --debug\t\t\t- force debug output logging\n"
#endif
#if 1
"-E or --vmmpath\t\t- vm manager path\n"
#endif
"-F or --fullscreen\t\t- start in fullscreen mode\n"
"-G or --lang langid\t\t- start with specified language\n"
"\t\t\t\t (e.g. en-US, or system)\n"
#ifdef _WIN32
"-H or --hwnd id,hwnd\t\t- sends back the main dialog's hwnd\n"
#endif
"-I or --image d:path\t\t- load 'path' as floppy image on drive d\n"
#ifdef USE_INSTRUMENT
"-J or --instrument name\t- set 'name' to be the profiling instrument\n"
#endif
"-L or --logfile pat\t\t- set 'path' to be the logfile\n"
"-M or --missing\t\t- dump missing machines and video cards\n"
"-N or --noconfirm\t\t- do not ask for confirmation on quit\n"
"-P or --vmpath path\t\t- set 'path' to be root for vm\n"
"-R or --rompath path\t\t- set 'path' to be ROM path\n"
#ifndef USE_SDL_UI
"-S or --settings\t\t\t- show only the settings dialog\n"
#endif
"-T or --testmode\t\t- test mode: execute the test mode entry\n"
"\t\t\t\t point on init/hard reset\n"
"-V or --vmname name\t\t- overrides the name of the running VM\n"
"-W or --nohook\t\t- disables keyboard hook\n"
"\t\t\t\t (compatibility-only outside Windows)\n"
"-X or --clear what\t\t- clears the 'what' (cmos/flash/both)\n"
"-Y or --donothing\t\t- do not show any UI or run the emulation\n"
"-Z or --lastvmpath\t\t- the last parameter is VM path rather\n"
"\t\t\t\t than config\n"
"\nA config file can be specified. If none is, the default file will be used.\n",
(s == NULL) ? "" : s);
#ifdef _WIN32
ui_msgbox(MBX_ANSI | ((s == NULL) ? MBX_INFO : MBX_WARNING), p);
#else
if (s == NULL)
pclog("%s", p);
else
ui_msgbox(MBX_ANSI | MBX_WARNING, p);
#endif
}
/*
* Perform initial startup of the PC.
*
@@ -478,6 +668,9 @@ pc_init(int argc, char *argv[])
time_t now;
int c;
int lvmp = 0;
#ifdef DEPRECATE_USAGE
int deprecated = 1;
#endif
#ifdef ENABLE_NG
int ng = 0;
#endif
@@ -485,7 +678,7 @@ pc_init(int argc, char *argv[])
uint32_t *uid;
uint32_t *shwnd;
#endif
uint32_t lang_init = 0;
int lang_init = 0;
/* Grab the executable's full path. */
plat_get_exe_name(exe_path, sizeof(exe_path) - 1);
@@ -535,40 +728,7 @@ usage:
}
}
printf("\nUsage: 86box [options] [cfg-file]\n\n");
printf("Valid options are:\n\n");
printf("-? or --help - show this information\n");
printf("-C or --config path - set 'path' to be config file\n");
#ifdef _WIN32
printf("-D or --debug - force debug output logging\n");
#endif
#if 0
printf("-E or --nographic - forces the old behavior\n");
#endif
printf("-F or --fullscreen - start in fullscreen mode\n");
printf("-G or --lang langid - start with specified language (e.g. en-US, or system)\n");
#ifdef _WIN32
printf("-H or --hwnd id,hwnd - sends back the main dialog's hwnd\n");
#endif
printf("-I or --image d:path - load 'path' as floppy image on drive d\n");
#ifdef USE_INSTRUMENT
printf("-J or --instrument name - set 'name' to be the profiling instrument\n");
#endif
printf("-K or --keycodes codes - set 'codes' to be the uncapture combination\n");
printf("-L or --logfile path - set 'path' to be the logfile\n");
printf("-M or --missing - dump missing machines and video cards\n");
printf("-N or --noconfirm - do not ask for confirmation on quit\n");
printf("-P or --vmpath path - set 'path' to be root for vm\n");
printf("-R or --rompath path - set 'path' to be ROM path\n");
#ifndef USE_SDL_UI
printf("-S or --settings - show only the settings dialog\n");
#endif
printf("-V or --vmname name - overrides the name of the running VM\n");
printf("-W or --nohook - disables keyboard hook (compatibility-only outside Windows)\n");
printf("-X or --clear what - clears the 'what' (cmos/flash/both)\n");
printf("-Y or --donothing - do not show any UI or run the emulation\n");
printf("-Z or --lastvmpath - the last parameter is VM path rather than config\n");
printf("\nA config file can be specified. If none is, the default file will be used.\n");
pc_show_usage(NULL);
return 0;
} else if (!strcasecmp(argv[c], "--lastvmpath") || !strcasecmp(argv[c], "-Z")) {
lvmp = 1;
@@ -576,13 +736,18 @@ usage:
} else if (!strcasecmp(argv[c], "--debug") || !strcasecmp(argv[c], "-D")) {
force_debug = 1;
#endif
#ifdef ENABLE_NG
} else if (!strcasecmp(argv[c], "--nographic") || !strcasecmp(argv[c], "-E")) {
/* Currently does nothing, but if/when we implement a built-in manager,
it's going to force the manager not to run, allowing the old usage
without parameter. */
ng = 1;
#endif
//#ifdef ENABLE_NG
} else if (!strcasecmp(argv[c], "--vmmpath") ||
!strcasecmp(argv[c], "-E")) {
/* Using this variable for vm manager path
Temporary solution!*/
if ((c+1) == argc) goto usage;
char *vp = argv[++c];
if ((strlen(vp) + 1) >= sizeof(vmm_path))
memcpy(vmm_path, vp, sizeof(vmm_path));
else
memcpy(vmm_path, vp, strlen(vp) + 1);
//#endif
} else if (!strcasecmp(argv[c], "--fullscreen") || !strcasecmp(argv[c], "-F")) {
start_in_fullscreen = 1;
} else if (!strcasecmp(argv[c], "--logfile") || !strcasecmp(argv[c], "-L")) {
@@ -595,6 +760,9 @@ usage:
goto usage;
ppath = argv[++c];
#ifdef DEPRECATE_USAGE
deprecated = 0;
#endif
} else if (!strcasecmp(argv[c], "--rompath") || !strcasecmp(argv[c], "-R")) {
if ((c + 1) == argc)
goto usage;
@@ -606,6 +774,9 @@ usage:
goto usage;
cfg = argv[++c];
#ifdef DEPRECATE_USAGE
deprecated = 0;
#endif
} else if (!strcasecmp(argv[c], "--image") || !strcasecmp(argv[c], "-I")) {
if ((c + 1) == argc)
goto usage;
@@ -634,6 +805,8 @@ usage:
} else if (!strcasecmp(argv[c], "--settings") || !strcasecmp(argv[c], "-S")) {
settings_only = 1;
#endif
} else if (!strcasecmp(argv[c], "--testmode") || !strcasecmp(argv[c], "-T")) {
test_mode = 1;
} else if (!strcasecmp(argv[c], "--noconfirm") || !strcasecmp(argv[c], "-N")) {
confirm_exit_cmdl = 0;
} else if (!strcasecmp(argv[c], "--missing") || !strcasecmp(argv[c], "-M")) {
@@ -642,13 +815,6 @@ usage:
do_nothing = 1;
} else if (!strcasecmp(argv[c], "--nohook") || !strcasecmp(argv[c], "-W")) {
hook_enabled = 0;
} else if (!strcasecmp(argv[c], "--keycodes") || !strcasecmp(argv[c], "-K")) {
if ((c + 1) == argc)
goto usage;
sscanf(argv[++c], "%03hX,%03hX,%03hX,%03hX,%03hX,%03hX",
&key_prefix_1_1, &key_prefix_1_2, &key_prefix_2_1, &key_prefix_2_2,
&key_uncapture_1, &key_uncapture_2);
} else if (!strcasecmp(argv[c], "--clearboth") || !strcasecmp(argv[c], "-X")) {
if ((c + 1) == argc)
goto usage;
@@ -709,11 +875,22 @@ usage:
ppath = argv[c++];
else
cfg = argv[c++];
#ifdef DEPRECATE_USAGE
deprecated = 0;
#endif
}
if (c != argc)
goto usage;
#ifdef DEPRECATE_USAGE
if (deprecated)
pc_show_usage("Running 86Box without a specified VM path and/or configuration\n"
"file has been deprected. Please specify one or use a manager\n"
"(Avalonia 86 is recommended).\n\n");
#endif
path_slash(usr_path);
path_slash(rom_path);
@@ -857,6 +1034,10 @@ usage:
}
pclog("# Configuration file: %s\n#\n\n", cfg_path);
if (strlen(vmm_path) != 0) {
vmm_enabled = 1;
pclog("# VM Manager enabled. Path: %s\n", vmm_path);
}
/*
* We are about to read the configuration file, which MAY
* put data into global variables (the hard- and floppy
@@ -870,6 +1051,13 @@ usage:
zip_global_init();
mo_global_init();
/* Initialize the keyboard accelerator list with default values */
for (int x = 0; x < NUM_ACCELS; x++) {
strcpy(acc_keys[x].name, def_acc_keys[x].name);
strcpy(acc_keys[x].desc, def_acc_keys[x].desc);
strcpy(acc_keys[x].seq, def_acc_keys[x].seq);
}
/* Load the configuration file. */
config_load();
@@ -1056,6 +1244,11 @@ pc_init_modules(void)
machine_status_init();
for (c = 0; c <= 0x7ff; c++) {
int64_t exp = c - 1023; /* 1023 = BIAS64 */
exp_pow_table[c] = pow(2.0, (double) exp);
}
if (do_nothing) {
do_nothing = 0;
exit(-1);
@@ -1067,13 +1260,52 @@ pc_init_modules(void)
void
pc_send_ca(uint16_t sc)
{
keyboard_input(1, 0x1D); /* Ctrl key pressed */
keyboard_input(1, 0x38); /* Alt key pressed */
keyboard_input(1, sc);
usleep(50000);
keyboard_input(0, sc);
keyboard_input(0, 0x38); /* Alt key released */
keyboard_input(0, 0x1D); /* Ctrl key released */
if (keyboard_mode >= 0x81) {
/* Use R-Alt because PS/55 DOS and OS/2 assign L-Alt Kanji */
keyboard_input(1, 0x1D); /* Ctrl key pressed */
if (keyboard_get_in_reset())
return;
keyboard_input(1, 0x138); /* R-Alt key pressed */
if (keyboard_get_in_reset())
return;
keyboard_input(1, sc);
if (keyboard_get_in_reset())
return;
usleep(50000);
if (keyboard_get_in_reset())
return;
keyboard_input(0, sc);
if (keyboard_get_in_reset())
return;
keyboard_input(0, 0x138); /* R-Alt key released */
if (keyboard_get_in_reset())
return;
keyboard_input(0, 0x1D); /* Ctrl key released */
if (keyboard_get_in_reset())
return;
} else {
keyboard_input(1, 0x1D); /* Ctrl key pressed */
if (keyboard_get_in_reset())
return;
keyboard_input(1, 0x38); /* Alt key pressed */
if (keyboard_get_in_reset())
return;
keyboard_input(1, sc);
if (keyboard_get_in_reset())
return;
usleep(50000);
if (keyboard_get_in_reset())
return;
keyboard_input(0, sc);
if (keyboard_get_in_reset())
return;
keyboard_input(0, 0x38); /* Alt key released */
if (keyboard_get_in_reset())
return;
keyboard_input(0, 0x1D); /* Ctrl key released */
if (keyboard_get_in_reset())
return;
}
}
/* Send the machine a Control-Alt-DEL sequence. */
@@ -1090,6 +1322,27 @@ pc_send_cae(void)
pc_send_ca(1);
}
/*
Currently available API:
extern void resetx86(void);
extern void softresetx86(void);
extern void hardresetx86(void);
extern void prefetch_queue_set_pos(int pos);
extern void prefetch_queue_set_ip(uint16_t ip);
extern void prefetch_queue_set_prefetching(int p);
extern int prefetch_queue_get_pos(void);
extern uint16_t prefetch_queue_get_ip(void);
extern int prefetch_queue_get_prefetching(void);
extern int prefetch_queue_get_size(void);
*/
static void
pc_test_mode_entry_point(void)
{
pclog("Test mode entry point\n=====================\n");
}
void
pc_reset_hard_close(void)
{
@@ -1154,6 +1407,8 @@ pc_reset_hard_init(void)
* modules that are.
*/
keyboard_init();
/* Reset the IDE and SCSI presences */
other_ide_present = other_scsi_present = 0;
@@ -1230,6 +1485,10 @@ pc_reset_hard_init(void)
zip_hard_reset();
/* Reset any ISA ROM cards. */
isarom_reset();
/* Reset any ISA RTC cards. */
isartc_reset();
@@ -1291,6 +1550,9 @@ pc_reset_hard_init(void)
update_mouse_msg();
if (test_mode)
pc_test_mode_entry_point();
ui_hard_reset_completed();
}
@@ -1394,6 +1656,10 @@ pc_close(UNUSED(thread_t *ptr))
scsi_disk_close();
gdbstub_close();
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
mem_free();
#endif
}
#ifdef __APPLE__
@@ -1427,6 +1693,9 @@ pc_run(void)
pc_reset_hard_init();
}
/* Update the guest-CPU independent timer for devices with independent clock speed */
rivatimer_update_all();
/* Run a block of code. */
startblit();
cpu_exec((int32_t) cpu_s->rspeed / 100);
@@ -1477,6 +1746,8 @@ set_screen_size_monitor(int x, int y, int monitor_index)
{
int temp_overscan_x = monitors[monitor_index].mon_overscan_x;
int temp_overscan_y = monitors[monitor_index].mon_overscan_y;
int is_svga = (video_get_type_monitor(monitor_index) == VIDEO_FLAG_TYPE_SPECIAL) ||
(video_get_type_monitor(monitor_index) == VIDEO_FLAG_TYPE_8514);
double dx;
double dy;
double dtx;
@@ -1510,19 +1781,19 @@ set_screen_size_monitor(int x, int y, int monitor_index)
dty = (double) temp_overscan_y;
/* Account for possible overscan. */
if (video_get_type_monitor(monitor_index) != VIDEO_FLAG_TYPE_SPECIAL && (temp_overscan_y == 16)) {
if (!is_svga && (temp_overscan_y == 16)) {
/* CGA */
dy = (((dx - dtx) / 4.0) * 3.0) + dty;
} else if (video_get_type_monitor(monitor_index) != VIDEO_FLAG_TYPE_SPECIAL && (temp_overscan_y < 16)) {
} else if (!is_svga && (temp_overscan_y < 16)) {
/* MDA/Hercules */
dy = (x / 4.0) * 3.0;
dy = (dx / 4.0) * 3.0;
} else {
if (enable_overscan) {
/* EGA/(S)VGA with overscan */
dy = (((dx - dtx) / 4.0) * 3.0) + dty;
} else {
/* EGA/(S)VGA without overscan */
dy = (x / 4.0) * 3.0;
dy = (dx / 4.0) * 3.0;
}
}
monitors[monitor_index].mon_unscaled_size_y = (int) dy;
@@ -1639,3 +1910,16 @@ do_pause(int p)
}
atomic_store(&pause_ack, 0);
}
// Helper to find an accelerator key and return it's index in acc_keys
int FindAccelerator(const char *name) {
for(int x=0;x<NUM_ACCELS;x++)
{
if(strcmp(acc_keys[x].name, name) == 0)
{
return(x);
}
}
// No key was found
return -1;
}

19
src/CMakeLists.txt
View File

@@ -23,8 +23,6 @@ endif()
add_executable(86Box
86box.c
config.c
log.c
random.c
timer.c
io.c
acpi.c
@@ -41,15 +39,11 @@ add_executable(86Box
pci.c
mca.c
usb.c
fifo.c
fifo8.c
device.c
nvr.c
nvr_at.c
nvr_ps2.c
machine_status.c
ini.c
cJSON.c
)
if(CMAKE_SYSTEM_NAME MATCHES "Linux")
@@ -106,7 +100,11 @@ if(INSTRUMENT)
endif()
target_link_libraries(86Box cpu chipset mch dev mem fdd game cdrom zip mo hdd
net print scsi sio snd vid voodoo plat ui)
net print scsi sio snd utils vid voodoo plat ui)
if(HAIKU)
target_link_libraries(86Box be)
endif()
if(WIN32 AND ARCH STREQUAL "i386")
if(MINGW)
@@ -223,7 +221,6 @@ elseif(APPLE AND NOT QT)
COMPONENT Runtime)
endif()
# Install the PDB file on Windows builds
if(MSVC)
# CMake fully supports PDB files on MSVC-compatible compilers
@@ -253,7 +250,9 @@ add_subdirectory(printer)
add_subdirectory(sio)
add_subdirectory(scsi)
add_subdirectory(sound)
add_subdirectory(utils)
add_subdirectory(video)
if (APPLE)
add_subdirectory(mac)
endif()
@@ -264,3 +263,7 @@ else()
add_compile_definitions(USE_SDL_UI)
add_subdirectory(unix)
endif()
if(CMAKE_SYSTEM_NAME MATCHES "NetBSD")
add_custom_command(TARGET 86Box POST_BUILD COMMAND paxctl ARGS +m $<TARGET_FILE:86Box> COMMENT "Disable PaX MPROTECT")
endif()

47
src/acpi.c
View File

@@ -36,6 +36,7 @@
#include <86box/pit.h>
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/dma.h>
#include <86box/machine.h>
#include <86box/i2c.h>
#include <86box/video.h>
@@ -89,7 +90,7 @@ acpi_timer_get(acpi_t *dev)
}
static uint8_t
acpi_gp_timer_get(acpi_t *dev)
acpi_gp_timer_get(UNUSED(acpi_t *dev))
{
uint64_t clock = acpi_clock_get();
clock -= acpi_last_clock;
@@ -211,7 +212,10 @@ acpi_update_irq(acpi_t *dev)
if ((dev->regs.pmcntrl & 0x01) && sci_level) switch (dev->irq_mode) {
default:
picintlevel(1 << dev->irq_line, &dev->irq_state);
if (dev->irq_line != 0)
picintlevel(1 << dev->irq_line, &dev->irq_state);
else
dev->irq_state = 1;
break;
case 1:
pci_set_irq(dev->slot, dev->irq_pin, &dev->irq_state);
@@ -223,7 +227,10 @@ acpi_update_irq(acpi_t *dev)
break;
} else switch (dev->irq_mode) {
default:
picintclevel(1 << dev->irq_line, &dev->irq_state);
if (dev->irq_line != 0)
picintclevel(1 << dev->irq_line, &dev->irq_state);
else
dev->irq_state = 0;
break;
case 1:
pci_clear_irq(dev->slot, dev->irq_pin, &dev->irq_state);
@@ -1019,8 +1026,13 @@ acpi_reg_write_common_regs(UNUSED(int size), uint16_t addr, uint8_t val, void *p
nvr_reg_write(0x000f, 0xff, dev->nvr);
}
if (sus_typ & SUS_RESET_PCI)
if (sus_typ & SUS_RESET_PCI) {
/* DMA is part of the southbridge so it responds to PCI reset. */
dma_reset();
dma_set_at(1);
device_reset_all(DEVICE_PCI);
}
if (sus_typ & SUS_RESET_CPU)
cpu_alt_reset = 0;
@@ -2381,6 +2393,14 @@ acpi_reset(void *priv)
dev->regs.gpi_val = 0xfff57fc1;
if (!strcmp(machine_get_internal_name(), "ficva503a") || !strcmp(machine_get_internal_name(), "6via90ap"))
dev->regs.gpi_val |= 0x00000004;
/*
TriGem Delhi-III second GPI word:
- Bit 7 = Save CMOS (must be set);
- Bit 6 = Password jumper (must be set);
- Bit 5 = Enable Setup (must be set).
*/
else if (!strcmp(machine_get_internal_name(), "delhi3"))
dev->regs.gpi_val |= 0x00008000;
}
if (acpi_power_on) {
@@ -2473,10 +2493,9 @@ acpi_init(const device_t *info)
{
acpi_t *dev;
dev = (acpi_t *) malloc(sizeof(acpi_t));
dev = (acpi_t *) calloc(1, sizeof(acpi_t));
if (dev == NULL)
return NULL;
memset(dev, 0x00, sizeof(acpi_t));
cpu_to_acpi = ACPI_TIMER_FREQ / cpuclock;
dev->vendor = info->local;
@@ -2576,7 +2595,7 @@ const device_t acpi_ali_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2590,7 +2609,7 @@ const device_t acpi_intel_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2604,7 +2623,7 @@ const device_t acpi_via_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2618,7 +2637,7 @@ const device_t acpi_via_596b_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2632,7 +2651,7 @@ const device_t acpi_smc_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2646,7 +2665,7 @@ const device_t acpi_sis_5582_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2660,7 +2679,7 @@ const device_t acpi_sis_5595_1997_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -2674,7 +2693,7 @@ const device_t acpi_sis_5595_device = {
.init = acpi_init,
.close = acpi_close,
.reset = acpi_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = acpi_speed_changed,
.force_redraw = NULL,
.config = NULL

6
src/apm.c
View File

@@ -122,7 +122,7 @@ const device_t apm_device = {
.init = apm_init,
.close = apm_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -136,7 +136,7 @@ const device_t apm_pci_device = {
.init = apm_init,
.close = apm_close,
.reset = apm_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -150,7 +150,7 @@ const device_t apm_pci_acpi_device = {
.init = apm_init,
.close = apm_close,
.reset = apm_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

4
src/cdrom/CMakeLists.txt
View File

@@ -21,10 +21,8 @@ pkg_check_modules(SNDFILE REQUIRED IMPORTED_TARGET sndfile)
add_library(cdrom OBJECT
cdrom.c
cdrom_image_backend.c
cdrom_image_viso.c
cdrom_image.c
cdrom_ioctl.c
cdrom_image_viso.c
)
target_link_libraries(86Box PkgConfig::SNDFILE)

3913
src/cdrom/cdrom.c
View File

File diff suppressed because it is too large Load Diff

2182
src/cdrom/cdrom_image.c
View File

File diff suppressed because it is too large Load Diff

1499
src/cdrom/cdrom_image_backend.c
View File

File diff suppressed because it is too large Load Diff

147
src/cdrom/cdrom_image_viso.c
View File

@@ -21,7 +21,9 @@
#define __STDC_FORMAT_MACROS
#include <ctype.h>
#include <inttypes.h>
#ifdef IMAGE_VISO_LOG
#include <stdarg.h>
#endif
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
@@ -29,15 +31,16 @@
#include <sys/stat.h>
#include <time.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/bswap.h>
#include <86box/cdrom_image_backend.h>
#include <86box/cdrom.h>
#include <86box/cdrom_image.h>
#include <86box/cdrom_image_viso.h>
#include <86box/log.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/bswap.h>
#include <86box/plat_dir.h>
#include <86box/version.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#ifndef S_ISDIR
@@ -136,29 +139,30 @@ static const char rr_eid[] = "RRIP_1991A"; /* identifiers used in ER field for
static const char rr_edesc[] = "THE ROCK RIDGE INTERCHANGE PROTOCOL PROVIDES SUPPORT FOR POSIX FILE SYSTEM SEMANTICS.";
static int8_t tz_offset = 0;
#ifdef ENABLE_CDROM_IMAGE_VISO_LOG
int cdrom_image_viso_do_log = ENABLE_CDROM_IMAGE_VISO_LOG;
#ifdef IMAGE_VISO_LOG
int image_viso_do_log = IMAGE_VISO_LOG;
void
cdrom_image_viso_log(const char *fmt, ...)
image_viso_log(void *priv, const char *fmt, ...)
{
va_list ap;
if (cdrom_image_viso_do_log) {
if (image_viso_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
log_out(priv, fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_image_viso_log(fmt, ...)
# define image_viso_log(priv, fmt, ...)
#endif
static size_t
viso_pread(void *ptr, uint64_t offset, size_t size, size_t count, FILE *fp)
viso_pread(void *ptr, const uint64_t offset, const size_t size,
const size_t count, FILE *fp)
{
uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
const uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
if (fseeko64(fp, offset, SEEK_SET) != -1)
ret = fread(ptr, size, count, fp);
fseeko64(fp, cur_pos, SEEK_SET);
@@ -166,10 +170,11 @@ viso_pread(void *ptr, uint64_t offset, size_t size, size_t count, FILE *fp)
}
static size_t
viso_pwrite(const void *ptr, uint64_t offset, size_t size, size_t count, FILE *fp)
viso_pwrite(const void *ptr, const uint64_t offset, const size_t size,
const size_t count, FILE *fp)
{
uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
const uint64_t cur_pos = ftello64(fp);
size_t ret = 0;
if (fseeko64(fp, offset, SEEK_SET) != -1)
ret = fwrite(ptr, size, count, fp);
fseeko64(fp, cur_pos, SEEK_SET);
@@ -691,22 +696,22 @@ viso_read(void *priv, uint8_t *buffer, uint64_t seek, size_t count)
/* Close any existing FIFO entry's file. */
viso_entry_t *other_entry = viso->file_fifo[viso->file_fifo_pos];
if (other_entry && other_entry->file) {
cdrom_image_viso_log("VISO: Closing [%s]", other_entry->path);
image_viso_log(viso->tf.log, "Closing [%s]...\n", other_entry->path);
fclose(other_entry->file);
other_entry->file = NULL;
cdrom_image_viso_log("\n");
image_viso_log(viso->tf.log, "Done\n");
}
/* Open file. */
cdrom_image_viso_log("VISO: Opening [%s]", entry->path);
image_viso_log(viso->tf.log, "Opening [%s]...\n", entry->path);
if ((entry->file = fopen(entry->path, "rb"))) {
cdrom_image_viso_log("\n");
image_viso_log(viso->tf.log, "Done\n");
/* Add this entry to the FIFO. */
viso->file_fifo[viso->file_fifo_pos++] = entry;
viso->file_fifo_pos &= (sizeof(viso->file_fifo) / sizeof(viso->file_fifo[0])) - 1;
} else {
cdrom_image_viso_log(" => failed\n");
image_viso_log(viso->tf.log, "Failed\n");
/* Clear any existing FIFO entry. */
viso->file_fifo[viso->file_fifo_pos] = NULL;
@@ -753,12 +758,12 @@ viso_close(void *priv)
if (viso == NULL)
return;
cdrom_image_viso_log("VISO: close()\n");
image_viso_log(viso->tf.log, "close()\n");
/* De-allocate everything. */
if (tf->fp)
fclose(tf->fp);
#ifndef ENABLE_CDROM_IMAGE_VISO_LOG
#ifndef ENABLE_IMAGE_VISO_LOG
remove(nvr_path(viso->tf.fn));
#endif
@@ -777,21 +782,31 @@ viso_close(void *priv)
if (viso->entry_map)
free(viso->entry_map);
if (tf->log != NULL)
log_close(tf->log);
free(viso);
}
track_file_t *
viso_init(const char *dirname, int *error)
viso_init(const uint8_t id, const char *dirname, int *error)
{
cdrom_image_viso_log("VISO: init()\n");
/* Initialize our data structure. */
viso_t *viso = (viso_t *) calloc(1, sizeof(viso_t));
uint8_t *data = NULL;
uint8_t *p;
*error = 1;
if (viso == NULL)
goto end;
char n[1024] = { 0 };
sprintf(n, "CD-ROM %i VISO ", id + 1);
viso->tf.log = log_open(n);
image_viso_log(viso->tf.log, "init()\n");
viso->sector_size = VISO_SECTOR_SIZE;
viso->format = VISO_FORMAT_ISO | VISO_FORMAT_JOLIET | VISO_FORMAT_RR;
viso->use_version_suffix = (viso->format & VISO_FORMAT_ISO); /* cleared later if required */
@@ -802,7 +817,7 @@ viso_init(const char *dirname, int *error)
goto end;
/* Open temporary file. */
#ifdef ENABLE_CDROM_IMAGE_VISO_LOG
#ifdef ENABLE_IMAGE_VISO_LOG
strcpy(viso->tf.fn, "viso-debug.iso");
#else
plat_tempfile(viso->tf.fn, "viso", ".tmp");
@@ -812,7 +827,7 @@ viso_init(const char *dirname, int *error)
goto end;
/* Set up directory traversal. */
cdrom_image_viso_log("VISO: Traversing directories:\n");
image_viso_log(viso->tf.log, "Traversing directories:\n");
viso_entry_t *entry;
viso_entry_t *last_entry;
viso_entry_t *dir;
@@ -839,7 +854,7 @@ viso_init(const char *dirname, int *error)
if (!S_ISDIR(dir->stats.st_mode)) /* root is not a directory */
goto end;
dir->parent = dir; /* for the root's path table and .. entries */
cdrom_image_viso_log("[%08X] %s => [root]\n", dir, dir->path);
image_viso_log(viso->tf.log, "[%08X] %s => [root]\n", dir, dir->path);
/* Traverse directories, starting with the root. */
viso_entry_t **dir_entries = NULL;
@@ -889,7 +904,8 @@ viso_init(const char *dirname, int *error)
/* Set basename. */
strcpy(entry->name_short, children_count ? ".." : ".");
cdrom_image_viso_log("[%08X] %s => %s\n", entry, dir->path, entry->name_short);
image_viso_log(viso->tf.log, "[%08X] %s => %s\n", entry,
dir->path, entry->name_short);
}
/* Iterate through this directory's children again, making the entries. */
@@ -897,12 +913,16 @@ viso_init(const char *dirname, int *error)
rewinddir(dirp);
while ((readdir_entry = readdir(dirp))) {
/* Ignore . and .. pseudo-directories. */
if ((readdir_entry->d_name[0] == '.') && ((readdir_entry->d_name[1] == '\0') || (*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
if ((readdir_entry->d_name[0] == '.') &&
((readdir_entry->d_name[1] == '\0') ||
(*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
continue;
/* Add and fill entry. */
entry = dir_entries[children_count++] = (viso_entry_t *) calloc(1, sizeof(viso_entry_t) + dir_path_len + strlen(readdir_entry->d_name) + 2);
if (!entry)
entry = dir_entries[children_count++] =
(viso_entry_t *) calloc(1, sizeof(viso_entry_t) +
dir_path_len + strlen(readdir_entry->d_name) + 2);
if (entry == NULL)
break;
entry->parent = dir;
strcpy(entry->path, dir->path);
@@ -972,10 +992,12 @@ have_eltorito_entry:
continue;
}
cdrom_image_viso_log("[%08X] %s => [%-12s] %s\n", entry, dir->path, entry->name_short, entry->basename);
image_viso_log(viso->tf.log, "[%08X] %s => [%-12s] %s\n", entry,
dir->path, entry->name_short, entry->basename);
}
} else {
cdrom_image_viso_log("VISO: Failed to enumerate [%s], will be empty\n", dir->path);
image_viso_log(viso->tf.log, "Failed to enumerate [%s], will be empty\n",
dir->path);
}
/* Add terminator. */
@@ -1129,13 +1151,17 @@ next_dir:
/* Write El Torito boot descriptor. This is an awkward spot for
that, but the spec requires it to be the second descriptor. */
if (!i && eltorito_entry) {
cdrom_image_viso_log("VISO: Writing El Torito boot descriptor for entry [%08X]\n", eltorito_entry);
image_viso_log(viso->tf.log, "Writing El Torito boot descriptor for "
"entry [%08X]\n", eltorito_entry);
p = data;
if (!(viso->format & VISO_FORMAT_ISO))
VISO_LBE_32(p, ftello64(viso->tf.fp) / viso->sector_size); /* sector offset (HSF only) */
*p++ = 0; /* type */
memcpy(p, (viso->format & VISO_FORMAT_ISO) ? "CD001" : "CDROM", 5); /* standard ID */
/* Sector offset (HSF only). */
VISO_LBE_32(p, ftello64(viso->tf.fp) / viso->sector_size);
/* Type. */
*p++ = 0;
/* Standard ID. */
memcpy(p, (viso->format & VISO_FORMAT_ISO) ? "CD001" : "CDROM", 5);
p += 5;
*p++ = 1; /* version */
@@ -1236,7 +1262,7 @@ next_dir:
/* Write each path table. */
for (int i = 0; i <= ((max_vd << 1) | 1); i++) {
cdrom_image_viso_log("VISO: Generating path table #%d:\n", i);
image_viso_log(viso->tf.log, "Generating path table #%d:\n", i);
/* Save this path table's start offset. */
uint64_t pt_start = ftello64(viso->tf.fp);
@@ -1257,7 +1283,9 @@ next_dir:
continue;
}
cdrom_image_viso_log("[%08X] %s => %s\n", dir, dir->path, ((i & 2) || (dir == viso->root_dir)) ? dir->basename : dir->name_short);
image_viso_log(viso->tf.log, "[%08X] %s => %s\n", dir,
dir->path, ((i & 2) || (dir == viso->root_dir)) ? dir->basename :
dir->name_short);
/* Save this directory's path table index and offset. */
dir->pt_idx = pt_idx;
@@ -1325,7 +1353,7 @@ next_dir:
/* Write directory records for each type. */
int dir_type = VISO_DIR_CURRENT_ROOT;
for (int i = 0; i <= max_vd; i++) {
cdrom_image_viso_log("VISO: Generating directory record set #%d:\n", i);
image_viso_log(viso->tf.log, "Generating directory record set #%d:\n", i);
/* Go through directories. */
dir = viso->root_dir;
@@ -1368,8 +1396,10 @@ next_dir:
if ((entry == eltorito_entry) || (entry == eltorito_dir))
goto next_entry;
cdrom_image_viso_log("[%08X] %s => %s\n", entry, dir->path,
((dir_type == VISO_DIR_PARENT) ? ".." : ((dir_type < VISO_DIR_PARENT) ? "." : (i ? entry->basename : entry->name_short))));
image_viso_log(viso->tf.log, "[%08X] %s => %s\n", entry, dir->path,
((dir_type == VISO_DIR_PARENT) ? ".." :
((dir_type < VISO_DIR_PARENT) ? "." :
(i ? entry->basename : entry->name_short))));
/* Fill directory record. */
viso_fill_dir_record(data, entry, viso, dir_type);
@@ -1436,7 +1466,8 @@ next_entry:
/* Allocate entry map for sector->file lookups. */
size_t orig_sector_size = viso->sector_size;
while (1) {
cdrom_image_viso_log("VISO: Allocating entry map for %zu %zu-byte sectors\n", viso->entry_map_size, viso->sector_size);
image_viso_log(viso->tf.log, "Allocating entry map for %zu %zu-byte sectors\n",
viso->entry_map_size, viso->sector_size);
viso->entry_map = (viso_entry_t **) calloc(viso->entry_map_size, sizeof(viso_entry_t *));
if (viso->entry_map) {
/* Successfully allocated. */
@@ -1477,7 +1508,7 @@ next_entry:
viso->all_sectors = viso->metadata_sectors;
/* Go through files, assigning sectors to them. */
cdrom_image_viso_log("VISO: Assigning sectors to files:\n");
image_viso_log(viso->tf.log, "Assigning sectors to files:\n");
size_t base_factor = viso->sector_size / orig_sector_size;
viso_entry_t *prev_entry = viso->root_dir;
viso_entry_t **entry_map_p = viso->entry_map;
@@ -1522,7 +1553,8 @@ next_entry:
size_t size = entry->stats.st_size / viso->sector_size;
if (entry->stats.st_size % viso->sector_size)
size++; /* round up to the next sector */
cdrom_image_viso_log("[%08X] %s => %zu + %zu sectors\n", entry, entry->path, viso->all_sectors, size);
image_viso_log(viso->tf.log, "[%08X] %s => %zu + %zu sectors\n", entry,
entry->path, viso->all_sectors, size);
/* Allocate sectors to this file. */
viso->all_sectors += size;
@@ -1541,9 +1573,10 @@ next_entry:
viso_pwrite(data, viso->vol_size_offsets[i], 8, 1, viso->tf.fp);
/* Metadata processing is finished, read it back to memory. */
cdrom_image_viso_log("VISO: Reading back %zu %zu-byte sectors of metadata\n", viso->metadata_sectors, viso->sector_size);
image_viso_log(viso->tf.log, "Reading back %zu %zu-byte sectors of metadata\n",
viso->metadata_sectors, viso->sector_size);
viso->metadata = (uint8_t *) calloc(viso->metadata_sectors, viso->sector_size);
if (!viso->metadata)
if (viso->metadata == NULL)
goto end;
fseeko64(viso->tf.fp, 0, SEEK_SET);
size_t metadata_size = viso->metadata_sectors * viso->sector_size;
@@ -1554,7 +1587,7 @@ next_entry:
/* We no longer need the temporary file; close and delete it. */
fclose(viso->tf.fp);
viso->tf.fp = NULL;
#ifndef ENABLE_CDROM_IMAGE_VISO_LOG
#ifndef ENABLE_IMAGE_VISO_LOG
remove(nvr_path(viso->tf.fn));
#endif
@@ -1565,16 +1598,20 @@ end:
/* Set the function pointers. */
viso->tf.priv = viso;
if (!*error) {
cdrom_image_viso_log("VISO: Initialized\n");
image_viso_log(viso->tf.log, "Initialized\n");
viso->tf.read = viso_read;
viso->tf.get_length = viso_get_length;
viso->tf.close = viso_close;
return &viso->tf;
} else {
cdrom_image_viso_log("VISO: Initialization failed\n");
if (data)
free(data);
viso_close(&viso->tf);
if (viso != NULL) {
image_viso_log(viso->tf.log, "Initialization failed\n");
if (data)
free(data);
viso_close(&viso->tf);
}
return NULL;
}
}

267
src/cdrom/cdrom_ioctl.c
View File

@@ -1,267 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* CD-ROM passthrough support.
*
*
*
* Authors: TheCollector1995, <mariogplayer@gmail.com>,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2023 TheCollector1995.
* Copyright 2023 Miran Grca.
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/scsi_device.h>
#include <86box/cdrom.h>
#include <86box/plat_cdrom.h>
#ifdef ENABLE_CDROM_IOCTL_LOG
int cdrom_ioctl_do_log = ENABLE_CDROM_IOCTL_LOG;
void
cdrom_ioctl_log(const char *fmt, ...)
{
va_list ap;
if (cdrom_ioctl_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define cdrom_ioctl_log(fmt, ...)
#endif
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
static void
ioctl_get_track_info(cdrom_t *dev, uint32_t track, int end, track_info_t *ti)
{
TMSF tmsf;
plat_cdrom_get_audio_track_info(dev->local, end, track, &ti->number, &tmsf, &ti->attr);
ti->m = tmsf.min;
ti->s = tmsf.sec;
ti->f = tmsf.fr;
}
static void
ioctl_get_raw_track_info(cdrom_t *dev, int *num, raw_track_info_t *rti)
{
plat_cdrom_get_raw_track_info(dev->local, num, rti);
}
static void
ioctl_get_subchannel(cdrom_t *dev, uint32_t lba, subchannel_t *subc)
{
TMSF rel_pos;
TMSF abs_pos;
if ((dev->cd_status == CD_STATUS_PLAYING) || (dev->cd_status == CD_STATUS_PAUSED)) {
const uint32_t trk = plat_cdrom_get_track_start(dev->local, lba, &subc->attr, &subc->track);
FRAMES_TO_MSF(lba + 150, &abs_pos.min, &abs_pos.sec, &abs_pos.fr);
/* Absolute position should be adjusted by 150, not the relative ones. */
FRAMES_TO_MSF(lba - trk, &rel_pos.min, &rel_pos.sec, &rel_pos.fr);
subc->index = 1;
} else
plat_cdrom_get_audio_sub(dev->local, lba, &subc->attr, &subc->track, &subc->index,
&rel_pos, &abs_pos);
subc->abs_m = abs_pos.min;
subc->abs_s = abs_pos.sec;
subc->abs_f = abs_pos.fr;
subc->rel_m = rel_pos.min;
subc->rel_s = rel_pos.sec;
subc->rel_f = rel_pos.fr;
cdrom_ioctl_log("ioctl_get_subchannel(): %02X, %02X, %02i, %02i:%02i:%02i, %02i:%02i:%02i\n",
subc->attr, subc->track, subc->index, subc->abs_m, subc->abs_s, subc->abs_f,
subc->rel_m, subc->rel_s, subc->rel_f);
}
static int
ioctl_get_capacity(cdrom_t *dev)
{
int ret;
ret = plat_cdrom_get_last_block(dev->local);
cdrom_ioctl_log("GetCapacity=%x.\n", ret);
return ret;
}
static int
ioctl_is_track_audio(cdrom_t *dev, uint32_t pos, int ismsf)
{
int m;
int s;
int f;
if (dev->cd_status == CD_STATUS_DATA_ONLY)
return 0;
if (ismsf) {
m = (pos >> 16) & 0xff;
s = (pos >> 8) & 0xff;
f = pos & 0xff;
pos = MSFtoLBA(m, s, f) - 150;
}
/* GetTrack requires LBA. */
return plat_cdrom_is_track_audio(dev->local, pos);
}
static int
ioctl_is_track_pre(cdrom_t *dev, uint32_t lba)
{
return plat_cdrom_is_track_pre(dev->local, lba);
}
static int
ioctl_sector_size(cdrom_t *dev, uint32_t lba)
{
cdrom_ioctl_log("LBA=%x.\n", lba);
return plat_cdrom_get_sector_size(dev->local, lba);
}
static int
ioctl_read_sector(cdrom_t *dev, uint8_t *b, uint32_t lba)
{
cdrom_ioctl_log("cdrom_ioctl_read_sector(): Raw.\n");
return plat_cdrom_read_sector(dev->local, b, lba);
}
static int
ioctl_track_type(cdrom_t *dev, uint32_t lba)
{
int ret = CD_TRACK_UNK_DATA;
if (ioctl_is_track_audio(dev, lba, 0))
ret = CD_TRACK_AUDIO;
cdrom_ioctl_log("cdrom_ioctl_track_type(): %i\n", ret);
return ret;
}
static int
ioctl_ext_medium_changed(cdrom_t *dev)
{
int ret;
if ((dev->cd_status == CD_STATUS_PLAYING) || (dev->cd_status == CD_STATUS_PAUSED))
ret = 0;
else
ret = plat_cdrom_ext_medium_changed(dev->local);
if (ret == 1) {
dev->cd_status = CD_STATUS_STOPPED;
dev->cdrom_capacity = ioctl_get_capacity(dev);
} else if (ret == -1)
dev->cd_status = CD_STATUS_EMPTY;
return ret;
}
static void
ioctl_exit(cdrom_t *dev)
{
cdrom_ioctl_log("CDROM: ioctl_exit(%s)\n", dev->image_path);
dev->cd_status = CD_STATUS_EMPTY;
plat_cdrom_close(dev->local);
dev->local = NULL;
dev->ops = NULL;
}
static const cdrom_ops_t cdrom_ioctl_ops = {
ioctl_get_track_info,
ioctl_get_raw_track_info,
ioctl_get_subchannel,
ioctl_is_track_pre,
ioctl_sector_size,
ioctl_read_sector,
ioctl_track_type,
ioctl_ext_medium_changed,
ioctl_exit
};
static int
cdrom_ioctl_open_abort(cdrom_t *dev)
{
cdrom_ioctl_close(dev);
dev->ops = NULL;
dev->image_path[0] = 0;
return 1;
}
int
cdrom_ioctl_open(cdrom_t *dev, const char *drv)
{
const char *actual_drv = &(drv[8]);
int local_size = plat_cdrom_get_local_size();
/* Make sure to not STRCPY if the two are pointing
at the same place. */
if (drv != dev->image_path)
strcpy(dev->image_path, drv);
/* Open the image. */
if (strstr(drv, "ioctl://") != drv)
return cdrom_ioctl_open_abort(dev);
cdrom_ioctl_log("actual_drv = %s\n", actual_drv);
if (dev->local == NULL)
dev->local = calloc(1, local_size);
int i = plat_cdrom_set_drive(dev->local, actual_drv);
if (!i)
return cdrom_ioctl_open_abort(dev);
/* All good, reset state. */
dev->cd_status = CD_STATUS_STOPPED;
dev->seek_pos = 0;
dev->cd_buflen = 0;
dev->cdrom_capacity = ioctl_get_capacity(dev);
cdrom_ioctl_log("CD-ROM capacity: %i sectors (%" PRIi64 " bytes)\n",
dev->cdrom_capacity, ((uint64_t) dev->cdrom_capacity) << 11ULL);
/* Attach this handler to the drive. */
dev->ops = &cdrom_ioctl_ops;
return 0;
}
void
cdrom_ioctl_close(cdrom_t *dev)
{
cdrom_ioctl_log("CDROM: ioctl_close(%s)\n", dev->image_path);
if (dev && dev->ops && dev->ops->exit)
dev->ops->exit(dev);
}

61
src/cdrom/cdrom_mitsumi.c
View File

@@ -118,14 +118,6 @@ typedef struct mcd_t {
int newstat;
} mcd_t;
/* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
of the audio while audio still plays. With an absolute conversion, the counter is fine. */
#ifdef MSFtoLBA
#undef MSFtoLBA
#endif
#define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)
#define CD_BCD(x) (((x) % 10) | (((x) / 10) << 4))
#define CD_DCB(x) ((((x) &0xf0) >> 4) * 10 + ((x) &0x0f))
@@ -156,9 +148,9 @@ mitsumi_cdrom_is_ready(const cdrom_t *dev)
static void
mitsumi_cdrom_reset(mcd_t *dev)
{
cdrom_t cdrom;
dev->stat = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | STAT_CHANGE) : 0;
cdrom_t *cdrom = calloc(1, sizeof(cdrom_t));
dev->stat = mitsumi_cdrom_is_ready(cdrom) ? (STAT_READY | STAT_CHANGE) : 0;
dev->cmdrd_count = 0;
dev->cmdbuf_count = 0;
dev->buf_count = 0;
@@ -176,12 +168,12 @@ mitsumi_cdrom_reset(mcd_t *dev)
static int
mitsumi_cdrom_read_sector(mcd_t *dev, int first)
{
cdrom_t cdrom;
cdrom_t *cdrom = calloc(1, sizeof(cdrom_t));
uint8_t status;
int ret;
int ret = 0;
if (dev->drvmode == DRV_MODE_CDDA) {
status = cdrom_mitsumi_audio_play(&cdrom, dev->readmsf, dev->readcount);
status = cdrom_mitsumi_audio_play(cdrom, dev->readmsf, dev->readcount);
if (status == 1)
return status;
else
@@ -195,15 +187,15 @@ mitsumi_cdrom_read_sector(mcd_t *dev, int first)
dev->data = 0;
return 0;
}
cdrom_stop(&cdrom);
ret = cdrom_readsector_raw(&cdrom, dev->buf, cdrom.seek_pos, 0, 2, 0x10, (int *) &dev->readcount, 0);
cdrom_stop(cdrom);
ret = cdrom_readsector_raw(cdrom, dev->buf, cdrom->seek_pos, 0, 2, 0x10, (int *) &dev->readcount, 0);
if (ret <= 0)
return 0;
if (dev->mode & 0x40) {
dev->buf[12] = CD_BCD((dev->readmsf >> 16) & 0xff);
dev->buf[13] = CD_BCD((dev->readmsf >> 8) & 0xff);
}
dev->readmsf = cdrom_lba_to_msf_accurate(cdrom.seek_pos + 1);
dev->readmsf = cdrom_lba_to_msf_accurate(cdrom->seek_pos + 1);
dev->buf_count = dev->dmalen + 1;
dev->buf_idx = 0;
dev->data = 1;
@@ -224,7 +216,7 @@ static uint8_t
mitsumi_cdrom_in(uint16_t port, void *priv)
{
mcd_t *dev = (mcd_t *) priv;
uint8_t ret;
uint8_t ret = 0xff;
pclog("Mitsumi CD-ROM IN=%03x\n", port);
switch (port & 1) {
@@ -259,14 +251,14 @@ mitsumi_cdrom_in(uint16_t port, void *priv)
break;
}
return 0xff;
return ret;
}
static void
mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
{
mcd_t *dev = (mcd_t *) priv;
cdrom_t cdrom;
cdrom_t *cdrom = calloc(1, sizeof(cdrom_t));
pclog("Mitsumi CD-ROM OUT=%03x, val=%02x\n", port, val);
switch (port & 1) {
@@ -348,19 +340,19 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
break;
}
if (!dev->cmdrd_count)
dev->stat = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
dev->stat = mitsumi_cdrom_is_ready(cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
return;
}
dev->cmd = val;
dev->cmdbuf_idx = 0;
dev->cmdrd_count = 0;
dev->cmdbuf_count = 1;
dev->cmdbuf[0] = mitsumi_cdrom_is_ready(&cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
dev->cmdbuf[0] = mitsumi_cdrom_is_ready(cdrom) ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
dev->data = 0;
switch (val) {
case CMD_GET_INFO:
if (mitsumi_cdrom_is_ready(&cdrom)) {
cdrom_get_track_buffer(&cdrom, &(dev->cmdbuf[1]));
if (mitsumi_cdrom_is_ready(cdrom)) {
cdrom_get_track_buffer(cdrom, &(dev->cmdbuf[1]));
dev->cmdbuf_count = 10;
dev->readcount = 0;
} else {
@@ -369,8 +361,8 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
}
break;
case CMD_GET_Q:
if (mitsumi_cdrom_is_ready(&cdrom)) {
cdrom_get_q(&cdrom, &(dev->cmdbuf[1]), &dev->cur_toc_track, dev->mode & MODE_GET_TOC);
if (mitsumi_cdrom_is_ready(cdrom)) {
cdrom_get_q(cdrom, &(dev->cmdbuf[1]), &dev->cur_toc_track, dev->mode & MODE_GET_TOC);
dev->cmdbuf_count = 11;
dev->readcount = 0;
} else {
@@ -386,7 +378,7 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
break;
case CMD_STOPCDDA:
case CMD_STOP:
cdrom_stop(&cdrom);
cdrom_stop(cdrom);
dev->drvmode = DRV_MODE_STOP;
dev->cur_toc_track = 0;
break;
@@ -395,7 +387,7 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
break;
case CMD_READ1X:
case CMD_READ2X:
if (mitsumi_cdrom_is_ready(&cdrom)) {
if (mitsumi_cdrom_is_ready(cdrom)) {
dev->readcount = 0;
dev->drvmode = (val == CMD_READ1X) ? DRV_MODE_CDDA : DRV_MODE_READ;
dev->cmdrd_count = 6;
@@ -411,7 +403,7 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
dev->cmdbuf_count = 3;
break;
case CMD_EJECT:
cdrom_stop(&cdrom);
cdrom_stop(cdrom);
cdrom_eject(0);
dev->readcount = 0;
break;
@@ -440,10 +432,7 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
static void *
mitsumi_cdrom_init(UNUSED(const device_t *info))
{
mcd_t *dev;
dev = malloc(sizeof(mcd_t));
memset(dev, 0x00, sizeof(mcd_t));
mcd_t *dev = calloc(1, sizeof(mcd_t));
dev->irq = MCD_DEFAULT_IRQ;
dev->dma = MCD_DEFAULT_DMA;
@@ -470,12 +459,12 @@ mitsumi_cdrom_close(void *priv)
const device_t mitsumi_cdrom_device = {
.name = "Mitsumi CD-ROM interface",
.internal_name = "mcd",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 1,
.flags = DEVICE_ISA16,
.local = 0,
.init = mitsumi_cdrom_init,
.close = mitsumi_cdrom_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/82c100.c
View File

@@ -358,8 +358,7 @@ ct_82c100_init(UNUSED(const device_t *info))
{
ct_82c100_t *dev;
dev = (ct_82c100_t *) malloc(sizeof(ct_82c100_t));
memset(dev, 0x00, sizeof(ct_82c100_t));
dev = (ct_82c100_t *) calloc(1, sizeof(ct_82c100_t));
ct_82c100_reset(dev);
@@ -393,7 +392,7 @@ const device_t ct_82c100_device = {
.init = ct_82c100_init,
.close = ct_82c100_close,
.reset = ct_82c100_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

10
src/chipset/CMakeLists.txt
View File

@@ -17,7 +17,9 @@
add_library(chipset OBJECT
82c100.c
acc2036.c
acc2168.c
cs8220.c
cs8230.c
ali1429.c
ali1435.c
@@ -39,12 +41,15 @@ add_library(chipset OBJECT
intel_i450kx.c
intel_sio.c
intel_piix.c
isa486c.c
../ioapic.c
neat.c
olivetti_eva.c
opti283.c
opti291.c
opti391.c
opti495.c
opti498.c
opti499.c
opti602.c
opti822.c
@@ -71,6 +76,7 @@ add_library(chipset OBJECT
sis_5572_usb.c
sis_5595_pmu.c
sis_55xx.c
sl82c461.c
via_vt82c49x.c
via_vt82c505.c
gc100.c
@@ -83,7 +89,3 @@ add_library(chipset OBJECT
vl82c480.c
wd76c10.c
)
if(OLIVETTI)
target_sources(chipset PRIVATE olivetti_eva.c)
endif()

346
src/chipset/acc2036.c Normal file
View File

@@ -0,0 +1,346 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the ACC 2036 chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2025 Miran Grca.
*/
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/port_92.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
typedef struct {
uint32_t virt;
uint32_t phys;
mem_mapping_t mapping;
} ram_page_t;
typedef struct {
uint8_t reg;
uint8_t regs[32];
ram_page_t ram_mid_pages[24];
ram_page_t ems_pages[4];
} acc2036_t;
static uint8_t
acc2036_mem_read(uint32_t addr, void *priv)
{
ram_page_t *dev = (ram_page_t *) priv;
uint8_t ret = 0xff;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ret = ram[addr];
return ret;
}
static uint16_t
acc2036_mem_readw(uint32_t addr, void *priv)
{
ram_page_t *dev = (ram_page_t *) priv;
uint16_t ret = 0xffff;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ret = *(uint16_t *) &(ram[addr]);
return ret;
}
static void
acc2036_mem_write(uint32_t addr, uint8_t val, void *priv)
{
ram_page_t *dev = (ram_page_t *) priv;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ram[addr] = val;
}
static void
acc2036_mem_writew(uint32_t addr, uint16_t val, void *priv)
{
ram_page_t *dev = (ram_page_t *) priv;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
*(uint16_t *) &(ram[addr]) = val;
}
static void
acc2036_recalc(acc2036_t *dev)
{
uint32_t ems_bases[4] = { 0x000c0000, 0x000c8000, 0x000d0000, 0x000e0000 };
int start_i = (ems_bases[dev->regs[0x0c] & 0x03] - 0x000a0000) >> 14;
int end_i = start_i + 3;
for (int i = 0; i < 24; i++) {
ram_page_t *rp = &dev->ram_mid_pages[i];
mem_mapping_disable(&rp->mapping);
}
for (int i = 0; i < 4; i++) {
ram_page_t *ep = &dev->ems_pages[i];
mem_mapping_disable(&ep->mapping);
}
for (int i = 0; i < 24; i++) {
ram_page_t *rp = &dev->ram_mid_pages[i];
if ((dev->regs[0x03] & 0x08) && (i >= start_i) && (i <= end_i)) {
/* EMS */
ram_page_t *ep = &dev->ems_pages[i - start_i];
mem_mapping_disable(&rp->mapping);
mem_mapping_set_addr(&ep->mapping, ep->virt, 0x000040000);
mem_mapping_set_exec(&ep->mapping, ram + ep->phys);
mem_set_mem_state_both(ep->virt, 0x00004000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else {
int master_write;
int master_read;
int bit;
int ew_flag;
int er_flag;
int flags;
uint8_t val;
mem_mapping_set_addr(&rp->mapping, rp->virt, 0x000040000);
mem_mapping_set_exec(&rp->mapping, ram + rp->phys);
if ((i >= 8) && (i <= 15)) {
/* 0C0000-0DFFFF */
master_write = dev->regs[0x02] & 0x08;
master_read = dev->regs[0x02] & 0x04;
bit = ((i - 8) >> 1);
val = dev->regs[0x0d] & (1 << bit);
if (i >= 12) {
ew_flag = (dev->regs[0x07] & 0x80) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
er_flag = (dev->regs[0x07] & 0x80) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
} else {
ew_flag = (dev->regs[0x07] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
er_flag = (dev->regs[0x07] & 0x40) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
}
flags = (val && master_write) ? MEM_WRITE_INTERNAL : ew_flag;
flags |= (val && master_read) ? MEM_READ_INTERNAL : er_flag;
mem_set_mem_state_both(rp->virt, 0x00004000, flags);
} else if (i > 15) {
/* 0E0000-0FFFFF */
master_write = dev->regs[0x02] & 0x02;
master_read = dev->regs[0x02] & 0x01;
bit = ((i - 8) >> 2);
val = dev->regs[0x0c] & (1 << bit);
if (i >= 20) {
ew_flag = MEM_WRITE_EXTANY;
er_flag = MEM_READ_EXTANY;
} else {
ew_flag = (dev->regs[0x0c] & 0x10) ? MEM_WRITE_EXTANY : MEM_WRITE_EXTERNAL;
er_flag = (dev->regs[0x0c] & 0x10) ? MEM_READ_EXTANY : MEM_READ_EXTERNAL;
}
flags = (val && master_write) ? MEM_WRITE_INTERNAL : ew_flag;
flags |= (val && master_read) ? MEM_READ_INTERNAL : er_flag;
mem_set_mem_state_both(rp->virt, 0x00004000, flags);
}
}
}
if (dev->regs[0x00] & 0x40)
mem_set_mem_state_both(0x00fe0000, 0x00010000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else
mem_set_mem_state_both(0x00fe0000, 0x00010000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
for (int i = 0x01; i <= 0x06; i++) {
uint32_t base = 0x00fe0000 - (i * 0x00010000);
if (dev->regs[i] & 0x40)
mem_set_mem_state_both(base, 0x00008000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else
mem_set_mem_state_both(base, 0x00008000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
if (dev->regs[i] & 0x80)
mem_set_mem_state_both(base + 0x00008000, 0x00008000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
else
mem_set_mem_state_both(base + 0x00008000, 0x00008000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
mem_remap_top(0);
if (dev->regs[0x03] & 0x10) {
if (dev->regs[0x02] & 0x0c)
mem_remap_top(128);
else if (dev->regs[0x02] & 0x03)
mem_remap_top(256);
else
mem_remap_top(384);
}
flushmmucache_nopc();
}
static uint8_t
acc2036_in(uint16_t port, void *priv) {
acc2036_t *dev = (acc2036_t *) priv;
uint8_t reg = dev->reg - 0x20;
uint8_t ret = 0xff;
if (port & 0x0001) switch (dev->reg) {
default:
break;
case 0x20 ... 0x2e:
case 0x31 ... 0x3f:
ret = dev->regs[reg];
break;
} else
ret = dev->reg;
return ret;
}
static void
acc2036_out(uint16_t port, uint8_t val, void *priv) {
acc2036_t *dev = (acc2036_t *) priv;
uint8_t reg = dev->reg - 0x20;
if (port & 0x0001) switch (dev->reg) {
default:
break;
case 0x20 ... 0x23:
dev->regs[reg] = val;
acc2036_recalc(dev);
break;
case 0x24 ... 0x2b:
dev->regs[reg] = val;
dev->ems_pages[(reg - 0x04) >> 1].phys = ((dev->regs[reg & 0xfe] & 0x1f) << 19) |
((dev->regs[reg | 0x01] & 0x1f) << 14);
acc2036_recalc(dev);
break;
case 0x2c: case 0x2d:
dev->regs[reg] = val;
acc2036_recalc(dev);
break;
case 0x2e:
dev->regs[reg] = val | 0x10;
break;
case 0x31:
dev->regs[reg] = val;
mem_a20_alt = (val & 0x01);
mem_a20_recalc();
flushmmucache();
if (val & 0x02) {
softresetx86(); /* Pulse reset! */
cpu_set_edx();
flushmmucache();
}
break;
case 0x32 ... 0x3f:
dev->regs[reg] = val;
break;
} else
dev->reg = val;
}
static void
acc2036_close(void *priv)
{
acc2036_t *dev = (acc2036_t *) priv;
free(dev);
}
static void *
acc2036_init(UNUSED(const device_t *info))
{
acc2036_t *dev = (acc2036_t *) calloc(1, sizeof(acc2036_t));
for (int i = 0; i < 24; i++) {
ram_page_t *rp = &dev->ram_mid_pages[i];
rp->virt = 0x000a0000 + (i << 14);
rp->phys = 0x000a0000 + (i << 14);
mem_mapping_add(&rp->mapping, rp->virt, 0x00004000,
acc2036_mem_read, acc2036_mem_readw, NULL,
acc2036_mem_write, acc2036_mem_writew, NULL,
ram + rp->phys, MEM_MAPPING_INTERNAL, rp);
}
for (int i = 0; i < 4; i++) {
ram_page_t *ep = &dev->ems_pages[i];
ep->virt = 0x000d0000 + (i << 14);
ep->phys = 0x00000000 + (i << 14);
mem_mapping_add(&ep->mapping, ep->virt, 0x00004000,
acc2036_mem_read, acc2036_mem_readw, NULL,
acc2036_mem_write, acc2036_mem_writew, NULL,
ram + ep->phys, MEM_MAPPING_INTERNAL, ep);
mem_mapping_disable(&ep->mapping);
}
mem_mapping_disable(&ram_mid_mapping);
dev->regs[0x00] = 0x02;
dev->regs[0x0e] = 0x10;
dev->regs[0x11] = 0x01;
dev->regs[0x13] = 0x40;
dev->regs[0x15] = 0x40;
dev->regs[0x17] = 0x40;
dev->regs[0x19] = 0x40;
dev->regs[0x1b] = 0x40;
dev->regs[0x1c] = 0x22;
dev->regs[0x1d] = 0xc4;
dev->regs[0x1f] = 0x30;
acc2036_recalc(dev);
mem_a20_alt = 0x01;
mem_a20_recalc();
flushmmucache();
io_sethandler(0x00f2, 0x0002,
acc2036_in, NULL, NULL, acc2036_out, NULL, NULL, dev);
device_add(&port_92_device);
return dev;
}
const device_t acc2036_device = {
.name = "ACC 2036",
.internal_name = "acc2036",
.flags = 0,
.local = 0,
.init = acc2036_init,
.close = acc2036_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

5
src/chipset/acc2168.c
View File

@@ -184,8 +184,7 @@ acc2168_close(void *priv)
static void *
acc2168_init(UNUSED(const device_t *info))
{
acc2168_t *dev = (acc2168_t *) malloc(sizeof(acc2168_t));
memset(dev, 0, sizeof(acc2168_t));
acc2168_t *dev = (acc2168_t *) calloc(1, sizeof(acc2168_t));
device_add(&port_92_device);
io_sethandler(0x00f2, 0x0002, acc2168_read, NULL, NULL, acc2168_write, NULL, NULL, dev);
@@ -201,7 +200,7 @@ const device_t acc2168_device = {
.init = acc2168_init,
.close = acc2168_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

282
src/chipset/ali1409.c
View File

@@ -40,9 +40,8 @@
#include <86box/fdc.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_ALI1409_LOG
int ali1409_do_log = ENABLE_ALI1409_LOG;
@@ -62,91 +61,238 @@ ali1409_log(const char *fmt, ...)
#endif
typedef struct ali_1409_t {
uint8_t is_g;
uint8_t index;
uint8_t cfg_locked;
uint8_t reg_57h;
uint8_t regs[256];
uint8_t shadow[4];
uint8_t last_reg;
} ali1409_t;
/*
This here is because from the two BIOS'es I used to reverse engineer this,
it is unclear which of the two interpretations of the shadow RAM register
operation is correct.
The 16 kB interpretation appears to work fine right now but it may be wrong,
so I left the 32 kB interpretation in as well.
*/
#ifdef INTERPRETATION_32KB
#define SHADOW_SIZE 0x00008000
#else
#define SHADOW_SIZE 0x00004000
#endif
static void
ali1409_shadow_recalc(ali1409_t *dev)
{
uint32_t base = 0x000c0000;
for (uint8_t i = 0; i < 4; i++) {
uint8_t reg = 0x08 + i;
#ifdef INTERPRETATION_32KB
for (uint8_t j = 0; j < 4; j += 2) {
uint8_t mask = (0x03 << j);
#else
for (uint8_t j = 0; j < 4; j++) {
uint8_t mask = (0x01 << j);
#endif
uint8_t r_on = dev->regs[reg] & 0x10;
uint8_t w_on = dev->regs[reg] & 0x20;
uint8_t val = dev->regs[reg] & mask;
uint8_t xor = (dev->shadow[i] ^ dev->regs[reg]) & (mask | 0x30);
int read = r_on ? MEM_READ_INTERNAL : MEM_READ_EXTANY;
int write = w_on ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;
if (xor) {
#ifdef INTERPRETATION_32KB
switch (val >> j) {
case 0x00:
mem_set_mem_state_both(base, SHADOW_SIZE, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x01:
mem_set_mem_state_both(base, SHADOW_SIZE, MEM_READ_EXTANY | write);
break;
case 0x02:
mem_set_mem_state_both(base, SHADOW_SIZE, read | write);
break;
case 0x03:
mem_set_mem_state_both(base, SHADOW_SIZE, read | MEM_WRITE_EXTANY);
break;
}
#else
switch (val >> j) {
case 0x00:
mem_set_mem_state_both(base, SHADOW_SIZE, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 0x01:
mem_set_mem_state_both(base, SHADOW_SIZE, read | write);
break;
}
#endif
}
base += SHADOW_SIZE;
}
dev->shadow[i] = dev->regs[reg];
}
flushmmucache_nopc();
}
static void
ali1409_write(uint16_t addr, uint8_t val, void *priv)
{
ali1409_t *dev = (ali1409_t *) priv;
ali1409_log ("INPUT:addr %02x ,Value %02x \n" , addr , val);
ali1409_log("[%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, addr, val);
if (addr & 1) {
if (dev->cfg_locked) {
if (dev->last_reg == 0x14 && val == 0x09)
dev->cfg_locked = 0;
if (addr & 0x0001) {
if (dev->cfg_locked) {
if ((dev->last_reg == 0x14) && (val == 0x09))
dev->cfg_locked = 0;
dev->last_reg = val;
return;
}
dev->last_reg = val;
return;
}
if (dev->index == 0xff && val == 0xff)
dev->cfg_locked = 1;
else {
ali1409_log("Write reg %02x %02x %08x\n", dev->index, val, cs);
dev->regs[dev->index] = val;
/* It appears writing anything at all to register 0xFF locks it again. */
if (dev->index == 0xff)
dev->cfg_locked = 1;
else if (dev->index < 0x44) {
ali1409_log("[%04X:%08X] [W] Register %02X = %02X\n", CS, cpu_state.pc, dev->index, val);
switch (dev->index) {
case 0xa:
switch ((val >> 4) & 3) {
case 0:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
break;
case 1:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
break;
case 2:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xe0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
if (dev->index < 0x10) {
dev->regs[dev->index] = val;
/*
There are still a lot of unknown here, but unfortunately, this is
as far as I have been able to come with two BIOS'es that are
available (the Acer 100T and an AMI Color dated 07/07/91).
*/
switch (dev->index) {
case 0x02:
/*
- Bit 7: The RAS address hold time:
- 0: 1/2 T;
- 1: 1 T.
- Bits 6-4: The RAS precharge time:
- 0, 0, 0: 1.5 T;
- 0, 0, 1: 2 T;
- 0, 1, 0: 2.5 T;
- 0, 1, 1: 3 T;
- 1, 0, 0: 3.5 T;
- 1, 0, 1: 4 T;
- 1, 1, 0: Reserved;
- 1, 1, 1: Reserved.
- Bit 3: Early miss cycle:
- 0: Disabled;
- 1: Enabled.
*/
break;
case 0x03:
/*
- Bit 6: CAS pulse for read cycle:
- 0: 1 T;
- 1: 1.5 T or 2 T.
I can not get the 2.5 T or 3 T setting to apply so
I have no idea what bit governs that.
- Bits 5, 4: CAS pulse for write cycle:
- 0, 0: 0.5 T or 1 T;
- 0, 1: 1.5 T or 2 T;
- 1, 0: 2.5 T or 3 T;
- 1, 1: Reserved.
- Bit 3: CAS active for read cycle:
- 0: Disabled;
- 1: Enabled.
- Bit 2: CAS active for write cycle:
- 0: Disabled;
- 1: Enabled.
*/
break;
case 0x06:
/*
- Bits 6-4: Clock divider:
- 0, 0, 0: / 2;
- 0, 0, 1: / 4;
- 0, 1, 0: / 8;
- 0, 1, 1: Reserved;
- 1, 0, 0: / 3;
- 1, 0, 1: / 6;
- 1, 1, 0: / 5;
- 1, 1, 1: / 10.
*/
switch ((val >> 4) & 7) {
default:
case 3: /* Reserved */
cpu_set_isa_speed(7159091);
break;
case 0xb:
switch ((val >> 4) & 3) {
case 0:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_EXTANY| MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
case 0:
cpu_set_isa_speed(cpu_busspeed / 2);
break;
case 1:
cpu_set_isa_speed(cpu_busspeed / 4);
break;
case 2:
cpu_set_isa_speed(cpu_busspeed / 8);
break;
case 4:
cpu_set_isa_speed(cpu_busspeed / 3);
break;
case 5:
cpu_set_isa_speed(cpu_busspeed / 6);
break;
case 6:
cpu_set_isa_speed(cpu_busspeed / 5);
break;
case 7:
cpu_set_isa_speed(cpu_busspeed / 10);
break;
}
break;
case 0x08 ... 0x0b:
ali1409_shadow_recalc(dev);
break;
case 0x0c:
/*
This appears to be turbo in bit 4 (1 = on, 0 = off),
and bus speed in the rest of the bits.
*/
break;
case 0x0d:
cpu_cache_ext_enabled = !!(val & 0x08);
cpu_update_waitstates();
break;
}
} else
dev->index = val;
}
}
} else
dev->index = val;
}
static uint8_t
ali1409_read(uint16_t addr, void *priv)
{
ali1409_log ("reading at %02X\n",addr);
const ali1409_t *dev = (ali1409_t *) priv;
uint8_t ret = 0xff;
if (dev->cfg_locked)
ret = 0xff;
if (addr & 1) {
if ((dev->index >= 0xc0 || dev->index == 0x20) && cpu_iscyrix)
ret = 0xff;
else if (addr & 0x0001) {
if (dev->index < 0x44)
ret = dev->regs[dev->index];
} else
ret = dev->index;
} else
ret = dev->index;
ali1409_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
@@ -161,24 +307,22 @@ ali1409_close(void *priv)
}
static void *
ali1409_init(const device_t *info)
ali1409_init(UNUSED(const device_t *info))
{
ali1409_t *dev = (ali1409_t *) malloc(sizeof(ali1409_t));
memset(dev, 0, sizeof(ali1409_t));
ali1409_t *dev = (ali1409_t *) calloc(1, sizeof(ali1409_t));
dev->cfg_locked = 1;
/* M1409 Ports:
22h Index Port
23h Data Port
*/
ali1409_log ("Bus speed: %i",cpu_busspeed);
ali1409_log("Bus speed: %i\n", cpu_busspeed);
io_sethandler(0x0022, 0x0002, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
io_sethandler(0x037f, 0x0001, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
io_sethandler(0x03f3, 0x0001, ali1409_read, NULL, NULL, ali1409_write, NULL, NULL, dev);
dev->regs[0x0f] = 0x08;
cpu_set_isa_speed(7159091);
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
return dev;
}
@@ -191,7 +335,7 @@ const device_t ali1409_device = {
.init = ali1409_init,
.close = ali1409_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/ali1429.c
View File

@@ -331,8 +331,7 @@ ali1429_defaults(ali1429_t *dev)
static void *
ali1429_init(const device_t *info)
{
ali1429_t *dev = (ali1429_t *) malloc(sizeof(ali1429_t));
memset(dev, 0, sizeof(ali1429_t));
ali1429_t *dev = (ali1429_t *) calloc(1, sizeof(ali1429_t));
dev->cfg_locked = 1;
GREEN = info->local;
@@ -358,7 +357,7 @@ const device_t ali1429_device = {
.init = ali1429_init,
.close = ali1429_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -372,7 +371,7 @@ const device_t ali1429g_device = {
.init = ali1429_init,
.close = ali1429_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/ali1435.c
View File

@@ -282,8 +282,7 @@ ali1435_close(void *priv)
static void *
ali1435_init(UNUSED(const device_t *info))
{
ali1435_t *dev = (ali1435_t *) malloc(sizeof(ali1435_t));
memset(dev, 0, sizeof(ali1435_t));
ali1435_t *dev = (ali1435_t *) calloc(1, sizeof(ali1435_t));
dev->cfg_locked = 1;
@@ -308,7 +307,7 @@ const device_t ali1435_device = {
.init = ali1435_init,
.close = ali1435_close,
.reset = ali1435_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/ali1489.c
View File

@@ -470,8 +470,7 @@ ali1489_close(void *priv)
static void *
ali1489_init(UNUSED(const device_t *info))
{
ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t));
memset(dev, 0, sizeof(ali1489_t));
ali1489_t *dev = (ali1489_t *) calloc(1, sizeof(ali1489_t));
/* M1487/M1489
22h Index Port
@@ -499,7 +498,7 @@ const device_t ali1489_device = {
.init = ali1489_init,
.close = ali1489_close,
.reset = ali1489_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

23
src/chipset/ali1531.c
View File

@@ -22,6 +22,7 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
@@ -225,12 +226,8 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
ali1531_shadow_recalc(val, dev);
break;
case 0x50:
case 0x51:
case 0x52:
case 0x54:
case 0x55:
case 0x56:
case 0x50 ... 0x52:
case 0x54 ... 0x56:
dev->pci_conf[addr] = val;
break;
@@ -247,8 +244,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x86;
break;
case 0x59:
case 0x5a:
case 0x59 ... 0x5a:
case 0x5c:
dev->pci_conf[addr] = val;
break;
@@ -270,8 +266,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
spd_write_drbs_interleaved(dev->pci_conf, 0x60, 0x6f, 1);
break;
case 0x70:
case 0x71:
case 0x70 ... 0x71:
dev->pci_conf[addr] = val;
break;
@@ -283,8 +278,7 @@ ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
dev->pci_conf[addr] = val & 0x2b;
break;
case 0x76:
case 0x77:
case 0x76 ... 0x77:
dev->pci_conf[addr] = val;
break;
@@ -376,8 +370,7 @@ ali1531_close(void *priv)
static void *
ali1531_init(UNUSED(const device_t *info))
{
ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t));
memset(dev, 0, sizeof(ali1531_t));
ali1531_t *dev = (ali1531_t *) calloc(1, sizeof(ali1531_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1531_read, ali1531_write, dev, &dev->pci_slot);
@@ -396,7 +389,7 @@ const device_t ali1531_device = {
.init = ali1531_init,
.close = ali1531_close,
.reset = ali1531_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

6
src/chipset/ali1541.c
View File

@@ -22,6 +22,7 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
@@ -643,8 +644,7 @@ ali1541_close(void *priv)
static void *
ali1541_init(UNUSED(const device_t *info))
{
ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t));
memset(dev, 0, sizeof(ali1541_t));
ali1541_t *dev = (ali1541_t *) calloc(1, sizeof(ali1541_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1541_read, ali1541_write, dev, &dev->pci_slot);
@@ -665,7 +665,7 @@ const device_t ali1541_device = {
.init = ali1541_init,
.close = ali1541_close,
.reset = ali1541_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

8
src/chipset/ali1543.c
View File

@@ -22,6 +22,7 @@
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
@@ -1599,8 +1600,7 @@ ali1543_close(void *priv)
static void *
ali1543_init(const device_t *info)
{
ali1543_t *dev = (ali1543_t *) malloc(sizeof(ali1543_t));
memset(dev, 0, sizeof(ali1543_t));
ali1543_t *dev = (ali1543_t *) calloc(1, sizeof(ali1543_t));
/* Device 02: M1533 Southbridge */
pci_add_card(PCI_ADD_SOUTHBRIDGE, ali1533_read, ali1533_write, dev, &dev->pci_slot);
@@ -1673,7 +1673,7 @@ const device_t ali1543_device = {
.init = ali1543_init,
.close = ali1543_close,
.reset = ali1543_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1687,7 +1687,7 @@ const device_t ali1543c_device = {
.init = ali1543_init,
.close = ali1543_close,
.reset = ali1543_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/ali1621.c
View File

@@ -669,8 +669,7 @@ ali1621_close(void *priv)
static void *
ali1621_init(UNUSED(const device_t *info))
{
ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
memset(dev, 0, sizeof(ali1621_t));
ali1621_t *dev = (ali1621_t *) calloc(1, sizeof(ali1621_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, ali1621_read, ali1621_write, dev, &dev->pci_slot);
@@ -692,7 +691,7 @@ const device_t ali1621_device = {
.init = ali1621_init,
.close = ali1621_close,
.reset = ali1621_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

12
src/chipset/ali6117.c
View File

@@ -26,6 +26,7 @@
#include <86box/io.h>
#include <86box/pci.h>
#include <86box/pic.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/device.h>
@@ -466,8 +467,7 @@ ali6117_init(const device_t *info)
ali6117_log("ALI6117: init()\n");
ali6117_t *dev = (ali6117_t *) malloc(sizeof(ali6117_t));
memset(dev, 0, sizeof(ali6117_t));
ali6117_t *dev = (ali6117_t *) calloc(1, sizeof(ali6117_t));
dev->local = info->local;
@@ -494,12 +494,12 @@ ali6117_init(const device_t *info)
const device_t ali1217_device = {
.name = "ALi M1217",
.internal_name = "ali1217",
.flags = DEVICE_AT,
.flags = DEVICE_ISA16,
.local = 0x8,
.init = ali6117_init,
.close = ali6117_close,
.reset = ali6117_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -508,12 +508,12 @@ const device_t ali1217_device = {
const device_t ali6117d_device = {
.name = "ALi M6117D",
.internal_name = "ali6117d",
.flags = DEVICE_AT,
.flags = DEVICE_ISA16,
.local = 0x2,
.init = ali6117_init,
.close = ali6117_close,
.reset = ali6117_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

4
src/chipset/compaq_386.c
View File

@@ -772,7 +772,7 @@ const device_t compaq_386_device = {
.init = compaq_386_init,
.close = compaq_386_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -786,7 +786,7 @@ const device_t compaq_genoa_device = {
.init = compaq_genoa_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/contaq_82c59x.c
View File

@@ -322,8 +322,7 @@ contaq_82c59x_close(void *priv)
static void *
contaq_82c59x_init(const device_t *info)
{
contaq_82c59x_t *dev = (contaq_82c59x_t *) malloc(sizeof(contaq_82c59x_t));
memset(dev, 0x00, sizeof(contaq_82c59x_t));
contaq_82c59x_t *dev = (contaq_82c59x_t *) calloc(1, sizeof(contaq_82c59x_t));
dev->green = info->local;
@@ -359,7 +358,7 @@ const device_t contaq_82c596a_device = {
.init = contaq_82c59x_init,
.close = contaq_82c59x_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -373,7 +372,7 @@ const device_t contaq_82c597_device = {
.init = contaq_82c59x_init,
.close = contaq_82c59x_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/cs4031.c
View File

@@ -164,8 +164,7 @@ cs4031_close(void *priv)
static void *
cs4031_init(UNUSED(const device_t *info))
{
cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
memset(dev, 0, sizeof(cs4031_t));
cs4031_t *dev = (cs4031_t *) calloc(1, sizeof(cs4031_t));
dev->port_92 = device_add(&port_92_device);
@@ -185,7 +184,7 @@ const device_t cs4031_device = {
.init = cs4031_init,
.close = cs4031_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

289
src/chipset/cs8220.c Normal file
View File

@@ -0,0 +1,289 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of C&T CS8220 ("PC/AT") chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2025 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/chipset.h>
typedef struct {
uint32_t virt;
uint32_t phys;
uint32_t size;
mem_mapping_t mapping;
} ram_bank_t;
typedef struct {
uint8_t regs[3];
ram_bank_t ram_banks[3];
} cs8220_t;
static uint8_t
cs8220_mem_read(uint32_t addr, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint8_t ret = 0xff;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ret = ram[addr];
return ret;
}
static uint16_t
cs8220_mem_readw(uint32_t addr, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint16_t ret = 0xffff;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ret = *(uint16_t *) &(ram[addr]);
return ret;
}
static void
cs8220_mem_write(uint32_t addr, uint8_t val, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
ram[addr] = val;
}
static void
cs8220_mem_writew(uint32_t addr, uint16_t val, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
addr = (addr - dev->virt) + dev->phys;
if (addr < (mem_size << 10))
*(uint16_t *) &(ram[addr]) = val;
}
static uint8_t
cs8220_in(uint16_t port, void *priv) {
cs8220_t *dev = (cs8220_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x00a4 ... 0x00a5:
ret = dev->regs[port & 0x0001];
break;
case 0x00ab:
ret = dev->regs[2];
break;
}
return ret;
}
static void
cs8220_out(uint16_t port, uint8_t val, void *priv) {
cs8220_t *dev = (cs8220_t *) priv;
switch (port) {
case 0x00a4:
dev->regs[0] = val;
mem_a20_alt = val & 0x40;
mem_a20_recalc();
break;
case 0x00a5:
dev->regs[1] = val;
if (val & 0x01) {
mem_mapping_set_addr(&dev->ram_banks[0].mapping, 0, 0x000040000);
mem_mapping_disable(&dev->ram_banks[1].mapping);
mem_mapping_disable(&dev->ram_banks[2].mapping);
} else {
mem_mapping_set_addr(&dev->ram_banks[0].mapping, 0, dev->ram_banks[0].size);
mem_mapping_enable(&dev->ram_banks[1].mapping);
mem_mapping_enable(&dev->ram_banks[2].mapping);
}
break;
case 0x00ab:
dev->regs[2] = val;
break;
}
}
static void
cs8220_close(void *priv)
{
cs8220_t *dev = (cs8220_t *) priv;
free(dev);
}
static void *
cs8220_init(UNUSED(const device_t *info))
{
cs8220_t *dev = (cs8220_t *) calloc(1, sizeof(cs8220_t));
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
/*
Dell System 200: 640 kB soldered on-board, any other RAM is expansion.
*/
if (!strcmp(machine_get_internal_name(), "dells200")) switch (mem_size) {
default:
dev->ram_banks[2].virt = 0x00100000;
dev->ram_banks[2].phys = 0x000a0000;
dev->ram_banks[2].size = (mem_size << 10) - 0x000a0000;
fallthrough;
case 640:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
dev->ram_banks[1].virt = 0x00080000;
dev->ram_banks[1].phys = 0x00080000;
dev->ram_banks[1].size = 0x00020000;
break;
/*
We are limited to steps of equal size, so we have to simulate some
memory expansions to work around the chipset's limits.
*/
} else switch (mem_size) {
case 256:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00020000;
dev->ram_banks[1].virt = 0x00020000;
dev->ram_banks[1].phys = 0x00020000;
dev->ram_banks[1].size = 0x00020000;
break;
case 384:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00020000;
/* Pretend there's a 128k expansion. */
dev->ram_banks[2].virt = 0x00020000;
dev->ram_banks[2].phys = 0x00020000;
dev->ram_banks[2].size = 0x00040000;
break;
case 512:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
break;
default:
dev->ram_banks[2].virt = 0x00100000;
dev->ram_banks[2].phys = 0x000a0000;
dev->ram_banks[2].size = (mem_size << 10) - 0x000a0000;
fallthrough;
case 640:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
dev->ram_banks[1].virt = 0x00080000;
dev->ram_banks[1].phys = 0x00080000;
dev->ram_banks[1].size = 0x00020000;
break;
case 768:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
dev->ram_banks[1].virt = 0x00080000;
dev->ram_banks[1].phys = 0x00080000;
dev->ram_banks[1].size = 0x00020000;
/* Pretend there's a 128k expansion. */
dev->ram_banks[2].virt = 0x00100000;
dev->ram_banks[2].phys = 0x00080000;
dev->ram_banks[2].size = 0x00020000;
break;
case 896:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
dev->ram_banks[1].virt = 0x00080000;
dev->ram_banks[1].phys = 0x00080000;
dev->ram_banks[1].size = 0x00020000;
/* Pretend there's a 256k expansion. */
dev->ram_banks[2].virt = 0x00100000;
dev->ram_banks[2].phys = 0x00080000;
dev->ram_banks[2].size = 0x00040000;
break;
case 1024:
dev->ram_banks[0].virt = 0x00000000;
dev->ram_banks[0].phys = 0x00000000;
dev->ram_banks[0].size = 0x00080000;
dev->ram_banks[1].virt = 0x00100000;
dev->ram_banks[1].phys = 0x00080000;
dev->ram_banks[1].size = 0x00080000;
break;
}
if (dev->ram_banks[0].size > 0x00000000)
mem_mapping_add(&dev->ram_banks[0].mapping, dev->ram_banks[0].virt, dev->ram_banks[0].size,
cs8220_mem_read, cs8220_mem_readw, NULL,
cs8220_mem_write, cs8220_mem_writew, NULL,
ram + dev->ram_banks[0].phys, MEM_MAPPING_INTERNAL, &(dev->ram_banks[0]));
if (dev->ram_banks[1].size > 0x00000000)
mem_mapping_add(&dev->ram_banks[1].mapping, dev->ram_banks[1].virt, dev->ram_banks[1].size,
cs8220_mem_read, cs8220_mem_readw, NULL,
cs8220_mem_write, cs8220_mem_writew, NULL,
ram + dev->ram_banks[1].phys, MEM_MAPPING_INTERNAL, &(dev->ram_banks[1]));
if (dev->ram_banks[2].size > 0x00000000)
mem_mapping_add(&dev->ram_banks[2].mapping, dev->ram_banks[2].virt, dev->ram_banks[2].size,
cs8220_mem_read, cs8220_mem_readw, NULL,
cs8220_mem_write, cs8220_mem_writew, NULL,
ram + dev->ram_banks[2].phys, MEM_MAPPING_INTERNAL, &(dev->ram_banks[2]));
io_sethandler(0x00a4, 0x0002,
cs8220_in, NULL, NULL, cs8220_out, NULL, NULL, dev);
io_sethandler(0x00ab, 0x0001,
cs8220_in, NULL, NULL, cs8220_out, NULL, NULL, dev);
return dev;
}
const device_t cs8220_device = {
.name = "C&T CS8220 (PC/AT)",
.internal_name = "cs8220",
.flags = 0,
.local = 0,
.init = cs8220_init,
.close = cs8220_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

5
src/chipset/cs8230.c
View File

@@ -157,8 +157,7 @@ cs8230_close(void *priv)
static void *
cs8230_init(UNUSED(const device_t *info))
{
cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t));
memset(cs8230, 0, sizeof(cs8230_t));
cs8230_t *cs8230 = (cs8230_t *) calloc(1, sizeof(cs8230_t));
io_sethandler(0x0022, 0x0002, cs8230_read, NULL, NULL, cs8230_write, NULL, NULL, cs8230);
@@ -178,7 +177,7 @@ const device_t cs8230_device = {
.init = cs8230_init,
.close = cs8230_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/et6000.c
View File

@@ -137,8 +137,7 @@ et6000_close(void *priv)
static void *
et6000_init(UNUSED(const device_t *info))
{
et6000_t *dev = (et6000_t *) malloc(sizeof(et6000_t));
memset(dev, 0, sizeof(et6000_t));
et6000_t *dev = (et6000_t *) calloc(1, sizeof(et6000_t));
/* Port 92h */
device_add(&port_92_device);
@@ -162,7 +161,7 @@ const device_t et6000_device = {
.init = et6000_init,
.close = et6000_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

8
src/chipset/gc100.c
View File

@@ -27,6 +27,7 @@
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/nmi.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
@@ -208,8 +209,7 @@ gc100_close(void *priv)
static void *
gc100_init(const device_t *info)
{
gc100_t *dev = (gc100_t *) malloc(sizeof(gc100_t));
memset(dev, 0, sizeof(gc100_t));
gc100_t *dev = (gc100_t *) calloc(1, sizeof(gc100_t));
dev->reg[0x2] = 0xff;
dev->reg[0x3] = 0x0;
@@ -238,7 +238,7 @@ const device_t gc100_device = {
.init = gc100_init,
.close = gc100_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -252,7 +252,7 @@ const device_t gc100a_device = {
.init = gc100_init,
.close = gc100_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

17
src/chipset/headland.c
View File

@@ -594,8 +594,7 @@ headland_init(const device_t *info)
headland_t *dev;
int ht386 = 0;
dev = (headland_t *) malloc(sizeof(headland_t));
memset(dev, 0x00, sizeof(headland_t));
dev = (headland_t *) calloc(1, sizeof(headland_t));
dev->has_cri = (info->local & HEADLAND_HAS_CRI);
dev->has_sleep = (info->local & HEADLAND_HAS_SLEEP);
@@ -699,7 +698,7 @@ const device_t headland_gc10x_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -713,7 +712,7 @@ const device_t headland_gc113_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -727,7 +726,7 @@ const device_t headland_ht18a_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -741,7 +740,7 @@ const device_t headland_ht18b_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -755,7 +754,7 @@ const device_t headland_ht18c_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -769,7 +768,7 @@ const device_t headland_ht21c_d_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -783,7 +782,7 @@ const device_t headland_ht21e_device = {
.init = headland_init,
.close = headland_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/ims8848.c
View File

@@ -381,8 +381,7 @@ ims8848_close(void *priv)
static void *
ims8848_init(UNUSED(const device_t *info))
{
ims8848_t *dev = (ims8848_t *) malloc(sizeof(ims8848_t));
memset(dev, 0, sizeof(ims8848_t));
ims8848_t *dev = (ims8848_t *) calloc(1, sizeof(ims8848_t));
device_add(&port_92_device);
@@ -416,7 +415,7 @@ const device_t ims8848_device = {
.init = ims8848_init,
.close = ims8848_close,
.reset = ims8848_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/intel_420ex.c
View File

@@ -533,8 +533,7 @@ i420ex_speed_changed(void *priv)
static void *
i420ex_init(const device_t *info)
{
i420ex_t *dev = (i420ex_t *) malloc(sizeof(i420ex_t));
memset(dev, 0, sizeof(i420ex_t));
i420ex_t *dev = (i420ex_t *) calloc(1, sizeof(i420ex_t));
dev->smram = smram_add();
@@ -579,7 +578,7 @@ const device_t i420ex_device = {
.init = i420ex_init,
.close = i420ex_close,
.reset = i420ex_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = i420ex_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -593,7 +592,7 @@ const device_t i420ex_ide_device = {
.init = i420ex_init,
.close = i420ex_close,
.reset = i420ex_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = i420ex_speed_changed,
.force_redraw = NULL,
.config = NULL

56
src/chipset/intel_4x0.c
View File

@@ -1013,7 +1013,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430TX:
if (!dev->smram_locked) {
i4x0_smram_handler_phase0(dev);
regs[0x71] = (regs[0x71] & 0x20) | (val & 0xdf);
regs[0x71] = (regs[0x71] & 0x60) | (val & 0x9f);
regs[0x71] &= (val & 0x40);
i4x0_smram_handler_phase1(dev);
}
break;
@@ -1041,9 +1042,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x72] = (val & 0x7f);
else
regs[0x72] = (regs[0x72] & 0x87) | (val & 0x78);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x72] &= 0xbf;
if (val & 0x08) {
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x72] &= 0xbf;
}
}
} else {
if (dev->smram_locked)
@@ -1577,6 +1580,8 @@ i4x0_reset(void *priv)
dev->regs[0x68 + i] = 0x00;
}
dev->smram_locked = 0;
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
@@ -1608,11 +1613,9 @@ i4x0_close(void *priv)
static void *
i4x0_init(const device_t *info)
{
i4x0_t *dev = (i4x0_t *) malloc(sizeof(i4x0_t));
i4x0_t *dev = (i4x0_t *) calloc(1, sizeof(i4x0_t));
uint8_t *regs;
memset(dev, 0, sizeof(i4x0_t));
dev->smram_low = smram_add();
dev->smram_high = smram_add();
@@ -1658,7 +1661,12 @@ i4x0_init(const device_t *info)
regs[0x57] = 0x31;
regs[0x59] = 0x0f;
regs[0x60] = regs[0x61] = regs[0x62] = regs[0x63] = 0x02;
dev->max_drb = 3;
/* At the very least the 420ZX seems to read to 0x64, per the SB486PV. */
if (dev->type == INTEL_420ZX) {
regs[0x64] = 0x02;
dev->max_drb = 4;
} else
dev->max_drb = 3;
dev->drb_unit = 1;
dev->drb_default = 0x02;
break;
@@ -1967,7 +1975,7 @@ const device_t i420tx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1981,7 +1989,7 @@ const device_t i420zx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1995,7 +2003,7 @@ const device_t i430lx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2009,7 +2017,7 @@ const device_t i430nx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2023,7 +2031,7 @@ const device_t i430fx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2037,7 +2045,7 @@ const device_t i430fx_rev02_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2051,7 +2059,7 @@ const device_t i430hx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2065,7 +2073,7 @@ const device_t i430vx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2079,7 +2087,7 @@ const device_t i430tx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2093,7 +2101,7 @@ const device_t i440fx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2107,7 +2115,7 @@ const device_t i440lx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2121,7 +2129,7 @@ const device_t i440ex_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2135,7 +2143,7 @@ const device_t i440bx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2149,7 +2157,7 @@ const device_t i440bx_no_agp_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2163,7 +2171,7 @@ const device_t i440gx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -2177,7 +2185,7 @@ const device_t i440zx_device = {
.init = i4x0_init,
.close = i4x0_close,
.reset = i4x0_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/intel_82335.c
View File

@@ -171,8 +171,7 @@ intel_82335_close(void *priv)
static void *
intel_82335_init(UNUSED(const device_t *info))
{
intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t));
memset(dev, 0, sizeof(intel_82335_t));
intel_82335_t *dev = (intel_82335_t *) calloc(1, sizeof(intel_82335_t));
memset(dev->regs, 0, sizeof(dev->regs));
@@ -209,7 +208,7 @@ const device_t intel_82335_device = {
.init = intel_82335_init,
.close = intel_82335_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

6
src/chipset/intel_i450kx.c
View File

@@ -799,8 +799,8 @@ i450kx_close(void *priv)
static void *
i450kx_init(UNUSED(const device_t *info))
{
i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t));
memset(dev, 0, sizeof(i450kx_t));
i450kx_t *dev = (i450kx_t *) calloc(1, sizeof(i450kx_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, pb_read, pb_write, dev, &dev->pb_slot); /* Device 19h: Intel 450KX PCI Bridge PB */
pci_add_card(PCI_ADD_NORTHBRIDGE_SEC, mc_read, mc_write, dev, &dev->mc_slot); /* Device 14h: Intel 450KX Memory Controller MC */
@@ -824,7 +824,7 @@ const device_t i450kx_device = {
.init = i450kx_init,
.close = i450kx_close,
.reset = i450kx_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

122
src/chipset/intel_piix.c
View File

@@ -59,7 +59,6 @@ typedef struct piix_io_trap_t {
} piix_io_trap_t;
typedef struct _piix_ {
uint8_t cur_readout_reg;
uint8_t rev;
uint8_t type;
uint8_t func_shift;
@@ -67,7 +66,6 @@ typedef struct _piix_ {
uint8_t pci_slot;
uint8_t no_mirq0;
uint8_t regs[4][256];
uint8_t readout_regs[256];
uint16_t func0_id;
uint16_t nvr_io_base;
uint16_t acpi_io_base;
@@ -157,6 +155,7 @@ piix_ide_handlers(piix_t *dev, int bus)
uint16_t side;
if (bus & 0x01) {
piix_log("Disabling primary IDE...\n");
ide_pri_disable();
if (dev->type == 5) {
@@ -172,11 +171,14 @@ piix_ide_handlers(piix_t *dev, int bus)
ide_set_side(0, side);
}
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x41] & 0x80))
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x41] & 0x80)) {
piix_log("Enabling primary IDE...\n");
ide_pri_enable();
}
}
if (bus & 0x02) {
piix_log("Disabling secondary IDE...\n");
ide_sec_disable();
if (dev->type == 5) {
@@ -192,8 +194,10 @@ piix_ide_handlers(piix_t *dev, int bus)
ide_set_side(1, side);
}
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x43] & 0x80))
if ((dev->regs[1][0x04] & 0x01) && (dev->regs[1][0x43] & 0x80)) {
piix_log("Enabling secondary IDE...\n");
ide_sec_enable();
}
}
}
@@ -467,6 +471,13 @@ piix_write(int func, int addr, uint8_t val, void *priv)
uint8_t *fregs;
uint16_t base;
/* Dell OptiPlex Gn+ shows that register 02:FF is aliased in 01:FF. */
if ((dev->type == 4) && (func == 1) && (addr == 0xff))
func = 2;
if ((func == 1) || (addr == 0xf8) || (addr == 0xf9))
piix_log("[W] %02X:%02X = %02X\n", func, addr, val);
/* Return on unsupported function. */
if (dev->max_func > 0) {
if (func > dev->max_func)
@@ -738,6 +749,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[addr] = val;
break;
case 0xb0:
if (val & 0x10)
warning("Write %02X to B0\n", val);
if (dev->type == 4)
fregs[addr] = (fregs[addr] & 0x8c) | (val & 0x73);
else if (dev->type == 5)
@@ -747,6 +760,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
alt_access = !!(val & 0x20);
break;
case 0xb1:
if (val & 0x18)
warning("Write %02X to B1\n", val);
if (dev->type > 3)
fregs[addr] = val & 0xdf;
break;
@@ -925,6 +940,12 @@ piix_write(int func, int addr, uint8_t val, void *priv)
if (dev->type > 4)
fregs[addr] = val;
break;
case 0xf8:
case 0xf9:
/* Undocumented! */
if (dev->type == 4)
fregs[addr] = val;
break;
default:
break;
}
@@ -1171,6 +1192,10 @@ piix_read(int func, int addr, void *priv)
uint8_t ret = 0xff;
const uint8_t *fregs;
/* Dell OptiPlex Gn+ shows that register 02:FF is aliased in 01:FF. */
if ((dev->type == 4) && (func == 1) && (addr == 0xff))
func = 2;
if ((dev->type == 3) && (func == 2) && (dev->max_func == 1) && (addr >= 0x40))
ret = 0x00;
@@ -1185,31 +1210,6 @@ piix_read(int func, int addr, void *priv)
return ret;
}
static void
board_write(uint16_t port, uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
if (port == 0x00e0)
dev->cur_readout_reg = val;
else if (port == 0x00e1)
dev->readout_regs[dev->cur_readout_reg] = val;
}
static uint8_t
board_read(uint16_t port, void *priv)
{
const piix_t *dev = (piix_t *) priv;
uint8_t ret = 0x64;
if (port == 0x00e0)
ret = dev->cur_readout_reg;
else if (port == 0x00e1)
ret = dev->readout_regs[dev->cur_readout_reg];
return ret;
}
static void
piix_reset_hard(piix_t *dev)
{
@@ -1226,7 +1226,7 @@ piix_reset_hard(piix_t *dev)
sff_set_slot(dev->bm[1], dev->pci_slot);
sff_set_irq_pin(dev->bm[1], PCI_INTA);
sff_set_irq_line(dev->bm[1], 14);
sff_set_irq_line(dev->bm[1], 15);
sff_set_irq_mode(dev->bm[1], IRQ_MODE_LEGACY);
}
@@ -1342,6 +1342,10 @@ piix_reset_hard(piix_t *dev)
fregs[0x45] = 0x55;
fregs[0x46] = 0x01;
}
if (dev->type == 4) {
fregs[0xf8] = 0x30;
fregs[0xf9] = 0x0f;
}
if ((dev->type == 1) && (dev->rev == 2))
dev->max_func = 0; /* It starts with IDE disabled, then enables it. */
else
@@ -1538,8 +1542,7 @@ piix_speed_changed(void *priv)
static void *
piix_init(const device_t *info)
{
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));
piix_t *dev = (piix_t *) calloc(1, sizeof(piix_t));
dev->type = info->local & 0x0f;
/* If (dev->type == 4) and (dev->rev & 0x08), then this is PIIX4E. */
@@ -1618,47 +1621,16 @@ piix_init(const device_t *info)
else
cpu_set_isa_pci_div(3);
dma_alias_set();
if (dev->type > 1)
dma_alias_set();
else
dma_alias_set_piix();
if (dev->type < 4)
pci_enable_mirq(0);
if (dev->type < 3)
pci_enable_mirq(1);
dev->readout_regs[0] = 0xff;
dev->readout_regs[1] = 0x40;
dev->readout_regs[2] = 0xff;
/* Port E1 register 01 (TODO: Find how multipliers > 3.0 are defined):
Bit 6: 1 = can boot, 0 = no;
Bit 7, 1 = multiplier (00 = 2.5, 01 = 2.0, 10 = 3.0, 11 = 1.5);
Bit 5, 4 = bus speed (00 = 50 MHz, 01 = 66 MHz, 10 = 60 MHz, 11 = ????):
Bit 7, 5, 4, 1: 0000 = 125 MHz, 0010 = 166 MHz, 0100 = 150 MHz, 0110 = ??? MHz;
0001 = 100 MHz, 0011 = 133 MHz, 0101 = 120 MHz, 0111 = ??? MHz;
1000 = 150 MHz, 1010 = 200 MHz, 1100 = 180 MHz, 1110 = ??? MHz;
1001 = 75 MHz, 1011 = 100 MHz, 1101 = 90 MHz, 1111 = ??? MHz */
if (cpu_busspeed <= 40000000)
dev->readout_regs[1] |= 0x30;
else if ((cpu_busspeed > 40000000) && (cpu_busspeed <= 50000000))
dev->readout_regs[1] |= 0x00;
else if ((cpu_busspeed > 50000000) && (cpu_busspeed <= 60000000))
dev->readout_regs[1] |= 0x20;
else if (cpu_busspeed > 60000000)
dev->readout_regs[1] |= 0x10;
if (cpu_dmulti <= 1.5)
dev->readout_regs[1] |= 0x82;
else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
dev->readout_regs[1] |= 0x02;
else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
dev->readout_regs[1] |= 0x00;
else if (cpu_dmulti > 2.5)
dev->readout_regs[1] |= 0x80;
io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
#if 0
device_add(&i8254_sec_device);
#endif
@@ -1674,7 +1646,7 @@ const device_t piix_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1688,7 +1660,7 @@ const device_t piix_no_mirq_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1702,7 +1674,7 @@ const device_t piix_rev02_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1716,7 +1688,7 @@ const device_t piix3_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1730,7 +1702,7 @@ const device_t piix3_ioapic_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1744,7 +1716,7 @@ const device_t piix4_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1758,7 +1730,7 @@ const device_t piix4e_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -1772,7 +1744,7 @@ const device_t slc90e66_device = {
.init = piix_init,
.close = piix_close,
.reset = piix_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = piix_speed_changed,
.force_redraw = NULL,
.config = NULL

25
src/chipset/intel_sio.c
View File

@@ -355,7 +355,23 @@ sio_config_read(uint16_t port, UNUSED(void *priv))
ret = 0xff;
break;
case 5:
ret = 0xd3;
/*
Dell Dimension XPS P60 jumpers:
- Bit 5: Disable CMOS Setup (1 = yes, 0 = no).
Dell OptiPlex 560/L jumpers:
- Bit 1: Password (1 = disable, 0 = enable);
- Bit 5: Clear CMOS (1 = no, 0 = yes).
- Bits 7, 6: Board type:
- 0, 0 = L;
- 0, 1 = MT;
- 1, 0 = M;
- 1, 1 = M.
*/
if (!strcmp(machine_get_internal_name(), "opti560l"))
ret = 0x20;
else
ret = 0xd3;
switch (cpu_pci_speed) {
case 20000000:
@@ -508,8 +524,7 @@ sio_speed_changed(void *priv)
static void *
sio_init(const device_t *info)
{
sio_t *dev = (sio_t *) malloc(sizeof(sio_t));
memset(dev, 0, sizeof(sio_t));
sio_t *dev = (sio_t *) calloc(1, sizeof(sio_t));
pci_add_card(PCI_ADD_SOUTHBRIDGE, sio_read, sio_write, dev, &dev->pci_slot);
@@ -568,7 +583,7 @@ const device_t sio_device = {
.init = sio_init,
.close = sio_close,
.reset = sio_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = sio_speed_changed,
.force_redraw = NULL,
.config = NULL
@@ -582,7 +597,7 @@ const device_t sio_zb_device = {
.init = sio_init,
.close = sio_close,
.reset = sio_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = sio_speed_changed,
.force_redraw = NULL,
.config = NULL

131
src/chipset/isa486c.c Normal file
View File

@@ -0,0 +1,131 @@
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
typedef struct isa486c_t {
uint8_t regs[3];
} isa486c_t;
static void
isa486c_recalcmapping(isa486c_t *dev)
{
uint32_t shflags = 0;
uint32_t bases[5] = { 0x000c0000, 0x000c8000, 0x000d0000, 0x000d8000, 0x000e0000 };
uint32_t sizes[5] = { 0x00008000, 0x00008000, 0x00008000, 0x00008000, 0x00020000 };
if (dev->regs[1] & 0x20)
shflags = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
else
shflags = MEM_READ_INTERNAL | MEM_WRITE_EXTANY;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t i = 0; i < 5; i++)
if (dev->regs[1] & (1 << i)) {
if (i == 4) {
shadowbios = 1;
shadowbios_write = !!(dev->regs[1] & 0x20);
}
mem_set_mem_state_both(bases[i], sizes[i], shflags);
} else
mem_set_mem_state_both(bases[i], sizes[i], MEM_READ_EXTANY | MEM_WRITE_EXTANY);
flushmmucache_nopc();
}
static void
isa486c_write(uint16_t addr, uint8_t val, void *priv)
{
isa486c_t *dev = (isa486c_t *) priv;
switch (addr) {
case 0x0023:
dev->regs[0] = val;
break;
/*
Port 25h:
- Bit 0 = Video BIOS (C000-C7FF) shadow enabled;
- Bit 1 = C800-C8FF shadow enabled;
- Bit 2 = D000-D7FF shadow enabled;
- Bit 3 = D800-DFFF shadow enabled;
- Bit 4 = E000-FFFF shadow enabled (or F0000-FFFFF?);
- Bit 5 = If set, read from ROM, write to shadow;
- Bit 6 = KEN Video & BIOS enabled (cacheability!).
*/
case 0x0025:
dev->regs[1] = val;
isa486c_recalcmapping(dev);
break;
case 0x0027:
dev->regs[2] = val;
break;
}
}
static uint8_t
isa486c_read(uint16_t addr, void *priv)
{
isa486c_t *dev = (isa486c_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x0023:
ret = dev->regs[0];
break;
case 0x0025:
ret = dev->regs[1];
break;
case 0x0027:
ret = dev->regs[2];
break;
}
return ret;
}
static void
isa486c_close(void *priv)
{
isa486c_t *dev = (isa486c_t *) priv;
free(dev);
}
static void *
isa486c_init(UNUSED(const device_t *info))
{
isa486c_t *dev = (isa486c_t *) calloc(1, sizeof(isa486c_t));
io_sethandler(0x0023, 0x0001, isa486c_read, NULL, NULL, isa486c_write, NULL, NULL, dev);
io_sethandler(0x0025, 0x0001, isa486c_read, NULL, NULL, isa486c_write, NULL, NULL, dev);
io_sethandler(0x0027, 0x0001, isa486c_read, NULL, NULL, isa486c_write, NULL, NULL, dev);
return dev;
}
const device_t isa486c_device = {
.name = "ASUS ISA-486C Gate Array",
.internal_name = "isa486c",
.flags = 0,
.local = 0,
.init = isa486c_init,
.close = isa486c_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

809
src/chipset/neat.c
View File

File diff suppressed because it is too large Load Diff

32
src/chipset/olivetti_eva.c
View File

@@ -73,26 +73,24 @@ olivetti_eva_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x069:
dev->reg_069 = val;
/*
* Unfortunately, if triggered, the BIOS remapping function fails causing
* a fatal error. Therefore, this code section is currently commented.
*/
#if 0
if (val & 1) {
mem_remap_top(0);
if (val == 0x01) {
/*
* Set the register to 7 or above for the BIOS to trigger the
* memory remapping function if shadowing is active.
*/
dev->reg_069 = 0x7;
dev->reg_069 = 0x07;
}
if (val & 8) {
if (val & 0x08) {
/*
* Activate shadowing for region e0000-fffff
*/
mem_remap_top(256);
mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
} else {
mem_remap_top(384);
mem_set_mem_state_both(0xe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
#endif
break;
default:
break;
@@ -134,8 +132,7 @@ olivetti_eva_close(void *priv)
static void *
olivetti_eva_init(UNUSED(const device_t *info))
{
olivetti_eva_t *dev = (olivetti_eva_t *) malloc(sizeof(olivetti_eva_t));
memset(dev, 0, sizeof(olivetti_eva_t));
olivetti_eva_t *dev = (olivetti_eva_t *) calloc(1, sizeof(olivetti_eva_t));
/* GA98 registers */
dev->reg_065 = 0x00;
@@ -144,7 +141,7 @@ olivetti_eva_init(UNUSED(const device_t *info))
dev->reg_067 = 0x00;
/* RAM enable registers */
dev->reg_069 = 0x0;
dev->reg_069 = 0x00;
io_sethandler(0x0065, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
io_sethandler(0x0067, 0x0001, olivetti_eva_read, NULL, NULL, olivetti_eva_write, NULL, NULL, dev);
@@ -153,13 +150,6 @@ olivetti_eva_init(UNUSED(const device_t *info))
/* When shadowing is not enabled in BIOS, all upper memory is available as XMS */
mem_remap_top(384);
/*
* Default settings when NVRAM is cleared activate shadowing.
* Thus, to avoid boot errors, remap only 256k from UMB to XMS.
* Remove this block once BIOS memory remapping works.
*/
mem_remap_top(256);
return dev;
}
@@ -171,7 +161,7 @@ const device_t olivetti_eva_device = {
.init = olivetti_eva_init,
.close = olivetti_eva_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

46
src/chipset/opti283.c
View File

@@ -16,6 +16,7 @@
* Copyright 2021 Tiseno100.
* Copyright 2021 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -158,7 +159,20 @@ opti283_shadow_recalc(opti283_t *dev)
rom = dev->regs[0x11] & (1 << ((i >> 2) + 4));
opti283_log("OPTI 283: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4)));
if (sh_enable && rom) {
if (sh_copy) {
if (base >= 0x000e0000)
shadowbios_write |= 1;
if (base >= 0x000d0000)
dev->shadow_high |= 1;
if (base >= 0xe0000) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_EXTANY, WRITE_INTERNAL\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_EXTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
}
} else if (sh_enable && rom) {
if (base >= 0x000e0000)
shadowbios |= 1;
if (base >= 0x000d0000)
@@ -171,13 +185,8 @@ opti283_shadow_recalc(opti283_t *dev)
if (base >= 0x000e0000)
shadowbios_write |= 1;
if (sh_copy) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_EXTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_EXTERNAL\n", base, base + 0x3fff);
}
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
opti283_log("OPTI 283: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
}
} else {
if (base >= 0xe0000) {
@@ -239,9 +248,21 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
dev->regs[dev->index] = (dev->regs[dev->index] & 0x80) | (val & 0x7f);
break;
case 0x14:
case 0x14: {
double bus_clk;
switch (val & 0x01) {
default:
case 0x00:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x01:
bus_clk = cpu_busspeed / 4.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
reset_on_hlt = !!(val & 0x40);
fallthrough;
}
case 0x11:
case 0x12:
case 0x13:
@@ -284,8 +305,7 @@ opti283_close(void *priv)
static void *
opti283_init(UNUSED(const device_t *info))
{
opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
memset(dev, 0x00, sizeof(opti283_t));
opti283_t *dev = (opti283_t *) calloc(1, sizeof(opti283_t));
io_sethandler(0x0022, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
io_sethandler(0x0023, 0x0001, opti283_read, NULL, NULL, opti283_write, NULL, NULL, dev);
@@ -311,6 +331,8 @@ opti283_init(UNUSED(const device_t *info))
opti283_shadow_recalc(dev);
cpu_set_isa_speed((int) round(cpu_busspeed / 6.0));
device_add(&port_92_device);
return dev;
@@ -324,7 +346,7 @@ const device_t opti283_device = {
.init = opti283_init,
.close = opti283_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/opti291.c
View File

@@ -138,8 +138,7 @@ opti291_close(void *priv)
static void *
opti291_init(UNUSED(const device_t *info))
{
opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t));
memset(dev, 0, sizeof(opti291_t));
opti291_t *dev = (opti291_t *) calloc(1, sizeof(opti291_t));
io_sethandler(0x022, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
io_sethandler(0x024, 0x0001, opti291_read, NULL, NULL, opti291_write, NULL, NULL, dev);
@@ -161,7 +160,7 @@ const device_t opti291_device = {
.init = opti291_init,
.close = opti291_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

6
src/chipset/opti391.c
View File

@@ -374,7 +374,7 @@ const device_t opti381_device = {
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -388,7 +388,7 @@ const device_t opti481_device = {
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -402,7 +402,7 @@ const device_t opti391_device = {
.init = opti391_init,
.close = opti391_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

54
src/chipset/opti495.c
View File

@@ -8,14 +8,13 @@
*
* Implementation of the OPTi 82C493/82C495 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2020 Tiseno100.
* Copyright 2016-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -28,6 +27,7 @@
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_fallthrough.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
@@ -166,6 +166,27 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
case 0x26:
opti495_recalc(dev);
break;
case 0x25: {
double bus_clk;
switch (val & 0x03) {
default:
case 0x00:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x01:
bus_clk = cpu_busspeed / 4.0;
break;
case 0x02:
bus_clk = cpu_busspeed / 3.0;
break;
case 0x03:
bus_clk = (cpu_busspeed * 2.0) / 5.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
break;
}
}
}
@@ -219,8 +240,7 @@ opti495_close(void *priv)
static void *
opti495_init(const device_t *info)
{
opti495_t *dev = (opti495_t *) malloc(sizeof(opti495_t));
memset(dev, 0, sizeof(opti495_t));
opti495_t *dev = (opti495_t *) calloc(1, sizeof(opti495_t));
device_add(&port_92_device);
@@ -260,6 +280,8 @@ opti495_init(const device_t *info)
io_sethandler(0x00e1, 0x0002, opti495_read, NULL, NULL, opti495_write, NULL, NULL, dev);
cpu_set_isa_speed((int) round(cpu_busspeed / 6.0));
return dev;
}
@@ -271,21 +293,35 @@ const device_t opti493_device = {
.init = opti495_init,
.close = opti495_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti495_device = {
const device_t opti495slc_device = {
.name = "OPTi 82C495",
.internal_name = "opti495",
.internal_name = "opti495slc",
.flags = 0,
.local = OPTI495XLC,
.local = OPTI495SLC,
.init = opti495_init,
.close = opti495_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t opti495sx_device = {
.name = "OPTi 82C495SX",
.internal_name = "opti495sx",
.flags = 0,
.local = OPTI495SX,
.init = opti495_init,
.close = opti495_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

360
src/chipset/opti498.c Normal file
View File

@@ -0,0 +1,360 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the OPTi 82C498 chipset.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2025 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
#ifdef ENABLE_OPTI498_LOG
int opti498_do_log = ENABLE_OPTI498_LOG;
static void
opti498_log(const char *fmt, ...)
{
va_list ap;
if (opti498_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define opti498_log(fmt, ...)
#endif
typedef struct mem_remapping_t {
uint32_t phys;
uint32_t virt;
} mem_remapping_t;
typedef struct opti498_t {
uint8_t index;
/* 0x30 for 496/497, 0x70 for 498. */
uint8_t reg_base;
uint8_t shadow_high;
uint8_t regs[256];
mem_remapping_t mem_remappings[2];
mem_mapping_t mem_mappings[2];
} opti498_t;
static uint8_t
opti498_read_remapped_ram(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_ram((addr - dev->virt) + dev->phys, priv);
}
static uint16_t
opti498_read_remapped_ramw(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_ramw((addr - dev->virt) + dev->phys, priv);
}
static uint32_t
opti498_read_remapped_raml(uint32_t addr, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
return mem_read_raml((addr - dev->virt) + dev->phys, priv);
}
static void
opti498_write_remapped_ram(uint32_t addr, uint8_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_ram((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti498_write_remapped_ramw(uint32_t addr, uint16_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_ramw((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti498_write_remapped_raml(uint32_t addr, uint32_t val, void *priv)
{
const mem_remapping_t *dev = (mem_remapping_t *) priv;
mem_write_raml((addr - dev->virt) + dev->phys, val, priv);
}
static void
opti498_shadow_recalc(opti498_t *dev)
{
uint32_t base;
uint32_t rbase;
uint8_t sh_enable;
uint8_t sh_mode;
uint8_t rom;
uint8_t sh_copy;
shadowbios = shadowbios_write = 0;
dev->shadow_high = 0;
opti498_log("OPTI 498: %02X %02X %02X %02X\n", dev->regs[0x02], dev->regs[0x03], dev->regs[0x04], dev->regs[0x05]);
if (dev->regs[0x02] & 0x80) {
if (dev->regs[0x04] & 0x02) {
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
opti498_log("OPTI 498: F0000-FFFFF READ_EXTANY, WRITE_EXTANY\n");
} else {
shadowbios_write = 1;
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
opti498_log("OPTI 498: F0000-FFFFF READ_EXTANY, WRITE_INTERNAL\n");
}
} else {
shadowbios = 1;
mem_set_mem_state_both(0xf0000, 0x10000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
opti498_log("OPTI 498: F0000-FFFFF READ_INTERNAL, WRITE_DISABLED\n");
}
sh_copy = dev->regs[0x02] & 0x08;
for (uint8_t i = 0; i < 12; i++) {
base = 0xc0000 + (i << 14);
if (i >= 4)
sh_enable = dev->regs[0x03] & (1 << (i - 4));
else
sh_enable = dev->regs[0x04] & (1 << (i + 4));
sh_mode = dev->regs[0x02] & (1 << (i >> 2));
rom = dev->regs[0x02] & (1 << ((i >> 2) + 4));
opti498_log("OPTI 498: %i/%08X: %i, %i, %i\n", i, base, (i >= 4) ? (1 << (i - 4)) : (1 << (i + 4)), (1 << (i >> 2)), (1 << ((i >> 2) + 4)));
if (sh_copy) {
if (base >= 0x000e0000)
shadowbios_write |= 1;
if (base >= 0x000d0000)
dev->shadow_high |= 1;
if (base >= 0xe0000) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
opti498_log("OPTI 498: %08X-%08X READ_EXTANY, WRITE_INTERNAL\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_INTERNAL);
opti498_log("OPTI 498: %08X-%08X READ_EXTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
}
} else if (sh_enable && rom) {
if (base >= 0x000e0000)
shadowbios |= 1;
if (base >= 0x000d0000)
dev->shadow_high |= 1;
if (sh_mode) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_DISABLED);
opti498_log("OPTI 498: %08X-%08X READ_INTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
} else {
if (base >= 0x000e0000)
shadowbios_write |= 1;
mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
opti498_log("OPTI 498: %08X-%08X READ_INTERNAL, WRITE_INTERNAL\n", base, base + 0x3fff);
}
} else {
if (base >= 0xe0000) {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTANY | MEM_WRITE_DISABLED);
opti498_log("OPTI 498: %08X-%08X READ_EXTANY, WRITE_DISABLED\n", base, base + 0x3fff);
} else {
mem_set_mem_state_both(base, 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_DISABLED);
opti498_log("OPTI 498: %08X-%08X READ_EXTERNAL, WRITE_DISABLED\n", base, base + 0x3fff);
}
}
}
rbase = ((uint32_t) (dev->regs[0x05] & 0x3f)) << 20;
if (rbase > 0) {
dev->mem_remappings[0].virt = rbase;
mem_mapping_set_addr(&dev->mem_mappings[0], rbase, 0x00020000);
if (!dev->shadow_high) {
rbase += 0x00020000;
dev->mem_remappings[1].virt = rbase;
mem_mapping_set_addr(&dev->mem_mappings[1], rbase, 0x00020000);
} else
mem_mapping_disable(&dev->mem_mappings[1]);
} else {
mem_mapping_disable(&dev->mem_mappings[0]);
mem_mapping_disable(&dev->mem_mappings[1]);
}
flushmmucache_nopc();
}
static void
opti498_write(uint16_t addr, uint8_t val, void *priv)
{
opti498_t *dev = (opti498_t *) priv;
uint8_t reg = dev->index - dev->reg_base;
switch (addr) {
default:
break;
case 0x22:
dev->index = val;
break;
case 0x24:
opti498_log("OPTi 498: dev->regs[%02x] = %02x\n", dev->index, val);
if ((reg >= 0x00) && (reg <= 0x0b)) switch (reg) {
default:
break;
case 0x00:
dev->regs[reg] = (dev->regs[reg] & 0xc0) | (val & 0x3f);
break;
case 0x01:
case 0x07 ... 0x0b:
dev->regs[reg] = val;
break;
case 0x02:
case 0x03:
case 0x04:
case 0x05:
dev->regs[reg] = val;
opti498_shadow_recalc(dev);
break;
case 0x06: {
double bus_clk;
dev->regs[reg] = val;
switch (val & 0x03) {
default:
case 0x00:
bus_clk = cpu_busspeed / 8.0;
break;
case 0x01:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x02:
bus_clk = cpu_busspeed / 5.0;
break;
case 0x03:
bus_clk = cpu_busspeed / 4.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
reset_on_hlt = !!(val & 0x40);
break;
}
}
dev->index = 0xff;
break;
}
}
static uint8_t
opti498_read(uint16_t addr, void *priv)
{
opti498_t *dev = (opti498_t *) priv;
uint8_t reg = dev->index - dev->reg_base;
uint8_t ret = 0xff;
if (addr == 0x24) {
if ((reg >= 0x00) && (reg <= 0x0b))
ret = dev->regs[reg];
dev->index = 0xff;
}
return ret;
}
static void
opti498_close(void *priv)
{
opti498_t *dev = (opti498_t *) priv;
free(dev);
}
static void *
opti498_init(UNUSED(const device_t *info))
{
opti498_t *dev = (opti498_t *) calloc(1, sizeof(opti498_t));
dev->reg_base = info->local & 0xff;
io_sethandler(0x0022, 0x0001, opti498_read, NULL, NULL, opti498_write, NULL, NULL, dev);
io_sethandler(0x0024, 0x0001, opti498_read, NULL, NULL, opti498_write, NULL, NULL, dev);
dev->regs[0x00] = 0x1f;
dev->regs[0x01] = 0x8f;
dev->regs[0x02] = 0xf0;
dev->regs[0x07] = 0x70;
dev->regs[0x09] = 0x70;
dev->mem_remappings[0].phys = 0x000a0000;
dev->mem_remappings[1].phys = 0x000d0000;
mem_mapping_add(&dev->mem_mappings[0], 0, 0x00020000,
opti498_read_remapped_ram, opti498_read_remapped_ramw, opti498_read_remapped_raml,
opti498_write_remapped_ram, opti498_write_remapped_ramw, opti498_write_remapped_raml,
&ram[dev->mem_remappings[0].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[0]);
mem_mapping_disable(&dev->mem_mappings[0]);
mem_mapping_add(&dev->mem_mappings[1], 0, 0x00020000,
opti498_read_remapped_ram, opti498_read_remapped_ramw, opti498_read_remapped_raml,
opti498_write_remapped_ram, opti498_write_remapped_ramw, opti498_write_remapped_raml,
&ram[dev->mem_remappings[1].phys], MEM_MAPPING_INTERNAL, &dev->mem_remappings[1]);
mem_mapping_disable(&dev->mem_mappings[1]);
opti498_shadow_recalc(dev);
cpu_set_isa_speed((int) round(cpu_busspeed / 8.0));
device_add(&port_92_device);
return dev;
}
const device_t opti498_device = {
.name = "OPTi 82C498",
.internal_name = "opti498",
.flags = 0,
.local = 0x70,
.init = opti498_init,
.close = opti498_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

51
src/chipset/opti499.c
View File

@@ -16,6 +16,7 @@
* Copyright 2008-2020 Tiseno100.
* Copyright 2016-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -148,9 +149,28 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
default:
break;
case 0x20:
case 0x20: {
double coeff = (val & 0x10) ? 1.0 : 2.0;
double bus_clk;
switch (dev->regs[0x25] & 0x03) {
default:
case 0x00:
bus_clk = (cpu_busspeed * coeff) / 6.0;
break;
case 0x01:
bus_clk = (cpu_busspeed * coeff) / 5.0;
break;
case 0x02:
bus_clk = (cpu_busspeed * coeff) / 4.0;
break;
case 0x03:
bus_clk = (cpu_busspeed * coeff) / 3.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
reset_on_hlt = !(val & 0x02);
break;
}
case 0x21:
cpu_cache_ext_enabled = !!(dev->regs[0x21] & 0x10);
@@ -163,6 +183,28 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
case 0x2d:
opti499_recalc(dev);
break;
case 0x25: {
double coeff = (dev->regs[0x20] & 0x10) ? 1.0 : 2.0;
double bus_clk;
switch (val & 0x03) {
default:
case 0x00:
bus_clk = (cpu_busspeed * coeff) / 8.0;
break;
case 0x01:
bus_clk = (cpu_busspeed * coeff) / 6.0;
break;
case 0x02:
bus_clk = (cpu_busspeed * coeff) / 5.0;
break;
case 0x03:
bus_clk = (cpu_busspeed * coeff) / 4.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
break;
}
}
}
@@ -229,6 +271,8 @@ opti499_reset(void *priv)
cpu_update_waitstates();
opti499_recalc(dev);
cpu_set_isa_speed((int) round((cpu_busspeed * 2.0) / 6.0));
}
static void
@@ -242,8 +286,7 @@ opti499_close(void *priv)
static void *
opti499_init(UNUSED(const device_t *info))
{
opti499_t *dev = (opti499_t *) malloc(sizeof(opti499_t));
memset(dev, 0, sizeof(opti499_t));
opti499_t *dev = (opti499_t *) calloc(1, sizeof(opti499_t));
device_add(&port_92_device);
@@ -265,7 +308,7 @@ const device_t opti499_device = {
.init = opti499_init,
.close = opti499_close,
.reset = opti499_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/opti5x7.c
View File

@@ -172,8 +172,7 @@ opti5x7_close(void *priv)
static void *
opti5x7_init(const device_t *info)
{
opti5x7_t *dev = (opti5x7_t *) malloc(sizeof(opti5x7_t));
memset(dev, 0, sizeof(opti5x7_t));
opti5x7_t *dev = (opti5x7_t *) calloc(1, sizeof(opti5x7_t));
dev->is_pci = info->local;
@@ -193,7 +192,7 @@ const device_t opti5x7_device = {
.init = opti5x7_init,
.close = opti5x7_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -207,7 +206,7 @@ const device_t opti5x7_pci_device = {
.init = opti5x7_init,
.close = opti5x7_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

4
src/chipset/opti602.c
View File

@@ -218,7 +218,7 @@ const device_t opti601_device = {
.init = opti602_init,
.close = opti602_close,
.reset = opti602_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -232,7 +232,7 @@ const device_t opti602_device = {
.init = opti602_init,
.close = opti602_close,
.reset = opti602_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/opti822.c
View File

@@ -394,8 +394,7 @@ opti822_close(void *priv)
static void *
opti822_init(UNUSED(const device_t *info))
{
opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t));
memset(dev, 0, sizeof(opti822_t));
opti822_t *dev = (opti822_t *) calloc(1, sizeof(opti822_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, opti822_pci_read, opti822_pci_write, dev, &dev->pci_slot);
@@ -412,7 +411,7 @@ const device_t opti822_device = {
.init = opti822_init,
.close = opti822_close,
.reset = opti822_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

33
src/chipset/opti895.c
View File

@@ -16,6 +16,7 @@
* Copyright 2008-2020 Tiseno100.
* Copyright 2016-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -182,6 +183,27 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
smram_state_change(dev->smram, 0, !!(val & 0x80));
break;
case 0x25: {
double bus_clk;
switch (val & 0x03) {
default:
case 0x00:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x01:
bus_clk = cpu_busspeed / 5.0;
break;
case 0x02:
bus_clk = cpu_busspeed / 4.0;
break;
case 0x03:
bus_clk = cpu_busspeed / 3.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
break;
}
case 0xe0:
if (!(val & 0x01))
dev->forced_green = 0;
@@ -259,8 +281,7 @@ opti895_close(void *priv)
static void *
opti895_init(const device_t *info)
{
opti895_t *dev = (opti895_t *) malloc(sizeof(opti895_t));
memset(dev, 0, sizeof(opti895_t));
opti895_t *dev = (opti895_t *) calloc(1, sizeof(opti895_t));
device_add(&port_92_device);
@@ -295,6 +316,8 @@ opti895_init(const device_t *info)
smram_enable(dev->smram, 0x00030000, 0x000b0000, 0x00010000, 0, 1);
cpu_set_isa_speed((int) round(cpu_busspeed / 6.0));
return dev;
}
@@ -306,7 +329,7 @@ const device_t opti802g_device = {
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -320,7 +343,7 @@ const device_t opti802g_pci_device = {
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -334,7 +357,7 @@ const device_t opti895_device = {
.init = opti895_init,
.close = opti895_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

909
src/chipset/scamp.c
View File

File diff suppressed because it is too large Load Diff

9
src/chipset/scat.c
View File

@@ -1403,8 +1403,7 @@ scat_init(const device_t *info)
uint32_t k;
int sx;
dev = (scat_t *) malloc(sizeof(scat_t));
memset(dev, 0x00, sizeof(scat_t));
dev = (scat_t *) calloc(1, sizeof(scat_t));
dev->type = info->local;
sx = (dev->type == 32) ? 1 : 0;
@@ -1559,7 +1558,7 @@ const device_t scat_device = {
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1573,7 +1572,7 @@ const device_t scat_4_device = {
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1587,7 +1586,7 @@ const device_t scat_sx_device = {
.init = scat_init,
.close = scat_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

2
src/chipset/sis_5511.c
View File

@@ -165,7 +165,7 @@ const device_t sis_5511_device = {
.init = sis_5511_init,
.close = sis_5511_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/sis_5511_h2p.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
@@ -258,7 +259,7 @@ sis_5511_host_to_pci_write(int addr, uint8_t val, void *priv)
case 0x7a: /* DRAM Bank Register 2-1 */
case 0x7c: /* DRAM Bank Register 3-0 */
case 0x7e: /* DRAM Bank Register 3-1 */
spd_write_drbs(dev->pci_conf, 0x70, 0x7e, 0x82);
spd_write_drbs(dev->pci_conf, 0x70, 0x7e, 0x02);
break;
case 0x71: /* DRAM Bank Register 0-0 */
@@ -454,7 +455,7 @@ const device_t sis_5511_h2p_device = {
.init = sis_5511_host_to_pci_init,
.close = sis_5511_host_to_pci_close,
.reset = sis_5511_host_to_pci_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

8
src/chipset/sis_5513_ide.c
View File

@@ -456,7 +456,7 @@ const device_t sis_5513_ide_device = {
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -470,7 +470,7 @@ const device_t sis_5572_ide_device = {
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -484,7 +484,7 @@ const device_t sis_5582_ide_device = {
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -498,7 +498,7 @@ const device_t sis_5591_5600_ide_device = {
.init = sis_5513_ide_init,
.close = sis_5513_ide_close,
.reset = sis_5513_ide_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

21
src/chipset/sis_5513_p2i.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
@@ -106,7 +107,7 @@ sis_5513_apc_reset(sis_5513_pci_to_isa_t *dev)
{
memset(dev->apc_regs, 0x00, sizeof(dev->apc_regs));
if (dev->rev == 0b0) {
if (dev->rev == 0xb0) {
dev->apc_regs[0x03] = 0x80;
dev->apc_regs[0x04] = 0x38;
dev->apc_regs[0x07] = 0x01;
@@ -115,7 +116,7 @@ sis_5513_apc_reset(sis_5513_pci_to_isa_t *dev)
}
static void
sis_5513_apc_write(uint16_t addr, uint8_t val, void *priv)
sis_5513_apc_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t nvr_index = nvr_get_index(dev->nvr, 0);
@@ -135,7 +136,7 @@ sis_5513_apc_write(uint16_t addr, uint8_t val, void *priv)
}
static uint8_t
sis_5513_apc_read(uint16_t addr, void *priv)
sis_5513_apc_read(UNUSED(uint16_t addr), void *priv)
{
sis_5513_pci_to_isa_t *dev = (sis_5513_pci_to_isa_t *) priv;
uint8_t nvr_index = nvr_get_index(dev->nvr, 0);
@@ -1287,9 +1288,9 @@ sis_5513_pci_to_isa_init(UNUSED(const device_t *info))
acpi_set_nvr(dev->sis->acpi, dev->nvr);
/* Set up the NVR file's name. */
c = strlen(machine_get_internal_name()) + 9;
c = strlen(machine_get_nvr_name()) + 9;
dev->fn = (char *) malloc(c + 1);
sprintf(dev->fn, "%s_apc.nvr", machine_get_internal_name());
sprintf(dev->fn, "%s_apc.nvr", machine_get_nvr_name());
fp = nvr_fopen(dev->fn, "rb");
@@ -1318,7 +1319,7 @@ const device_t sis_5513_p2i_device = {
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1332,7 +1333,7 @@ const device_t sis_5572_p2i_device = {
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1347,7 +1348,7 @@ const device_t sis_5582_p2i_device = {
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1362,7 +1363,7 @@ const device_t sis_5595_1997_p2i_device = {
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1376,7 +1377,7 @@ const device_t sis_5595_p2i_device = {
.init = sis_5513_pci_to_isa_init,
.close = sis_5513_pci_to_isa_close,
.reset = sis_5513_pci_to_isa_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

2
src/chipset/sis_5571.c
View File

@@ -177,7 +177,7 @@ const device_t sis_5571_device = {
.init = sis_5571_init,
.close = sis_5571_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

3
src/chipset/sis_5571_h2p.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
@@ -451,7 +452,7 @@ const device_t sis_5571_h2p_device = {
.init = sis_5571_host_to_pci_init,
.close = sis_5571_host_to_pci_close,
.reset = sis_5571_host_to_pci_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/sis_5571_old.c
View File

@@ -732,8 +732,7 @@ sis_5571_close(void *priv)
static void *
sis_5571_init(UNUSED(const device_t *info))
{
sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t));
memset(dev, 0x00, sizeof(sis_5571_t));
sis_5571_t *dev = (sis_5571_t *) calloc(1, sizeof(sis_5571_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, memory_pci_bridge_read, memory_pci_bridge_write, dev, &dev->nb_slot);
pci_add_card(PCI_ADD_SOUTHBRIDGE, pci_isa_bridge_read, pci_isa_bridge_write, dev, &dev->sb_slot);
@@ -765,7 +764,7 @@ const device_t sis_5571_device = {
.init = sis_5571_init,
.close = sis_5571_close,
.reset = sis_5571_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

6
src/chipset/sis_5572_usb.c
View File

@@ -288,7 +288,7 @@ const device_t sis_5572_usb_device = {
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -302,7 +302,7 @@ const device_t sis_5582_usb_device = {
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -316,7 +316,7 @@ const device_t sis_5595_usb_device = {
.init = sis_5572_usb_init,
.close = sis_5572_usb_close,
.reset = sis_5572_usb_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

2
src/chipset/sis_5581.c
View File

@@ -177,7 +177,7 @@ const device_t sis_5581_device = {
.init = sis_5581_init,
.close = sis_5581_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

3
src/chipset/sis_5581_h2p.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
@@ -545,7 +546,7 @@ const device_t sis_5581_h2p_device = {
.init = sis_5581_host_to_pci_init,
.close = sis_5581_host_to_pci_close,
.reset = sis_5581_host_to_pci_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

4
src/chipset/sis_5591.c
View File

@@ -189,7 +189,7 @@ const device_t sis_5591_1997_device = {
.init = sis_5591_init,
.close = sis_5591_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -203,7 +203,7 @@ const device_t sis_5591_device = {
.init = sis_5591_init,
.close = sis_5591_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

3
src/chipset/sis_5591_h2p.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
@@ -486,7 +487,7 @@ const device_t sis_5591_h2p_device = {
.init = sis_5591_host_to_pci_init,
.close = sis_5591_host_to_pci_close,
.reset = sis_5591_host_to_pci_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

6
src/chipset/sis_5595_pmu.c
View File

@@ -119,7 +119,7 @@ sis_5595_pmu_trap_io_mask(int size, uint16_t addr, uint8_t write, uint8_t val, v
}
static void
sis_5595_pmu_trap_io_ide_bm(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
sis_5595_pmu_trap_io_ide_bm(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
{
sis_5595_pmu_io_trap_t *trap = (sis_5595_pmu_io_trap_t *) priv;
sis_5595_pmu_t *dev = (sis_5595_pmu_t *) trap->priv;
@@ -433,7 +433,7 @@ const device_t sis_5595_1997_pmu_device = {
.init = sis_5595_pmu_init,
.close = sis_5595_pmu_close,
.reset = sis_5595_pmu_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -447,7 +447,7 @@ const device_t sis_5595_pmu_device = {
.init = sis_5595_pmu_init,
.close = sis_5595_pmu_close,
.reset = sis_5595_pmu_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

2
src/chipset/sis_55xx.c
View File

@@ -89,7 +89,7 @@ const device_t sis_55xx_common_device = {
.init = sis_55xx_common_init,
.close = sis_55xx_common_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

4
src/chipset/sis_5600.c
View File

@@ -189,7 +189,7 @@ const device_t sis_5600_1997_device = {
.init = sis_5600_init,
.close = sis_5600_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -203,7 +203,7 @@ const device_t sis_5600_device = {
.init = sis_5600_init,
.close = sis_5600_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

3
src/chipset/sis_5600_h2p.c
View File

@@ -22,6 +22,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
@@ -427,7 +428,7 @@ const device_t sis_5600_h2p_device = {
.init = sis_5600_host_to_pci_init,
.close = sis_5600_host_to_pci_close,
.reset = sis_5600_host_to_pci_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/sis_85c310.c
View File

@@ -130,8 +130,7 @@ rabbit_close(void *priv)
static void *
rabbit_init(UNUSED(const device_t *info))
{
rabbit_t *dev = (rabbit_t *) malloc(sizeof(rabbit_t));
memset(dev, 0, sizeof(rabbit_t));
rabbit_t *dev = (rabbit_t *) calloc(1, sizeof(rabbit_t));
io_sethandler(0x0022, 0x0002, rabbit_read, NULL, NULL, rabbit_write, NULL, NULL, dev);
@@ -146,7 +145,7 @@ const device_t rabbit_device = {
.init = rabbit_init,
.close = rabbit_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/sis_85c496.c
View File

@@ -637,8 +637,7 @@ static void
*
sis_85c496_init(const device_t *info)
{
sis_85c496_t *dev = malloc(sizeof(sis_85c496_t));
memset(dev, 0x00, sizeof(sis_85c496_t));
sis_85c496_t *dev = calloc(1, sizeof(sis_85c496_t));
dev->smram = smram_add();
@@ -702,7 +701,7 @@ const device_t sis_85c496_device = {
.init = sis_85c496_init,
.close = sis_85c496_close,
.reset = sis_85c496_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -716,7 +715,7 @@ const device_t sis_85c496_ls486e_device = {
.init = sis_85c496_init,
.close = sis_85c496_close,
.reset = sis_85c496_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

579
src/chipset/sis_85c4xx.c
View File

@@ -15,6 +15,7 @@
*
* Copyright 2019-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -33,27 +34,384 @@
#include <86box/mem.h>
#include <86box/smram.h>
#include <86box/pic.h>
#include <86box/plat_fallthrough.h>
#include <86box/keyboard.h>
#include <86box/machine.h>
#include <86box/chipset.h>
typedef struct ram_bank_t {
uint32_t virt_base;
uint32_t virt_size;
uint32_t phys_base;
uint32_t phys_size;
mem_mapping_t mapping;
} ram_bank_t;
typedef struct sis_85c4xx_t {
uint8_t cur_reg;
uint8_t tries;
uint8_t reg_base;
uint8_t reg_last;
uint8_t reg_00;
uint8_t is_471;
uint8_t force_flush;
uint8_t shadowed;
uint8_t smram_enabled;
uint8_t pad;
uint8_t regs[39];
uint8_t scratch[2];
uint32_t mem_state[8];
smram_t *smram;
port_92_t *port_92;
uint8_t cur_reg;
uint8_t tries;
uint8_t reg_base;
uint8_t reg_last;
uint8_t reg_00;
uint8_t is_471;
uint8_t ram_banks_val;
uint8_t force_flush;
uint8_t shadowed;
uint8_t smram_enabled;
uint8_t pad;
uint8_t regs[39];
uint8_t scratch[2];
uint32_t mem_state[8];
ram_bank_t ram_banks[8];
smram_t * smram;
port_92_t * port_92;
} sis_85c4xx_t;
static uint8_t ram_4xx[64] = { 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00,
0x04, 0x00, 0x05, 0x00, 0x0b, 0x00, 0x00, 0x00,
0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00,
0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00,
0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09,
0x04, 0x04, 0x05, 0x05, 0x0b, 0x0b, 0x0b, 0x0b,
0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d,
0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e,
0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f,
0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d,
0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d, 0x3d };
static uint8_t ram_asus[64] = { 0x00, 0x00, 0x01, 0x10, 0x10, 0x20, 0x03, 0x11,
0x11, 0x05, 0x05, 0x12, 0x12, 0x13, 0x13, 0x13,
0x13, 0x21, 0x06, 0x14, 0x14, 0x15, 0x15, 0x15,
0x15, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
0x1d, 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17,
0x17, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
0x1e, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f,
0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f };
static uint8_t ram_tg486g[64] = { 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11,
0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13,
0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 0x15,
0x15, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d, 0x1d,
0x1d, 0x16, 0x16, 0x16, 0x16, 0x17, 0x17, 0x17,
0x17, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e,
0x1e, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f,
0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f };
static uint32_t banks_471[64][4] = { { 0x00100000, 0x00000000, 0x00000000, 0x00000000 }, /* 0x00 */
{ 0x00100000, 0x00100000, 0x00000000, 0x00000000 },
{ 0x00100000, 0x00100000, 0x00200000, 0x00000000 },
{ 0x00100000, 0x00100000, 0x00400000, 0x00000000 },
{ 0x00100000, 0x00100000, 0x00200000, 0x00400000 },
{ 0x00100000, 0x00100000, 0x00400000, 0x00400000 },
{ 0x00100000, 0x00100000, 0x01000000, 0x00000000 },
{ 0x00200000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00200000, 0x00200000, 0x00000000, 0x00000000 }, /* 0x08 */
{ 0x00200000, 0x00400000, 0x00000000, 0x00000000 },
{ 0x00200000, 0x00200000, 0x00400000, 0x00000000 },
{ 0x00200000, 0x00200000, 0x00400000, 0x00400000 },
{ 0x00200000, 0x01000000, 0x00000000, 0x00000000 },
{ 0x00200000, 0x00200000, 0x01000000, 0x00000000 },
{ 0x00200000, 0x00200000, 0x00400000, 0x01000000 },
{ 0x00200000, 0x00200000, 0x01000000, 0x01000000 },
{ 0x00400000, 0x00000000, 0x00000000, 0x00000000 }, /* 0x10 */
{ 0x00400000, 0x00400000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x00400000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x00400000, 0x00400000 },
{ 0x00400000, 0x01000000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x01000000, 0x00000000 },
{ 0x00400000, 0x01000000, 0x01000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x01000000, 0x01000000 },
{ 0x00800000, 0x00000000, 0x00000000, 0x00000000 }, /* 0x18 */
{ 0x00800000, 0x00800000, 0x00000000, 0x00000000 },
{ 0x00800000, 0x00800000, 0x00800000, 0x00000000 },
{ 0x00800000, 0x00800000, 0x00800000, 0x00800000 },
{ 0x01000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x01000000, 0x01000000, 0x00000000, 0x00000000 },
{ 0x01000000, 0x01000000, 0x01000000, 0x00000000 },
{ 0x01000000, 0x01000000, 0x01000000, 0x01000000 },
{ 0x00100000, 0x00400000, 0x00000000, 0x00000000 }, /* 0x20 */
{ 0x00100000, 0x01000000, 0x00000000, 0x00000000 },
{ 0x00100000, 0x04000000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x00800000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x04000000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x04000000, 0x00000000 },
{ 0x01000000, 0x04000000, 0x00000000, 0x00000000 },
{ 0x01000000, 0x01000000, 0x04000000, 0x00000000 },
{ 0x04000000, 0x00000000, 0x00000000, 0x00000000 }, /* 0x28 */
{ 0x04000000, 0x04000000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x02000000, 0x00000000, 0x00000000 },
{ 0x00400000, 0x02000000, 0x02000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x02000000, 0x00000000 },
{ 0x00400000, 0x00400000, 0x02000000, 0x02000000 },
{ 0x01000000, 0x02000000, 0x00000000, 0x00000000 },
{ 0x01000000, 0x02000000, 0x02000000, 0x00000000 },
{ 0x01000000, 0x01000000, 0x02000000, 0x00000000 }, /* 0x30 */
{ 0x01000000, 0x01000000, 0x02000000, 0x02000000 },
{ 0x02000000, 0x00000000, 0x00000000, 0x00000000 },
{ 0x02000000, 0x02000000, 0x00000000, 0x00000000 },
{ 0x02000000, 0x02000000, 0x02000000, 0x00000000 },
{ 0x02000000, 0x02000000, 0x02000000, 0x02000000 },
{ 0x00400000, 0x00800000, 0x00800000, 0x00000000 },
{ 0x00400000, 0x00800000, 0x00800000, 0x00800000 },
{ 0x00400000, 0x00400000, 0x00800000, 0x00000000 }, /* 0x38 */
{ 0x00400000, 0x00400000, 0x00800000, 0x00800000 },
{ 0x00800000, 0x01000000, 0x00000000, 0x00000000 },
{ 0x00800000, 0x00800000, 0x00800000, 0x01000000 },
{ 0x00800000, 0x00800000, 0x01000000, 0x00000000 },
{ 0x00800000, 0x00800000, 0x01000000, 0x01000000 },
{ 0x00800000, 0x00800000, 0x02000000, 0x00000000 },
{ 0x00800000, 0x00800000, 0x02000000, 0x02000000 } };
static uint32_t
sis_85c471_get_row(ram_bank_t *dev, uint32_t addr)
{
uint32_t ret = 0x00000000;
switch (dev->virt_size) {
case 0x00100000:
case 0x00200000:
ret |= (addr >> 13) & 0x00000001;
ret |= ((addr >> 12) & 0x00000001) << 1;
ret |= ((addr >> 14) & 0x0000003f) << 2;
ret |= ((addr >> 11) & 0x00000001) << 8;
ret |= ((addr >> 20) & 0x00000001) << 9;
ret |= ((addr >> 22) & 0x00000001) << 10;
ret |= ((addr >> 24) & 0x00000001) << 11;
break;
case 0x00400000:
case 0x00800000:
ret |= (addr >> 13) & 0x00000001;
ret |= ((addr >> 12) & 0x00000001) << 1;
ret |= ((addr >> 14) & 0x000000ff) << 2;
ret |= ((addr >> 22) & 0x00000001) << 10;
ret |= ((addr >> 24) & 0x00000001) << 11;
break;
case 0x01000000:
case 0x02000000:
case 0x04000000:
ret |= (addr >> 13) & 0x00000001;
ret |= ((addr >> 22) & 0x00000001) << 1;
ret |= ((addr >> 14) & 0x000000ff) << 2;
ret |= ((addr >> 23) & 0x00000001) << 10;
ret |= ((addr >> 24) & 0x00000001) << 11;
break;
}
return ret;
}
static uint32_t
sis_85c471_get_col(ram_bank_t *dev, uint32_t addr)
{
uint32_t ret = 0x00000000;
switch (dev->virt_size) {
case 0x00100000:
case 0x00200000:
ret |= (addr >> 3) & 0x00000001;
ret |= ((addr >> 2) & 0x00000001) << 1;
ret |= ((addr >> 4) & 0x0000003f) << 2;
ret |= ((addr >> 10) & 0x00000001) << 8;
ret |= ((addr >> 21) & 0x00000001) << 9;
ret |= ((addr >> 23) & 0x00000001) << 10;
ret |= ((addr >> 25) & 0x00000001) << 11;
break;
case 0x00400000:
case 0x00800000:
ret |= (addr >> 3) & 0x00000001;
ret |= ((addr >> 2) & 0x00000001) << 1;
ret |= ((addr >> 4) & 0x000000ff) << 2;
ret |= ((addr >> 23) & 0x00000001) << 10;
ret |= ((addr >> 25) & 0x00000001) << 11;
break;
case 0x01000000:
case 0x02000000:
case 0x04000000:
ret |= (addr >> 3) & 0x00000001;
ret |= ((addr >> 2) & 0x00000001) << 1;
ret |= ((addr >> 4) & 0x000001ff) << 2;
ret |= ((addr >> 25) & 0x00000001) << 11;
break;
}
return ret;
}
static uint32_t
sis_85c471_set_row(ram_bank_t *dev, uint32_t addr)
{
uint32_t ret = 0x00000000;
switch (dev->phys_size) {
case 0x00100000:
ret = (addr & 0x1ff) << 11;
break;
case 0x00200000:
ret = (addr & 0x3ff) << 11;
break;
case 0x00400000:
ret = (addr & 0x3ff) << 12;
break;
case 0x00800000:
ret = (addr & 0x7ff) << 12;
break;
case 0x01000000:
ret = (addr & 0x7ff) << 13;
break;
case 0x02000000:
ret = (addr & 0xfff) << 13;
break;
case 0x04000000:
ret = (addr & 0xfff) << 14;
break;
}
return ret;
}
static uint32_t
sis_85c471_set_col(ram_bank_t *dev, uint32_t addr)
{
uint32_t ret = 0x00000000;
switch (dev->phys_size) {
case 0x00100000:
case 0x00200000:
ret = (addr & 0x1ff) << 2;
break;
case 0x00400000:
case 0x00800000:
ret = (addr & 0x3ff) << 2;
break;
case 0x01000000:
case 0x02000000:
ret = (addr & 0x7ff) << 2;
break;
case 0x04000000:
ret = (addr & 0xfff) << 2;
break;
}
return ret;
}
uint8_t reg09 = 0x00;
static uint8_t
sis_85c471_read_ram(uint32_t addr, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint8_t ret = 0xff;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
ret = ram[addr];
return ret;
}
static uint16_t
sis_85c471_read_ramw(uint32_t addr, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint16_t ret = 0xffff;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
ret = *(uint16_t *) &(ram[addr]);
return ret;
}
static uint32_t
sis_85c471_read_raml(uint32_t addr, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint32_t ret = 0xffffffff;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
ret = *(uint32_t *) &(ram[addr]);
return ret;
}
static void
sis_85c471_write_ram(uint32_t addr, uint8_t val, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
ram[addr] = val;
}
static void
sis_85c471_write_ramw(uint32_t addr, uint16_t val, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
*(uint16_t *) &(ram[addr]) = val;
}
static void
sis_85c471_write_raml(uint32_t addr, uint32_t val, void *priv)
{
ram_bank_t *dev = (ram_bank_t *) priv;
uint32_t rel = addr - dev->virt_base;
uint32_t row = sis_85c471_set_row(dev, sis_85c471_get_row(dev, rel));
uint32_t col = sis_85c471_set_col(dev, sis_85c471_get_col(dev, rel));
uint32_t dw = rel & 0x00000003;
rel = row | col | dw;
addr = (rel + dev->phys_base);
if ((addr < (mem_size << 10)) && (rel < dev->phys_size))
*(uint32_t *) &(ram[addr]) = val;
}
static void
sis_85c4xx_recalcremap(sis_85c4xx_t *dev)
{
@@ -158,6 +516,62 @@ sis_85c4xx_sw_smi_handler(sis_85c4xx_t *dev)
NULL, NULL, NULL, sis_85c4xx_sw_smi_out, NULL, NULL, dev);
}
static void
sis_85c471_banks_split(uint32_t *b_ex, uint32_t *banks)
{
for (uint8_t i = 0; i < 4; i++) {
if ((banks[i] == 0x00200000) || (banks[i] == 0x00800000) ||
(banks[i] == 0x02000000))
b_ex[i << 1] = b_ex[(i << 1) + 1] = banks[i] >> 1;
else {
b_ex[i << 1] = banks[i];
b_ex[(i << 1) + 1] = 0x00000000;
}
}
}
static void
sis_85c471_banks_recalc(sis_85c4xx_t *dev)
{
reg09 = dev->regs[0x09];
for (uint8_t i = 0; i < 8; i++)
mem_mapping_disable(&dev->ram_banks[i].mapping);
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_high_mapping);
mem_set_mem_state_both(1 << 20, 127 << 20, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL);
if ((dev->regs[0x09] & 0x3f) == dev->ram_banks_val) {
if (mem_size > 1024) {
mem_mapping_enable(&ram_low_mapping);
mem_mapping_enable(&ram_high_mapping);
mem_set_mem_state_both(1 << 20, (mem_size << 10) - (1 << 20),
MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
} else {
uint8_t banks_val = dev->regs[0x09] & 0x3f;
uint32_t *banks = banks_471[banks_val];
uint32_t b_ex[8] = { 0x00000000 };
uint32_t size = 0x00000000;
sis_85c471_banks_split(b_ex, banks);
for (uint8_t i = 0; i < 8; i++) if (b_ex[i] != 0x00000000) {
dev->ram_banks[i].virt_base = size;
dev->ram_banks[i].virt_size = b_ex[i];
mem_mapping_set_addr(&dev->ram_banks[i].mapping, size, b_ex[i]);
size += b_ex[i];
}
mem_set_mem_state_both(1 << 20, 127 << 20, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
}
flushmmucache_nopc();
}
static void
sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
{
@@ -174,12 +588,25 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
case 0x23:
if ((dev->cur_reg >= dev->reg_base) && (dev->cur_reg <= dev->reg_last)) {
valxor = val ^ dev->regs[rel_reg];
if (rel_reg == 0x00)
if (!dev->is_471 && (rel_reg == 0x00))
dev->regs[rel_reg] = (dev->regs[rel_reg] & 0x1f) | (val & 0xe0);
else
dev->regs[rel_reg] = val;
switch (rel_reg) {
case 0x00:
if (dev->is_471) {
if (val & 0x01) {
kbc_at_set_fast_reset(0);
cpu_cpurst_on_sr = 1;
} else {
kbc_at_set_fast_reset(1);
cpu_cpurst_on_sr = 0;
}
}
break;
case 0x01:
cpu_cache_ext_enabled = ((val & 0x84) == 0x84);
cpu_update_waitstates();
@@ -190,6 +617,13 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
case 0x08:
if (valxor)
sis_85c4xx_recalcmapping(dev);
if ((rel_reg == 0x08) && dev->is_471)
flushmmucache();
break;
case 0x09:
if (dev->is_471)
sis_85c471_banks_recalc(dev);
break;
case 0x0b:
@@ -198,6 +632,41 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
sis_85c4xx_recalcremap(dev);
break;
case 0x10:
if (dev->reg_base == 0x50) {
double bus_clk;
switch (val & 0xe0) {
default:
case 0x00:
bus_clk = 7159091.0;
break;
case 0x02:
bus_clk = cpu_busspeed / 10.0;
break;
case 0x04:
bus_clk = cpu_busspeed / 8.0;
break;
case 0x06:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x80:
bus_clk = cpu_busspeed / 5.0;
break;
case 0xa0:
bus_clk = cpu_busspeed / 4.0;
break;
case 0xc0:
bus_clk = cpu_busspeed / 3.0;
break;
case 0xe0:
bus_clk = cpu_busspeed / 2.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
}
break;
case 0x13:
if (dev->is_471 && (valxor & 0xf0)) {
smram_disable(dev->smram);
@@ -297,14 +766,6 @@ sis_85c4xx_reset(void *priv)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;
int mem_size_mb = mem_size >> 10;
static uint8_t ram_4xx[64] = { 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x00, 0x0b, 0x00, 0x00, 0x00,
0x19, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1b, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
static uint8_t ram_471[64] = { 0x00, 0x00, 0x01, 0x01, 0x02, 0x20, 0x09, 0x09, 0x04, 0x04, 0x05, 0x05, 0x0b, 0x0b, 0x0b, 0x0b,
0x13, 0x21, 0x06, 0x06, 0x0d, 0x0d, 0x0d, 0x0d, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e,
0x1b, 0x1b, 0x1b, 0x1b, 0x0f, 0x0f, 0x0f, 0x0f, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e };
memset(dev->regs, 0x00, sizeof(dev->regs));
@@ -313,13 +774,44 @@ sis_85c4xx_reset(void *priv)
if (dev->is_471) {
dev->regs[0x09] = 0x40;
if (mem_size_mb >= 64) {
if ((mem_size_mb >= 65) && (mem_size_mb < 68))
dev->regs[0x09] |= 0x22;
if (!strcmp(machine_get_internal_name(), "vli486sv2g")) {
if (mem_size_mb == 64)
dev->regs[0x09] |= 0x1f;
else
dev->regs[0x09] |= 0x24;
} else
dev->regs[0x09] |= ram_asus[mem_size_mb];
} else if (mem_size_mb >= 64) {
if ((mem_size_mb >= 64) && (mem_size_mb < 68))
dev->regs[0x09] |= 0x33;
else if ((mem_size_mb >= 68) && (mem_size_mb < 72))
dev->regs[0x09] |= 0x2b;
else if ((mem_size_mb >= 72) && (mem_size_mb < 80))
dev->regs[0x09] |= 0x2d;
else if ((mem_size_mb >= 80) && (mem_size_mb < 96))
dev->regs[0x09] |= 0x2f;
else if ((mem_size_mb >= 96) && (mem_size_mb < 128))
dev->regs[0x09] |= 0x34;
else
dev->regs[0x09] |= 0x35;
} else if (!strcmp(machine_get_internal_name(), "tg486g"))
dev->regs[0x09] |= ram_tg486g[mem_size_mb];
else
dev->regs[0x09] |= ram_471[mem_size_mb];
dev->ram_banks_val = dev->regs[0x09] & 0x3f;
dev->regs[0x09] = 0x00;
uint32_t *banks = banks_471[dev->ram_banks_val];
uint32_t b_ex[8] = { 0x00000000 };
uint32_t size = 0x00000000;
sis_85c471_banks_split(b_ex, banks);
for (uint8_t i = 0; i < 8; i++) {
dev->ram_banks[i].phys_base = size;
dev->ram_banks[i].phys_size = b_ex[i];
size += b_ex[i];
}
dev->regs[0x11] = 0x09;
dev->regs[0x12] = 0xff;
@@ -332,6 +824,11 @@ sis_85c4xx_reset(void *priv)
port_92_remove(dev->port_92);
soft_reset_mask = 0;
sis_85c471_banks_recalc(dev);
kbc_at_set_fast_reset(1);
cpu_cpurst_on_sr = 0;
} else {
/* Bits 6 and 7 must be clear on the SiS 40x. */
if (dev->reg_base == 0x60)
@@ -352,6 +849,9 @@ sis_85c4xx_reset(void *priv)
dev->force_flush = 1;
sis_85c4xx_recalcmapping(dev);
if (dev->reg_base == 0x50)
cpu_set_isa_speed((int) round(7159091.0));
}
static void
@@ -368,19 +868,26 @@ sis_85c4xx_close(void *priv)
static void *
sis_85c4xx_init(const device_t *info)
{
sis_85c4xx_t *dev = (sis_85c4xx_t *) malloc(sizeof(sis_85c4xx_t));
memset(dev, 0, sizeof(sis_85c4xx_t));
sis_85c4xx_t *dev = (sis_85c4xx_t *) calloc(1, sizeof(sis_85c4xx_t));
dev->is_471 = (info->local >> 8) & 0xff;
dev->reg_base = info->local & 0xff;
if (dev->is_471) {
dev->reg_last = dev->reg_base + 0x76;
dev->reg_last = 0x76;
dev->smram = smram_add();
dev->port_92 = device_add(&port_92_device);
for (uint8_t i = 0; i < 8; i++) {
mem_mapping_add(&dev->ram_banks[i].mapping, 0x00000000, 0x00000000,
sis_85c471_read_ram, sis_85c471_read_ramw, sis_85c471_read_raml,
sis_85c471_write_ram, sis_85c471_write_ramw, sis_85c471_write_raml,
NULL, MEM_MAPPING_INTERNAL, &(dev->ram_banks[i]));
mem_mapping_disable(&dev->ram_banks[i].mapping);
}
} else
dev->reg_last = dev->reg_base + 0x11;
@@ -403,7 +910,7 @@ const device_t sis_85c401_device = {
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -417,7 +924,7 @@ const device_t sis_85c460_device = {
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -432,7 +939,7 @@ const device_t sis_85c461_device = {
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -446,7 +953,7 @@ const device_t sis_85c471_device = {
.init = sis_85c4xx_init,
.close = sis_85c4xx_close,
.reset = sis_85c4xx_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

9
src/chipset/sis_85c50x.c
View File

@@ -24,6 +24,7 @@
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/apm.h>
#include <86box/machine.h>
@@ -684,7 +685,7 @@ const device_t sis_85c50x_device = {
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -698,7 +699,7 @@ const device_t sis_550x_85c503_device = {
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -712,7 +713,7 @@ const device_t sis_85c50x_5503_device = {
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -726,7 +727,7 @@ const device_t sis_550x_device = {
.init = sis_85c50x_init,
.close = sis_85c50x_close,
.reset = sis_85c50x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

362
src/chipset/sl82c461.c Normal file
View File

@@ -0,0 +1,362 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Symphony SL82C461 (Haydn II) chipset.
*
* Symphony SL82C461 Configuration Registers (WARNING: May be inaccurate!):
*
* - Register 00h:
* - Bit 6: External cache present (if clear, AMI BIOS'es will not
* allow enabling external cache).
*
* - Register 01h:
* - Bit 0: Fast Gate A20 Enable (Handler mostly).
* Is it? Enabling/disabling fast gate A20 doesn't appear
* to do much to any register at all.
*
* - Register 02h:
* - Bit 0: Optional Chipset Turbo Pin;
* - Bits 4-2:
* - 000 = CLK2/3;
* - 001 = CLK2/4;
* - 010 = CLK2/5;
* - 011 = 7.159 MHz (ATCLK2);
* - 100 = CLK2/6;
* - 110 = CLK2/2.5;
* - 111 = CLK2/2.
*
* - Register 06h:
* - Bit 2: Decoupled Refresh Option.
*
* - Register 08h:
* - Bits 3, 2: I/O Recovery Time (SYSCLK):
* - 0, 0 = 0;
* - 1, 1 = 12.
* - Bit 1: Extended ALE.
*
* - Register 25h:
* Bit 7 here causes AMI 111192 CMOS Setup to return 7168 KB RAM
* instead of 6912 KB. This is 256 KB off. Relocation?
* Also, returning bit 5 clear instead of set, causes the AMI BIOS
* to set bits 0,1 of register 45h to 1,0 instead of 0,1.
*
* - Register 2Dh:
* - Bit 7: Enable 256KB Memory Relocation;
* - Bit 6: Enable 384KB Memory Relocation, bit 7 must also be set.
*
* - Register 2Eh:
* - Bit 7: CC000-CFFFF Shadow Read Enable;
* - Bit 6: CC000-CFFFF Shadow Write Enable;
* - Bit 5: C8000-CBFFF Shadow Read Enable;
* - Bit 4: C8000-CBFFF Shadow Write Enable;
* - Bit 3: C4000-C7FFF Shadow Read Enable;
* - Bit 2: C4000-C7FFF Shadow Write Enable;
* - Bit 1: C0000-C3FFF Shadow Read Enable;
* - Bit 0: C0000-C3FFF Shadow Write Enable.
*
* - Register 2Fh:
* - Bit 7: DC000-DFFFF Shadow Read Enable;
* - Bit 6: DC000-DFFFF Shadow Write Enable;
* - Bit 5: D8000-DBFFF Shadow Read Enable;
* - Bit 4: D8000-DBFFF Shadow Write Enable;
* - Bit 3: D4000-D7FFF Shadow Read Enable;
* - Bit 2: D4000-D7FFF Shadow Write Enable;
* - Bit 1: D0000-D3FFF Shadow Read Enable;
* - Bit 0: D0000-D3FFF Shadow Write Enable.
*
* - Register 30h:
* - Bit 7: E0000-EFFFF Shadow Read Enable;
* - Bit 6: E0000-EFFFF Shadow Write Enable.
*
* - Register 31h:
* - Bit 7: F0000-FFFFF Shadow Read Enable;
* - Bit 6: F0000-FFFFF Shadow Write Enable.
*
* - Register 33h (NOTE: Waitstates also affect register 32h):
* - Bits 3, 0:
* - 0,0 = 0 W/S;
* - 1,0 = 1 W/S;
* - 1,1 = 2 W/S.
*
* - Register 40h:
* - Bit 3: External Cache Enabled (0 = yes, 1 = no);
* I also see bits 5, 4, 3 of register 44h affected:
* - 38h (so all 3 set) when cache is disabled;
* - 00h (all 3 clear) when it's enabled.
*
* - Register 45h:
* - Bit 3: Video Shadow RAM Cacheable;
* - Bit 4: Adapter Shadow RAM Cacheable;
* - Bit 5: BIOS Shadow RAM Cacheable.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
* Copyright 2025 Miran Grca.
* Copyright 2021-2025 Tiseno100.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/chipset.h>
typedef struct {
uint8_t index;
uint8_t regs[256];
uint8_t shadow[4];
} sl82c461_t;
#ifdef ENABLE_SL82C461_LOG
int sl82c461_do_log = ENABLE_SL82C461_LOG;
static void
sl82c461_log(const char *fmt, ...)
{
va_list ap;
if (sl82c461_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define sl82c461_log(fmt, ...)
#endif
static void
sl82c461_recalcmapping(sl82c461_t *dev)
{
int do_shadow = 0;
for (uint32_t i = 0; i < 8; i += 2) {
if ((dev->regs[0x2e] ^ dev->shadow[0x00]) & (3 << i)) {
uint32_t base = 0x000c0000 + ((i >> 1) << 14);
uint32_t read = ((dev->regs[0x2e] >> i) & 0x02) ? MEM_READ_INTERNAL :
MEM_READ_EXTANY;
uint32_t write = ((dev->regs[0x2e] >> i) & 0x01) ? MEM_WRITE_INTERNAL :
MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x00004000, read | write);
do_shadow++;
}
if ((dev->regs[0x2f] ^ dev->shadow[0x01]) & (3 << i)) {
uint32_t base = 0x000d0000 + ((i >> 1) << 14);
uint32_t read = ((dev->regs[0x2f] >> i) & 0x02) ? MEM_READ_INTERNAL :
MEM_READ_EXTANY;
uint32_t write = ((dev->regs[0x2f] >> i) & 0x01) ? MEM_WRITE_INTERNAL :
MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x00004000, read | write);
do_shadow++;
}
}
if ((dev->regs[0x30] ^ dev->shadow[0x02]) & 0xc0) {
uint32_t base = 0x000e0000;
uint32_t read = ((dev->regs[0x30] >> 6) & 0x02) ? MEM_READ_INTERNAL :
MEM_READ_EXTANY;
uint32_t write = ((dev->regs[0x30] >> 6) & 0x01) ? MEM_WRITE_INTERNAL :
MEM_WRITE_EXTANY;
mem_set_mem_state_both(base, 0x00010000, read | write);
do_shadow++;
}
if ((dev->regs[0x31] ^ dev->shadow[0x03]) & 0xc0) {
uint32_t base = 0x000f0000;
uint32_t read = ((dev->regs[0x31] >> 6) & 0x02) ? MEM_READ_INTERNAL :
MEM_READ_EXTANY;
uint32_t write = ((dev->regs[0x31] >> 6) & 0x01) ? MEM_WRITE_INTERNAL :
MEM_WRITE_EXTANY;
shadowbios = !!((dev->regs[0x31] >> 6) & 0x02);
shadowbios_write = !!((dev->regs[0x31] >> 6) & 0x01);
mem_set_mem_state_both(base, 0x00010000, read | write);
do_shadow++;
}
if (do_shadow) {
memcpy(dev->shadow, &(dev->regs[0x2e]), 4 * sizeof(uint8_t));
flushmmucache_nopc();
}
}
static void
sl82c461_write(uint16_t addr, uint8_t val, void *priv)
{
sl82c461_t *dev = (sl82c461_t *) priv;
sl82c461_log("[%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, addr, val);
if (addr & 0x0001) {
dev->regs[dev->index] = val;
switch (dev->index) {
case 0x01:
/* NOTE: This is to be verified. */
mem_a20_alt = val & 1;
mem_a20_recalc();
break;
case 0x02: {
double bus_clk;
switch (val & 0x1c) {
case 0x00:
bus_clk = cpu_busspeed / 3.0;
break;
case 0x04:
bus_clk = cpu_busspeed / 4.0;
break;
case 0x08:
bus_clk = cpu_busspeed / 5.0;
break;
default:
case 0x0c:
bus_clk = 7159091.0;
break;
case 0x10:
bus_clk = cpu_busspeed / 6.0;
break;
case 0x18:
bus_clk = cpu_busspeed / 2.5;
break;
case 0x1c:
bus_clk = cpu_busspeed / 2.0;
break;
}
cpu_set_isa_speed((int) round(bus_clk));
break;
} case 0x2d:
switch (val & 0xc0) {
case 0xc0:
mem_remap_top(384);
break;
case 0x80:
mem_remap_top(256);
break;
default:
case 0x00:
mem_remap_top(0);
break;
}
break;
case 0x2e ... 0x31:
sl82c461_recalcmapping(dev);
break;
case 0x33:
switch (val & 0x09) {
default:
case 0x00:
cpu_waitstates = 0;
break;
case 0x08:
cpu_waitstates = 1;
break;
case 0x09:
cpu_waitstates = 2;
break;
}
cpu_update_waitstates();
break;
case 0x40:
cpu_cache_ext_enabled = !(val & 0x08);
cpu_update_waitstates();
break;
}
} else
dev->index = val;
}
static uint8_t
sl82c461_read(uint16_t addr, void *priv)
{
sl82c461_t *dev = (sl82c461_t *) priv;
uint8_t ret = 0x00;
if (addr & 0x0001)
if (dev->index == 0x00)
ret = dev->regs[dev->index] | 0x40;
else
ret = dev->regs[dev->index];
else
ret = dev->index;
sl82c461_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
return ret;
}
static void
sl82c461_close(void *priv)
{
sl82c461_t *dev = (sl82c461_t *) priv;
free(dev);
}
static void *
sl82c461_init(const device_t *info)
{
sl82c461_t *dev = (sl82c461_t *) calloc(1, sizeof(sl82c461_t));
dev->regs[0x00] = 0x40;
dev->regs[0x02] = 0x0c;
dev->regs[0x40] = 0x08;
memset(dev->shadow, 0xff, 4 * sizeof(uint8_t));
mem_a20_alt = 0x00;
mem_a20_recalc();
cpu_set_isa_speed(7159091.0);
sl82c461_recalcmapping(dev);
cpu_waitstates = 0;
cpu_cache_ext_enabled = 0;
cpu_update_waitstates();
io_sethandler(0x00a8, 2,
sl82c461_read, NULL, NULL,
sl82c461_write, NULL, NULL, dev);
return dev;
}
const device_t sl82c461_device = {
.name = "Symphony SL82C461 (Haydn II)",
.internal_name = "sis_85c471",
.flags = 0,
.local = 0,
.init = sl82c461_init,
.close = sl82c461_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

54
src/chipset/stpc.c
View File

@@ -912,8 +912,7 @@ stpc_init(const device_t *info)
{
stpc_log("STPC: init()\n");
stpc_t *dev = (stpc_t *) malloc(sizeof(stpc_t));
memset(dev, 0, sizeof(stpc_t));
stpc_t *dev = (stpc_t *) calloc(1, sizeof(stpc_t));
dev->local = info->local;
@@ -963,8 +962,7 @@ stpc_serial_init(UNUSED(const device_t *info))
{
stpc_log("STPC: serial_init()\n");
stpc_serial_t *dev = (stpc_serial_t *) malloc(sizeof(stpc_serial_t));
memset(dev, 0, sizeof(stpc_serial_t));
stpc_serial_t *dev = (stpc_serial_t *) calloc(1, sizeof(stpc_serial_t));
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
@@ -977,39 +975,24 @@ stpc_serial_init(UNUSED(const device_t *info))
static void
stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
{
uint8_t old_addr = (dev->reg1 & 0x03);
uint8_t new_addr = (val & 0x03);
const uint8_t new_addr = (val & 0x03);
switch (old_addr) {
case 0x1:
lpt3_remove();
break;
case 0x2:
lpt1_remove();
break;
case 0x3:
lpt2_remove();
break;
default:
break;
}
lpt1_remove();
switch (new_addr) {
case 0x1:
stpc_log("STPC: Remapping parallel port to LPT3\n");
lpt3_init(0x3bc);
lpt1_setup(LPT_MDA_ADDR);
break;
case 0x2:
stpc_log("STPC: Remapping parallel port to LPT1\n");
lpt1_init(0x378);
lpt1_setup(LPT1_ADDR);
break;
case 0x3:
stpc_log("STPC: Remapping parallel port to LPT2\n");
lpt2_init(0x278);
lpt1_setup(LPT2_ADDR);
break;
default:
@@ -1017,9 +1000,11 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
break;
}
dev->reg1 = (val & 0x08);
dev->reg1 |= new_addr;
dev->reg1 |= 0x84; /* reserved bits that default to 1; hardwired? */
if (dev != NULL) {
dev->reg1 = (val & 0x08);
dev->reg1 |= new_addr;
dev->reg1 |= 0x84; /* reserved bits that default to 1; hardwired? */
}
}
static void
@@ -1076,8 +1061,7 @@ stpc_lpt_init(UNUSED(const device_t *info))
{
stpc_log("STPC: lpt_init()\n");
stpc_lpt_t *dev = (stpc_lpt_t *) malloc(sizeof(stpc_lpt_t));
memset(dev, 0, sizeof(stpc_lpt_t));
stpc_lpt_t *dev = (stpc_lpt_t *) calloc(1, sizeof(stpc_lpt_t));
stpc_lpt_reset(dev);
@@ -1096,7 +1080,7 @@ const device_t stpc_client_device = {
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1110,7 +1094,7 @@ const device_t stpc_consumer2_device = {
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1124,7 +1108,7 @@ const device_t stpc_elite_device = {
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1138,7 +1122,7 @@ const device_t stpc_atlas_device = {
.init = stpc_init,
.close = stpc_close,
.reset = stpc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1153,7 +1137,7 @@ const device_t stpc_serial_device = {
.init = stpc_serial_init,
.close = stpc_serial_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1167,7 +1151,7 @@ const device_t stpc_lpt_device = {
.init = stpc_lpt_init,
.close = stpc_lpt_close,
.reset = stpc_lpt_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

11
src/chipset/umc_8886.c
View File

@@ -82,6 +82,8 @@
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/keyboard.h>
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/port_92.h>
@@ -392,8 +394,7 @@ umc_8886_close(void *priv)
static void *
umc_8886_init(const device_t *info)
{
umc_8886_t *dev = (umc_8886_t *) malloc(sizeof(umc_8886_t));
memset(dev, 0, sizeof(umc_8886_t));
umc_8886_t *dev = (umc_8886_t *) calloc(1, sizeof(umc_8886_t));
/* Device 12: UMC 8886xx */
pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev, &dev->pci_slot);
@@ -431,7 +432,7 @@ const device_t umc_8886f_device = {
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -445,7 +446,7 @@ const device_t umc_8886af_device = {
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -459,7 +460,7 @@ const device_t umc_8886bf_device = {
.init = umc_8886_init,
.close = umc_8886_close,
.reset = umc_8886_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

5
src/chipset/umc_8890.c
View File

@@ -38,6 +38,7 @@
#include <86box/smram.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_UMC_8890_LOG
int umc_8890_do_log = ENABLE_UMC_8890_LOG;
@@ -209,7 +210,7 @@ umc_8890_close(void *priv)
static void *
umc_8890_init(const device_t *info)
umc_8890_init(UNUSED(const device_t *info))
{
umc_8890_t *dev = (umc_8890_t *) calloc(1, sizeof(umc_8890_t));
@@ -234,7 +235,7 @@ const device_t umc_8890_device = {
.init = umc_8890_init,
.close = umc_8890_close,
.reset = umc_8890_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

58
src/chipset/umc_hb4.c
View File

@@ -270,6 +270,8 @@ hb4_smram(hb4_t *dev)
}
umc_smram_recalc(dev->smram_base >> 12, 1);
flushmmucache();
}
static void
@@ -398,60 +400,10 @@ hb4_close(void *priv)
free(dev);
}
static void
ims8848_write(uint16_t addr, uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *) priv;
switch (addr) {
case 0x22:
dev->idx = val;
break;
case 0x23:
if (((val & 0x0f) == ((dev->idx >> 4) & 0x0f)) && ((val & 0xf0) == ((dev->idx << 4) & 0xf0)))
dev->access_data = 1;
break;
case 0x24:
if (dev->access_data)
dev->access_data = 0;
break;
default:
break;
}
}
static uint8_t
ims8848_read(uint16_t addr, void *priv)
{
uint8_t ret = 0xff;
hb4_t *dev = (hb4_t *) priv;
switch (addr) {
case 0x22:
ret = dev->idx;
break;
case 0x23:
ret = (dev->idx >> 4) | (dev->idx << 4);
break;
case 0x24:
if (dev->access_data) {
ret = dev->pci_conf[dev->idx];
dev->access_data = 0;
}
break;
default:
break;
}
return ret;
}
static void *
hb4_init(UNUSED(const device_t *info))
{
hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));
hb4_t *dev = (hb4_t *) calloc(1, sizeof(hb4_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev, &dev->pci_slot); /* Device 10: UMC 8881x */
@@ -464,8 +416,6 @@ hb4_init(UNUSED(const device_t *info))
dev->smram_base = 0x000a0000;
hb4_reset(dev);
io_sethandler(0x0022, 0x0003, ims8848_read, NULL, NULL, ims8848_write, NULL, NULL, dev);
return dev;
}
@@ -477,7 +427,7 @@ const device_t umc_hb4_device = {
.init = hb4_init,
.close = hb4_close,
.reset = hb4_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

19
src/chipset/via_apollo.c
View File

@@ -725,8 +725,7 @@ via_apollo_reset(void *priv)
static void *
via_apollo_init(const device_t *info)
{
via_apollo_t *dev = (via_apollo_t *) malloc(sizeof(via_apollo_t));
memset(dev, 0, sizeof(via_apollo_t));
via_apollo_t *dev = (via_apollo_t *) calloc(1, sizeof(via_apollo_t));
dev->smram = smram_add();
if (dev->id != VIA_8601)
@@ -793,7 +792,7 @@ const device_t via_vpx_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -807,7 +806,7 @@ const device_t amd640_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -821,7 +820,7 @@ const device_t via_vp3_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -835,7 +834,7 @@ const device_t via_mvp3_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -849,7 +848,7 @@ const device_t via_apro_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -863,7 +862,7 @@ const device_t via_apro133_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -877,7 +876,7 @@ const device_t via_apro133a_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -891,7 +890,7 @@ const device_t via_vt8601_device = {
.init = via_apollo_init,
.close = via_apollo_close,
.reset = via_apollo_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

175
src/chipset/via_pipc.c
View File

@@ -59,8 +59,10 @@
listings on forums, as VIA's datasheets are not very helpful regarding those. */
#define VIA_PIPC_586A 0x05862500
#define VIA_PIPC_586B 0x05864700
#define VIA_PIPC_586 0x0586
#define VIA_PIPC_596A 0x05960900
#define VIA_PIPC_596B 0x05962300
#define VIA_PIPC_596 0x0596
#define VIA_PIPC_686A 0x06861400
#define VIA_PIPC_686B 0x06864000
#define VIA_PIPC_8231 0x82311000
@@ -413,7 +415,9 @@ pipc_reset_hard(void *priv)
dev->power_regs[0x34] = 0x68;
dev->power_regs[0x40] = 0x20;
dev->power_regs[0x42] = 0x50;
dev->power_regs[0x42] = ((dev->local >> 16) == VIA_PIPC_586) ? 0x00 : 0x50;
acpi_set_irq_line(dev->acpi, 0x00);
dev->power_regs[0x48] = 0x01;
if (dev->local == VIA_PIPC_686B) {
@@ -489,14 +493,28 @@ pipc_reset_hard(void *priv)
}
dev->ac97_regs[i][0x1c] = 0x01;
if (i == 0) {
dev->ac97_regs[i][0x34] = 0xc0;
dev->ac97_regs[i][0xc0] = 0x01;
dev->ac97_regs[i][0xc1] = 0x00;
dev->ac97_regs[i][0xc2] = 0x03;
dev->ac97_regs[i][0xc3] = 0x00;
dev->ac97_regs[i][0xc4] = 0x00;
dev->ac97_regs[i][0xc5] = 0x00;
dev->ac97_regs[i][0xc6] = 0x00;
dev->ac97_regs[i][0xc7] = 0x00;
}
dev->ac97_regs[i][0x3d] = 0x03;
if (i == 0)
if (i == 0) {
dev->ac97_regs[i][0x40] = 0x01;
dev->ac97_regs[i][0x43] = 0x1c;
dev->ac97_regs[i][0x48] = 0x01;
dev->ac97_regs[i][0x4b] = 0x02;
dev->ac97_regs[i][0x43] = 0x1c;
dev->ac97_regs[i][0x48] = 0x01;
dev->ac97_regs[i][0x4b] = 0x00;
}
pipc_sgd_handlers(dev, i);
pipc_codec_handlers(dev, i);
@@ -738,10 +756,12 @@ pipc_codec_handlers(pipc_t *dev, uint8_t modem)
if (!dev->ac97)
return;
uint32_t base = (dev->ac97_regs[modem][0x1d] << 8);
if (modem)
ac97_via_remap_modem_codec(dev->ac97, dev->ac97_regs[1][0x1d] << 8, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO);
ac97_via_remap_modem_codec(dev->ac97, base, dev->ac97_regs[1][0x04] & PCI_COMMAND_IO);
else
ac97_via_remap_audio_codec(dev->ac97, dev->ac97_regs[0][0x1d] << 8, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO);
ac97_via_remap_audio_codec(dev->ac97, base, dev->ac97_regs[0][0x04] & PCI_COMMAND_IO);
}
static uint8_t
@@ -1200,7 +1220,7 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
case 0x77:
if ((dev->local >= VIA_PIPC_686A) && (val & 0x10))
pclog("PIPC: Warning: Internal I/O APIC enabled.\n");
warning("PIPC: Warning: Internal I/O APIC enabled.\n");
nvr_via_wp_set(!!(val & 0x04), 0x32, dev->nvr);
nvr_via_wp_set(!!(val & 0x02), 0x0d, dev->nvr);
break;
@@ -1484,36 +1504,39 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
break;
}
} else if (func <= pm_func + 2) { /* AC97 / MC97 */
/* Read-only addresses. */
if ((addr < 0x4) || ((addr >= 0x6) && (addr < 0x9)) || ((addr >= 0xc) && (addr < 0x11)) || (addr == 0x16) || (addr == 0x17) || (addr == 0x1a) || (addr == 0x1b) || ((addr >= 0x1e) && (addr < 0x2c)) || ((addr >= 0x30) && (addr < 0x34)) || ((addr >= 0x35) && (addr < 0x3c)) || ((addr >= 0x3d) && (addr < 0x41)) || ((addr >= 0x45) && (addr < 0x4a)) || (addr >= 0x4c))
return;
/* Small shortcut. */
func = func - pm_func - 1;
/* Check disable bits and specific read-only addresses for both controllers. */
if ((func == 0) && (((addr >= 0x09) && (addr < 0xc)) || (addr == 0x44) || (dev->pci_isa_regs[0x85] & 0x04)))
/* Check disable bits. */
if ((func == 0) && (dev->pci_isa_regs[0x85] & 0x04))
return;
if ((func == 1) && ((addr == 0x14) || (addr == 0x15) || (addr == 0x18) || (addr == 0x19) || (addr == 0x42) || (addr == 0x43) || (addr == 0x48) || (addr == 0x4a) || (addr == 0x4b) || (dev->pci_isa_regs[0x85] & 0x08)))
if ((func == 1) && (dev->pci_isa_regs[0x85] & 0x08))
return;
switch (addr) {
case 0x04:
dev->ac97_regs[func][addr] = val;
dev->ac97_regs[func][addr] = val & 0x01;
pipc_sgd_handlers(dev, func);
if (func == 0) {
pipc_fmnmi_handlers(dev, func);
pipc_sb_handlers(dev, func);
}
pipc_codec_handlers(dev, func);
pipc_fmnmi_handlers(dev, func);
break;
case 0x09:
case 0x0a:
case 0x0b:
if (dev->ac97_regs[func][0x44] & 0x20)
/* Not writable on audio, only on modem. */
if ((func == 1) && (dev->ac97_regs[func][0x44] & 0x20))
dev->ac97_regs[func][addr] = val;
break;
case 0x10:
/*
The lowest 10 bytes are always 0x01, indicating
a 256-byte I/O space.
*/
case 0x11:
dev->ac97_regs[func][addr] = val;
pipc_sgd_handlers(dev, func);
@@ -1521,21 +1544,26 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
case 0x14:
case 0x15:
if (addr == 0x14)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_fmnmi_handlers(dev, func);
/* Not present on modem. */
if (func == 0) {
if (addr == 0x14)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_fmnmi_handlers(dev, func);
}
break;
case 0x18:
case 0x19:
if (addr == 0x18)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_sb_handlers(dev, func);
/* Not present on modem. */
if (func == 0) {
if (addr == 0x18)
val = (val & 0xfc) | 1;
dev->ac97_regs[func][addr] = val;
pipc_sb_handlers(dev, func);
}
break;
case 0x1c:
case 0x1d:
dev->ac97_regs[func][addr] = val;
pipc_codec_handlers(dev, func);
@@ -1545,39 +1573,84 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
case 0x2d:
case 0x2e:
case 0x2f:
if ((func == 0) && (dev->ac97_regs[func][0x42] & 0x20))
if (((func == 0) && (dev->ac97_regs[func][0x42] & 0x20)) ||
((func == 1) && (dev->ac97_regs[func][0x44] & 0x10)))
dev->ac97_regs[func][addr] = val;
break;
case 0x3c:
dev->ac97_regs[func][addr] = val & 0x0f;
break;
case 0x41:
dev->ac97_regs[func][addr] = val;
ac97_via_write_control(dev->ac97, func, val);
break;
case 0x42:
case 0x4a:
case 0x4b:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val;
gameport_remap(dev->gameport, (dev->ac97_regs[0][0x42] & 0x08) ? ((dev->ac97_regs[0][0x4b] << 8) | (dev->ac97_regs[0][0x4a] & 0xf8)) : 0);
if (addr == 0x42)
pipc_sb_handlers(dev, func);
case 0x4a ... 0x4b:
if (func == 0) {
dev->ac97_regs[func][addr] = val;
gameport_remap(dev->gameport, (dev->ac97_regs[func][0x42] & 0x08) ?
((dev->ac97_regs[func][0x4b] << 8) |
(dev->ac97_regs[func][0x4a] & 0xf8)) : 0);
if (addr == 0x42)
pipc_sb_handlers(dev, func);
}
break;
case 0x43:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val;
if (func == 0)
dev->ac97_regs[func][addr] = val;
break;
case 0x44:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0xf0;
if (func == 1)
dev->ac97_regs[func][addr] = val & 0xf0;
break;
case 0x45:
case 0x48:
dev->ac97_regs[0][addr] = dev->ac97_regs[1][addr] = val & 0x0f;
if (func == 0)
dev->ac97_regs[func][addr] = val & 0x0f;
break;
case 0x80:
case 0x81:
case 0x82:
dev->ac97_regs[func][addr] = val;
break;
case 0x83:
dev->ac97_regs[func][addr] = ((dev->ac97_regs[func][addr] & 0x01) |
(val & 0xc0)) & ~(val & 0x0a);
break;
case 0x88:
case 0x89:
dev->ac97_regs[func][addr] = val;
break;
case 0x8a:
case 0x8b:
dev->ac97_regs[func][addr] &= ~val;
break;
case 0x8e:
case 0x8f:
dev->ac97_regs[func][addr] = val;
break;
case 0xc4:
if (func == 0)
dev->ac97_regs[func][addr] = (dev->ac97_regs[func][addr] & 0x0c) |
(val & 0x03);
break;
case 0xc5:
if (func == 0)
dev->ac97_regs[func][addr] = (dev->ac97_regs[func][addr] & 0x60) |
(val & 0x9f);
break;
default:
dev->ac97_regs[func][addr] = val;
break;
}
}
@@ -1593,6 +1666,9 @@ pipc_reset(void *priv)
pipc_write(pm_func, 0x48, 0x01, priv);
pipc_write(pm_func, 0x49, 0x00, priv);
dev->power_regs[0x42] = ((dev->local >> 16) == VIA_PIPC_586) ? 0x00 : 0x50;
acpi_set_irq_line(dev->acpi, 0x00);
pipc_write(1, 0x04, 0x80, priv);
pipc_write(1, 0x09, 0x85, priv);
pipc_write(1, 0x10, 0xf1, priv);
@@ -1627,8 +1703,7 @@ pipc_reset(void *priv)
static void *
pipc_init(const device_t *info)
{
pipc_t *dev = (pipc_t *) malloc(sizeof(pipc_t));
memset(dev, 0, sizeof(pipc_t));
pipc_t *dev = (pipc_t *) calloc(1, sizeof(pipc_t));
pipc_log("PIPC: init()\n");
@@ -1695,6 +1770,8 @@ pipc_init(const device_t *info)
acpi_set_nvr(dev->acpi, dev->nvr);
acpi_init_gporeg(dev->acpi, 0xff, 0xbf, 0xff, 0x7f);
acpi_set_irq_mode(dev->acpi, 0);
}
return dev;
@@ -1721,7 +1798,7 @@ const device_t via_vt82c586b_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1735,7 +1812,7 @@ const device_t via_vt82c596a_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1749,7 +1826,7 @@ const device_t via_vt82c596b_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1763,7 +1840,7 @@ const device_t via_vt82c686a_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1777,7 +1854,7 @@ const device_t via_vt82c686b_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -1791,7 +1868,7 @@ const device_t via_vt8231_device = {
.init = pipc_init,
.close = pipc_close,
.reset = pipc_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

15
src/chipset/via_vt82c49x.c
View File

@@ -275,8 +275,8 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
case 0x71:
if (dev->has_ide) {
ide_pri_disable();
ide_set_base(0, (val & 0x40) ? 0x170 : 0x1f0);
ide_set_side(0, (val & 0x40) ? 0x376 : 0x3f6);
ide_set_base(0, (val & 0x40) ? HDC_SECONDARY_BASE : HDC_PRIMARY_BASE);
ide_set_side(0, (val & 0x40) ? HDC_SECONDARY_SIDE : HDC_PRIMARY_SIDE);
if (val & 0x01)
ide_pri_enable();
vt82c49x_log("VT82C496 IDE now %sabled as %sary\n", (val & 0x01) ? "en" : "dis",
@@ -342,8 +342,7 @@ vt82c49x_close(void *priv)
static void *
vt82c49x_init(const device_t *info)
{
vt82c49x_t *dev = (vt82c49x_t *) malloc(sizeof(vt82c49x_t));
memset(dev, 0x00, sizeof(vt82c49x_t));
vt82c49x_t *dev = (vt82c49x_t *) calloc(1, sizeof(vt82c49x_t));
dev->smram_smm = smram_add();
dev->smram_low = smram_add();
@@ -375,7 +374,7 @@ const device_t via_vt82c49x_device = {
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -389,7 +388,7 @@ const device_t via_vt82c49x_pci_device = {
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = vt82c49x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -403,7 +402,7 @@ const device_t via_vt82c49x_ide_device = {
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -417,7 +416,7 @@ const device_t via_vt82c49x_pci_ide_device = {
.init = vt82c49x_init,
.close = vt82c49x_close,
.reset = vt82c49x_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

7
src/chipset/via_vt82c505.c
View File

@@ -167,7 +167,7 @@ vt82c505_in(uint16_t addr, void *priv)
static void
vt82c505_reset(void *priv)
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
vt82c505_t *dev = (vt82c505_t *) calloc(1, sizeof(vt82c505_t));
dev->pci_conf[0x04] = 0x07;
dev->pci_conf[0x07] = 0x00;
@@ -204,8 +204,7 @@ vt82c505_close(void *priv)
static void *
vt82c505_init(UNUSED(const device_t *info))
{
vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
memset(dev, 0, sizeof(vt82c505_t));
vt82c505_t *dev = (vt82c505_t *) calloc(1, sizeof(vt82c505_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, vt82c505_read, vt82c505_write, dev, &dev->pci_slot);
@@ -232,7 +231,7 @@ const device_t via_vt82c505_device = {
.init = vt82c505_init,
.close = vt82c505_close,
.reset = vt82c505_reset,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

109
src/chipset/vl82c480.c
View File

@@ -24,14 +24,16 @@
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/port_92.h>
#include <86box/chipset.h>
typedef struct vl82c480_t {
uint8_t idx;
uint8_t regs[256];
uint8_t idx;
uint8_t regs[256];
uint32_t banks[4];
} vl82c480_t;
static int
@@ -59,7 +61,7 @@ vl82c480_shflags(uint8_t access)
}
static void
vl82c480_recalc(vl82c480_t *dev)
vl82c480_recalc_shadow(vl82c480_t *dev)
{
uint32_t base;
uint8_t access;
@@ -69,8 +71,8 @@ vl82c480_recalc(vl82c480_t *dev)
for (uint8_t i = 0; i < 6; i++) {
for (uint8_t j = 0; j < 8; j += 2) {
base = 0x000a0000 + (i << 16) + (j << 13);
access = (dev->regs[0x0d + i] >> j) & 3;
base = 0x000a0000 + (i << 16) + (j << 13);
access = (dev->regs[0x0d + i] >> j) & 3;
mem_set_mem_state(base, 0x4000, vl82c480_shflags(access));
shadowbios |= ((base >= 0xe0000) && (access & 0x02));
shadowbios_write |= ((base >= 0xe0000) && (access & 0x01));
@@ -80,6 +82,37 @@ vl82c480_recalc(vl82c480_t *dev)
flushmmucache();
}
static void
vl82c480_recalc_banks(vl82c480_t *dev)
{
uint32_t sizes[8] = { 0, 0, 1024, 2048, 4096, 8192, 16384, 32768 };
uint8_t shifts[4] = { 0, 4, 0, 4 };
uint8_t regs[4] = { 0x02, 0x02, 0x03, 0x03 };
uint32_t total = 0;
for (uint8_t i = 0; i < 4; i++) {
uint8_t shift = shifts[i];
uint8_t reg = regs[i];
uint8_t cfg = (dev->regs[reg] >> shift) & 0x7;
uint32_t size = sizes[cfg];
total += MIN(dev->banks[i], size);
}
if (total > 1024) {
mem_mapping_set_addr(&ram_low_mapping, 0x00000000, 0x000a0000);
mem_mapping_set_addr(&ram_high_mapping, 0x00100000, (total - 1024) << 10);
} else {
if (total >= 1024)
mem_mapping_set_addr(&ram_low_mapping, 0x00000000, 0x000a0000);
else
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_high_mapping);
}
flushmmucache();
}
static void
vl82c480_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -91,11 +124,18 @@ vl82c480_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0xed:
if (dev->idx >= 0x01 && dev->idx <= 0x24) {
if (((dev->idx >= 0x01) && (dev->idx <= 0x19)) ||
((dev->idx >= 0x20) && (dev->idx <= 0x24))) {
switch (dev->idx) {
default:
dev->regs[dev->idx] = val;
break;
case 0x02: case 0x03:
dev->regs[dev->idx] = val;
if (!strcmp(machine_get_internal_name(), "martin") ||
!strcmp(machine_get_internal_name(), "prolineamt"))
vl82c480_recalc_banks(dev);
break;
case 0x04:
if (dev->regs[0x00] == 0x98)
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x08) | (val & 0xf7);
@@ -108,14 +148,9 @@ vl82c480_write(uint16_t addr, uint8_t val, void *priv)
case 0x07:
dev->regs[dev->idx] = (dev->regs[dev->idx] & 0x40) | (val & 0xbf);
break;
case 0x0d:
case 0x0e:
case 0x0f:
case 0x10:
case 0x11:
case 0x12:
case 0x0d ... 0x12:
dev->regs[dev->idx] = val;
vl82c480_recalc(dev);
vl82c480_recalc_shadow(dev);
break;
}
}
@@ -124,8 +159,8 @@ vl82c480_write(uint16_t addr, uint8_t val, void *priv)
/* TODO: This is actually Fast A20 disable. */
#if 0
case 0xee:
if (mem_a20_alt)
outb(0x92, inb(0x92) & ~2);
mem_a20_alt = 0x00;
mem_a20_recalc();
break;
#endif
@@ -146,14 +181,16 @@ vl82c480_read(uint16_t addr, void *priv)
break;
case 0xed:
ret = dev->regs[dev->idx];
if (((dev->idx >= 0x01) && (dev->idx <= 0x19)) ||
((dev->idx >= 0x20) && (dev->idx <= 0x24)))
ret = dev->regs[dev->idx];
break;
/* TODO: This is actually Fast A20 enable. */
#if 0
case 0xee:
if (!mem_a20_alt)
outb(0x92, inb(0x92) | 2);
mem_a20_alt = 0x02;
mem_a20_recalc();
break;
#endif
@@ -180,8 +217,12 @@ vl82c480_close(void *priv)
static void *
vl82c480_init(const device_t *info)
{
vl82c480_t *dev = (vl82c480_t *) malloc(sizeof(vl82c480_t));
memset(dev, 0, sizeof(vl82c480_t));
vl82c480_t *dev = (vl82c480_t *) calloc(1, sizeof(vl82c480_t));
uint32_t sizes[8] = { 0, 0, 1024, 2048, 4096, 8192, 16384, 32768 };
uint32_t ms = mem_size;
uint8_t min_i = !strcmp(machine_get_internal_name(), "prolineamt") ? 1 : 0;
uint8_t min_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 4 : 2;
uint8_t max_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 8 : 7;
dev->regs[0x00] = info->local;
dev->regs[0x01] = 0xff;
@@ -192,9 +233,31 @@ vl82c480_init(const device_t *info)
dev->regs[0x07] = 0x21;
dev->regs[0x08] = 0x38;
if (!strcmp(machine_get_internal_name(), "prolineamt")) {
dev->banks[0] = 4096;
/* Bank 0 is ignored if 64 MB is installed. */
if (ms != 65536)
ms -= 4096;
}
if (ms > 0) for (uint8_t i = min_i; i < 4; i++) {
for (uint8_t j = min_j; j < max_j; j++) {
if (ms >= sizes[j])
dev->banks[i] = sizes[j];
else
break;
}
ms -= dev->banks[i];
if ((ms == 0) || (dev->banks[i] == 0))
break;
}
io_sethandler(0x00ec, 0x0004, vl82c480_read, NULL, NULL, vl82c480_write, NULL, NULL, dev);
device_add(&port_92_device);
device_add(&port_92_pci_device);
return dev;
}
@@ -207,7 +270,7 @@ const device_t vl82c480_device = {
.init = vl82c480_init,
.close = vl82c480_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
@@ -221,7 +284,7 @@ const device_t vl82c486_device = {
.init = vl82c480_init,
.close = vl82c480_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

444
src/chipset/wd76c10.c
View File

@@ -37,6 +37,7 @@
#include <86box/port_92.h>
#include <86box/serial.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/chipset.h>
/* Lock/Unlock Procedures */
@@ -64,9 +65,10 @@ wd76c10_log(const char *fmt, ...)
#endif
typedef struct {
uint32_t enable;
uint32_t phys_on, enable;
uint32_t virt_addr, phys_addr;
uint32_t virt_size, phys_size;
uint32_t adj_virt_addr, adj_virt_size;
} ram_bank_t;
typedef struct {
@@ -102,6 +104,7 @@ typedef struct
int locked;
uint32_t mem_top, hmwp_base;
uint32_t fast;
ram_bank_t ram_banks[5];
@@ -120,6 +123,40 @@ static uint32_t bank_sizes[4] = { 0x00020000, /* 64 Kbit X 16 = 1024 Kbit
0x00200000, /* 1 Mbit X 16 = 16 Mbit = 2 MB, 10x10 */
0x00800000 }; /* 4 Mbit X 16 = 64 Mbit = 8 MB, 11x11 */
static uint32_t
wd76c10_calc_phys(uint32_t row, uint32_t col, uint32_t size, uint32_t a0)
{
uint32_t ret = WD76C10_ADDR_INVALID;
switch (size) {
default:
ret = WD76C10_ADDR_INVALID;
break;
case 0x00020000:
row = (row & 0x0000ff) << 9;
col = (col & 0x0000ff) << 1;
ret = row | col | a0;
break;
case 0x00080000:
row = (row & 0x0001ff) << 10;
col = (col & 0x0001ff) << 1;
ret = row | col | a0;
break;
case 0x00200000:
row = (row & 0x0003ff) << 11;
col = (col & 0x0003ff) << 1;
ret = row | col | a0;
break;
case 0x00800000:
row = (row & 0x0007ff) << 12;
col = (col & 0x0007ff) << 1;
ret = row | col | a0;
break;
}
return ret;
}
static uint32_t
wd76c10_calc_addr(wd76c10_t *dev, uint32_t addr)
{
@@ -158,20 +195,303 @@ wd76c10_calc_addr(wd76c10_t *dev, uint32_t addr)
ret = WD76C10_ADDR_INVALID;
/* Then, handle the physical memory banks. */
int ilv4 = (dev->mem_ctl >> 8) & 4;
int8_t add = 0;
uint32_t pg = (dev->mem_ctl & 0x0800);
uint32_t nrt = WD76C10_ADDR_INVALID;
if (ret != WD76C10_ADDR_INVALID) {
if (dev->fast) for (int8_t i = 0; i < 4; i++) {
rb = &(dev->ram_banks[i]);
uint32_t ret2 = ret - rb->phys_addr;
if (rb->phys_on && (ret >= rb->phys_addr) &&
(ret < (rb->phys_addr + rb->phys_size))) {
if (ret2 < rb->phys_size)
nrt = ret2 + rb->phys_addr;
break;
}
} else for (int8_t i = 0; i < 4; i++) {
rb = &(dev->ram_banks[i]);
int ilv2 = (dev->mem_ctl >> 8) & (1 << (i >> 1));
uint32_t size = rb->virt_size;
uint32_t ret2 = ret - rb->virt_addr;
uint32_t ret4 = ret2;
uint32_t row = WD76C10_ADDR_INVALID;
uint32_t col = WD76C10_ADDR_INVALID;
uint32_t rb_or = 0;
if (ilv4) {
size <<= 2;
switch (rb->virt_size) {
default:
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00020000:
if (pg) {
row = (ret2 >> 9) & 0x0000fc;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 9) & 0x000003;
} else
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00080000:
if (pg) {
row = (ret2 >> 9) & 0x0000f8;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 10) & 0x000003;
} else
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00200000:
if (pg) {
row = (ret2 >> 9) & 0x0000f0;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 23) & 0x000001) << 3;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 11) & 0x000003;
} else
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00800000:
if (pg) {
row = (ret2 >> 9) & 0x0000e0;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 23) & 0x000001) << 3;
row |= ((ret2 >> 24) & 0x000001) << 4;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 12) & 0x000003;
} else
ret4 = WD76C10_ADDR_INVALID;
break;
}
add = 3;
} else if (ilv2) {
size <<= 1;
switch (rb->virt_size) {
default:
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00020000:
if (pg) {
row = (ret2 >> 9) & 0x0000fe;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 9) & 0x000001;
} else {
row = (ret2 >> 1) & 0x0007fe;
row |= (ret2 >> 13) & 0x000001;
col = (ret2 >> 9) & 0x0000ef;
col |= ((ret2 >> 17) & 0x000001) << 4;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
rb_or = (ret2 >> 1) & 0x000001;
}
break;
case 0x00080000:
if (pg) {
row = (ret2 >> 9) & 0x0000fc;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 10) & 0x000001;
} else {
row = (ret2 >> 1) & 0x0007fe;
row |= (ret2 >> 13) & 0x000001;
col = (ret2 >> 9) & 0x0000ee;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 19) & 0x000001) << 4;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
rb_or = (ret2 >> 1) & 0x000001;
}
break;
case 0x00200000:
if (pg) {
row = (ret2 >> 9) & 0x0000f8;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 11) & 0x000001;
} else {
row = (ret2 >> 1) & 0x0007fe;
row |= (ret2 >> 13) & 0x000001;
col = (ret2 >> 9) & 0x0000ec;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 19) & 0x000001) << 1;
col |= ((ret2 >> 21) & 0x000001) << 4;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
rb_or = (ret2 >> 1) & 0x000001;
}
break;
case 0x00800000:
if (pg) {
row = (ret2 >> 9) & 0x0000f0;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 23) & 0x000001) << 3;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x000007ff;
rb_or = (ret2 >> 12) & 0x000001;
} else {
row = (ret2 >> 1) & 0x0007fe;
row |= (ret2 >> 13) & 0x000001;
col = (ret2 >> 9) & 0x0000e0;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 19) & 0x000001) << 1;
col |= ((ret2 >> 21) & 0x000001) << 2;
col |= ((ret2 >> 23) & 0x000001) << 3;
col |= ((ret2 >> 12) & 0x000001) << 4;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
rb_or = (ret2 >> 1) & 0x000001;
}
break;
}
add = 1;
} else if (pg) switch (rb->virt_size) {
default:
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00020000:
row = (ret2 >> 9) & 0x0000ff;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x0007ff;
break;
case 0x00080000:
row = (ret2 >> 9) & 0x0000fe;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x0007ff;
break;
case 0x00200000:
row = (ret2 >> 9) & 0x0000fc;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x0007ff;
break;
case 0x00800000:
row = (ret2 >> 9) & 0x0000f8;
row |= (ret2 >> 17) & 0x000001;
row |= ((ret2 >> 19) & 0x000001) << 1;
row |= ((ret2 >> 21) & 0x000001) << 2;
row |= ((ret2 >> 18) & 0x000001) << 8;
row |= ((ret2 >> 20) & 0x000001) << 9;
row |= ((ret2 >> 22) & 0x000001) << 10;
col = (ret2 >> 1) & 0x0007ff;
break;
} else switch (rb->virt_size) {
default:
ret4 = WD76C10_ADDR_INVALID;
break;
case 0x00020000:
row = (ret2 >> 1) & 0x0007ff;
col = (ret2 >> 9) & 0x0000ff;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
break;
case 0x00080000:
row = (ret2 >> 1) & 0x0007ff;
col = (ret2 >> 9) & 0x0000fe;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
break;
case 0x00200000:
row = (ret2 >> 1) & 0x0007ff;
col = (ret2 >> 9) & 0x0000fc;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 19) & 0x000001) << 1;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
break;
case 0x00800000:
row = (ret2 >> 1) & 0x0007ff;
col = (ret2 >> 9) & 0x0000f8;
col |= (ret2 >> 17) & 0x000001;
col |= ((ret2 >> 19) & 0x000001) << 1;
col |= ((ret2 >> 21) & 0x000001) << 2;
col |= ((ret2 >> 18) & 0x000001) << 8;
col |= ((ret2 >> 20) & 0x000001) << 9;
col |= ((ret2 >> 22) & 0x000001) << 10;
break;
}
if (row != WD76C10_ADDR_INVALID) {
ret4 = wd76c10_calc_phys(row & 0x0007ff, col & 0x0007ff,
rb->phys_size, ret2 & 0x000001);
if (ilv4 || ilv2)
rb = &(dev->ram_banks[i | rb_or]);
i += add;
}
if (rb->enable && (ret >= rb->virt_addr) &&
(ret < (rb->virt_addr + size))) {
if ((ret4 != WD76C10_ADDR_INVALID) && (rb->phys_size > 0x00000000))
nrt = ret4 + rb->phys_addr;
break;
}
}
ret = nrt;
}
if (ret >= (mem_size << 10))
/* The physical memory address is too high or disabled, which is invalid. */
ret = WD76C10_ADDR_INVALID;
/* Otherwise, map it to the correct bank so the BIOS can auto-size it correctly. */
else for (uint8_t i = 0; i < 4; i++) {
rb = &(dev->ram_banks[i]);
if (rb->enable && (ret >= rb->virt_addr) && (ret < (rb->virt_addr + rb->virt_size))) {
if (rb->phys_size == 0x00000000)
ret = WD76C10_ADDR_INVALID;
else
ret = ((ret - rb->virt_addr) % rb->phys_size) + rb->phys_addr;
break;
}
}
return ret;
}
@@ -184,8 +504,12 @@ wd76c10_read_ram(uint32_t addr, void *priv)
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
ret = mem_read_ram(addr, priv);
if (addr != WD76C10_ADDR_INVALID) {
if (dev->fast)
ret = mem_read_ram(addr, priv);
else
ret = ram[addr];
}
return ret;
}
@@ -198,8 +522,12 @@ wd76c10_read_ramw(uint32_t addr, void *priv)
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
ret = mem_read_ramw(addr, priv);
if (addr != WD76C10_ADDR_INVALID) {
if (dev->fast)
ret = mem_read_ramw(addr, priv);
else
ret = *(uint16_t *) &(ram[addr]);
}
return ret;
}
@@ -211,8 +539,12 @@ wd76c10_write_ram(uint32_t addr, uint8_t val, void *priv)
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
mem_write_ram(addr, val, priv);
if (addr != WD76C10_ADDR_INVALID) {
if (dev->fast)
mem_write_ram(addr, val, priv);
else
ram[addr] = val;
}
}
static void
@@ -222,8 +554,12 @@ wd76c10_write_ramw(uint32_t addr, uint16_t val, void *priv)
addr = wd76c10_calc_addr(dev, addr);
if (addr != WD76C10_ADDR_INVALID)
mem_write_ramw(addr, val, priv);
if (addr != WD76C10_ADDR_INVALID) {
if (dev->fast)
mem_write_ramw(addr, val, priv);
else
*(uint16_t *) &(ram[addr]) = val;
}
}
static void
@@ -257,6 +593,9 @@ wd76c10_recalc_exec(wd76c10_t *dev, uint32_t base, uint32_t size)
static void
wd76c10_banks_recalc(wd76c10_t *dev)
{
int match = 0;
dev->fast = 0;
for (uint8_t i = 0; i < 4; i++) {
ram_bank_t *rb = &(dev->ram_banks[i]);
uint8_t bit = i << 1;
@@ -265,8 +604,42 @@ wd76c10_banks_recalc(wd76c10_t *dev)
rb->enable = (dev->split_sa >> bit) & 0x01;
rb->virt_addr = ((uint32_t) dev->bank_bases[i]) << 17;
if (rb->enable) {
rb->adj_virt_addr = rb->virt_addr;
rb->adj_virt_size = rb->virt_size;
if (dev->mem_ctl & 0x0400)
rb->adj_virt_addr += (i * rb->adj_virt_size);
else if ((dev->mem_ctl >> 8) & (1 << (i >> 1)))
rb->adj_virt_addr += ((i & 1) * rb->adj_virt_size);
} else {
rb->adj_virt_addr = WD76C10_ADDR_INVALID;
rb->adj_virt_size = 0x00000000;
}
if ((rb->enable == rb->phys_on) &&
(rb->adj_virt_addr == rb->phys_addr) &&
(rb->adj_virt_size == rb->phys_size))
match++;
}
dev->fast = (match == 4);
for (uint8_t i = 0; i < 4; i++) {
ram_bank_t *rb = &(dev->ram_banks[i]);
if (cpu_use_exec)
wd76c10_recalc_exec(dev, rb->virt_addr, rb->virt_size);
wd76c10_log("Bank %i (%s), physical: %i, %08X-%08X, "
"virtual: %i, %08X-%08X, adj.: %i, %08X-%08X\n",
i, dev->fast ? "FAST" : "SLOW",
rb->phys_on,
rb->phys_addr, rb->phys_addr + rb->phys_size - 1,
rb->enable,
rb->virt_addr, rb->virt_addr + rb->virt_size - 1,
rb->enable,
rb->adj_virt_addr, rb->adj_virt_addr + rb->adj_virt_size - 1);
}
}
@@ -541,16 +914,16 @@ wd76c10_ser_par_cs_recalc(wd76c10_t *dev)
lpt1_remove();
switch ((dev->ser_par_cs >> 9) & 0x03) {
case 1:
lpt1_init(0x3bc);
lpt1_irq(7);
lpt1_setup(LPT_MDA_ADDR);
lpt1_irq(LPT1_IRQ);
break;
case 2:
lpt1_init(0x378);
lpt1_irq(7);
lpt1_setup(LPT1_ADDR);
lpt1_irq(LPT1_IRQ);
break;
case 3:
lpt1_init(0x278);
lpt1_irq(7);
lpt1_setup(LPT2_ADDR);
lpt1_irq(LPT1_IRQ);
break;
}
}
@@ -879,12 +1252,12 @@ wd76c10_reset(void *priv)
static void *
wd76c10_init(const device_t *info)
wd76c10_init(UNUSED(const device_t *info))
{
wd76c10_t *dev = (wd76c10_t *) calloc(1, sizeof(wd76c10_t));
uint32_t total_mem = mem_size << 10;
uint32_t accum_mem = 0x00000000;
ram_bank_t *rb;
ram_bank_t *rb = NULL;
/* Calculate the physical RAM banks. */
for (uint8_t i = 0; i < 4; i++) {
@@ -898,11 +1271,22 @@ wd76c10_init(const device_t *info)
}
}
if (size != 0x00000000) {
rb->phys_on = 1;
rb->phys_addr = accum_mem;
rb->phys_size = size;
wd76c10_log("Bank %i size: %5i KiB, starting at %5i KiB\n", i, rb->phys_size >> 10, rb->phys_addr >> 10);
total_mem -= size;
accum_mem += size;
}
} else
rb->phys_addr = WD76C10_ADDR_INVALID;
}
if (mem_size == 3072) {
/* Reorganize the banks a bit so, we have 2048, 0, 512, 512. */
ram_bank_t rt = dev->ram_banks[3];
dev->ram_banks[3] = dev->ram_banks[2];
dev->ram_banks[2] = dev->ram_banks[1];
dev->ram_banks[1] = rt;
}
rb = &(dev->ram_banks[4]);
@@ -1022,7 +1406,7 @@ const device_t wd76c10_device = {
.init = wd76c10_init,
.close = wd76c10_close,
.reset = NULL,
{ .available = NULL },
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL

60
src/codegen/codegen_ops_arith.h
View File

@@ -1,5 +1,5 @@
static uint32_t
ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropINC_rw(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
@@ -22,7 +22,7 @@ ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc;
}
static uint32_t
ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropINC_rl(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
@@ -45,7 +45,7 @@ ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc;
}
static uint32_t
ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropDEC_rw(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
@@ -68,7 +68,7 @@ ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc;
}
static uint32_t
ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropDEC_rl(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
@@ -93,7 +93,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
#define ROP_ARITH_RMW(name, op, writeback) \
static uint32_t \
rop##name##_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_b_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -129,7 +129,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_w_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -165,7 +165,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_l_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -203,7 +203,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
#define ROP_ARITH_RM(name, op, writeback) \
static uint32_t \
rop##name##_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_b_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -233,7 +233,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_w_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -263,7 +263,7 @@ ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_l_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -299,7 +299,7 @@ ROP_ARITH_RM(ADD, ADD, 1)
ROP_ARITH_RM(SUB, SUB, 1)
static uint32_t
ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_b_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -326,7 +326,7 @@ ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, c
return op_pc + 1;
}
static uint32_t
ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_w_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -353,7 +353,7 @@ ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, c
return op_pc + 1;
}
static uint32_t
ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_l_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -381,7 +381,7 @@ ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, c
}
static uint32_t
ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_b_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -408,7 +408,7 @@ ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_w_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -435,7 +435,7 @@ ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_l_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -463,7 +463,7 @@ ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
}
static uint32_t
ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropADD_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -478,7 +478,7 @@ ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropADD_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -493,7 +493,7 @@ ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropADD_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -510,7 +510,7 @@ ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
}
static uint32_t
ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -525,7 +525,7 @@ ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -540,7 +540,7 @@ ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropCMP_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -557,7 +557,7 @@ ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
}
static uint32_t
ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropSUB_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -572,7 +572,7 @@ ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropSUB_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -587,7 +587,7 @@ ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropSUB_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -604,7 +604,7 @@ ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
}
static uint32_t
rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
rop80(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
uint32_t imm;
@@ -679,7 +679,7 @@ rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblo
}
static uint32_t
rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
rop81_w(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
uint32_t imm;
@@ -753,7 +753,7 @@ rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc + 3;
}
static uint32_t
rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
rop81_l(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
uint32_t imm;
@@ -827,7 +827,7 @@ rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
}
static uint32_t
rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
rop83_w(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
uint32_t imm;
@@ -904,7 +904,7 @@ rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc + 2;
}
static uint32_t
rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
rop83_l(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
uint32_t imm;

206
src/codegen/codegen_ops_fpu.h
View File

@@ -1,5 +1,5 @@
static uint32_t
ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFXCH(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
@@ -9,7 +9,7 @@ ropFXCH(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
}
static uint32_t
ropFLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFLD(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
@@ -19,7 +19,7 @@ ropFLD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codebl
}
static uint32_t
ropFST(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFST(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
@@ -28,7 +28,7 @@ ropFST(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codebl
return op_pc;
}
static uint32_t
ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSTP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
@@ -39,7 +39,7 @@ ropFSTP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
}
static uint32_t
ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFLDs(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -57,7 +57,7 @@ ropFLDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc + 1;
}
static uint32_t
ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFLDd(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -76,7 +76,7 @@ ropFLDd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
}
static uint32_t
ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFILDw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -94,7 +94,7 @@ ropFILDw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc + 1;
}
static uint32_t
ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFILDl(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -112,7 +112,7 @@ ropFILDl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc + 1;
}
static uint32_t
ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFILDq(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -133,7 +133,7 @@ ropFILDq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
}
static uint32_t
ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSTs(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;
@@ -153,7 +153,7 @@ ropFSTs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc + 1;
}
static uint32_t
ropFSTd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSTd(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg1;
@@ -194,24 +194,28 @@ ropFSTPd(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return new_pc;
}
#define ropFarith(name, size, load, op) \
static uint32_t \
ropF##name##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(FPU_##name); \
\
return op_pc + 1; \
#define ropFarith(name, size, load, op) \
static uint32_t \
ropF##name##size(UNUSED(uint8_t opcode), \
uint32_t fetchdat, \
uint32_t op_32, \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(FPU_##name); \
\
return op_pc + 1; \
}
ropFarith(ADD, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
@@ -239,32 +243,40 @@ ropFarith(MUL, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUB, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUBR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
#define ropFcompare(name, size, load, op) \
static uint32_t \
ropF##name##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(); \
\
return op_pc + 1; \
} \
static uint32_t ropF##name##P##size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t new_pc = ropF##name##size(opcode, fetchdat, op_32, op_pc, block); \
\
FP_POP(); \
\
return new_pc; \
#define ropFcompare(name, size, load, op) \
static uint32_t \
ropF##name##size(UNUSED(uint8_t opcode), \
uint32_t fetchdat, \
uint32_t op_32, \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
x86seg *target_seg; \
\
FP_ENTER(); \
op_pc--; \
target_seg = FETCH_EA(op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32); \
\
STORE_IMM_ADDR_L((uintptr_t) &cpu_state.oldpc, op_old_pc); \
\
CHECK_SEG_READ(target_seg); \
load(target_seg); \
\
op(); \
\
return op_pc + 1; \
} \
static uint32_t ropF##name##P##size(uint8_t opcode, \
uint32_t fetchdat, \
uint32_t op_32, \
uint32_t op_pc, \
codeblock_t *block) \
{ \
uint32_t new_pc = ropF##name##size(opcode, fetchdat, op_32, op_pc, block); \
\
FP_POP(); \
\
return new_pc; \
}
ropFcompare(COM, s, MEM_LOAD_ADDR_EA_L, FP_COMPARE_S);
@@ -348,7 +360,7 @@ ropFSUBs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
#endif
static uint32_t
ropFADD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFADD(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_ADD, 0, opcode & 7);
@@ -356,7 +368,7 @@ ropFADD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
static uint32_t
ropFCOM(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFCOM(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
@@ -364,7 +376,7 @@ ropFCOM(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
static uint32_t
ropFDIV(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIV(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIV, 0, opcode & 7);
@@ -372,7 +384,7 @@ ropFDIV(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
static uint32_t
ropFDIVR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIVR(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, 0, opcode & 7);
@@ -380,7 +392,7 @@ ropFDIVR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFMUL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFMUL(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_MUL, 0, opcode & 7);
@@ -388,7 +400,7 @@ ropFMUL(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
static uint32_t
ropFSUB(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUB(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUB, 0, opcode & 7);
@@ -396,7 +408,7 @@ ropFSUB(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
static uint32_t
ropFSUBR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUBR(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, 0, opcode & 7);
@@ -405,7 +417,7 @@ ropFSUBR(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
}
static uint32_t
ropFADDr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFADDr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
@@ -413,7 +425,7 @@ ropFADDr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFDIVr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIVr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
@@ -421,7 +433,7 @@ ropFDIVr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFDIVRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIVRr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
@@ -429,7 +441,7 @@ ropFDIVRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc;
}
static uint32_t
ropFMULr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFMULr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
@@ -437,7 +449,7 @@ ropFMULr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFSUBr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUBr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
@@ -445,7 +457,7 @@ ropFSUBr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFSUBRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUBRr(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
@@ -454,7 +466,7 @@ ropFSUBRr(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
}
static uint32_t
ropFADDP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFADDP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_ADD, opcode & 7, 0);
@@ -463,7 +475,7 @@ ropFADDP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFCOMP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_COMPARE_REG(0, opcode & 7);
@@ -472,7 +484,7 @@ ropFCOMP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIVP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIV, opcode & 7, 0);
@@ -481,7 +493,7 @@ ropFDIVP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFDIVRP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_DIVR, opcode & 7, 0);
@@ -490,7 +502,7 @@ ropFDIVRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return op_pc;
}
static uint32_t
ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFMULP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_MUL, opcode & 7, 0);
@@ -499,7 +511,7 @@ ropFMULP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUBP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUB, opcode & 7, 0);
@@ -508,7 +520,7 @@ ropFSUBP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc;
}
static uint32_t
ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSUBRP(uint8_t opcode, UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_OP_REG(FPU_SUBR, opcode & 7, 0);
@@ -518,7 +530,7 @@ ropFSUBRP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
}
static uint32_t
ropFCOMPP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFCOMPP(UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_COMPARE_REG(0, 1);
@@ -528,7 +540,7 @@ ropFCOMPP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
}
static uint32_t
ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSTSW_AX(UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
@@ -540,7 +552,7 @@ ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, c
}
static uint32_t
ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFISTw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;
@@ -560,7 +572,7 @@ ropFISTw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc + 1;
}
static uint32_t
ropFISTl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFISTl(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;
@@ -599,7 +611,7 @@ ropFISTPl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
return new_pc;
}
static uint32_t
ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFISTPq(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg1;
@@ -623,7 +635,7 @@ ropFISTPq(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
}
static uint32_t
ropFLDCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFLDCW(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
@@ -640,7 +652,7 @@ ropFLDCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
return op_pc + 1;
}
static uint32_t
ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFSTCW(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg;
x86seg *target_seg;
@@ -658,7 +670,7 @@ ropFSTCW(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, code
}
static uint32_t
ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropFCHS(UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_FCHS();
@@ -666,17 +678,21 @@ ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return op_pc;
}
#define opFLDimm(name, v) \
static uint32_t \
ropFLD##name(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
static double fp_imm = v; \
static uint64_t *fptr = (uint64_t *) &fp_imm; \
\
FP_ENTER(); \
FP_LOAD_IMM_Q(*fptr); \
\
return op_pc; \
#define opFLDimm(name, v) \
static uint32_t \
ropFLD##name(UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), \
UNUSED(uint32_t op_32), \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
static double fp_imm = v; \
static uint64_t *fptr = (uint64_t *) &fp_imm; \
\
FP_ENTER(); \
FP_LOAD_IMM_Q(*fptr); \
\
return op_pc; \
}
// clang-format off
@@ -689,7 +705,7 @@ opFLDimm(Z, 0.0)
// clang-format on
static uint32_t
ropFLDLN2(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
ropFLDLN2(UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
FP_ENTER();
FP_LOAD_IMM_Q(0x3fe62e42fefa39f0ULL);

94
src/codegen/codegen_ops_jump.h
View File

@@ -1,5 +1,5 @@
static uint32_t
ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropJMP_r8(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
uint32_t offset = fetchdat & 0xff;
@@ -12,7 +12,7 @@ ropJMP_r8(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, cod
}
static uint32_t
ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropJMP_r16(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
uint16_t offset = fetchdat & 0xffff;
@@ -22,7 +22,7 @@ ropJMP_r16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, co
}
static uint32_t
ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropJMP_r32(UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
uint32_t offset = fastreadl(cs + op_pc);
@@ -32,7 +32,7 @@ ropJMP_r32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, co
}
static uint32_t
ropJCXZ(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropJCXZ(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
uint32_t offset = fetchdat & 0xff;
@@ -51,7 +51,7 @@ ropJCXZ(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
}
static uint32_t
ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropLOOP(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
uint32_t offset = fetchdat & 0xff;
@@ -214,45 +214,51 @@ BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int not )
}
}
#define ropBRANCH(name, func, not ) \
static uint32_t \
rop##name(uint8_t opcode, uint32_t fetchdat, \
uint32_t op_32, uint32_t op_pc, \
codeblock_t *block) \
{ \
uint32_t offset = fetchdat & 0xff; \
\
if (offset & 0x80) \
offset |= 0xffffff00; \
\
func(1, op_pc, offset, not ); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w(uint8_t opcode, \
uint32_t fetchdat, uint32_t op_32, \
uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t offset = fetchdat & 0xffff; \
\
if (offset & 0x8000) \
offset |= 0xffff0000; \
\
func(2, op_pc, offset, not ); \
\
return op_pc + 2; \
} \
static uint32_t \
rop##name##_l(uint8_t opcode, \
uint32_t fetchdat, uint32_t op_32, \
uint32_t op_pc, codeblock_t *block) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
\
func(4, op_pc, offset, not ); \
\
return op_pc + 4; \
#define ropBRANCH(name, func, not ) \
static uint32_t \
rop##name(UNUSED(uint8_t opcode), \
uint32_t fetchdat, \
UNUSED(uint32_t op_32), \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
uint32_t offset = fetchdat & 0xff; \
\
if (offset & 0x80) \
offset |= 0xffffff00; \
\
func(1, op_pc, offset, not ); \
\
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w(UNUSED(uint8_t opcode), \
uint32_t fetchdat, \
UNUSED(uint32_t op_32), \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
uint32_t offset = fetchdat & 0xffff; \
\
if (offset & 0x8000) \
offset |= 0xffff0000; \
\
func(2, op_pc, offset, not ); \
\
return op_pc + 2; \
} \
static uint32_t \
rop##name##_l(UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), \
UNUSED(uint32_t op_32), \
uint32_t op_pc, \
UNUSED(codeblock_t *block)) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
\
func(4, op_pc, offset, not ); \
\
return op_pc + 4; \
}
// clang-format off

48
src/codegen/codegen_ops_logic.h
View File

@@ -1,6 +1,6 @@
#define ROP_LOGIC(name, op, writeback) \
static uint32_t \
rop##name##_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_b_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -33,7 +33,7 @@
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_w_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -66,7 +66,7 @@
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_l_rmw(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -99,7 +99,7 @@
return op_pc + 1; \
} \
static uint32_t \
rop##name##_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_b_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -126,7 +126,7 @@
return op_pc + 1; \
} \
static uint32_t \
rop##name##_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_w_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -153,7 +153,7 @@
return op_pc + 1; \
} \
static uint32_t \
rop##name##_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
rop##name##_l_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block)) \
{ \
int src_reg; \
int dst_reg; \
@@ -185,7 +185,7 @@ ROP_LOGIC(OR, OR, 1)
ROP_LOGIC(XOR, XOR, 1)
static uint32_t
ropTEST_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_b_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -209,7 +209,7 @@ ropTEST_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropTEST_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_w_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -233,7 +233,7 @@ ropTEST_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropTEST_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_l_rm(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
int src_reg;
int dst_reg;
@@ -258,7 +258,7 @@ ropTEST_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
}
static uint32_t
ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropAND_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -270,7 +270,7 @@ ropAND_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropAND_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -282,7 +282,7 @@ ropAND_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropAND_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -296,7 +296,7 @@ ropAND_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
}
static uint32_t
ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropOR_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -308,7 +308,7 @@ ropOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropOR_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -320,7 +320,7 @@ ropOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropOR_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -334,7 +334,7 @@ ropOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
}
static uint32_t
ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -346,7 +346,7 @@ ropTEST_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
return op_pc + 1;
}
static uint32_t
ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -358,7 +358,7 @@ ropTEST_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
return op_pc + 2;
}
static uint32_t
ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropTEST_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -372,7 +372,7 @@ ropTEST_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_p
}
static uint32_t
ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropXOR_AL_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_B(REG_AL);
@@ -384,7 +384,7 @@ ropXOR_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 1;
}
static uint32_t
ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropXOR_AX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_W(REG_AX);
@@ -396,7 +396,7 @@ ropXOR_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc,
return op_pc + 2;
}
static uint32_t
ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropXOR_EAX_imm(UNUSED(uint8_t opcode), uint32_t fetchdat, UNUSED(uint32_t op_32), uint32_t op_pc, UNUSED(codeblock_t *block))
{
int host_reg = LOAD_REG_L(REG_EAX);
@@ -410,7 +410,7 @@ ropXOR_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc
}
static uint32_t
ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropF6(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;
@@ -458,7 +458,7 @@ ropF6(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblo
return 0;
}
static uint32_t
ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropF7_w(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;
@@ -506,7 +506,7 @@ ropF7_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeb
return 0;
}
static uint32_t
ropF7_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
ropF7_l(UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, UNUSED(codeblock_t *block))
{
x86seg *target_seg;
int host_reg;

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