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Cleanup some unused code + UI test

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This commit is contained in:
starfrost013
2025-07-05 00:50:10 +01:00
parent ebea107e82
commit 383a8f468d
6 changed files with 30 additions and 34 deletions
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7
src/include/86box/nv/classes/vid_nv3_classes.h
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@@ -14,7 +14,7 @@
* (they are converted to pointers). In the case of NV3, these map directly to the PHYSICAL PGRAPH REGISTERS while sitting in RAMHT!!!!.
*
* Also, these class IDs don't relate to the internal architecture of the GPU.
* Effectively, the NVIDIA drivers are faking shit. There are only 16 classes but the drivers recognise many more. See nv3_object_classes_driver.txt for the list of
* Effectively, the NVIDIA drivers are faking shit. There are only 22 classes but the drivers recognise many more and have a different naming scheme. See nv3_object_classes_driver.txt for the list of
* classes recognised by the driver.
* This is why the Class IDs you see here are not the same as you may see in other places.
*
@@ -32,11 +32,6 @@
#include <stdio.h>
#include <stdlib.h>
// This is slower, but these need to map *****EXACTLY***** to the registers in PGRAPH,
// or everything FUCKS UP
//
// DO NOT REMOVE! DO NOT REMOVE! DO NOT REMOVE!
// CLass names for debugging
extern const char* nv3_class_names[];

24
src/include/86box/nv/vid_nv3.h
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@@ -935,7 +935,6 @@ extern const device_config_t nv3t_config[]; // Confi
#define NV3_CRTC_REGISTER_I2C 0x3E
#define NV3_CRTC_REGISTER_I2C_GPIO 0x3F
// where the fuck is GDC?
#define NV3_CRTC_BANKED_128K_A0000 0x00
#define NV3_CRTC_BANKED_64K_A0000 0x04
#define NV3_CRTC_BANKED_32K_B0000 0x08
@@ -1066,7 +1065,7 @@ typedef struct nv3_pbus_s
typedef struct nv3_pfifo_cache_s
{
bool push0; // Can we even access this cache?
bool push0; // Can we even access this cache?
uint8_t put_address; // Trigger a DMA into the value you put here.
uint8_t get_address; // Trigger a DMA from the value you put here into where you were going.
uint8_t channel; // The DMA channel ID of this cache.
@@ -1180,7 +1179,7 @@ typedef struct nv3_pgraph_context_control_s
} nv3_pgraph_context_control_t;
/* DMA object context info
Context uploaded from CACHE0/CACH1 by DMA Puller
Context uploaded from CACHE0/CACHE1 by DMA Puller
*/
typedef struct nv3_pgraph_context_user_s
{
@@ -1193,7 +1192,7 @@ typedef struct nv3_pgraph_context_user_s
bool reserved3 : 1;
uint8_t channel : 7;
uint8_t reserved2 : 3;
uint8_t class : 5;
uint8_t class_id : 5;
uint8_t subchannel : 3;
uint16_t reserved : 13;
};
@@ -1468,19 +1467,6 @@ typedef enum nv3_ramin_ramro_reason_e
} nv3_ramin_ramro_reason;
/* This is a gigantic error handling system */
typedef struct nv3_ramin_ramro_entry_s
{
//todo
} nv3_ramin_ramro_entry_t;
// Anti-fuckup device
typedef struct nv3_ramin_ramro_s
{
} nv3_ramin_ramro_t;
// context for unused channels
typedef struct nv3_ramin_ramfc_s
{
@@ -1533,10 +1519,10 @@ typedef struct nv3_s
nv3_pextdev_t pextdev; // Chip configuration
nv3_ptimer_t ptimer; // programmable interval timer
nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects
nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission
// (ramro does not need a struct)
nv3_ramin_ramfc_t ramfc; // context for unused channels
nv3_ramin_ramau_t ramau; // auxillary weirdnes
nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important!
nv3_ramin_t pramin; // INstance memory for graphics objects. Very important!
nv3_pvideo_t pvideo; // Video overlay
nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface
//more here

22
src/qt/qt_gpudebug_visualnv.cpp
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@@ -6,7 +6,7 @@
*
* This file is part of the 86Box distribution.
*
* GPU Debugging Tools - VRAM Viewer implementation
* GPU Debugging Tools - Visual NV Debugger implementation
*
*
*
@@ -35,13 +35,18 @@
#include <qt_gpudebug_visualnv.hpp>
#include "ui_qt_gpudebug_visualnv.h"
/* NOTE: DO NOT REMOVE */
#include <86box/nv/vid_nv3.h>
/* 86Box core includes */
extern "C"
{
/* NOTE: DO NOT REMOVE */
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/video.h>
#include <86box/nv/vid_nv.h>
#include <86box/nv/vid_nv3.h>
}
VisualNVDialog::VisualNVDialog(QWidget *parent)
@@ -49,9 +54,16 @@ VisualNVDialog::VisualNVDialog(QWidget *parent)
, ui(new Ui::VisualNVDialog)
{
ui->setupUi(this);
connect(ui->btnLoadSavestate, &QPushButton::clicked, this, &VisualNVDialog::on_btnLoadSavestate_clicked);
}
// VisualNV dialog destructor
VisualNVDialog::~VisualNVDialog()
{
}
void VisualNVDialog::on_btnLoadSavestate_clicked()
{
warning("THIS IS VisualNVDialog::on_btnLoadSavestate_clicked!!!! (throws into hole)");
}

3
src/qt/qt_gpudebug_visualnv.hpp
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@@ -32,6 +32,9 @@ class VisualNVDialog : public QDialog
public:
explicit VisualNVDialog(QWidget *parent = nullptr);
~VisualNVDialog();
void on_btnLoadSavestate_clicked();
protected:
private:
Ui::VisualNVDialog* ui;

4
src/qt/qt_gpudebug_visualnv.ui
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@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<ui version="4.0">
<class>VisualNVDialog</class>
<widget class="QDialog" name="VisualNVialog">
<widget class="QDialog" name="VisualNVDialog">
<property name="geometry">
<rect>
<x>0</x>
@@ -144,7 +144,7 @@
<string>&lt;html&gt;&lt;head/&gt;&lt;body&gt;&lt;p&gt;Pixel Depth&lt;/p&gt;&lt;/body&gt;&lt;/html&gt;</string>
</property>
</widget>
<widget class="QPushButton" name="loadSavestateBtn">
<widget class="QPushButton" name="btnLoadSavestate">
<property name="geometry">
<rect>
<x>10</x>

4
src/video/nv/nv3/nv3_core.c
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@@ -614,7 +614,7 @@ void nv3_recalc_timings(svga_t* svga)
case NV3_CRTC_REGISTER_PIXELMODE_16BPP:
/* This is some sketchy shit that is an attempt at an educated guess
at pixel clock differences between 9x and NT only in 16bpp. If there is ever an error on 9x with "interlaced" looking graphics,
this is what's causing it. Possibly fucking up *ReactOS* of all things */
this is what's causing it. Possibly fucking up the drivers under *ReactOS* of all things */
if ((svga->crtc[NV3_CRTC_REGISTER_VRETRACESTART] >> 1) & 0x01)
svga->rowoffset += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0xE0) << 2;
else
@@ -710,7 +710,7 @@ uint8_t nv3_svga_read(uint16_t addr, void* priv)
ret = nv3->nvbase.svga.crtcreg;
break;
case NV3_CRTC_REGISTER_WTF:
ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers
ret = 0x08; // Required to not freeze in certain situations on v3.xx drivers. Even though this register doesn't actually exist lol
break;
case NV3_CRTC_REGISTER_CURRENT:
// Support the extended NVIDIA CRTC register range