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Fixes

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This commit is contained in:
Jasmine Iwanek
2022-08-11 22:03:08 -04:00
parent fae0eb7bf8
commit 3ed2b10241
4 changed files with 16 additions and 11 deletions
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4
src/device/smbus_piix4.c
View File

@@ -344,10 +344,10 @@ unknown_protocol:
}
/* Finish transfer. */
if (dev->local == SMBUS_INTEL_ICH2) // ICH2 SMBus specific. Transfer on Byte command doesn't stop till their specific points.
if (dev->local == SMBUS_INTEL_ICH2) { // ICH2 SMBus specific. Transfer on Byte command doesn't stop till their specific points.
if (!dev->byte_rw)
i2c_stop(i2c_smbus, smbus_addr);
else
} else
i2c_stop(i2c_smbus, smbus_addr);
}
break;

14
src/sio/sio_it8702.c
View File

@@ -268,14 +268,13 @@ it8702_read(uint16_t addr, void *priv)
{
it8702_t *dev = (it8702_t *) priv;
if(addr == 0x2e)
if(addr == 0x2e) {
return dev->index;
else if(addr == 0x2f) {
if(dev->index == 0x02) /* The Configure Control register is Write Only */
} else if(addr == 0x2f) {
if(dev->index == 0x02) { /* The Configure Control register is Write Only */
return 0xff;
else
switch(dev->index)
{
} else {
switch(dev->index) {
case 0x07:
return dev->ldn;
@@ -315,7 +314,10 @@ it8702_read(uint16_t addr, void *priv)
default:
return 0xff;
}
}
}
return 0xff;
}

6
src/sio/sio_nsc366.c
View File

@@ -221,12 +221,14 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
case 0x20 ... 0x2d:
switch (dev->index - 0x20) {
case 0x01:
if (!dev->siofc_lock)
if (!dev->siofc_lock) {
if (val & 0x80) {
dev->sio_config[dev->index - 0x20] = val | 0x80;
dev->siofc_lock = 1;
} else
} else {
dev->sio_config[dev->index - 0x20] = val;
}
}
break;
case 0x02:

3
src/win/Makefile.mingw
View File

@@ -539,7 +539,8 @@ MAINOBJ := 86box.o config.o log.o random.o timer.o io.o acpi.o apm.o dma.o ddma
usb.o device.o nvr.o nvr_at.o nvr_ps2.o machine_status.o \
$(VNCOBJ)
MEMOBJ := catalyst_flash.o i2c_eeprom.o intel_flash.o mem.o rom.o smram.o spd.o sst_flash.o
MEMOBJ := catalyst_flash.o i2c_eeprom.o intel_flash.o mem.o rom.o smram.o spd.o sst_flash.o \
815ep_spd_hack.o
CPUOBJ := $(DYNARECOBJ) \
$(CGTOBJ) \