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Merge branch 'temp' into temp

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This commit is contained in:
OBattler
2020-03-23 22:02:52 +01:00
committed by GitHub
parent 35895fcddd 9870b9e0bb
commit 43f2bb849b
56 changed files with 2098 additions and 7819 deletions
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1
src/86box.h
View File

@@ -99,6 +99,7 @@ extern int vid_cga_contrast, /* (C) video */
gfxcard; /* (C) graphics/video card */
extern int serial_enabled[], /* (C) enable serial ports */
bugger_enabled, /* (C) enable ISAbugger */
postcard_enabled, /* (C) enable POST card */
isamem_type[], /* (C) enable ISA mem cards */
isartc_type; /* (C) enable ISA RTC card */
extern int sound_is_float, /* (C) sound uses FP values */

1
src/chipset/chipset.h
View File

@@ -44,6 +44,7 @@ extern const device_t i430tx_device;
#if defined(DEV_BRANCH) && defined(USE_I686)
extern const device_t i440fx_device;
extern const device_t i440bx_device;
extern const device_t i440zx_device;
#endif
/* NEAT */

183
src/chipset/intel_4x0.c
View File

@@ -44,7 +44,8 @@ enum
INTEL_430TX
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX,
INTEL_440BX
INTEL_440BX,
INTEL_440ZX
#endif
};
@@ -64,8 +65,6 @@ typedef struct
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
// pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
@@ -103,7 +102,6 @@ pm2_cntrl_read(uint16_t addr, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
// pclog("PM2_CTL read: %02X\n", dev->pm2_cntrl & 0x01);
return dev->pm2_cntrl & 0x01;
}
@@ -113,7 +111,6 @@ pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
// pclog("PM2_CTL write: %02X\n", val);
dev->pm2_cntrl = val & 0x01;
}
@@ -131,15 +128,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
if (func > dev->max_func) {
if (func > dev->max_func)
#else
if (func > 0) {
if (func > 0)
#endif
// pclog("invalid write %02X to %02X:%02X\n", val, func, addr);
return;
}
// pclog("write %02X to %02X:%02X\n", val, func, addr);
if ((addr >= 0x10) && (addr < 0x4f))
return;
@@ -149,7 +142,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
#endif
default:
regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
@@ -166,7 +159,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_420TX: case INTEL_420ZX: case INTEL_430LX: case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440FX: case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x05] = (regs[0x05] & ~0x01) | (val & 0x01);
break;
@@ -185,7 +178,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x07] &= ~(val & 0xf9);
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x07] &= ~(val & 0xf0);
break;
#endif
@@ -211,7 +204,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x12:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x12] = (val & 0xc0);
i4x0_mask_bar(regs);
break;
@@ -219,7 +212,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x13:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x13] = val;
i4x0_mask_bar(regs);
break;
@@ -227,7 +220,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr]) {
regs[addr] = val;
regs_l[addr] = 1;
@@ -274,6 +267,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x50] = (regs[0x50] & 0x14) | (val & 0xeb);
break;
case INTEL_440ZX:
regs[0x50] = (regs[0x50] & 0x34) | (val & 0xcb);
break;
#endif
}
break;
@@ -286,7 +282,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x51] = (val & 0xc3);
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x51] = (regs[0x50] & 0x70) | (val & 0x8f);
break;
#endif
@@ -308,7 +304,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x52] = val;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x52] = val & 0x07;
break;
#endif
@@ -326,6 +322,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX: case INTEL_430TX:
regs[0x53] = val & 0x3f;
break;
case INTEL_440BX:
/* Not applicable to 440ZX as that does not support ECC. */
regs[0x53] = val;
break;
}
break;
case 0x54:
@@ -400,6 +400,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x57] = val & 0x3f;
break;
case INTEL_440ZX:
regs[0x57] = val & 0x2f;
break;
#endif
}
break;
@@ -411,7 +414,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case INTEL_430NX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x58] = val & 0x03;
break;
@@ -492,6 +495,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440ZX:
#endif
default:
regs[addr] = val;
@@ -512,6 +516,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -528,6 +533,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -538,6 +544,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430NX: case INTEL_430HX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
case INTEL_440ZX:
#endif
regs[addr] = val;
break;
@@ -565,6 +572,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0x68] = (regs[0x68] & 0x38) | (val & 0xc7);
break;
case INTEL_440ZX:
regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
break;
#endif
}
break;
@@ -579,6 +589,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_430VX:
regs[0x69] = val & 0x07;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440ZX:
regs[0x69] = val & 0x3f;
break;
#endif
}
break;
case 0x6a: case 0x6b:
@@ -589,6 +604,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#endif
regs[addr] = val;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440ZX:
if (addr == 0x6a)
regs[addr] = val & 0xfc;
else
regs[addr] = val & 0x33;
break;
#endif
}
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
@@ -597,6 +620,12 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
if (addr == 0x6c)
regs[addr] = val & 0x03;
else if (addr == 0x6d)
regs[addr] = val & 0xcf;
break;
}
break;
#endif
@@ -652,7 +681,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x73] = val & 0x03;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x73] = val;
break;
#endif
@@ -662,7 +691,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
switch (dev->type) {
case INTEL_430VX:
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
#endif
regs[0x74] = val;
break;
@@ -672,13 +701,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x75: case 0x76:
case 0x7b:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
}
break;
case 0x77:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x77] = val & 0x03;
}
break;
@@ -689,7 +718,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x78] = val & 0xcf;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x78] = val & 0x0f;
break;
#endif
@@ -702,10 +731,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
// pclog("430TX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x79] = val;
break;
#endif
@@ -714,12 +742,11 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x7a:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (regs[0x7a] & 0x0a) | (val & 0xf5);
io_removehandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
if (val & 0x40)
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
// pclog("440BX: PM2_CTL now %sabled\n", (val & 0x40) ? "en" : "dis");
break;
}
break;
@@ -731,7 +758,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
regs[0x7c] = val & 0x8f;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val & 0x1f;
break;
#endif
@@ -753,7 +780,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x80:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x80] &= ~(val & 0x03);
break;
}
@@ -768,7 +795,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440FX:
regs[0x80] = val & 0x1b;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7c] = val;
break;
#endif
@@ -780,6 +807,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX: case INTEL_440BX:
#endif
/* Not applicable on 82443ZX. */
regs[0x91] &= ~(val & 0x11);
break;
}
@@ -787,7 +815,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
#if defined(DEV_BRANCH) && defined(USE_I686)
case 0x92:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x92] &= ~(val & 0x1f);
break;
}
@@ -802,28 +830,28 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xa8: case 0xa9:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0x03);
break;
}
break;
case 0xb0:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb0] = (val & 0x80);
break;
}
break;
case 0xb1:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb1] = (val & 0xa0);
break;
}
break;
case 0xb4:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb4] = (val & 0x3f);
i4x0_mask_bar(regs);
break;
@@ -831,17 +859,37 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xb9:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xb9] = (val & 0xf0);
break;
}
break;
case 0xba: case 0xbb: case 0xca: case 0xcb:
case 0xba: case 0xbb:
case 0xd0: case 0xd1: case 0xd2: case 0xd3: case 0xd4: case 0xd5: case 0xd6: case 0xd7:
switch (dev->type) {
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
break;
case 0xca:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xe7;
break;
}
break;
case 0xcb:
switch (dev->type) {
case INTEL_440BX:
regs[addr] = val;
break;
case INTEL_440ZX:
regs[addr] = val & 0xa7;
break;
}
break;
case 0xcc:
@@ -849,12 +897,15 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case INTEL_440BX:
regs[0xcc] = (val & 0x7f);
break;
case INTEL_440ZX:
regs[0xcc] = (val & 0x58);
break;
}
break;
case 0xe0: case 0xe1: case 0xe2: case 0xe3: case 0xe4:
case 0xe8: case 0xe9: case 0xea: case 0xeb: case 0xec:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = val;
break;
@@ -862,7 +913,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe5: case 0xed:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
if (!regs_l[addr])
regs[addr] = (val & 0x3f);
break;
@@ -870,7 +921,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xe7:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xe7] = 0x80;
for (i = 0; i < 16; i++)
regs_l[0xe0 + i] = !!(val & 0x80);
@@ -882,14 +933,14 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0xf0:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xf0] = (val & 0xc0);
break;
}
break;
case 0xf1:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0xf1] = (val & 0x03);
break;
}
@@ -897,21 +948,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
} else if (func == 1) switch (addr) {
case 0x04:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x04] = (val & 0x1f);
break;
}
break;
case 0x05:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x05] = (val & 0x01);
break;
}
break;
case 0x0d: case 0x1b:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf8);
break;
}
@@ -920,7 +971,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x21: case 0x23:
case 0x25: case 0x27:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = val;
break;
}
@@ -929,21 +980,21 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
case 0x20: case 0x22:
case 0x24: case 0x26:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[addr] = (val & 0xf0);
break;
}
break;
case 0x1f:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x1f] &= ~(val & 0xf0);
break;
}
break;
case 0x3e:
switch (dev->type) {
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x3e] = (val & 0xed);
break;
}
@@ -965,13 +1016,12 @@ i4x0_read(int func, int addr, void *priv)
#endif
#if defined(DEV_BRANCH) && defined(USE_I686)
if (func > dev->max_func) {
if (func > dev->max_func)
#else
if (func > 0) {
if (func > 0)
#endif
ret = 0xff;
// pclog("invalid read %02X from %02X:%02X\n", ret, func, addr);
} else {
else {
ret = regs[addr];
#if defined(DEV_BRANCH) && defined(USE_I686)
/* Special behavior for 440FX register 0x93 which is basically TRC in PCI space
@@ -979,7 +1029,6 @@ i4x0_read(int func, int addr, void *priv)
if ((func == 0) && (addr == 0x93) && (dev->type == INTEL_440FX))
ret = (ret & 0xf9) | (trc_read(0x0093, NULL) & 0x06);
#endif
// pclog("read %02X from %02X:%02X\n", ret, func, addr);
}
return ret;
@@ -1006,7 +1055,7 @@ i4x0_reset(void *priv)
i4x0_write(0, 0x72, 0x00, priv);
#if defined(DEV_BRANCH) && defined(USE_I686)
if (dev->type == INTEL_440BX) {
if ((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) {
for (i = 0; i <= dev->max_func; i++)
memset(dev->regs_locked[i], 0x00, 256 * sizeof(uint8_t));
}
@@ -1185,11 +1234,12 @@ static void
regs[0x71] = 0x10;
regs[0x72] = 0x02;
break;
case INTEL_440BX:
case INTEL_440BX: case INTEL_440ZX:
regs[0x7a] = (info->local >> 8) & 0xff;
dev->max_func = (regs[0x7a] & 0x02) ? 0 : 1;
regs[0x02] = (regs[0x7a] & 0x02) ? 0x92 : 0x90; regs[0x03] = 0x71; /* 82443BX */
regs[0x06] = (regs[0x7a] & 0x02) ? 0x00 : 0x10;
regs[0x08] = 0x02;
regs[0x10] = 0x08;
regs[0x34] = (regs[0x7a] & 0x02) ? 0x00 : 0xa0;
@@ -1234,7 +1284,7 @@ static void
smbase = 0xa0000;
#if defined(DEV_BRANCH) && defined(USE_I686)
if ((dev->type == INTEL_440BX) && (dev->max_func == 1)) {
if (((dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX)) && (dev->max_func == 1)) {
regs = (uint8_t *) dev->regs[1];
regs[0x00] = 0x86; regs[0x01] = 0x80; /* Intel */
@@ -1421,4 +1471,19 @@ const device_t i440bx_device =
NULL,
NULL
};
const device_t i440zx_device =
{
"Intel 82443ZX",
DEVICE_PCI,
0x8000 | INTEL_440ZX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#endif

529
src/chipset/intel_4x0.c.old
View File

@@ -1,529 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel PCISet chips from 420TX to 440FX.
*
* Version: @(#)intel_4x0.c 1.0.3 2020/01/24
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019,2020 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "cpu.h"
#include "mem.h"
#include "86box_io.h"
#include "rom.h"
#include "pci.h"
#include "device.h"
#include "keyboard.h"
#include "chipset.h"
enum
{
INTEL_420TX,
INTEL_430LX,
INTEL_430NX,
INTEL_430FX,
INTEL_430FX_PB640,
INTEL_430HX,
INTEL_430VX,
INTEL_430TX
#if defined(DEV_BRANCH) && defined(USE_I686)
,INTEL_440FX
#endif
};
typedef struct
{
uint8_t pm2_cntrl;
uint8_t regs[256];
int type;
} i4x0_t;
static void
i4x0_map(uint32_t addr, uint32_t size, int state)
{
// pclog("i4x0_map(%08X, %08X, %02X)\n", addr, size, state);
switch (state & 3) {
case 0:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
break;
case 1:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_EXTANY);
break;
case 2:
mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
break;
case 3:
mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
break;
}
flushmmucache_nopc();
}
static void
i4x0_write(int func, int addr, uint8_t val, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
if (func)
return;
pclog("write %02X to %08X\n", val, addr);
if ((addr >= 0x10) && (addr < 0x4f))
return;
switch (addr) {
case 0x00: case 0x01: case 0x02: case 0x03:
case 0x08: case 0x09: case 0x0a: case 0x0b:
case 0x0c: case 0x0e:
return;
case 0x04: /*Command register*/
if (dev->type >= INTEL_430FX) {
if (dev->type == INTEL_430FX_PB640)
val &= 0x06;
else
val &= 0x02;
} else
val &= 0x42;
val |= 0x04;
break;
case 0x05:
if (dev->type >= INTEL_430FX)
val = 0;
else
val &= 0x01;
break;
case 0x06: /*Status*/
val = 0;
break;
case 0x07:
if (dev->type >= INTEL_430HX) {
val &= 0x80;
val |= 0x02;
} else {
val = 0x02;
if (dev->type == INTEL_430FX_PB640)
val |= 0x20;
}
break;
case 0x52: /*Cache Control Register*/
#if defined(DEV_BRANCH) && defined(USE_I686)
if (dev->type < INTEL_440FX) {
#endif
cpu_cache_ext_enabled = (val & 0x01);
cpu_update_waitstates();
#if defined(DEV_BRANCH) && defined(USE_I686)
}
#endif
break;
case 0x59: /*PAM0*/
if ((dev->regs[0x59] ^ val) & 0xf0) {
i4x0_map(0xf0000, 0x10000, val >> 4);
shadowbios = (val & 0x10);
}
break;
case 0x5a: /*PAM1*/
if ((dev->regs[0x5a] ^ val) & 0x0f)
i4x0_map(0xc0000, 0x04000, val & 0xf);
if ((dev->regs[0x5a] ^ val) & 0xf0)
i4x0_map(0xc4000, 0x04000, val >> 4);
break;
case 0x5b: /*PAM2*/
if ((dev->regs[0x5b] ^ val) & 0x0f)
i4x0_map(0xc8000, 0x04000, val & 0xf);
if ((dev->regs[0x5b] ^ val) & 0xf0)
i4x0_map(0xcc000, 0x04000, val >> 4);
break;
case 0x5c: /*PAM3*/
if ((dev->regs[0x5c] ^ val) & 0x0f)
i4x0_map(0xd0000, 0x04000, val & 0xf);
if ((dev->regs[0x5c] ^ val) & 0xf0)
i4x0_map(0xd4000, 0x04000, val >> 4);
break;
case 0x5d: /*PAM4*/
if ((dev->regs[0x5d] ^ val) & 0x0f)
i4x0_map(0xd8000, 0x04000, val & 0xf);
if ((dev->regs[0x5d] ^ val) & 0xf0)
i4x0_map(0xdc000, 0x04000, val >> 4);
break;
case 0x5e: /*PAM5*/
if ((dev->regs[0x5e] ^ val) & 0x0f)
i4x0_map(0xe0000, 0x04000, val & 0xf);
if ((dev->regs[0x5e] ^ val) & 0xf0)
i4x0_map(0xe4000, 0x04000, val >> 4);
break;
case 0x5f: /*PAM6*/
if ((dev->regs[0x5f] ^ val) & 0x0f)
i4x0_map(0xe8000, 0x04000, val & 0xf);
if ((dev->regs[0x5f] ^ val) & 0xf0)
i4x0_map(0xec000, 0x04000, val >> 4);
break;
case 0x72: /*SMRAM*/
if ((dev->type >= INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x48))
i4x0_map(0xa0000, 0x20000, ((val & 0x48) == 0x48) ? 3 : 0);
else if ((dev->type < INTEL_430FX) && ((dev->regs[0x72] ^ val) & 0x20))
i4x0_map(0xa0000, 0x20000, ((val & 0x20) == 0x20) ? 3 : 0);
break;
case 0x73: case 0x74:
// pclog("Access %i at %08X\n", dev->regs[0x73] & 3, dev->regs[0x74] << 19);
break;
}
dev->regs[addr] = val;
}
static uint8_t
i4x0_read(int func, int addr, void *priv)
{
i4x0_t *dev = (i4x0_t *) priv;
uint8_t ret = 0xff;
if (!func) {
ret = dev->regs[addr];
pclog("read %02X from %08X\n", ret, addr);
// if (addr == 0x50)
// pclog("read %02X from %08X\n", ret, addr);
}
return ret;
}
static void
i4x0_reset(void *priv)
{
i4x0_t *i4x0 = (i4x0_t *)priv;
i4x0_write(0, 0x59, 0x00, priv);
i4x0_write(0, 0x5e, 0x00, priv);
i4x0_write(0, 0x5f, 0x00, priv);
if (i4x0->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, priv);
smbase = 0xa0000;
}
static void
i4x0_close(void *p)
{
i4x0_t *i4x0 = (i4x0_t *)p;
free(i4x0);
}
static uint8_t
pm2_cntrl_read(uint16_t addr, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
return dev->pm2_cntrl & 0x01;
}
static void
pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
{
i4x0_t *dev = (i4x0_t *) p;
dev->pm2_cntrl = val & 0x01;
}
static void
*i4x0_init(const device_t *info)
{
i4x0_t *i4x0 = (i4x0_t *) malloc(sizeof(i4x0_t));
memset(i4x0, 0, sizeof(i4x0_t));
i4x0->type = info->local;
i4x0->regs[0x00] = 0x86; i4x0->regs[0x01] = 0x80; /*Intel*/
switch(i4x0->type) {
case INTEL_420TX:
i4x0->regs[0x02] = 0x83; i4x0->regs[0x03] = 0x04; /*82424TX/ZX*/
i4x0->regs[0x08] = 0x03; /*A3 stepping*/
i4x0->regs[0x50] = 0x80;
// i4x0->regs[0x50] = 0x23;
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430LX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x03; /*A3 stepping*/
i4x0->regs[0x50] = 0x80;
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430NX:
i4x0->regs[0x02] = 0xa3; i4x0->regs[0x03] = 0x04; /*82434LX/NX*/
i4x0->regs[0x08] = 0x10; /*A0 stepping*/
i4x0->regs[0x50] = 0xA0;
i4x0->regs[0x52] = 0x44; /*256kb PLB cache*/
i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
break;
case INTEL_430FX:
case INTEL_430FX_PB640:
i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
if (i4x0->type == INTEL_430FX_PB640)
i4x0->regs[0x08] = 0x02; /*???? stepping*/
else
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x40; /*256kb PLB cache*/
break;
case INTEL_430HX:
i4x0->regs[0x02] = 0x50; i4x0->regs[0x03] = 0x12; /*82439HX*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x51] = 0x20;
i4x0->regs[0x52] = 0xB5; /*512kb cache*/
i4x0->regs[0x56] = 0x52; /*DRAM control*/
// i4x0->regs[0x59] = 0x40;
// i4x0->regs[0x5A] = i4x0->regs[0x5B] = i4x0->regs[0x5C] = i4x0->regs[0x5D] = 0x44;
// i4x0->regs[0x5E] = i4x0->regs[0x5F] = 0x44;
i4x0->regs[0x65] = i4x0->regs[0x66] = i4x0->regs[0x67] = 0x02;
i4x0->regs[0x68] = 0x11;
break;
case INTEL_430VX:
i4x0->regs[0x02] = 0x30; i4x0->regs[0x03] = 0x70; /*82437VX*/
// i4x0->regs[0x02] = 0x2d; i4x0->regs[0x03] = 0x12; /*SB82437FX-66*/
i4x0->regs[0x08] = 0x00; /*A0 stepping*/
i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
i4x0->regs[0x53] = 0x14;
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x67] = 0x11;
i4x0->regs[0x69] = 0x03;
i4x0->regs[0x70] = 0x20;
i4x0->regs[0x74] = 0x0e;
i4x0->regs[0x78] = 0x23;
break;
case INTEL_430TX:
io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, i4x0);
i4x0->regs[0x02] = 0x00; i4x0->regs[0x03] = 0x71; /*82439TX*/
i4x0->regs[0x08] = 0x01; /*A0 stepping*/
i4x0->regs[0x52] = 0x42; /*256kb PLB cache*/
i4x0->regs[0x53] = 0x14;
i4x0->regs[0x56] = 0x52; /*DRAM control*/
i4x0->regs[0x65] = 0x02;
i4x0->regs[0x67] = 0x80;
i4x0->regs[0x69] = 0x03;
i4x0->regs[0x70] = 0x20;
break;
#if defined(DEV_BRANCH) && defined(USE_I686)
case INTEL_440FX:
i4x0->regs[0x02] = 0x37; i4x0->regs[0x03] = 0x12; /*82441FX*/
i4x0->regs[0x08] = 0x02; /*A0 stepping*/
i4x0->regs[0x2c] = 0xf4;
i4x0->regs[0x2d] = 0x1a;
i4x0->regs[0x2f] = 0x11;
i4x0->regs[0x51] = 0x01;
i4x0->regs[0x53] = 0x80;
i4x0->regs[0x58] = 0x10;
i4x0->regs[0x5a] = i4x0->regs[0x5b] = i4x0->regs[0x5c] = i4x0->regs[0x5d] = 0x11;
i4x0->regs[0x5e] = 0x11;
i4x0->regs[0x5f] = 0x31;
break;
#endif
}
i4x0->regs[0x04] = 0x06; i4x0->regs[0x05] = 0x00;
#if defined(DEV_BRANCH) && defined(USE_I686)
if (i4x0->type == INTEL_440FX)
i4x0->regs[0x06] = 0x80;
#endif
if (i4x0->type == INTEL_430FX)
i4x0->regs[0x07] = 0x82;
#if defined(DEV_BRANCH) && defined(USE_I686)
else if (i4x0->type != INTEL_440FX)
#else
else
#endif
i4x0->regs[0x07] = 0x02;
i4x0->regs[0x0b] = 0x06;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x57] = 0x01;
else
i4x0->regs[0x57] = 0x31;
i4x0->regs[0x60] = i4x0->regs[0x61] = i4x0->regs[0x62] = i4x0->regs[0x63] = 0x02;
i4x0->regs[0x64] = 0x02;
if (i4x0->type >= INTEL_430FX)
i4x0->regs[0x72] = 0x02;
#if defined(DEV_BRANCH) && defined(USE_I686)
if (i4x0->type == INTEL_440FX) {
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
}
#endif
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, i4x0);
i4x0_write(0, 0x59, 0x00, i4x0);
i4x0_write(0, 0x5a, 0x00, i4x0);
i4x0_write(0, 0x5b, 0x00, i4x0);
i4x0_write(0, 0x5c, 0x00, i4x0);
i4x0_write(0, 0x5d, 0x00, i4x0);
i4x0_write(0, 0x5e, 0x00, i4x0);
i4x0_write(0, 0x5f, 0x00, i4x0);
smbase = 0xa0000;
return i4x0;
}
const device_t i420tx_device =
{
"Intel 82424TX",
DEVICE_PCI,
INTEL_420TX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430lx_device =
{
"Intel 82434LX",
DEVICE_PCI,
INTEL_430LX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430nx_device =
{
"Intel 82434NX",
DEVICE_PCI,
INTEL_430NX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_device =
{
"Intel SB82437FX-66",
DEVICE_PCI,
INTEL_430FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430fx_pb640_device =
{
"Intel SB82437FX-66 (PB640)",
DEVICE_PCI,
INTEL_430FX_PB640,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430hx_device =
{
"Intel 82439HX",
DEVICE_PCI,
INTEL_430HX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430vx_device =
{
"Intel 82437VX",
DEVICE_PCI,
INTEL_430VX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
const device_t i430tx_device =
{
"Intel 82439TX",
DEVICE_PCI,
INTEL_430TX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#if defined(DEV_BRANCH) && defined(USE_I686)
const device_t i440fx_device =
{
"Intel 82441FX",
DEVICE_PCI,
INTEL_440FX,
i4x0_init,
i4x0_close,
i4x0_reset,
NULL,
NULL,
NULL,
NULL
};
#endif

9
src/chipset/sis_85c496.c
View File

@@ -120,8 +120,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
if ((addr >= 4 && addr < 8) || addr >= 0x40)
dev->pci_conf[addr] = val;
pclog("SiS 496 Write: %02X %02X %02X\n", func, addr, val);
valxor = old ^ val;
switch (addr) {
@@ -144,7 +142,6 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
port_92_remove(dev->port_92);
if (val & 0x02)
port_92_add(dev->port_92);
pclog("Port 92: %sabled\n", (val & 0x02) ? "En" : "Dis");
}
break;
@@ -199,10 +196,8 @@ sis_85c496_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x67:
if (valxor & 0x60) {
if (valxor & 0x60)
port_92_set_features(dev->port_92, !!(val & 0x20), !!(val & 0x40));
pclog("[Port 92] Set features: %sreset, %sA20\n", !!(val & 0x20) ? "" : "no ", !!(val & 0x40) ? "" : "no ");
}
break;
case 0x82:
@@ -252,8 +247,6 @@ sis_85c496_read(int func, int addr, void *priv)
break;
}
pclog("SiS 496 Read: %02X %02X %02X\n", func, addr, ret);
return ret;
}

6
src/config.c
View File

@@ -806,6 +806,7 @@ load_other_peripherals(void)
ide_qua_enabled = !!config_get_int(cat, "ide_qua", 0);
bugger_enabled = !!config_get_int(cat, "bugger_enabled", 0);
postcard_enabled = !!config_get_int(cat, "postcard_enabled", 0);
for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c);
@@ -1686,6 +1687,11 @@ save_other_peripherals(void)
else
config_set_int(cat, "bugger_enabled", bugger_enabled);
if (postcard_enabled == 0)
config_delete_var(cat, "postcard_enabled");
else
config_set_int(cat, "postcard_enabled", postcard_enabled);
for (c = 0; c < ISAMEM_MAX; c++) {
sprintf(temp, "isamem%d_type", c);
if (isamem_type[c] == 0)

46
src/cpu_common/cpu_table.c
View File

@@ -228,18 +228,18 @@ CPU cpus_486DLC[] = {
CPU cpus_i486S1[] = {
/*i486*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX2, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX2, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX2, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX2, 50000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX2, 66666666, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*Only added the DX4 OverDrive as the others would be redundant*/
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
@@ -270,6 +270,28 @@ CPU cpus_Cx486S1[] = {
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
};
CPU cpus_i486[] = {
/*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},
{"i486SX/20", CPU_i486SX, 20000000, 1, 0x420, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/25", CPU_i486SX, 25000000, 1, 0x422, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486SX/33", CPU_i486SX, 33333333, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486SX2/50", CPU_i486SX, 50000000, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486SX2/66 (Q0569)", CPU_i486SX, 66666666, 2, 0x45b, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 8},
{"i486DX/25", CPU_i486DX, 25000000, 1, 0x404, 0, 0, CPU_SUPPORTS_DYNAREC, 4, 4,3,3, 3},
{"i486DX/33", CPU_i486DX, 33333333, 1, 0x414, 0, 0, CPU_SUPPORTS_DYNAREC, 6, 6,3,3, 4},
{"i486DX/50", CPU_i486DX, 50000000, 1, 0x411, 0, 0, CPU_SUPPORTS_DYNAREC, 8, 8,4,4, 6},
{"i486DX2/40", CPU_i486DX, 40000000, 2, 0x430, 0x430, 0, CPU_SUPPORTS_DYNAREC, 7, 7,6,6, 5},
{"i486DX2/50", CPU_i486DX, 50000000, 2, 0x433, 0x433, 0, CPU_SUPPORTS_DYNAREC, 8, 8,6,6, 6},
{"i486DX2/66", CPU_i486DX, 66666666, 2, 0x435, 0x435, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6, 8},
{"iDX4/75", CPU_iDX4, 75000000, 3, 0x480, 0x480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, 100000000, 3, 0x483, 0x483, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4 OverDrive 75", CPU_iDX4, 75000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9, 9},
{"iDX4 OverDrive 100", CPU_iDX4, 100000000, 3, 0x1480, 0x1480, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9, 12},
{"Pentium OverDrive 63", CPU_PENTIUM, 62500000, 5/2, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7, 15/2},
{"Pentium OverDrive 83", CPU_PENTIUM, 83333333, 5/2, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8, 10},
{"", -1, 0, 0, 0, 0, 0, 0, 0, 0,0,0, 0}
};
CPU cpus_i486[] = {
/*i486/P24T*/
{"i486SX/16", CPU_i486SX, 16000000, 1, 0x42a, 0, 0, CPU_SUPPORTS_DYNAREC, 3, 3,3,3, 2},

8
src/cpu_new/codegen_ops_misc.c
View File

@@ -359,11 +359,11 @@ uint32_t ropFF_16(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
uop_MOVZX(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
uop_MOVZX(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/
@@ -466,11 +466,11 @@ uint32_t ropFF_32(codeblock_t *block, ir_data_t *ir, uint8_t opcode, uint32_t fe
return -1;
case 0x28: /*JMP far*/
uop_MOV(ir, IREG_pc, src_reg);
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4);
uop_LOAD_FUNC_ARG_REG(ir, 0, IREG_temp1_W);
uop_LOAD_FUNC_ARG_IMM(ir, 1, cpu_state.oldpc);
uop_LOAD_FUNC_ARG_IMM(ir, 1, op_pc + 1);
uop_CALL_FUNC(ir, loadcsjmp);
uop_MOV(ir, IREG_pc, src_reg);
return -1;
case 0x30: /*PUSH*/

32
src/disk/hdc_ide.c
View File

@@ -278,6 +278,8 @@ ide_irq_raise(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
ide_log("IDE %i: IRQ raise\n", ide->board);
if (!(ide->fdisk & 2)) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -298,6 +300,8 @@ ide_irq_lower(ide_t *ide)
/* ide_log("Lowering IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
ide_log("IDE %i: IRQ lower\n", ide->board);
if (ide->irqstat) {
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
@@ -318,6 +322,7 @@ ide_irq_update(ide_t *ide)
/* ide_log("Raising IRQ %i (board %i)\n", ide_boards[ide->board]->irq, ide->board); */
if (!(ide->fdisk & 2) && ide->irqstat) {
ide_log("IDE %i: IRQ update raise\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq) {
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
ide_bm[ide->board]->set_irq(ide->board | 0x40, ide_bm[ide->board]->priv);
@@ -326,6 +331,7 @@ ide_irq_update(ide_t *ide)
picint(1 << ide_boards[ide->board]->irq);
}
} else if (ide->fdisk & 2) {
ide_log("IDE %i: IRQ update lower\n", ide->board);
if (ide_bm[ide->board] && ide_bm[ide->board]->set_irq)
ide_bm[ide->board]->set_irq(ide->board, ide_bm[ide->board]->priv);
else if (ide_boards[ide->board]->irq != -1)
@@ -877,11 +883,17 @@ ide_atapi_callback(ide_t *ide)
switch(ide->sc->packet_status) {
case PHASE_IDLE:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_IDLE\n");
#endif
ide->sc->pos = 0;
ide->sc->phase = 1;
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
return;
case PHASE_COMMAND:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_COMMAND\n");
#endif
ide->sc->status = BUSY_STAT | (ide->sc->status & ERR_STAT);
if (ide->packet_command) {
ide->packet_command(ide->sc, ide->sc->atapi_cdb);
@@ -890,6 +902,9 @@ ide_atapi_callback(ide_t *ide)
}
return;
case PHASE_COMPLETE:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_COMPLETE\n");
#endif
ide->sc->status = READY_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
@@ -897,12 +912,18 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_DATA_IN:
case PHASE_DATA_OUT:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_DATA_IN or PHASE_DATA_OUT\n");
#endif
ide->sc->status = READY_STAT | DRQ_STAT | (ide->sc->status & ERR_STAT);
ide->sc->phase = !(ide->sc->packet_status & 0x01) << 1;
ide_irq_raise(ide);
return;
case PHASE_DATA_IN_DMA:
case PHASE_DATA_OUT_DMA:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_DATA_IN_DMA or PHASE_DATA_OUT_DMA\n");
#endif
out = (ide->sc->packet_status & 0x01);
if (ide_bm[ide->board] && ide_bm[ide->board]->dma) {
@@ -932,11 +953,17 @@ ide_atapi_callback(ide_t *ide)
return;
case PHASE_ERROR:
#ifdef ENABLE_IDE_LOG
ide_log("PHASE_ERROR\n");
#endif
ide->sc->status = READY_STAT | ERR_STAT;
ide->sc->phase = 3;
ide->sc->packet_status = PHASE_NONE;
ide_irq_raise(ide);
return;
default:
ide_log("PHASE_UNKNOWN %02X\n", ide->sc->packet_status);
return;
}
}
@@ -1001,6 +1028,9 @@ ide_atapi_packet_read(ide_t *ide, int length)
if (!dev || !dev->temp_buffer || (dev->packet_status != PHASE_DATA_IN))
return 0;
if (dev->packet_status == PHASE_DATA_IN)
ide_log("PHASE_DATA_IN read: %i, %i< %i, %i\n", dev->request_pos, dev->max_transfer_len, dev->pos, dev->packet_len);
bufferw = (uint16_t *) dev->temp_buffer;
bufferl = (uint32_t *) dev->temp_buffer;
@@ -1689,7 +1719,7 @@ ide_read_data(ide_t *ide, int length)
ide->secount = (ide->secount - 1) & 0xff;
if (ide->secount) {
ide_next_sector(ide);
ide->atastat = BSY_STAT;
ide->atastat = BSY_STAT | READY_STAT | DSC_STAT;
if (ide->command == WIN_READ_MULTIPLE)
ide_callback(ide_boards[ide->board]);
else

13
src/disk/hdc_ide_sff8038i.c
View File

@@ -373,14 +373,16 @@ sff_bus_master_set_irq(int channel, void *priv)
channel &= 0x01;
if (dev->status & 0x04) {
if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
sff_log("SFF8038i: Channel %i IRQ raise\n", channel);
if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_set_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_set_irq(dev->slot, dev->irq_pin);
else
picint(1 << (14 + channel));
} else {
if ((dev->irq_mode == 2) && (channel & 1) && pci_use_mirq(0))
sff_log("SFF8038i: Channel %i IRQ lower\n", channel);
if ((dev->irq_mode == 2) && channel && pci_use_mirq(0))
pci_clear_mirq(0, 0);
else if (dev->irq_mode == 1)
pci_clear_irq(dev->slot, dev->irq_pin);
@@ -419,6 +421,10 @@ sff_reset(void *p)
{
int i = 0;
#ifdef ENABLE_SFF_LOG
sff_log("SFF8038i: Reset\n");
#endif
for (i = 0; i < CDROM_NUM; i++) {
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
(cdrom[i].ide_channel < 4) && cdrom[i].priv)
@@ -429,6 +435,9 @@ sff_reset(void *p)
(zip_drives[i].ide_channel < 4) && zip_drives[i].priv)
zip_reset((scsi_common_t *) zip_drives[i].priv);
}
sff_bus_master_set_irq(0x00, p);
sff_bus_master_set_irq(0x01, p);
}

2
src/disk/hdc_st506_at.c
View File

@@ -463,7 +463,7 @@ mfm_readw(uint16_t port, void *priv)
mfm->secount = (mfm->secount - 1) & 0xff;
if (mfm->secount) {
next_sector(mfm);
mfm->status = STAT_BUSY;
mfm->status = STAT_BUSY | STAT_READY | STAT_DSC;
timer_set_delay_u64(&mfm->callback_timer, SECTOR_TIME);
} else
ui_sb_update_icon(SB_HDD|HDD_BUS_MFM, 0);

6
src/disk/zip.c
View File

@@ -815,8 +815,14 @@ zip_update_request_length(zip_t *dev, int len, int block_len)
/* For media access commands, make sure the requested DRQ length matches the block length. */
switch (dev->current_cdb[0]) {
case 0x08:
case 0x0a:
case 0x28:
case 0x2a:
case 0xa8:
case 0xaa:
/* Round it to the nearest 2048 bytes. */
dev->max_transfer_len = (dev->max_transfer_len >> 9) << 9;
/* Make sure total length is not bigger than sum of the lengths of
all the requested blocks. */
bt = (dev->requested_blocks * block_len);

47
src/floppy/fdc.c
View File

@@ -702,10 +702,6 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = 0x00;
fdc->pnum = fdc->ptot = 0;
}
if (val&4) {
fdc->stat = 0x80;
fdc->pnum = fdc->ptot = 0;
}
if ((val&4) && !(fdc->dor&4)) {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
@@ -775,7 +771,16 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat |= 0x10;
fdc_log("Starting FDC command %02X\n",fdc->command);
switch (fdc->command & 0x1f) {
if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) ||
((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) ||
((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) ||
((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) ||
((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d))
fdc->processed_cmd = fdc->command & 0x1f;
else
fdc->processed_cmd = fdc->command;
switch (fdc->processed_cmd) {
case 0x01: /*Mode*/
if (fdc->flags & FDC_FLAG_NSC) {
fdc->pnum = 0;
@@ -921,7 +926,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
}
if (fdc->pnum == fdc->ptot) {
fdc_log("Got all params %02X\n", fdc->command);
fdc->interrupt = fdc->command & 0x1F;
fdc->interrupt = fdc->processed_cmd;
fdc->reset_stat = 0;
/* Disable timer if enabled. */
timer_disable(&fdc->timer);
@@ -950,7 +955,7 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
break;
}
/* Process the firt phase of the command. */
switch (fdc->interrupt & 0x1F) {
switch (fdc->processed_cmd) {
case 0x02: /* Read a track */
fdc_io_command_phase1(fdc, 0);
fdc->read_track_sector.id.c = fdc->params[1];
@@ -1072,7 +1077,8 @@ fdc_write(uint16_t addr, uint8_t val, void *priv)
fdc->stat = (1 << fdc->drive);
if (!(fdc->flags & FDC_FLAG_PCJR))
fdc->stat |= 0x80;
fdc->head = (fdc->params[0] & 4) ? 1 : 0;
/* fdc->head = (fdc->params[0] & 4) ? 1 : 0; */
fdc->head = 0; /* TODO: See if this is correct. */
fdc->st0 = fdc->params[0] & 0x03;
fdc->st0 |= (fdc->params[0] & 4);
fdc->st0 |= 0x80;
@@ -1210,21 +1216,22 @@ fdc_read(uint16_t addr, void *priv)
}
} else {
if (is486 || !fdc->enable_3f1)
return 0xff;
ret = 0xff;
else {
ret = 0x70;
ret = 0x70;
drive = real_drive(fdc, fdc->dor & 3);
drive = real_drive(fdc, fdc->dor & 3);
if (drive)
ret &= ~0x40;
else
ret &= ~0x20;
if (drive)
ret &= ~0x40;
else
ret &= ~0x20;
if (fdc->dor & 0x10)
ret |= 1;
if (fdc->dor & 0x20)
ret |= 2;
if (fdc->dor & 0x10)
ret |= 1;
if (fdc->dor & 0x20)
ret |= 2;
}
}
break;
case 2:

2
src/floppy/fdc.h
View File

@@ -36,7 +36,7 @@
typedef struct {
uint8_t dor, stat, command, dat, st0, swap;
uint8_t dor, stat, command, processed_cmd, dat, st0, swap;
uint8_t swwp, disable_write;
uint8_t params[256], res[256];
uint8_t specify[256], format_dat[256];

2
src/floppy/fdd_86f.c
View File

@@ -826,7 +826,7 @@ d86f_byteperiod(int drive)
int
d86f_is_mfm(int drive)
{
return (d86f_track_flags(drive) & 8) ? 1 : 0;
return ((d86f_track_flags(drive) & 0x18) == 0x08) ? 1 : 0;
}

36
src/hwm.c Normal file
View File

@@ -0,0 +1,36 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Common functions for hardware monitor chips.
*
* Version: @(#)hwm.c 1.0.0 2020/03/22
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#include <stdint.h>
#include "device.h"
#include "hwm.h"
hwm_values_t hwm_values;
void
hwm_set_values(hwm_values_t new_values)
{
hwm_values = new_values;
}
hwm_values_t*
hwm_get_values()
{
return &hwm_values;
}

38
src/hwm.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for the hardware monitor chips.
*
* Version: @(#)hwm.h 1.0.0 2020/03/21
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#ifndef EMU_HWM_H
# define EMU_HWM_H
#define VDIV(v, r1, r2) (((v) * (r2)) / ((r1) + (r2)))
typedef struct _hwm_values_ {
uint16_t fans[4];
uint8_t temperatures[4];
uint8_t voltages[8];
} hwm_values_t;
extern void hwm_set_values(hwm_values_t new_values);
extern hwm_values_t* hwm_get_values();
extern const device_t w83781d_device;
extern const device_t as99127f_device;
#endif /*EMU_HWM_H*/

482
src/hwm_w83781d.c Normal file
View File

@@ -0,0 +1,482 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Winbond W83781D hardware monitoring chip.
*
* Version: @(#)hwm_w83781d.c 1.0.0 2020/03/21
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "device.h"
#include "86box_io.h"
#include "smbus.h"
#include "hwm.h"
#define W83781D_SMBUS 0x10000
#define W83781D_AS99127F 0x20000
#define W83781D_VENDOR_ID ((dev->local & W83781D_AS99127F) ? 0x12C3 : 0x5CA3)
#define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
#define W83781D_RPM_TO_REG(r, d) CLAMP(1350000 / (r * d), 1, 255)
#define W83781D_TEMP_TO_REG(t) ((t) * 8) << 5
typedef struct {
uint32_t local;
hwm_values_t* values;
uint8_t regs[64];
uint8_t regs_bank1[6];
uint8_t regs_bank2[6];
uint8_t addr_register;
uint8_t data_register;
uint8_t smbus_addr_main;
uint8_t smbus_addr_temp2;
uint8_t smbus_addr_temp3;
uint8_t hbacs;
uint8_t active_bank;
} w83781d_t;
static uint8_t w83781d_isa_read(uint16_t port, void *priv);
static uint8_t w83781d_smbus_read_byte(uint8_t addr, void *priv);
static uint8_t w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv);
static uint16_t w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv);
static uint8_t w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank);
static void w83781d_isa_write(uint16_t port, uint8_t val, void *priv);
static void w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv);
static void w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv);
static void w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv);
static uint8_t w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank);
static void w83781d_reset(w83781d_t *dev, uint8_t initialization);
static void
w83781d_remap(w83781d_t *dev)
{
if (!(dev->local & W83781D_SMBUS)) return;
smbus_removehandler(0x00, 0x80,
w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
dev);
if (dev->smbus_addr_main) smbus_sethandler(dev->smbus_addr_main, 1,
w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
dev);
if (dev->smbus_addr_temp2) smbus_sethandler(dev->smbus_addr_temp2, 1,
w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
dev);
if (dev->smbus_addr_temp3) smbus_sethandler(dev->smbus_addr_temp3, 1,
w83781d_smbus_read_byte, w83781d_smbus_read_byte_cmd, w83781d_smbus_read_word_cmd, NULL,
w83781d_smbus_write_byte, w83781d_smbus_write_byte_cmd, w83781d_smbus_write_word_cmd, NULL,
dev);
}
static uint8_t
w83781d_isa_read(uint16_t port, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
uint8_t ret = 0xFF;
switch (port - (dev->local & 0xFFFF)) {
case 0x0:
ret = dev->addr_register & 0x7F;
break;
case 0x1:
ret = w83781d_read(dev, dev->addr_register, dev->active_bank);
if (dev->active_bank == 0 &&
(dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
(dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
}
return ret;
}
static uint8_t
w83781d_smbus_read_byte(uint8_t addr, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
return w83781d_read(dev, dev->addr_register, 0);
}
static uint8_t
w83781d_smbus_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
return w83781d_read(dev, cmd, 0);
}
static uint16_t
w83781d_smbus_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
uint8_t rethi = 0;
uint8_t retlo = 0;
uint8_t bank = 0;
if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
if (addr == dev->smbus_addr_temp2)
bank = 2;
else
bank = 3;
switch (cmd & 0x3) {
case 0x0:
rethi = w83781d_read(dev, 0x50, bank);
retlo = w83781d_read(dev, 0x51, bank);
break;
case 0x1:
rethi = retlo = w83781d_read(dev, 0x52, bank);
break;
case 0x2:
rethi = w83781d_read(dev, 0x53, bank);
retlo = w83781d_read(dev, 0x54, bank);
break;
case 0x3:
rethi = w83781d_read(dev, 0x55, bank);
retlo = w83781d_read(dev, 0x56, bank);
break;
}
return (retlo << 8) | rethi; /* byte-swapped for some reason */
}
return w83781d_read(dev, cmd, bank);
}
static uint8_t
w83781d_read(w83781d_t *dev, uint8_t reg, uint8_t bank)
{
uint8_t ret = 0;
if ((reg >> 4) == 0x5 && bank != 0) {
/* bank-switched temperature registers */
if (bank == 1)
ret = dev->regs_bank1[reg - 0x50];
else
ret = dev->regs_bank2[reg - 0x50];
} else {
/* regular registers */
if (reg == 0x4F) /* special case for two-byte vendor ID register */
ret = dev->hbacs ? (W83781D_VENDOR_ID >> 8) : (W83781D_VENDOR_ID & 0xFF);
else if (reg >= 0x60) /* read auto-increment value RAM registers from their non-auto-increment locations */
ret = dev->regs[reg - 0x40];
else
ret = dev->regs[reg - 0x20];
}
return ret;
}
static void
w83781d_isa_write(uint16_t port, uint8_t val, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
switch (port - (dev->local & 0xFFFF)) {
case 0x0:
dev->addr_register = val & 0x7F;
break;
case 0x1:
w83781d_write(dev, dev->addr_register, val, dev->active_bank);
if (dev->active_bank == 0 &&
(dev->addr_register == 0x41 || dev->addr_register == 0x43 || dev->addr_register == 0x45 || dev->addr_register == 0x56 ||
(dev->addr_register >= 0x60 && dev->addr_register < 0x7F))) {
/* auto-increment registers */
dev->addr_register++;
}
break;
}
}
static void
w83781d_smbus_write_byte(uint8_t addr, uint8_t val, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
dev->addr_register = val;
}
static void
w83781d_smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
w83781d_write(dev, cmd, val, 0);
}
static void
w83781d_smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
uint8_t valhi = (val >> 8);
uint8_t vallo = (val & 0xFF);
uint8_t bank = 0;
if (addr == dev->smbus_addr_temp2 || addr == dev->smbus_addr_temp3) {
if (addr == dev->smbus_addr_temp2)
bank = 2;
else
bank = 3;
switch (cmd & 0x3) {
case 0x0:
w83781d_write(dev, 0x50, valhi, bank);
w83781d_write(dev, 0x51, vallo, bank);
break;
case 0x1:
w83781d_write(dev, 0x52, vallo, bank);
break;
case 0x2:
w83781d_write(dev, 0x53, valhi, bank);
w83781d_write(dev, 0x54, vallo, bank);
break;
case 0x3:
w83781d_write(dev, 0x55, valhi, bank);
w83781d_write(dev, 0x56, vallo, bank);
break;
break;
}
return;
}
w83781d_write(dev, cmd, vallo, bank);
}
static uint8_t
w83781d_write(w83781d_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
{
uint8_t remap = 0;
if ((reg >> 4) == 0x5 && bank != 0) {
/* bank-switched temperature registers */
switch (reg) {
case 0x50: case 0x51:
/* read-only registers */
return 0;
}
if (bank == 1)
dev->regs_bank1[reg - 0x50] = val;
else
dev->regs_bank2[reg - 0x50] = val;
return 1;
}
/* regular registers */
switch (reg) {
case 0x41: case 0x42: case 0x4F: case 0x58:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: case 0x28: case 0x29: case 0x2A:
case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: case 0x68: case 0x69: case 0x6A:
/* read-only registers */
return 0;
}
if (reg >= 0x60) /* write auto-increment value RAM registers to their non-auto-increment locations */
dev->regs[reg - 0x40] = val;
else
dev->regs[reg - 0x20] = val;
switch (reg) {
case 0x40:
if (val >> 7) {
/* INITIALIZATION bit set: reset all registers except main SMBus address */
w83781d_reset(dev, 1);
}
break;
case 0x47:
/* update FAN1/FAN2 values to match the new divisor */
dev->regs[0x08] = W83781D_RPM_TO_REG(dev->values->fans[0], 1 << ((dev->regs[0x27] >> 4) & 0x3));
dev->regs[0x09] = W83781D_RPM_TO_REG(dev->values->fans[1], 1 << ((dev->regs[0x27] >> 6) & 0x3));
break;
case 0x48:
if (dev->local & W83781D_SMBUS) {
dev->smbus_addr_main = (dev->regs[0x28] & 0x7F);
remap = 1;
}
break;
case 0x4A:
if (dev->local & W83781D_SMBUS) {
/* DIS_T2 and DIS_T3 bits can disable those interfaces */
if ((dev->regs[0x2A] >> 3) & 0x1)
dev->smbus_addr_temp2 = 0x00;
else
dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x2A] & 0x7);
if (dev->regs[0x2A] >> 7)
dev->smbus_addr_temp3 = 0x00;
else
dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x2A] >> 4) & 0x7);
remap = 1;
}
break;
case 0x4B:
/* update FAN3 value to match the new divisor */
dev->regs[0x0A] = W83781D_RPM_TO_REG(dev->values->fans[2], 1 << ((dev->regs[0x2B] >> 6) & 0x3));
break;
case 0x4E:
dev->hbacs = (dev->regs[0x2E] & 0x80);
/* FIXME: Winbond's datasheet does not specify how BANKSEL[0:2] work */
if (dev->regs[0x2E] & 0x1)
dev->active_bank = 0;
else if (dev->regs[0x2E] & 0x2)
dev->active_bank = 1;
else if (dev->regs[0x2E] & 0x4)
dev->active_bank = 2;
break;
}
if (remap)
w83781d_remap(dev);
return 1;
}
static void
w83781d_reset(w83781d_t *dev, uint8_t initialization)
{
memset(dev->regs, 0, 64);
memset(dev->regs_bank1, 0, 6);
memset(dev->regs_bank2, 0, 6);
/* WARNING: Array elements are register - 0x20. */
uint8_t i;
for (i = 0; i <= 6; i++)
dev->regs[i] = dev->values->voltages[i];
dev->regs[0x07] = dev->values->temperatures[0];
for (i = 0; i <= 2; i++)
dev->regs[0x08 + i] = W83781D_RPM_TO_REG(dev->values->fans[i], 2);
dev->regs[0x20] = 0x01;
dev->regs[0x26] = 0x40;
dev->regs[0x27] = 0x50;
if (dev->local & W83781D_SMBUS) {
if (!initialization) /* don't reset main SMBus address if the reset was triggered by the INITIALIZATION bit */
dev->smbus_addr_main = 0x2D;
dev->regs[0x28] = dev->smbus_addr_main;
dev->regs[0x2A] = 0x01;
dev->smbus_addr_temp2 = 0x48 + (dev->regs[0x2A] & 0x7);
dev->smbus_addr_temp3 = 0x48 + ((dev->regs[0x2A] >> 4) & 0x7);
} else {
dev->regs[0x28] = 0x00;
dev->regs[0x2A] = 0x88;
dev->smbus_addr_temp2 = dev->smbus_addr_temp3 = 0x00;
}
dev->regs[0x29] = 0x02;
dev->regs[0x2B] = 0x44;
dev->regs[0x2C] = 0x01;
dev->regs[0x2D] = 0x15;
dev->regs[0x2E] = 0x80;
dev->hbacs = (dev->regs[0x2E] & 0x80);
dev->regs[0x2F] = W83781D_VENDOR_ID >> 8;
dev->regs[0x37] = 0x80;
dev->regs[0x38] = (dev->local & W83781D_AS99127F) ? 0x31 : 0x10;
/* WARNING: Array elements are register - 0x50. */
uint16_t temp;
temp = W83781D_TEMP_TO_REG(dev->values->temperatures[1]);
dev->regs_bank1[0x0] = temp >> 8;
dev->regs_bank1[0x1] = temp & 0xFF;
dev->regs_bank1[0x3] = 0x4B;
dev->regs_bank1[0x5] = 0x50;
temp = W83781D_TEMP_TO_REG(dev->values->temperatures[2]);
dev->regs_bank2[0x0] = temp >> 8;
dev->regs_bank2[0x1] = temp & 0xFF;
dev->regs_bank2[0x3] = 0x4B;
dev->regs_bank2[0x5] = 0x50;
w83781d_remap(dev);
}
static void
w83781d_close(void *priv)
{
w83781d_t *dev = (w83781d_t *) priv;
uint16_t isa_io = dev->local & 0xFFFF;
if (isa_io)
io_removehandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
free(dev);
}
static void *
w83781d_init(const device_t *info)
{
w83781d_t *dev = (w83781d_t *) malloc(sizeof(w83781d_t));
memset(dev, 0, sizeof(w83781d_t));
dev->local = info->local;
dev->values = hwm_get_values();
w83781d_reset(dev, 0);
uint16_t isa_io = dev->local & 0xFFFF;
if (isa_io)
io_sethandler(isa_io, 2, w83781d_isa_read, NULL, NULL, w83781d_isa_write, NULL, NULL, dev);
return dev;
}
const device_t w83781d_device = {
"Winbond W83781D Hardware Monitor",
DEVICE_ISA,
0x295 | W83781D_SMBUS,
w83781d_init, w83781d_close, NULL,
NULL, NULL, NULL,
NULL
};
/*
* ASUS rebadged version of the W83781D.
* Some claim it's SMBus-only, yet the BIOS clearly reads most values over ISA,
* except TEMP3 (CPU Temperature) which is read over SMBus.
*/
const device_t as99127f_device = {
"ASUS AS99127F Hardware Monitor",
DEVICE_ISA,
0x295 | W83781D_SMBUS | W83781D_AS99127F,
w83781d_init, w83781d_close, NULL,
NULL, NULL, NULL,
NULL
};

561
src/intel_flash - Cópia.c
View File

@@ -1,561 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the Intel 1 Mbit and 2 Mbit, 8-bit and
* 16-bit flash devices.
*
* Version: @(#)intel_flash.c 1.0.19 2019/06/25
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include "86box.h"
#include "device.h"
#include "mem.h"
#include "machine.h"
#include "timer.h"
#include "nvr.h"
#include "plat.h"
#define FLAG_BYTEMODE 4
#define FLAG_WORD 4
#define FLAG_BXB 2
#define FLAG_INV_A16 1
enum
{
BLOCK_MAIN1,
BLOCK_MAIN2,
BLOCK_DATA1,
BLOCK_DATA2,
BLOCK_BOOT,
BLOCKS_NUM
};
enum
{
CMD_READ_ARRAY = 0xff,
CMD_IID = 0x90,
CMD_READ_STATUS = 0x70,
CMD_CLEAR_STATUS = 0x50,
CMD_ERASE_SETUP = 0x20,
CMD_ERASE_CONFIRM = 0xd0,
CMD_ERASE_SUSPEND = 0xb0,
CMD_PROGRAM_SETUP = 0x40,
CMD_PROGRAM_SETUP_ALT = 0x10
};
typedef struct flash_t
{
uint8_t command, status,
pad, flags,
*array;
uint16_t flash_id, pad16;
uint32_t program_addr,
block_start[BLOCKS_NUM], block_end[BLOCKS_NUM],
block_len[BLOCKS_NUM];
mem_mapping_t mapping[4], mapping_h[8];
} flash_t;
static wchar_t flash_path[1024];
static uint16_t flash_readw(uint32_t addr, void *p);
static uint8_t
flash_read(uint32_t addr, void *p)
{
flash_t *dev = (flash_t *) p;
uint8_t ret = 0xff;
if (dev->flags & FLAG_WORD)
return flash_readw(addr, p) & 0xff;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
switch (dev->command) {
case CMD_READ_ARRAY:
default:
ret = dev->array[addr];
break;
case CMD_IID:
/* Yes, & 2 is correct for the 100BX/200BX in BYTE mode. */
if (addr & 1)
ret = dev->flash_id & 0xff;
else
ret = 0x89;
// pclog("id b %i: %02X\n", addr & 1, ret);
break;
case CMD_READ_STATUS:
ret = dev->status;
break;
}
#if 0
if ((dev->command & 0x0f) && (dev->command != 0xff))
ret = dev->status;
#endif
return ret;
}
static uint16_t
flash_readw(uint32_t addr, void *p)
{
flash_t *dev = (flash_t *) p;
uint16_t *q;
uint16_t ret = 0xffff;
if (!(dev->flags & FLAG_WORD))
return flash_read(addr, p) | (flash_read(addr + 1, p) << 8);
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
if (dev->flags & FLAG_WORD)
addr &= 0xfffffffe;
q = (uint16_t *)&(dev->array[addr]);
ret = *q;
switch (dev->command) {
case CMD_READ_ARRAY:
default:
break;
case CMD_IID:
// pclog("id w %i: %02X\n", addr & 2, ret);
if (addr & 2)
ret = dev->flash_id;
else
ret = 0x0089;
break;
case CMD_READ_STATUS:
ret = dev->status;
break;
}
return ret;
}
static uint32_t
flash_readl(uint32_t addr, void *p)
{
flash_t *dev = (flash_t *)p;
uint32_t *q;
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
q = (uint32_t *)&(dev->array[addr]);
return *q;
// return flash_readw(addr, p) | (flash_readw(addr + 2, p) << 16);
}
static void flash_writew(uint32_t addr, uint16_t val, void *p);
static void
flash_write(uint32_t addr, uint8_t val, void *p)
{
flash_t *dev = (flash_t *) p;
int i;
uint32_t bb_mask = biosmask & 0xffffe000;
uint32_t o = addr;
if (biosmask == 0x3ffff)
bb_mask &= 0xffffc000;
if (dev->flags & FLAG_WORD) {
flash_writew(addr, val, p);
return;
}
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
if ((addr >= 0x2e400) && (addr <= 0x2e43f)) {
dev->array[addr] = val;
return;
}
switch (dev->command) {
case CMD_ERASE_SETUP:
if (val == CMD_ERASE_CONFIRM) {
for (i = 0; i < 3; i++) {
if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
}
dev->status = 0x80;
}
dev->command = CMD_READ_STATUS;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
if (((addr & bb_mask) != (dev->block_start[4] & bb_mask)) && (addr == dev->program_addr))
dev->array[addr] = val;
dev->command = CMD_READ_STATUS;
dev->status = 0x80;
break;
default:
dev->command = val;
// pclog("[%04X:%08X] (%08X, %02X) [%08X] command b = %02X\n", CS, cpu_state.pc, cpu_state.seg_cs.base, opcode, o, dev->command);
#if 0
if (val == 0x93) {
FILE *f = fopen("d:\\queen\\86boxnew\\mem.dmp", "wb");
for (i = 0; i < 1114096; i++)
fputc(mem_readb_phys(i), f);
fclose(f);
f = fopen("d:\\queen\\86boxnew\\highbios.dmp", "wb");
for (i = 0; i < 524288; i++)
fputc(mem_readb_phys(i + 0xfff80000), f);
fclose(f);
fatal("Fo' shizzle da nizzle\n");
}
#endif
switch (val) {
case CMD_CLEAR_STATUS:
dev->status = 0;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
dev->program_addr = addr;
break;
}
}
}
static void
flash_writew(uint32_t addr, uint16_t val, void *p)
{
flash_t *dev = (flash_t *) p;
int i;
uint32_t bb_mask = biosmask & 0xffffe000;
if (biosmask == 0x3ffff)
bb_mask &= 0xffffc000;
if (!(dev->flags & FLAG_WORD)) {
// flash_write(addr, val & 0xff, p);
// flash_write(addr + 1, (val >> 8) & 0xff, p);
return;
}
if (dev->flags & FLAG_INV_A16)
addr ^= 0x10000;
addr &= biosmask;
if (dev->flags & FLAG_WORD) switch (dev->command) {
case CMD_ERASE_SETUP:
if (val == CMD_ERASE_CONFIRM) {
for (i = 0; i < 3; i++) {
if ((addr >= dev->block_start[i]) && (addr <= dev->block_end[i]))
memset(&(dev->array[dev->block_start[i]]), 0xff, dev->block_len[i]);
}
dev->status = 0x80;
}
dev->command = CMD_READ_STATUS;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
if (((addr & bb_mask) != (dev->block_start[4] & bb_mask)) && (addr == dev->program_addr))
*(uint16_t *) (&dev->array[addr]) = val;
dev->command = CMD_READ_STATUS;
dev->status = 0x80;
break;
default:
dev->command = val & 0xff;
// pclog("command w = %02X\n", dev->command);
switch (val) {
case CMD_CLEAR_STATUS:
dev->status = 0;
break;
case CMD_PROGRAM_SETUP:
case CMD_PROGRAM_SETUP_ALT:
dev->program_addr = addr;
break;
}
}
}
static void
flash_writel(uint32_t addr, uint32_t val, void *p)
{
flash_writew(addr, val & 0xffff, p);
flash_writew(addr + 2, (val >> 16) & 0xffff, p);
}
static void
intel_flash_add_mappings(flash_t *dev)
{
int max = 2, i = 0;
uint32_t base, fbase;
uint32_t sub = 0x20000;
if (biosmask == 0x3ffff) {
sub = 0x40000;
max = 4;
}
for (i = 0; i < max; i++) {
if (biosmask == 0x3ffff)
base = 0xc0000 + (i << 16);
else
base = 0xe0000 + (i << 16);
fbase = base & biosmask;
if (dev->flags & FLAG_INV_A16)
fbase ^= 0x10000;
memcpy(&dev->array[fbase], &rom[base & biosmask], 0x10000);
if ((max == 2) || (i >= 2)) {
mem_mapping_add(&(dev->mapping[i]), base, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
}
mem_mapping_add(&(dev->mapping_h[i]), (base | 0xfff00000) - sub, 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
mem_mapping_add(&(dev->mapping_h[i + 4]), (base | 0xfff00000), 0x10000,
flash_read, flash_readw, flash_readl,
flash_write, flash_writew, flash_writel,
dev->array + fbase, MEM_MAPPING_EXTERNAL|MEM_MAPPING_ROMCS, (void *) dev);
}
}
static void *
intel_flash_init(const device_t *info)
{
FILE *f;
int l;
flash_t *dev;
wchar_t *machine_name, *flash_name;
uint8_t type = info->local & 0xff;
dev = malloc(sizeof(flash_t));
memset(dev, 0, sizeof(flash_t));
l = strlen(machine_get_internal_name_ex(machine))+1;
machine_name = (wchar_t *) malloc(l * sizeof(wchar_t));
mbstowcs(machine_name, machine_get_internal_name_ex(machine), l);
l = wcslen(machine_name)+5;
flash_name = (wchar_t *)malloc(l*sizeof(wchar_t));
swprintf(flash_name, l, L"%ls.bin", machine_name);
if (wcslen(flash_name) <= 1024)
wcscpy(flash_path, flash_name);
else
wcsncpy(flash_path, flash_name, 1024);
dev->flags = info->local & 0xff;
mem_mapping_disable(&bios_mapping);
mem_mapping_disable(&bios_high_mapping);
dev->array = (uint8_t *) malloc(biosmask + 1);
memset(dev->array, 0xff, biosmask + 1);
if (biosmask == 0x3ffff) {
if (dev->flags & FLAG_WORD)
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x2275 : 0x2274;
else
dev->flash_id = (dev->flags & FLAG_BXB) ? 0x7D : 0x7C;
/* The block lengths are the same both flash types. */
dev->block_len[BLOCK_MAIN1] = 0x20000;
dev->block_len[BLOCK_MAIN2] = 0x18000;
dev->block_len[BLOCK_DATA1] = 0x02000;
dev->block_len[BLOCK_DATA2] = 0x02000;
dev->block_len[BLOCK_BOOT] = 0x04000;
if (dev->flags & FLAG_BXB) { /* 28F002BX-B/28F200BX-B */
dev->block_start[BLOCK_MAIN1] = 0x20000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x3ffff;
dev->block_start[BLOCK_MAIN2] = 0x08000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0x1ffff;
dev->block_start[BLOCK_DATA1] = 0x06000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x07fff;
dev->block_start[BLOCK_DATA2] = 0x04000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x05fff;
dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x03fff;
} else { /* 28F002BX-T/28F200BX-T */
dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1ffff;
dev->block_start[BLOCK_MAIN2] = 0x20000; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0x37fff;
dev->block_start[BLOCK_DATA1] = 0x38000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x39fff;
dev->block_start[BLOCK_DATA2] = 0x3a000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x3bfff;
dev->block_start[BLOCK_BOOT] = 0x3c000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x3ffff;
}
} else {
dev->flash_id = (type & FLAG_BXB) ? 0x95 : 0x94;
/* The block lengths are the same both flash types. */
dev->block_len[BLOCK_MAIN1] = 0x1c000;
dev->block_len[BLOCK_MAIN2] = 0x00000;
dev->block_len[BLOCK_DATA1] = 0x01000;
dev->block_len[BLOCK_DATA2] = 0x01000;
dev->block_len[BLOCK_BOOT] = 0x02000;
if (dev->flags & FLAG_BXB) { /* 28F001BX-B/28F100BX-B */
dev->block_start[BLOCK_MAIN1] = 0x04000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1ffff;
dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x02000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x02fff;
dev->block_start[BLOCK_DATA2] = 0x03000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x03fff;
dev->block_start[BLOCK_BOOT] = 0x00000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x01fff;
} else { /* 28F001BX-T/28F100BX-T */
dev->block_start[BLOCK_MAIN1] = 0x00000; /* MAIN BLOCK 1 */
dev->block_end[BLOCK_MAIN1] = 0x1bfff;
dev->block_start[BLOCK_MAIN2] = 0xfffff; /* MAIN BLOCK 2 */
dev->block_end[BLOCK_MAIN2] = 0xfffff;
dev->block_start[BLOCK_DATA1] = 0x1c000; /* DATA AREA 1 BLOCK */
dev->block_end[BLOCK_DATA1] = 0x1cfff;
dev->block_start[BLOCK_DATA2] = 0x1d000; /* DATA AREA 2 BLOCK */
dev->block_end[BLOCK_DATA2] = 0x1dfff;
dev->block_start[BLOCK_BOOT] = 0x1e000; /* BOOT BLOCK */
dev->block_end[BLOCK_BOOT] = 0x1ffff;
}
}
intel_flash_add_mappings(dev);
dev->command = CMD_READ_ARRAY;
dev->status = 0;
f = nvr_fopen(flash_path, L"rb");
if (f) {
fread(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f);
if (dev->block_len[BLOCK_MAIN2])
fread(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f);
fread(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f);
fread(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f);
fclose(f);
}
free(flash_name);
free(machine_name);
if (dev->flags & FLAG_WORD)
dev->flags &= ~FLAG_WORD;
return dev;
}
static void
intel_flash_close(void *p)
{
FILE *f;
flash_t *dev = (flash_t *)p;
f = nvr_fopen(flash_path, L"wb");
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN1]]), dev->block_len[BLOCK_MAIN1], 1, f);
if (dev->block_len[BLOCK_MAIN2])
fwrite(&(dev->array[dev->block_start[BLOCK_MAIN2]]), dev->block_len[BLOCK_MAIN2], 1, f);
fwrite(&(dev->array[dev->block_start[BLOCK_DATA1]]), dev->block_len[BLOCK_DATA1], 1, f);
fwrite(&(dev->array[dev->block_start[BLOCK_DATA2]]), dev->block_len[BLOCK_DATA2], 1, f);
fclose(f);
free(dev);
}
/* For AMI BIOS'es - Intel 28F001BXT with A16 pin inverted. */
const device_t intel_flash_bxt_ami_device =
{
"Intel 28F001BXT/28F002BXT Flash BIOS",
0,
FLAG_INV_A16,
intel_flash_init,
intel_flash_close,
NULL,
NULL, NULL, NULL, NULL
};
#if defined(DEV_BRANCH) && defined(USE_TC430HX)
const device_t intel_flash_bxtw_ami_device =
{
"Intel 28F100BXT/28F200BXT Flash BIOS",
0,
FLAG_INV_A16 | FLAG_WORD,
intel_flash_init,
intel_flash_close,
NULL,
NULL, NULL, NULL, NULL
};
#endif
const device_t intel_flash_bxt_device =
{
"Intel 28F001BXT/28F002BXT Flash BIOS",
0, 0,
intel_flash_init,
intel_flash_close,
NULL,
NULL, NULL, NULL, NULL
};
const device_t intel_flash_bxb_device =
{
"Intel 28F001BXB/28F002BXB Flash BIOS",
0, FLAG_BXB,
intel_flash_init,
intel_flash_close,
NULL,
NULL, NULL, NULL, NULL
};

12
src/intel_flash.c
View File

@@ -90,11 +90,6 @@ flash_read(uint32_t addr, void *p)
addr &= biosmask;
switch (dev->command) {
case 0x00:
case 0x93:
ret = 0xff;
break;
case CMD_READ_ARRAY:
default:
ret = dev->array[addr];
@@ -102,7 +97,7 @@ flash_read(uint32_t addr, void *p)
case CMD_IID:
if (addr & 1)
ret = dev->flash_id & 0xff;
ret = dev->flash_id & 0xff;
else
ret = 0x89;
break;
@@ -134,11 +129,6 @@ flash_readw(uint32_t addr, void *p)
ret = *q;
if (dev->flags & FLAG_WORD) switch (dev->command) {
case 0x00:
case 0x93:
ret = 0xffff;
break;
case CMD_READ_ARRAY:
default:
break;

1131
src/intel_piix - Cópia.c
View File

File diff suppressed because it is too large Load Diff

291
src/intel_piix.c
View File

@@ -35,6 +35,7 @@
#include "device.h"
#include "apm.h"
#include "keyboard.h"
#include "machine.h"
#include "mem.h"
#include "timer.h"
#include "nvr.h"
@@ -46,6 +47,7 @@
#include "hdc_ide_sff8038i.h"
#include "zip.h"
#include "machine.h"
#include "smbus.h"
#include "piix.h"
@@ -87,11 +89,12 @@ typedef struct
typedef struct
{
uint8_t stat, ctl, cmd, addr,
uint8_t stat, next_stat, ctl, cmd, addr,
data0, data1,
index,
data[32];
} smbus_t;
pc_timer_t command_timer;
} piix_smbus_t;
typedef struct
@@ -107,7 +110,7 @@ typedef struct
sff8038i_t *bm[2];
ddma_t ddma[2];
power_t power;
smbus_t smbus;
piix_smbus_t smbus;
nvr_t * nvr;
} piix_t;
@@ -140,12 +143,18 @@ void do_irq(piix_t *dev, int func, int level)
return;
if (level) {
// pci_set_irq(dev->pci_slot, dev->regs[func][0x3d]);
#ifdef WRONG_SPEC
pci_set_irq(dev->pci_slot, dev->regs[func][0x3d]);
#else
picintlevel(1 << 9);
#endif
piix_log("Raising IRQ...\n");
} else {
// pci_clear_irq(dev->pci_slot, dev->regs[func][0x3d]);
#ifdef WRONG_SPEC
pci_clear_irq(dev->pci_slot, dev->regs[func][0x3d]);
#else
picintc(1 << 9);
#endif
piix_log("Lowering IRQ...\n");
}
}
@@ -367,7 +376,7 @@ power_reg_readl(uint16_t addr, void *p)
break;
}
// pclog("ACPI: Read L %08X from %04X\n", ret, addr);
piix_log("ACPI: Read L %08X from %04X\n", ret, addr);
return ret;
}
@@ -392,7 +401,7 @@ power_reg_readw(uint16_t addr, void *p)
break;
}
// pclog("ACPI: Read W %08X from %04X\n", ret, addr);
piix_log("ACPI: Read W %08X from %04X\n", ret, addr);
return ret;
}
@@ -409,11 +418,11 @@ power_reg_read(uint16_t addr, void *p)
switch (addr & 0x3f) {
case 0x30: case 0x31: case 0x32:
ret = dev->power.gporeg[addr & 0x03];
// pclog("ACPI: Read B %02X from GPIREG %01X\n", ret, addr & 0x03);
piix_log("ACPI: Read B %02X from GPIREG %01X\n", ret, addr & 0x03);
break;
case 0x34: case 0x35: case 0x36: case 0x37:
ret = dev->power.gporeg[addr & 0x03];
// pclog("ACPI: Read B %02X from GPOREG %01X\n", ret, addr & 0x03);
piix_log("ACPI: Read B %02X from GPOREG %01X\n", ret, addr & 0x03);
break;
default:
ret16 = power_reg_readw(addr, p);
@@ -433,7 +442,7 @@ power_reg_write(uint16_t addr, uint8_t val, void *p)
{
piix_t *dev = (piix_t *) p;
// pclog("ACPI: Write %02X to %04X\n", val, addr);
piix_log("ACPI: Write %02X to %04X\n", val, addr);
switch (addr & 0x3f) {
case 0x34: case 0x35: case 0x36: case 0x37:
@@ -457,17 +466,145 @@ power_update_io_mapping(piix_t *dev)
static uint8_t
smbus_reg_read(uint16_t addr, void *p)
smbus_reg_read(uint16_t addr, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t ret = 0x00;
switch (addr - dev->smbus_io_base) {
case 0x00:
ret = dev->smbus.stat;
break;
case 0x02:
dev->smbus.index = 0;
ret = dev->smbus.ctl;
break;
case 0x03:
ret = dev->smbus.cmd;
break;
case 0x04:
ret = dev->smbus.addr;
break;
case 0x05:
ret = dev->smbus.data0;
break;
case 0x06:
ret = dev->smbus.data1;
break;
case 0x07:
ret = dev->smbus.data[dev->smbus.index++];
if (dev->smbus.index > 31)
dev->smbus.index = 0;
break;
}
piix_log("smbus_reg_read %02x %02x\n", addr - dev->smbus_io_base, ret);
return ret;
}
static void
smbus_reg_write(uint16_t addr, uint8_t val, void *p)
smbus_reg_write(uint16_t addr, uint8_t val, void *priv)
{
piix_t *dev = (piix_t *) priv;
uint8_t smbus_addr;
uint8_t smbus_read;
uint16_t temp;
piix_log("smbus_reg_write %02x %02x\n", addr - dev->smbus_io_base, val);
dev->smbus.next_stat = 0;
switch (addr - dev->smbus_io_base) {
case 0x00:
/* some status bits are reset by writing 1 to them */
for (smbus_addr = 0x02; smbus_addr <= 0x10; smbus_addr = smbus_addr << 1) {
if (val & smbus_addr)
dev->smbus.stat = dev->smbus.stat & ~smbus_addr;
}
break;
case 0x02:
dev->smbus.ctl = val & ~(0x40); /* START always reads 0 */
if (val & 0x40) { /* dispatch command if START is set */
smbus_addr = (dev->smbus.addr >> 1);
if (!smbus_has_device(smbus_addr)) {
/* raise DEV_ERR if no device is at this address */
dev->smbus.next_stat = 0x4;
break;
}
smbus_read = (dev->smbus.addr & 0x01);
switch ((val >> 2) & 0x7) {
case 0x0: /* quick R/W */
dev->smbus.next_stat = 0x2;
break;
case 0x1: /* byte R/W */
if (smbus_read)
dev->smbus.data0 = smbus_read_byte(smbus_addr);
else
smbus_write_byte(smbus_addr, dev->smbus.data0);
dev->smbus.next_stat = 0x2;
break;
case 0x2: /* byte data R/W */
if (smbus_read)
dev->smbus.data0 = smbus_read_byte_cmd(smbus_addr, dev->smbus.cmd);
else
smbus_write_byte_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data0);
dev->smbus.next_stat = 0x2;
break;
case 0x3: /* word data R/W */
if (smbus_read) {
temp = smbus_read_word_cmd(smbus_addr, dev->smbus.cmd);
dev->smbus.data0 = (temp & 0xFF);
dev->smbus.data1 = (temp >> 8);
} else {
temp = (dev->smbus.data1 << 8) | dev->smbus.data0;
smbus_write_word_cmd(smbus_addr, dev->smbus.cmd, temp);
}
dev->smbus.next_stat = 0x2;
break;
case 0x5: /* block R/W */
if (smbus_read)
dev->smbus.data0 = smbus_read_block_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data);
else
smbus_write_block_cmd(smbus_addr, dev->smbus.cmd, dev->smbus.data, dev->smbus.data0);
dev->smbus.next_stat = 0x2;
break;
}
}
break;
case 0x03:
dev->smbus.cmd = val;
break;
case 0x04:
dev->smbus.addr = val;
break;
case 0x05:
dev->smbus.data0 = val;
break;
case 0x06:
dev->smbus.data1 = val;
break;
case 0x07:
dev->smbus.data[dev->smbus.index++] = val;
if (dev->smbus.index > 31)
dev->smbus.index = 0;
break;
}
if (dev->smbus.next_stat) {
dev->smbus.stat = 0x1;
timer_disable(&dev->smbus.command_timer);
timer_set_delay_u64(&dev->smbus.command_timer, 10 * TIMER_USEC);
}
}
static void
smbus_inter(void *priv)
{
piix_t *dev = (piix_t *) priv;
dev->smbus.stat = dev->smbus.next_stat;
}
@@ -494,7 +631,7 @@ piix_write(int func, int addr, uint8_t val, void *priv)
if (func > dev->max_func)
return;
// pclog("PIIX function %i write: %02X to %02X\n", func, val, addr);
piix_log("PIIX function %i write: %02X to %02X\n", func, val, addr);
fregs = (uint8_t *) dev->regs[func];
if (func == 0) switch (addr) {
@@ -717,6 +854,10 @@ piix_write(int func, int addr, uint8_t val, void *priv)
fregs[0x21] = val;
piix_ide_bm_handlers(dev);
break;
case 0x3c:
piix_log("IDE IRQ write: %02X\n", val);
fregs[0x3c] = val;
break;
case 0x40: case 0x42:
fregs[addr] = val;
break;
@@ -884,7 +1025,7 @@ piix_read(int func, int addr, void *priv)
fregs = (uint8_t *) dev->regs[func];
ret = fregs[addr];
// pclog("PIIX function %i read: %02X from %02X\n", func, ret, addr);
piix_log("PIIX function %i read: %02X from %02X\n", func, ret, addr);
}
return ret;
@@ -944,7 +1085,9 @@ piix_reset_hard(piix_t *dev)
sff_set_irq_mode(dev->bm[1], 0);
}
// pclog("piix_reset_hard()\n");
#ifdef ENABLE_PIIX_LOG
piix_log("piix_reset_hard()\n");
#endif
ide_pri_disable();
ide_sec_disable();
}
@@ -953,10 +1096,9 @@ piix_reset_hard(piix_t *dev)
nvr_at_handler(0, 0x0072, dev->nvr);
nvr_wp_set(0, 0, dev->nvr);
nvr_wp_set(0, 1, dev->nvr);
} else
nvr_at_handler(1, 0x0072, dev->nvr);
nvr_at_handler(1, 0x0074, dev->nvr);
nvr_at_handler(1, 0x0076, dev->nvr);
nvr_at_handler(1, 0x0074, dev->nvr);
nvr_at_handler(1, 0x0076, dev->nvr);
}
/* Clear all 4 functions' arrays and set their vendor and device ID's. */
for (i = 0; i < 4; i++) {
@@ -968,7 +1110,7 @@ piix_reset_hard(piix_t *dev)
/* Function 0: PCI to ISA Bridge */
fregs = (uint8_t *) dev->regs[0];
// pclog("PIIX Function 0: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
piix_log("PIIX Function 0: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = (dev->type > 0) ? 0x07 : 0x06; /* Check the value for the PB640 PIIX. */
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x08] = (dev->type > 0) ? 0x00 : 0x02; /* Should normal PIIX alos return 0x02? */
@@ -994,7 +1136,7 @@ piix_reset_hard(piix_t *dev)
/* Function 1: IDE */
if (dev->type > 0) {
fregs = (uint8_t *) dev->regs[1];
// pclog("PIIX Function 1: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
piix_log("PIIX Function 1: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = (dev->type > 3) ? 0x05 : 0x07;
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x09] = 0x80;
@@ -1006,7 +1148,7 @@ piix_reset_hard(piix_t *dev)
/* Function 2: USB */
if (dev->type > 2) {
fregs = (uint8_t *) dev->regs[2];
// pclog("PIIX Function 2: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
piix_log("PIIX Function 2: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x04] = 0x05;
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x0a] = 0x03; fregs[0x0b] = 0x0c;
@@ -1022,11 +1164,13 @@ piix_reset_hard(piix_t *dev)
/* Function 3: Power Management */
if (dev->type > 3) {
fregs = (uint8_t *) dev->regs[3];
// pclog("PIIX Function 3: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
piix_log("PIIX Function 3: 8086:%02X%02X\n", fregs[0x03], fregs[0x02]);
fregs[0x06] = 0x80; fregs[0x07] = 0x02;
fregs[0x0a] = 0x80; fregs[0x0b] = 0x06;
/* NOTE: The Specification Update says this should default to 0x00 and be read-only. */
// fregs[0x3d] = 0x01;
#ifdef WRONG_SPEC
fregs[0x3d] = 0x01;
#endif
fregs[0x40] = 0x01;
fregs[0x90] = 0x01;
dev->max_func = 3;
@@ -1063,6 +1207,9 @@ piix_close(void *p)
static void
*piix_init(const device_t *info)
{
int i;
CPU *cpu_s = &machines[machine].cpu[cpu_manufacturer].cpus[cpu];
piix_t *dev = (piix_t *) malloc(sizeof(piix_t));
memset(dev, 0, sizeof(piix_t));
@@ -1071,14 +1218,14 @@ static void
dev->func0_id = info->local >> 16;
dev->pci_slot = pci_add_card(PCI_ADD_SOUTHBRIDGE, piix_read, piix_write, dev);
// pclog("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
piix_log("PIIX%i: Added to slot: %02X\n", dev->type, dev->pci_slot);
if (dev->type > 0) { /* PB640's PIIX has no IDE part. */
dev->bm[0] = device_add_inst(&sff8038i_device, 1);
dev->bm[1] = device_add_inst(&sff8038i_device, 2);
}
if (dev->type >= 3)
if (dev->type > 3)
dev->nvr = device_add(&piix4_nvr_device);
piix_reset_hard(dev);
@@ -1114,65 +1261,57 @@ static void
else if (cpu_busspeed > 0x60000000)
dev->readout_regs[1] |= 0x10;
#if 0
switch (machines[machine].cpu[cpu_manufacturer].cpus[cpu_effective].rspeed) {
case 75000000:
dev->readout_regs[1] |= 0x82; /* 50 MHz * 1.5 multiplier */
break;
case 90000000:
dev->readout_regs[1] |= 0x82; /* 60 MHz * 1.5 multiplier */
break;
case 100000000:
if ((dev->readout_regs[1] & 0x30) == 0x10)
dev->readout_regs[1] |= 0x82; /* 66 MHz * 1.5 multiplier */
else
dev->readout_regs[1] |= 0x02; /* 50 MHz * 2.0 multiplier */
break;
case 12000000:
dev->readout_regs[1] |= 0x02; /* 60 MHz * 2.0 multiplier */
break;
case 125000000:
dev->readout_regs[1] |= 0x00; /* 50 MHz * 2.5 multiplier */
break;
case 133333333:
dev->readout_regs[1] |= 0x02; /* 66 MHz * 2.0 multiplier */
break;
case 150000000:
if ((dev->readout_regs[1] & 0x30) == 0x20)
dev->readout_regs[1] |= 0x00; /* 60 MHz * 2.5 multiplier */
else
dev->readout_regs[1] |= 0x80; /* 50 MHz * 3.0 multiplier */
break;
case 166666666:
dev->readout_regs[1] |= 0x00; /* 66 MHz * 2.5 multiplier */
break;
case 180000000:
dev->readout_regs[1] |= 0x80; /* 60 MHz * 3.0 multiplier */
break;
case 200000000:
dev->readout_regs[1] |= 0x80; /* 66 MHz * 3.0 multiplier */
break;
}
#else
if (cpu_dmulti <= 1.5)
dev->readout_regs[1] |= 0x82;
else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
dev->readout_regs[1] |= 0x02;
else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
dev->readout_regs[1] |= 0x00;
else if (cpu_dmulti > 2.5)
dev->readout_regs[1] |= 0x80;
#endif
if (cpu_dmulti <= 1.5)
dev->readout_regs[1] |= 0x82;
else if ((cpu_dmulti > 1.5) && (cpu_dmulti <= 2.0))
dev->readout_regs[1] |= 0x02;
else if ((cpu_dmulti > 2.0) && (cpu_dmulti <= 2.5))
dev->readout_regs[1] |= 0x00;
else if (cpu_dmulti > 2.5)
dev->readout_regs[1] |= 0x80;
io_sethandler(0x0078, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
io_sethandler(0x00e0, 0x0002, board_read, NULL, NULL, board_write, NULL, NULL, dev);
dev->board_config[0] = 0xff;
/* Register 0x0079: */
/* Bit 7: 0 = Keep password, 0 = Clear password. */
/* Bit 6: 0 = NVRAM cleared by jumper, 1 = NVRAM normal. */
/* Bit 5: 0 = CMOS Setup disabled, 1 = CMOS Setup enabled. */
/* Bit 4: External CPU clock (Switch 8). */
/* Bit 3: External CPU clock (Switch 7). */
/* 50 MHz: Switch 7 = Off, Switch 8 = Off. */
/* 60 MHz: Switch 7 = On, Switch 8 = Off. */
/* 66 MHz: Switch 7 = Off, Switch 8 = On. */
/* Bit 2: 0 = On-board audio absent, 1 = On-board audio present. */
dev->board_config[1] = 0x64;
/* Bit 0: 0 = 1.5x multiplier, 0 = 2x multiplier. */
dev->board_config[1] = 0xe0;
if ((cpu_s->rspeed == 75000000) && (cpu_busspeed == 50000000))
dev->board_config[1] |= 0x01;
else if ((cpu_s->rspeed == 90000000) && (cpu_busspeed == 60000000))
dev->board_config[1] |= (0x01 | 0x08);
else if ((cpu_s->rspeed == 100000000) && (cpu_busspeed == 50000000))
dev->board_config[1] |= 0x00;
else if ((cpu_s->rspeed == 100000000) && (cpu_busspeed == 66666666))
dev->board_config[1] |= (0x01 | 0x10);
else if ((cpu_s->rspeed == 120000000) && (cpu_busspeed == 60000000))
dev->board_config[1] |= 0x08;
else if ((cpu_s->rspeed == 133333333) && (cpu_busspeed == 66666666))
dev->board_config[1] |= 0x10;
else
dev->board_config[1] |= 0x10; /* TODO: how are the overdrive processors configured? */
smbus_init();
dev->smbus.stat = 0;
dev->smbus.ctl = 0;
dev->smbus.cmd = 0;
dev->smbus.addr = 0;
dev->smbus.data0 = 0;
dev->smbus.data1 = 0;
dev->smbus.index = 0;
for (i = 0; i < 32; i++)
dev->smbus.data[i] = 0;
timer_add(&dev->smbus.command_timer, smbus_inter, dev, 0);
return dev;
}

5
src/keyboard_at.c
View File

@@ -2210,7 +2210,8 @@ kbd_read(uint16_t port, void *priv)
atkbd_t *dev = (atkbd_t *)priv;
uint8_t ret = 0xff;
sub_cycles(ISA_CYCLES(8));
if ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_NOREF)
sub_cycles(ISA_CYCLES(8));
if (((dev->flags & KBC_VEN_MASK) == KBC_VEN_XI8088) && (port == 0x63))
port = 0x61;
@@ -2622,4 +2623,4 @@ uint8_t
keyboard_at_get_mouse_scan(void)
{
return(mouse_scan ? 0x10 : 0x00);
}
}

21
src/machine/m_at_socket7_s7.c
View File

@@ -315,7 +315,7 @@ machine_at_tc430hx_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -526,13 +526,8 @@ machine_at_txp4_init(const machine_t *model)
{
int ret;
#if 0
ret = bios_load_linear(L"roms/machines/txp4/5itw003.bin",
ret = bios_load_linear(L"roms/machines/txp4/0112L.001",
0x000e0000, 131072, 0);
#else
ret = bios_load_linear(L"roms/machines/txp4/TX5I0108.AWD",
0x000e0000, 131072, 0);
#endif
if (bios_only || !ret)
return ret;
@@ -545,7 +540,7 @@ machine_at_txp4_init(const machine_t *model)
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
@@ -605,13 +600,11 @@ machine_at_sp586tx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i430tx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);

70
src/machine/m_at_socket8.c
View File

@@ -6,7 +6,7 @@
*
* This file is part of the 86Box distribution.
*
* Implementation of Socket 8 machines.
* Implementation of Socket 8 and Slot 1 machines.
*
* Version: @(#)m_at_socket8.c 1.0.0 2019/05/16
*
@@ -34,7 +34,9 @@
#include "piix.h"
#include "sio.h"
#include "sst_flash.h"
#include "hwm.h"
#include "video.h"
#include "cpu.h"
#include "machine.h"
@@ -114,7 +116,7 @@ machine_at_6abx3_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
@@ -136,6 +138,67 @@ machine_at_6abx3_init(const machine_t *model)
return ret;
}
int
machine_at_p2bls_init(const machine_t *model)
{
int ret;
ret = bios_load_linear(L"roms/machines/p2bls/1014ls.003",
0x000c0000, 262144, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x06, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x04, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&piix4_device);
device_add(&keyboard_ps2_pci_device);
device_add(&w83977ef_device);
device_add(&sst_flash_39sf020_device);
hwm_values_t machine_hwm = {
{ /* fan speeds */
3000, /* Chassis */
3000, /* CPU */
3000, /* Power */
0
}, { /* temperatures */
30, /* MB */
0, /* unused */
27, /* CPU */
0
}, { /* voltages (divisors other than 16 = unclear how that number was achieved) */
2800 / 16, /* VCORE (2.8V by default) */
0, /* unused */
3300 / 16, /* +3.3V */
5000 / 27, /* +5V */
VDIV(12000, 28, 10) / 16, /* +12V (with 28K/10K resistor divider suggested in the W83781D datasheet) */
12000 / 55, /* -12V */
5000 / 24, /* -5V */
0
}
};
if (model->cpu[cpu_manufacturer].cpus[cpu_effective].cpu_type == CPU_PENTIUM2D)
machine_hwm.voltages[0] = 2050 / 16; /* set lower VCORE (2.05V) for Deschutes */
hwm_set_values(machine_hwm);
device_add(&as99127f_device);
return ret;
}
int
machine_at_p6bxt_init(const machine_t *model)
{
@@ -167,6 +230,7 @@ machine_at_p6bxt_init(const machine_t *model)
return ret;
}
int
machine_at_63a_init(const machine_t *model)
{
@@ -192,7 +256,7 @@ machine_at_63a_init(const machine_t *model)
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4); // Integrated Sound?
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_NORMAL, 1, 2, 3, 4);
device_add(&i440bx_device);
device_add(&i440zx_device);
device_add(&piix4_device);
device_add(&w83977tf_device);
device_add(&keyboard_ps2_pci_device);

2
src/machine/machine.h
View File

@@ -306,7 +306,7 @@ extern int machine_at_i440fx_init(const machine_t *);
extern int machine_at_s1668_init(const machine_t *);
extern int machine_at_6abx3_init(const machine_t *);
extern int machine_at_p2bls_init(const machine_t *);
extern int machine_at_p6bxt_init(const machine_t *);
extern int machine_at_63a_init(const machine_t *);
#endif

11
src/machine/machine_table.c
View File

@@ -226,10 +226,10 @@ const machine_t machines[] = {
{ "[Socket 7 VX] Jetway J656VXD", "j656vxd", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_j656vxd_init, NULL },
{ "[Socket 7 VX] Shuttle HOT-557", "430vx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 127, machine_at_i430vx_init, NULL },
{ "[Socket 7 TX] Acorp 5TX52", "5tx52", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_5tx52_init, NULL },
{ "[Socket 7 TX] ASUS TXP4", "txp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_txp4_init, NULL },
{ "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_ym430tx_init, NULL },
{ "[Socket 7 TX] San-LI/Superpower SP-586TX","sp586tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 128, 8, 255, machine_at_sp586tx_init, NULL },
{ "[Socket 7 TX] Acorp 5TX52", "5tx52", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_5tx52_init, NULL },
{ "[Socket 7 TX] ASUS TXP4", "txp4", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_txp4_init, NULL },
{ "[Socket 7 TX] Intel YM430TX", "ym430tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_ym430tx_init, NULL },
{ "[Socket 7 TX] San-LI/Superpower SP-586TX","sp586tx", MACHINE_CPUS_PENTIUM_S7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_sp586tx_init, NULL },
{ "[Super Socket 7] FIC VA-503+", "ficva503p", MACHINE_CPUS_PENTIUM_SS7, MACHINE_PCI | MACHINE_ISA | MACHINE_VLB | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 512, 8, 255, machine_at_mvp3_init, NULL },
@@ -238,8 +238,7 @@ const machine_t machines[] = {
{ "[Socket 8 FX] Tyan Titan-Pro ATX", "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 127, machine_at_s1668_init, NULL },
{ "[Slot 1 BX] Lucky Star 6ABX3", "6abx3", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_6abx3_init, NULL },
{ "[Slot 1 BX] ASUS P2B-LS", "p2bls", {{"Intel", cpus_PentiumII}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p2bls_init, NULL },
{ "[Socket 370 BX] ECS P6BXT-A+", "p6bxt", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 1024, 8, 255, machine_at_p6bxt_init, NULL },
{ "[Socket 370 ZX] Soltek SL-63A1", "63a", {{"Intel", cpus_PGA370}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, MACHINE_PCI | MACHINE_ISA | MACHINE_AT | MACHINE_PS2 | MACHINE_HDC, 8, 256, 8, 255, machine_at_63a_init, NULL },
#endif

22
src/mouse_ps2.c
View File

@@ -143,6 +143,27 @@ ps2_write(uint8_t val, void *priv)
keyboard_at_adddata_mouse(dev->sample_rate);
break;
case 0xeb: /* Get mouse data */
keyboard_at_adddata_mouse(0xfa);
temp = 0;
if (dev->x < 0)
temp |= 0x10;
if (dev->y < 0)
temp |= 0x20;
if (mouse_buttons & 1)
temp |= 1;
if (mouse_buttons & 2)
temp |= 2;
if ((mouse_buttons & 4) && (dev->flags & FLAG_INTELLI))
temp |= 4;
keyboard_at_adddata_mouse(temp);
keyboard_at_adddata_mouse(dev->x & 0xff);
keyboard_at_adddata_mouse(dev->y & 0xff);
if (dev->flags & FLAG_INTMODE)
keyboard_at_adddata_mouse(dev->z);
break;
case 0xf2: /* read ID */
keyboard_at_adddata_mouse(0xfa);
if (dev->flags & FLAG_INTMODE)
@@ -169,6 +190,7 @@ ps2_write(uint8_t val, void *priv)
case 0xff: /* reset */
dev->mode = MODE_STREAM;
dev->flags &= 0x88;
mouse_queue_start = mouse_queue_end = 0;
keyboard_at_adddata_mouse(0xfa);
keyboard_at_adddata_mouse(0xaa);
keyboard_at_adddata_mouse(0x00);

6
src/pc.c
View File

@@ -49,6 +49,7 @@
#include "nvr.h"
#include "machine.h"
#include "bugger.h"
#include "postcard.h"
#include "isamem.h"
#include "isartc.h"
#include "lpt.h"
@@ -112,6 +113,7 @@ int vid_cga_contrast = 0, /* (C) video */
force_43 = 0; /* (C) video */
int serial_enabled[SERIAL_MAX] = {0,0}, /* (C) enable serial ports */
bugger_enabled = 0, /* (C) enable ISAbugger */
postcard_enabled = 0, /* (C) enable POST card */
isamem_type[ISAMEM_MAX] = { 0,0,0,0 }, /* (C) enable ISA mem cards */
isartc_type = 0; /* (C) enable ISA RTC card */
int gfxcard = 0; /* (C) graphics/video card */
@@ -779,7 +781,9 @@ pc_reset_hard_init(void)
/* Needs the status bar... */
if (bugger_enabled)
device_add(&bugger_device);
device_add(&bugger_device);
if (postcard_enabled)
device_add(&postcard_device);
/* Reset the CPU module. */
resetx86();

39
src/pci.c
View File

@@ -127,7 +127,15 @@ pci_write(uint16_t port, uint8_t val, void *priv)
pci_log("Writing to PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_cards[slot].write(pci_func, pci_index | (port & 3), val, pci_cards[slot].priv);
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
break;
@@ -150,7 +158,15 @@ pci_read(uint16_t port, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].read)
return pci_cards[slot].read(pci_func, pci_index | (port & 3), pci_cards[slot].priv);
#ifdef ENABLE_PCI_LOG
else
pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
return 0xff;
@@ -237,10 +253,15 @@ pci_type2_write(uint16_t port, uint8_t val, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].write)
pci_cards[slot].write(pci_func, pci_index | (port & 3), val, pci_cards[slot].priv);
#ifdef ENABLE_PCI_LOG
else
pclog("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
} else
pclog("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Writing to empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Writing to unassigned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
}
}
@@ -265,10 +286,15 @@ pci_type2_read(uint16_t port, void *priv)
if (slot != 0xff) {
if (pci_cards[slot].read)
return pci_cards[slot].read(pci_func, pci_index | (port & 3), pci_cards[slot].priv);
#ifdef ENABLE_PCI_LOG
else
pclog("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
} else
pclog("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
pci_log("Reading from empty PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
#ifdef ENABLE_PCI_LOG
else
pci_log("Reading from unasisgned PCI card on slot %02X (pci_cards[%i]) (%02X:%02X)...\n", pci_card, slot, pci_func, pci_index);
#endif
}
return 0xff;
@@ -649,7 +675,6 @@ void
trc_write(uint16_t port, uint8_t val, void *priv)
{
pci_log("TRC Write: %02X\n", val);
pclog("[%04X:%08X] TRC Write: %02X\n", CS, cpu_state.pc, val);
if (!(trc_reg & 4) && (val & 4))
trc_reset(val);

56
src/pic.c
View File

@@ -345,6 +345,35 @@ pic2_write(uint16_t addr, uint8_t val, void *priv)
pic.pend &= ~4;
pic_updatepending();
} else if (!(val & 8)) { /*OCW2*/
#ifdef ENABLE_PIC_LOG
switch ((val >> 5) & 0x07) {
case 0x00:
pic_log("Rotate in automatic EOI mode (clear)\n");
break;
case 0x01:
pic_log("Non-specific EOI command\n");
break;
case 0x02:
pic_log("No operation\n");
break;
case 0x03:
pic_log("Specific EOI command\n");
break;
case 0x04:
pic_log("Rotate in automatic EOI mode (set)\n");
break;
case 0x05:
pic_log("Rotate on on-specific EOI command\n");
break;
case 0x06:
pic_log("Set priority command\n");
break;
case 0x07:
pic_log("Rotate on specific EOI command\n");
break;
}
#endif
pic2.ocw2 = val;
if ((val & 0xE0) == 0x60) {
pic2.ins &= ~(1 << (val & 7));
@@ -512,21 +541,32 @@ pic_process_interrupt(PIC* target_pic, int c)
{
uint8_t pending = target_pic->pend & ~target_pic->mask;
int ret = -1;
/* TODO: On init, a PIC need to get a pointer to one of these, and rotate as needed
if in rotate mode. */
/* 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
int priority_xt[16] = { 7, 6, 5, 4, 3, 2, 1, 0, -1, -1, -1, -1, -1, -1, -1, -1 };
int priority_at[16] = { 14, 13, -1, 4, 3, 2, 1, 0, 12, 11, 10, 9, 8, 7, 6, 5 };
int i;
int pic_int = c & 7;
int pic_int_num = 1 << pic_int;
int in_service = 0;
in_service = (target_pic->ins & (pic_int_num - 1)); /* Is anything of higher priority already in service? */
in_service |= (target_pic->ins & pic_int_num); /* Is the current IRQ already in service? */
if (AT) {
/* AT-specific stuff. */
if (c >= 8)
in_service |= (pic.ins & 0x03); /* IRQ 8 to 15, are IRQ's with higher priorities than the
cascade IRQ already in service? */
/* For IRQ 0 to 7, the cascade IRQ's in service bit indicates that one or
more IRQ's between 8 and 15 are already in service. */
for (i = 0; i < 16; i++) {
if ((priority_at[i] != -1) && (priority_at[i] >= priority_at[c])) {
if (i < 8)
in_service |= (pic.ins & (1 << i));
else
in_service |= (pic2.ins & (1 << i));
}
}
} else {
for (i = 0; i < 16; i++) {
if ((priority_xt[i] != -1) && (priority_xt[i] >= priority_xt[c]))
in_service |= (pic.ins & (1 << i));
}
}
if ((pending & pic_int_num) && !in_service) {

142
src/postcard.c Normal file
View File

@@ -0,0 +1,142 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a port 80h POST diagnostic card.
*
* Version: @(#)postcard.c 1.0.0 2020/03/23
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "86box.h"
#include "86box_io.h"
#include "device.h"
#include "machine.h"
#include "plat.h"
#include "ui.h"
#include "postcard.h"
static uint16_t postcard_port;
static uint8_t postcard_written;
static uint8_t postcard_code, postcard_prev_code;
#define UISTR_LEN 13
static char postcard_str[UISTR_LEN]; /* UI output string */
extern void ui_sb_bugui(char *__str);
#ifdef ENABLE_POSTCARD_LOG
int postcard_do_log = ENABLE_POSTCARD_LOG;
static void
postcard_log(const char *fmt, ...)
{
va_list ap;
if (postcard_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
int postcard_do_log = 0;
#define postcard_log(fmt, ...)
#endif
static void
postcard_setui(void)
{
if (!postcard_written)
sprintf(postcard_str, "POST: -- --");
else if (postcard_written == 1)
sprintf(postcard_str, "POST: %02X --", postcard_code);
else
sprintf(postcard_str, "POST: %02X %02X", postcard_code, postcard_prev_code);
ui_sb_bugui(postcard_str);
if (postcard_do_log) {
/* log same string sent to the UI */
int len = strlen(postcard_str);
postcard_str[len + 1] = '\0';
postcard_str[len] = '\n';
postcard_log(postcard_str);
}
}
static void
postcard_reset(void)
{
postcard_written = 0;
postcard_code = postcard_prev_code = 0x00;
postcard_setui();
}
static void
postcard_write(uint16_t port, uint8_t val, void *priv)
{
postcard_prev_code = postcard_code;
postcard_code = val;
if (postcard_written < 2)
postcard_written++;
postcard_setui();
}
static void *
postcard_init(const device_t *info)
{
postcard_reset();
if (machines[machine].flags & MACHINE_MCA)
postcard_port = 0x680; /* MCA machines */
else if (strstr(machines[machine].name, " PS/2 "))
postcard_port = 0x90; /* ISA PS/2 machines */
else
postcard_port = 0x80; /* AT and clone machines */
postcard_log("POST card initializing on port %04Xh\n", postcard_port);
if (postcard_port) io_sethandler(postcard_port, 1,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
return postcard_write;
}
static void
postcard_close(UNUSED(void *priv))
{
if (postcard_port) io_removehandler(postcard_port, 1,
NULL, NULL, NULL, postcard_write, NULL, NULL, NULL);
}
const device_t postcard_device = {
"POST Card",
DEVICE_ISA,
0,
postcard_init, postcard_close, NULL,
NULL, NULL, NULL,
NULL
};

35
src/postcard.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of a port 80h POST diagnostic card.
*
* Version: @(#)postcard.c 1.0.0 2020/03/23
*
* Author: RichardG, <richardg867@gmail.com>
* Copyright 2020 RichardG.
*/
#ifndef POSTCARD_H
# define POSTCARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Global variables. */
extern const device_t postcard_device;
/* Functions. */
#ifdef __cplusplus
}
#endif
#endif /*BUGGER_H*/

6
src/rom.c
View File

@@ -121,7 +121,7 @@ rom_read(uint32_t addr, void *priv)
return 0xff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xff;
return(rom->rom[addr & rom->mask]);
return(rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
@@ -139,7 +139,7 @@ rom_readw(uint32_t addr, void *priv)
return 0xffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffff;
return(*(uint16_t *)&rom->rom[addr & rom->mask]);
return(*(uint16_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]);
}
@@ -157,7 +157,7 @@ rom_readl(uint32_t addr, void *priv)
return 0xffffffff;
if (addr >= (rom->mapping.base + rom->sz))
return 0xffffffff;
return(*(uint32_t *)&rom->rom[addr & rom->mask]);
return(*(uint32_t *)&rom->rom[(addr - rom->mapping.base) & rom->mask]);
}

3
src/scsi/scsi.c
View File

@@ -74,7 +74,8 @@ static SCSI_CARD scsi_cards[] = {
{ "[MCA] BusLogic BT-640A", "bt640a", &buslogic_640a_device, },
{ "[PCI] BusLogic BT-958D", "bt958d", &buslogic_pci_device, },
{ "[PCI] NCR 53C810", "ncr53c810", &ncr53c810_pci_device, },
//{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
{ "[PCI] NCR 53C825A", "ncr53c825a", &ncr53c825a_pci_device, },
{ "[PCI] NCR 53C860", "ncr53c860", &ncr53c860_pci_device, },
{ "[PCI] NCR 53C875", "ncr53c875", &ncr53c875_pci_device, },
{ "[VLB] BusLogic BT-445S", "bt445s", &buslogic_445s_device, },
{ "", "", NULL, },

4
src/scsi/scsi_cdrom.c
View File

@@ -562,6 +562,10 @@ scsi_cdrom_update_request_length(scsi_cdrom_t *dev, int len, int block_len)
case 0x08:
case 0x28:
case 0xa8:
/* Round it to the nearest 2048 bytes. */
dev->max_transfer_len = (dev->max_transfer_len >> 11) << 11;
/* FALLTHROUGH */
case 0xb9:
case 0xbe:
/* Make sure total length is not bigger than sum of the lengths of

67
src/scsi/scsi_ncr53c8xx.c
View File

@@ -49,8 +49,11 @@
#define NCR53C8XX_ROM L"roms/scsi/ncr53c8xx/NCR307.BIN"
#define HA_ID 7
#define CHIP_810 0x01
#define CHIP_825 0x03
#define CHIP_860 0x06
#define CHIP_875 0x0f
#define NCR_SCNTL0_TRG 0x01
@@ -302,6 +305,10 @@ typedef struct {
uint32_t adder;
pc_timer_t timer;
#ifdef USE_WDTR
uint8_t tr_set[16];
#endif
} ncr53c8xx_t;
@@ -401,7 +408,7 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
dev->scntl3 = 0;
dev->sstat0 = 0;
dev->sstat1 = 0;
dev->scid = 7;
dev->scid = HA_ID;
dev->sxfer = 0;
dev->socl = 0;
dev->sdid = 0;
@@ -428,13 +435,21 @@ ncr53c8xx_soft_reset(ncr53c8xx_t *dev)
if (dev->chip >= CHIP_825) {
/* This *IS* a wide SCSI controller, so reset all SCSI
devices. */
for (i = 0; i < 16; i++)
for (i = 0; i < 16; i++) {
#ifdef USE_WDTR
dev->tr_set[i] = 0;
#endif
scsi_device_reset(&scsi_devices[i]);
}
} else {
/* This is *NOT* a wide SCSI controller, so do not touch
SCSI devices with ID's >= 8. */
for (i = 0; i < 8; i++)
for (i = 0; i < 8; i++) {
#ifdef USE_WDTR
dev->tr_set[i] = 0;
#endif
scsi_device_reset(&scsi_devices[i]);
}
}
}
@@ -802,9 +817,9 @@ ncr53c8xx_do_wdtr(ncr53c8xx_t *dev, int exponent)
ncr53c8xx_log("Target-initiated WDTR (%08X)\n", dev);
ncr53c8xx_set_phase(dev, PHASE_MI);
dev->msg_action = 4;
ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
ncr53c8xx_add_msg_byte(dev, 0x01); /* EXTENDED MESSAGE */
ncr53c8xx_add_msg_byte(dev, 0x02); /* EXTENDED MESSAGE LENGTH */
ncr53c8xx_add_msg_byte(dev, 0x03); /* WIDE DATA TRANSFER REQUEST */
ncr53c8xx_add_msg_byte(dev, exponent); /* TRANSFER WIDTH EXPONENT (16-bit) */
}
#endif
@@ -925,13 +940,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
break;
case 3:
ncr53c8xx_log("WDTR (ignored)\n");
#ifdef USE_WDTR
dev->tr_set[dev->sdid] = 1;
#endif
if (arg > 0x01) {
ncr53c8xx_bad_message(dev, msg);
return;
}
#ifdef USE_WDTR
ncr53c8xx_set_phase(dev, PHASE_CMD);
#endif
break;
case 5:
ncr53c8xx_log("PPR (ignored)\n");
@@ -960,9 +976,14 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
break;
case 0x0c:
/* BUS DEVICE RESET message, reset wide transfer request. */
#ifdef USE_WDTR
dev->tr_set[dev->sdid] = 0;
#endif
/* FALLTHROUGH */
case 0x06:
case 0x0e:
case 0x0c:
/* clear the current I/O process */
scsi_device_command_stop(sd);
ncr53c8xx_disconnect(dev);
@@ -977,10 +998,11 @@ ncr53c8xx_do_msgout(ncr53c8xx_t *dev, uint8_t id)
dev->current_lun = msg & 7;
ncr53c8xx_log("Select LUN %d\n", dev->current_lun);
#ifdef USE_WDTR
ncr53c8xx_do_wdtr(dev, 0x01);
#else
ncr53c8xx_set_phase(dev, PHASE_CMD);
if ((dev->chip == CHIP_875) && !dev->tr_set[dev->sdid])
ncr53c8xx_do_wdtr(dev, 0x01);
else
#endif
ncr53c8xx_set_phase(dev, PHASE_CMD);
}
break;
}
@@ -2625,6 +2647,7 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_pci_bar[0].addr_regs[0] = 1;
ncr53c8xx_pci_bar[1].addr_regs[0] = 0;
dev->chip = info->local;
ncr53c8xx_pci_regs[0x04] = 3;
ncr53c8xx_mem_init(dev, 0x0fffff00);
@@ -2632,12 +2655,14 @@ ncr53c8xx_init(const device_t *info)
dev->has_bios = device_get_config_int("bios");
if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (dev->chip >= CHIP_825) {
if (dev->chip == CHIP_875) {
dev->chip_rev = 0x04;
dev->nvr_path = L"ncr53c875.nvr";
} else if (dev->chip == CHIP_860) {
dev->chip_rev = 0x04;
dev->nvr_path = L"ncr53c860.nvr";
} else {
dev->chip_rev = 0x26;
dev->nvr_path = L"ncr53c825a.nvr";
@@ -2654,8 +2679,8 @@ ncr53c8xx_init(const device_t *info)
ncr53c8xx_bios_disable(dev);
#endif
} else {
if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
/* if (dev->has_bios)
rom_init(&dev->bios, NCR53C8XX_ROM, 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL); */
dev->nvr_path = L"ncr53c810.nvr";
}
@@ -2715,6 +2740,16 @@ const device_t ncr53c825a_pci_device =
ncr53c8xx_pci_config
};
const device_t ncr53c860_pci_device =
{
"NCR 53c860 (SCSI)",
DEVICE_PCI,
CHIP_860,
ncr53c8xx_init, ncr53c8xx_close, NULL,
NULL, NULL, NULL,
ncr53c8xx_pci_config
};
const device_t ncr53c875_pci_device =
{
"NCR 53c875 (SCSI)",

1
src/scsi/scsi_ncr53c8xx.h
View File

@@ -27,6 +27,7 @@
extern const device_t ncr53c810_pci_device;
extern const device_t ncr53c825a_pci_device;
extern const device_t ncr53c860_pci_device;
extern const device_t ncr53c875_pci_device;

1
src/sio.h
View File

@@ -35,6 +35,7 @@ extern const device_t w83877tf_device;
extern const device_t w83877tf_acorp_device;
extern const device_t w83977f_device;
extern const device_t w83977tf_device;
extern const device_t w83977ef_device;
#endif /*EMU_SIO_H*/

321
src/sio_um8669f - Cópia.c
View File

@@ -1,321 +0,0 @@
/*um8669f :
aa to 108 unlocks
next 108 write is register select (Cx?)
data read/write to 109
55 to 108 locks
C1
bit 7 - enable PnP registers
PnP registers :
07 - device :
0 = FDC
1 = COM1
2 = COM2
3 = LPT1
5 = Game port
30 - enable
60/61 - addr
70 - IRQ
74 - DMA*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include "86box.h"
#include "device.h"
#include "86box_io.h"
#include "timer.h"
#include "pci.h"
#include "lpt.h"
#include "serial.h"
#include "fdd.h"
#include "fdc.h"
#include "sio.h"
#define DEV_FDC 0
#define DEV_COM1 1
#define DEV_COM2 2
#define DEV_LPT1 3
#define DEV_GAME 5
#define REG_DEVICE 0x07
#define REG_ENABLE 0x30
#define REG_ADDRHI 0x60
#define REG_ADDRLO 0x61
#define REG_IRQ 0x70
#define REG_DMA 0x74
typedef struct um8669f_t
{
int locked, cur_reg_108,
cur_reg, cur_device,
pnp_active;
uint8_t regs_108[256];
struct {
int enable;
uint16_t addr;
int irq;
int dma;
} dev[8];
fdc_t *fdc;
serial_t *uart[2];
} um8669f_t;
static void
um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t valxor = 0;
uint8_t lpt_irq = 0xff;
if (port == 0x279)
dev->cur_reg = val;
else {
if (dev->cur_reg == REG_DEVICE)
dev->cur_device = val & 7;
else {
switch (dev->cur_reg) {
case REG_ENABLE:
valxor = dev->dev[dev->cur_device].enable ^ val;
dev->dev[dev->cur_device].enable = val;
break;
case REG_ADDRLO:
valxor = (dev->dev[dev->cur_device].addr & 0xff) ^ val;
dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0xff00) | val;
break;
case REG_ADDRHI:
valxor = ((dev->dev[dev->cur_device].addr >> 8) & 0xff) ^ val;
dev->dev[dev->cur_device].addr = (dev->dev[dev->cur_device].addr & 0x00ff) | (val << 8);
break;
case REG_IRQ:
valxor = dev->dev[dev->cur_device].irq ^ val;
dev->dev[dev->cur_device].irq = val;
break;
case REG_DMA:
valxor = dev->dev[dev->cur_device].dma ^ val;
dev->dev[dev->cur_device].dma = val;
break;
default:
valxor = 0;
break;
}
switch (dev->cur_device) {
case DEV_FDC:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
fdc_remove(dev->fdc);
if (dev->dev[DEV_FDC].enable & 1)
fdc_set_base(dev->fdc, 0x03f0);
}
break;
case DEV_COM1:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
serial_remove(dev->uart[0]);
if (dev->dev[DEV_COM1].enable & 1)
serial_setup(dev->uart[0], dev->dev[DEV_COM1].addr, dev->dev[DEV_COM1].irq);
}
break;
case DEV_COM2:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
serial_remove(dev->uart[1]);
if (dev->dev[DEV_COM2].enable & 1)
serial_setup(dev->uart[1], dev->dev[DEV_COM2].addr, dev->dev[DEV_COM2].irq);
}
break;
case DEV_LPT1:
if ((dev->cur_reg == REG_ENABLE) && valxor) {
lpt1_remove();
if (dev->dev[DEV_LPT1].enable & 1)
lpt1_init(dev->dev[DEV_LPT1].addr);
}
if (dev->dev[DEV_LPT1].irq <= 15)
lpt_irq = dev->dev[DEV_LPT1].irq;
lpt1_irq(lpt_irq);
break;
}
}
}
}
static uint8_t
um8669f_pnp_read(uint16_t port, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t ret = 0xff;
switch (dev->cur_reg) {
case REG_DEVICE:
ret = dev->cur_device;
break;
case REG_ENABLE:
ret = dev->dev[dev->cur_device].enable;
break;
case REG_ADDRLO:
ret = dev->dev[dev->cur_device].addr & 0xff;
break;
case REG_ADDRHI:
ret = dev->dev[dev->cur_device].addr >> 8;
break;
case REG_IRQ:
ret = dev->dev[dev->cur_device].irq;
break;
case REG_DMA:
ret = dev->dev[dev->cur_device].dma;
break;
}
return ret;
}
void um8669f_write(uint16_t port, uint8_t val, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
int new_pnp_active;
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
} else {
if (port == 0x108) {
if (val == 0x55)
dev->locked = 1;
else
dev->cur_reg_108 = val;
} else {
dev->regs_108[dev->cur_reg_108] = val;
if (dev->cur_reg_108 == 0xc1) {
new_pnp_active = !!(dev->regs_108[0xc1] & 0x80);
if (new_pnp_active != dev->pnp_active) {
if (new_pnp_active) {
io_sethandler(0x0279, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_sethandler(0x0a79, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_sethandler(0x03e3, 0x0001,
um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
} else {
io_removehandler(0x0279, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x0a79, 0x0001,
NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x03e3, 0x0001,
um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
}
dev->pnp_active = new_pnp_active;
}
}
}
}
}
uint8_t um8669f_read(uint16_t port, void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
uint8_t ret = 0xff;
if (!dev->locked) {
if (port == 0x108)
ret = dev->cur_reg_108; /* ??? */
else
ret = dev->regs_108[dev->cur_reg_108];
}
return ret;
}
void
um8669f_reset(um8669f_t *dev)
{
fdc_reset(dev->fdc);
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
lpt1_remove();
lpt1_init(0x378);
if (dev->pnp_active) {
io_removehandler(0x0279, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x0a79, 0x0001, NULL, NULL, NULL, um8669f_pnp_write, NULL, NULL, dev);
io_removehandler(0x03e3, 0x0001, um8669f_pnp_read, NULL, NULL, NULL, NULL, NULL, dev);
dev->pnp_active = 0;
}
dev->locked = 1;
dev->dev[DEV_FDC].enable = 1;
dev->dev[DEV_FDC].addr = 0x03f0;
dev->dev[DEV_FDC].irq = 6;
dev->dev[DEV_FDC].dma = 2;
dev->dev[DEV_COM1].enable = 1;
dev->dev[DEV_COM1].addr = 0x03f8;
dev->dev[DEV_COM1].irq = 4;
dev->dev[DEV_COM2].enable = 1;
dev->dev[DEV_COM2].addr = 0x02f8;
dev->dev[DEV_COM2].irq = 3;
dev->dev[DEV_LPT1].enable = 1;
dev->dev[DEV_LPT1].addr = 0x0378;
dev->dev[DEV_LPT1].irq = 7;
}
static void
um8669f_close(void *priv)
{
um8669f_t *dev = (um8669f_t *) priv;
free(dev);
}
static void *
um8669f_init(const device_t *info)
{
um8669f_t *dev = (um8669f_t *) malloc(sizeof(um8669f_t));
memset(dev, 0, sizeof(um8669f_t));
dev->fdc = device_add(&fdc_at_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
um8669f_reset(dev);
return dev;
}
const device_t um8669f_device = {
"UMC UM8669F Super I/O",
0,
0,
um8669f_init, um8669f_close, NULL,
NULL, NULL, NULL,
NULL
};

27
src/sio_um8669f.c
View File

@@ -80,8 +80,6 @@ um8669f_pnp_write(uint16_t port, uint8_t val, void *priv)
uint8_t valxor = 0;
uint8_t lpt_irq = 0xff;
pclog("Write %02X at %04X\n", val, port);
if (port == 0x279)
dev->cur_reg = val;
else {
@@ -189,8 +187,6 @@ um8669f_write(uint16_t port, uint8_t val, void *priv)
um8669f_t *dev = (um8669f_t *) priv;
int new_pnp_active;
pclog("Write %02X at %04X\n", val, port);
if (dev->locked) {
if ((port == 0x108) && (val == 0xaa))
dev->locked = 0;
@@ -297,20 +293,6 @@ um8669f_close(void *priv)
}
void
um8669f_detect_write(uint16_t port, uint8_t val, void *priv)
{
pclog("Write %02X at %04X\n", val, port);
}
uint8_t
um8669f_detect_read(uint16_t port, void *priv)
{
return 0xff;
}
static void *
um8669f_init(const device_t *info)
{
@@ -325,15 +307,6 @@ um8669f_init(const device_t *info)
io_sethandler(0x0108, 0x0002,
um8669f_read, NULL, NULL, um8669f_write, NULL, NULL, dev);
io_sethandler(0x0370, 0x0002,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03bd, 0x0001,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03bf, 0x0001,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
io_sethandler(0x03f0, 0x0002,
um8669f_detect_read, NULL, NULL, um8669f_detect_write, NULL, NULL, dev);
um8669f_reset(dev);
return dev;

1
src/sio_w83877f.c
View File

@@ -253,7 +253,6 @@ w83877f_write(uint16_t port, uint8_t val, void *priv)
return;
} else if ((port == 0x252) || (port == 0x3f1)) {
if (dev->locked) {
pclog("dev->locked\n");
if (dev->rw_locked)
return;
if ((dev->cur_reg >= 0x26) && (dev->cur_reg <= 0x27))

46
src/sio_w83977f.c
View File

@@ -88,7 +88,6 @@ w83977f_fdc_handler(w83977f_t *dev)
fdc_remove(dev->fdc);
pclog("fdc: %02X %02X %04X\n", dev->dev_regs[0][0x00], dev->regs[0x22], io_base);
if ((dev->dev_regs[0][0x00] & 0x01) && (dev->regs[0x22] & 0x01) && (io_base >= 0x100) && (io_base <= 0xff8))
fdc_set_base(dev->fdc, io_base);
@@ -153,8 +152,6 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
uint8_t valxor = 0;
uint8_t ld = dev->regs[7];
pclog("W83977F Write: %04X %02X\n", port, val);
if (index) {
if ((val == 0x87) && !dev->locked) {
if (dev->tries) {
@@ -191,8 +188,8 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
switch (dev->cur_reg) {
case 0x02:
if (valxor & 0x02)
softresetx86();
/* if (valxor & 0x02)
softresetx86(); */
break;
case 0x22:
if (valxor & 0x20)
@@ -205,8 +202,11 @@ w83977f_write(uint16_t port, uint8_t val, void *priv)
w83977f_fdc_handler(dev);
break;
case 0x26:
if (valxor & 0x40)
w83977f_remap(dev);
if (valxor & 0x20)
dev->rw_locked = (val & 0x20) ? 1 : 0;
break;
case 0x30:
if (valxor & 0x01) switch (ld) {
case 0x00:
@@ -329,8 +329,6 @@ w83977f_read(uint16_t port, void *priv)
}
}
pclog("W83977F Read: %04X %02X\n", port, ret);
return ret;
}
@@ -344,8 +342,13 @@ w83977f_reset(w83977f_t *dev)
for (i = 0; i < 256; i++)
memset(dev->dev_regs[i], 0, 208);
dev->regs[0x20] = 0x97;
dev->regs[0x21] = dev->type ? 0x73 : 0x71;
if (dev->type < 2) {
dev->regs[0x20] = 0x97;
dev->regs[0x21] = dev->type ? 0x73 : 0x71;
} else {
dev->regs[0x20] = 0x52;
dev->regs[0x21] = 0xf0;
}
dev->regs[0x22] = 0xff;
dev->regs[0x24] = dev->type ? 0x84 : 0xa4;
@@ -368,9 +371,9 @@ w83977f_reset(w83977f_t *dev)
dev->dev_regs[1][0x30] = 0x03; dev->dev_regs[1][0x31] = 0x78;
dev->dev_regs[1][0x40] = 0x07;
if (!dev->type)
dev->dev_regs[1][0x41] = 0x02; /* Read-only */
dev->dev_regs[1][0x41] = 0x01 /*0x02*/; /* Read-only */
dev->dev_regs[1][0x44] = 0x04;
dev->dev_regs[1][0xc0] = 0x3c; /* The datasheet says default is 3f, but also default is priner mode. */
dev->dev_regs[1][0xc0] = 0x3c; /* The datasheet says default is 3f, but also default is printer mode. */
/* Logical Device 2 (UART A) */
dev->dev_regs[2][0x00] = 0x01;
@@ -404,6 +407,7 @@ w83977f_reset(w83977f_t *dev)
if (!dev->type)
dev->dev_regs[5][0x01] = 0x02;
dev->dev_regs[5][0x30] = 0x00; dev->dev_regs[5][0x31] = 0x60;
dev->dev_regs[5][0x32] = 0x00; dev->dev_regs[5][0x33] = 0x64;
dev->dev_regs[5][0x40] = 0x01;
if (!dev->type)
dev->dev_regs[5][0x41] = 0x02; /* Read-only */
@@ -448,10 +452,12 @@ w83977f_reset(w83977f_t *dev)
/* Logical Device 9 (Auxiliary I/O Part III) */
if (dev->type) {
dev->dev_regs[7][0xb0] = 0x01; dev->dev_regs[7][0xb1] = 0x01;
dev->dev_regs[7][0xb2] = 0x01; dev->dev_regs[7][0xb3] = 0x01;
dev->dev_regs[7][0xb4] = 0x01; dev->dev_regs[7][0xb5] = 0x01;
dev->dev_regs[7][0xb6] = 0x01; dev->dev_regs[7][0xb7] = 0x01;
dev->dev_regs[9][0xb0] = 0x01; dev->dev_regs[9][0xb1] = 0x01;
dev->dev_regs[9][0xb2] = 0x01; dev->dev_regs[9][0xb3] = 0x01;
dev->dev_regs[9][0xb4] = 0x01; dev->dev_regs[9][0xb5] = 0x01;
dev->dev_regs[9][0xb6] = 0x01; dev->dev_regs[9][0xb7] = 0x01;
dev->dev_regs[10][0xc0] = 0x8f;
}
fdc_reset(dev->fdc);
@@ -517,3 +523,13 @@ const device_t w83977tf_device = {
NULL, NULL, NULL,
NULL
};
const device_t w83977ef_device = {
"Winbond W83977TF Super I/O",
0,
2,
w83977f_init, w83977f_close, NULL,
NULL, NULL, NULL,
NULL
};

410
src/smbus.c Normal file
View File

@@ -0,0 +1,410 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implement SMBus (System Management Bus) and its operations.
*
* Version: @(#)smbus.c 1.0.0 2020/03/21
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include "86box.h"
#include "smbus.h"
#define NADDRS 128 /* SMBus supports 128 addresses */
#define MAX(a, b) ((a) > (b) ? (a) : (b))
typedef struct _smbus_ {
uint8_t (*read_byte)(uint8_t addr, void *priv);
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv);
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv);
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv);
void (*write_byte)(uint8_t addr, uint8_t val, void *priv);
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv);
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv);
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv);
void *priv;
struct _smbus_ *prev, *next;
} smbus_t;
int smbus_initialized = 0;
smbus_t *smbus[NADDRS], *smbus_last[NADDRS];
#define ENABLE_SMBUS_LOG 1
#ifdef ENABLE_SMBUS_LOG
int smbus_do_log = ENABLE_SMBUS_LOG;
static void
smbus_log(const char *fmt, ...)
{
va_list ap;
if (smbus_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define smbus_log(fmt, ...)
#endif
#ifdef ENABLE_SMBUS_LOG
static uint8_t smbus_null_read_byte(uint8_t addr, void *priv) { smbus_log("SMBus: read_byte(%02x)\n", addr); return(0xff); }
static uint8_t smbus_null_read_byte_cmd(uint8_t addr, uint8_t cmd, void *priv) { smbus_log("SMBus: read_byte_cmd(%02x, %02x)\n", addr, cmd); return(0xff); }
static uint16_t smbus_null_read_word_cmd(uint8_t addr, uint8_t cmd, void *priv) { smbus_log("SMBus: read_word_cmd(%02x, %02x)\n", addr, cmd); return(0xffff); }
static uint8_t smbus_null_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv) { smbus_log("SMBus: read_block_cmd(%02x, %02x)\n", addr, cmd); return(0x00); };
static void smbus_null_write_byte(uint8_t addr, uint8_t val, void *priv) { smbus_log("SMBus: write_byte(%02x, %02x)\n", addr, val); }
static void smbus_null_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val, void *priv) { smbus_log("SMBus: write_byte_cmd(%02x, %02x, %02x)\n", addr, cmd, val); }
static void smbus_null_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val, void *priv) { smbus_log("SMBus: write_word_cmd(%02x, %02x, %04x)\n", addr, cmd, val); }
static void smbus_null_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv) { smbus_log("SMBus: write_block_cmd(%02x, %02x, %02x)\n", addr, cmd, len); }
#endif
void
smbus_init(void)
{
int c;
smbus_t *p, *q;
if (!smbus_initialized) {
for (c=0; c<NADDRS; c++)
smbus[c] = smbus_last[c] = NULL;
smbus_initialized = 1;
}
for (c=0; c<NADDRS; c++) {
if (smbus_last[c]) {
/* Address c has at least one handler. */
p = smbus_last[c];
/* After this loop, p will have the pointer to the first handler. */
while (p) {
q = p->prev;
free(p);
p = q;
}
p = NULL;
}
#ifdef ENABLE_SMBUS_LOG
/* smbus[c] should be the only handler, pointing at the NULL catch handler. */
p = (smbus_t *) malloc(sizeof(smbus_t));
memset(p, 0, sizeof(smbus_t));
smbus[c] = smbus_last[c] = p;
p->next = NULL;
p->prev = NULL;
p->read_byte = smbus_null_read_byte;
p->read_byte_cmd = smbus_null_read_byte_cmd;
p->read_word_cmd = smbus_null_read_word_cmd;
p->read_block_cmd = smbus_null_read_block_cmd;
p->write_byte = smbus_null_write_byte;
p->write_byte_cmd = smbus_null_write_byte_cmd;
p->write_word_cmd = smbus_null_write_word_cmd;
p->write_block_cmd = smbus_null_write_block_cmd;
p->priv = NULL;
#else
/* smbus[c] should be NULL. */
smbus[c] = smbus_last[c] = NULL;
#endif
}
}
void
smbus_sethandler(uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv)
{
int c;
smbus_t *p, *q = NULL;
for (c = 0; c < size; c++) {
p = smbus_last[base + c];
q = (smbus_t *) malloc(sizeof(smbus_t));
memset(q, 0, sizeof(smbus_t));
if (p) {
p->next = q;
q->prev = p;
} else {
smbus[base + c] = q;
q->prev = NULL;
}
q->read_byte = read_byte;
q->read_byte_cmd = read_byte_cmd;
q->read_word_cmd = read_word_cmd;
q->read_block_cmd = read_block_cmd;
q->write_byte = write_byte;
q->write_byte_cmd = write_byte_cmd;
q->write_word_cmd = write_word_cmd;
q->write_block_cmd = write_block_cmd;
q->priv = priv;
q->next = NULL;
smbus_last[base + c] = q;
}
}
void
smbus_removehandler(uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv)
{
int c;
smbus_t *p;
for (c = 0; c < size; c++) {
p = smbus[base + c];
if (!p)
continue;
while(p) {
if ((p->read_byte == read_byte) && (p->read_byte_cmd == read_byte_cmd) &&
(p->read_word_cmd == read_word_cmd) && (p->read_block_cmd == read_block_cmd) &&
(p->write_byte == write_byte) && (p->write_byte_cmd == write_byte_cmd) &&
(p->write_word_cmd == write_word_cmd) && (p->write_block_cmd == write_block_cmd) &&
(p->priv == priv)) {
if (p->prev)
p->prev->next = p->next;
else
smbus[base + c] = p->next;
if (p->next)
p->next->prev = p->prev;
else
smbus_last[base + c] = p->prev;
free(p);
p = NULL;
break;
}
p = p->next;
}
}
}
void
smbus_handler(int set, uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv)
{
if (set)
smbus_sethandler(base, size, read_byte, read_byte_cmd, read_word_cmd, read_block_cmd, write_byte, write_byte_cmd, write_word_cmd, write_block_cmd, priv);
else
smbus_removehandler(base, size, read_byte, read_byte_cmd, read_word_cmd, read_block_cmd, write_byte, write_byte_cmd, write_word_cmd, write_block_cmd, priv);
}
uint8_t
smbus_has_device(uint8_t addr)
{
return(!!smbus[addr]);
}
uint8_t
smbus_read_byte(uint8_t addr)
{
uint8_t ret = 0xff;
smbus_t *p;
int found = 0;
p = smbus[addr];
if (p) {
while(p) {
if (p->read_byte) {
ret &= p->read_byte(addr, p->priv);
found++;
}
p = p->next;
}
}
return(ret);
}
uint8_t
smbus_read_byte_cmd(uint8_t addr, uint8_t cmd)
{
uint8_t ret = 0xff;
smbus_t *p;
int found = 0;
p = smbus[addr];
if (p) {
while(p) {
if (p->read_byte_cmd) {
ret &= p->read_byte_cmd(addr, cmd, p->priv);
found++;
}
p = p->next;
}
}
return(ret);
}
uint16_t
smbus_read_word_cmd(uint8_t addr, uint8_t cmd)
{
uint16_t ret = 0xffff;
smbus_t *p;
int found = 0;
p = smbus[addr];
if (p) {
while(p) {
if (p->read_word_cmd) {
ret &= p->read_word_cmd(addr, cmd, p->priv);
found++;
}
p = p->next;
}
}
return(ret);
}
uint8_t
smbus_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data)
{
uint8_t ret = 0;
smbus_t *p;
int found = 0;
p = smbus[addr];
if (p) {
while(p) {
if (p->read_block_cmd) {
ret = MAX(ret, p->read_block_cmd(addr, cmd, data, p->priv));
found++;
}
p = p->next;
}
}
return(ret);
}
void
smbus_write_byte(uint8_t addr, uint8_t val)
{
smbus_t *p;
int found = 0;
if (smbus[addr]) {
p = smbus[addr];
while(p) {
if (p->write_byte) {
p->write_byte(addr, val, p->priv);
found++;
}
p = p->next;
}
}
return;
}
void
smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val)
{
smbus_t *p;
int found = 0;
if (smbus[addr]) {
p = smbus[addr];
while(p) {
if (p->write_byte_cmd) {
p->write_byte_cmd(addr, cmd, val, p->priv);
found++;
}
p = p->next;
}
}
return;
}
void
smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val)
{
smbus_t *p;
int found = 0;
if (smbus[addr]) {
p = smbus[addr];
while(p) {
if (p->write_word_cmd) {
p->write_word_cmd(addr, cmd, val, p->priv);
found++;
}
p = p->next;
}
}
return;
}
void
smbus_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len)
{
smbus_t *p;
int found = 0;
p = smbus[addr];
if (p) {
while(p) {
if (p->write_block_cmd) {
p->write_block_cmd(addr, cmd, data, len, p->priv);
found++;
}
p = p->next;
}
}
return;
}

67
src/smbus.h Normal file
View File

@@ -0,0 +1,67 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for the SMBus handler.
*
* Version: @(#)smbus.h 1.0.0 2020/03/21
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#ifndef EMU_SMBUS_H
# define EMU_SMBUS_H
extern void smbus_init(void);
extern void smbus_sethandler(uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv);
extern void smbus_removehandler(uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv);
extern void smbus_handler(int set, uint8_t base, int size,
uint8_t (*read_byte)(uint8_t addr, void *priv),
uint8_t (*read_byte_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint16_t (*read_word_cmd)(uint8_t addr, uint8_t cmd, void *priv),
uint8_t (*read_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, void *priv),
void (*write_byte)(uint8_t addr, uint8_t val, void *priv),
void (*write_byte_cmd)(uint8_t addr, uint8_t cmd, uint8_t val, void *priv),
void (*write_word_cmd)(uint8_t addr, uint8_t cmd, uint16_t val, void *priv),
void (*write_block_cmd)(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len, void *priv),
void *priv);
extern uint8_t smbus_has_device(uint8_t addr);
extern uint8_t smbus_read_byte(uint8_t addr);
extern uint8_t smbus_read_byte_cmd(uint8_t addr, uint8_t cmd);
extern uint16_t smbus_read_word_cmd(uint8_t addr, uint8_t cmd);
extern uint8_t smbus_read_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data);
extern void smbus_write_byte(uint8_t addr, uint8_t val);
extern void smbus_write_byte_cmd(uint8_t addr, uint8_t cmd, uint8_t val);
extern void smbus_write_word_cmd(uint8_t addr, uint8_t cmd, uint16_t val);
extern void smbus_write_block_cmd(uint8_t addr, uint8_t cmd, uint8_t *data, uint8_t len);
#endif /*EMU_SMBUS_H*/

12
src/sound/snd_opl_backend.c
View File

@@ -134,21 +134,11 @@ opl_write(int nr, uint16_t addr, uint8_t val)
uint8_t
opl_read(int nr, uint16_t addr)
{
FILE *f;
int i;
if (!(addr & 1))
return (opl[nr].status & opl[nr].status_mask) | (opl[nr].is_opl3 ? 0 : 0x06);
if (opl[nr].is_opl3 && ((addr & 3) == 3)) {
f = fopen("c:\\emu_dev\\awe32seg.dmp", "wb");
for (i = 0; i < 65536; i++)
fputc(readmembl(cs + i), f);
fclose(f);
fatal("[%04X:%08X] (%08X) Read 00 from %04X\n", CS, cpu_state.pc, cs + cpu_state.pc, addr);
if (opl[nr].is_opl3 && ((addr & 3) == 3))
return 0x00;
}
return opl[nr].is_opl3 ? 0 : 0xff;
}

9
src/sound/snd_sb.c
View File

@@ -679,13 +679,9 @@ void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
if (!(addr & 1))
{
pclog("CT1745: write IDX : %02X\n", val);
mixer->index = val;
}
else
{
pclog("CT1745: write REG%02X: %02X\n", mixer->index, val);
// TODO: and this? 001h:
/*DESCRIPTION
Contains previously selected register value. Mixer Data Register value
@@ -868,10 +864,8 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
sb_ct1745_mixer_t *mixer = &sb->mixer_sb16;
uint8_t temp, ret = 0xff;
if (!(addr & 1)) {
if (!(addr & 1))
ret = mixer->index;
pclog("CT1745: read IDX : %02X\n", ret);
}
sb_log("sb_ct1745: received register READ: %02X\t%02X\n", mixer->index, mixer->regs[mixer->index]);
@@ -1008,7 +1002,6 @@ uint8_t sb_ct1745_mixer_read(uint16_t addr, void *p)
break;
}
pclog("CT1745: read REG%02X: %02X\n", mixer->index, ret);
return ret;
}

196
src/sst_flash.c
View File

@@ -34,18 +34,20 @@
typedef struct sst_t
{
uint8_t id, is_39, page_bytes, pad;
uint8_t id, is_39, page_bytes, sdp;
int command_state, id_mode,
erase, dirty;
dirty;
uint32_t size, mask;
uint32_t size, mask,
page_mask, page_base;
uint8_t page_buffer[128];
uint8_t *array;
mem_mapping_t mapping[8], mapping_h[8];
pc_timer_t page_load_timer;
pc_timer_t page_write_timer;
} sst_t;
@@ -53,6 +55,7 @@ static wchar_t flash_path[1024];
#define SST_CHIP_ERASE 0x10 /* Both 29 and 39, 6th cycle */
#define SST_SDP_DISABLE 0x20 /* Only 29, Software data protect disable and write - treat as write */
#define SST_SECTOR_ERASE 0x30 /* Only 39, 6th cycle */
#define SST_SET_ID_MODE_ALT 0x60 /* Only 29, 6th cycle */
#define SST_ERASE 0x80 /* Both 29 and 39 */
@@ -74,63 +77,82 @@ static wchar_t flash_path[1024];
static void
sst_new_command(sst_t *dev, uint8_t val)
sst_sector_erase(sst_t *dev, uint32_t addr)
{
switch (val) {
memset(&dev->array[addr & (dev->mask & ~0xfff)], 0xff, 4096);
dev->dirty = 1;
}
static void
sst_new_command(sst_t *dev, uint32_t addr, uint8_t val)
{
if (dev->command_state == 5) switch (val) {
case SST_CHIP_ERASE:
if (dev->erase)
memset(dev->array, 0xff, 0x20000);
memset(dev->array, 0xff, 0x20000);
dev->command_state = 0;
dev->erase = 0;
break;
case SST_ERASE:
case SST_SDP_DISABLE:
if (!dev->is_39)
dev->sdp = 0;
dev->command_state = 0;
dev->erase = 1;
break;
case SST_SET_ID_MODE:
if (!dev->id_mode)
dev->id_mode = 1;
case SST_SECTOR_ERASE:
if (dev->is_39)
sst_sector_erase(dev, addr);
dev->command_state = 0;
dev->erase = 0;
break;
case SST_SET_ID_MODE_ALT:
if (!dev->is_39 && dev->erase && !dev->id_mode)
dev->id_mode = 1;
dev->id_mode = 1;
dev->command_state = 0;
dev->erase = 0;
break;
case SST_BYTE_PROGRAM:
dev->command_state = 3;
if (!dev->is_39) {
dev->page_bytes = 0;
timer_set_delay_u64(&dev->page_load_timer, 100 * TIMER_USEC);
}
dev->erase = 0;
break;
case SST_CLEAR_ID_MODE:
if (dev->id_mode)
dev->id_mode = 0;
dev->command_state = 0;
dev->erase = 0;
break;
default:
dev->command_state = 0;
dev->erase = 0;
break;
} else switch (val) {
case SST_ERASE:
dev->command_state = 3;
break;
case SST_SET_ID_MODE:
dev->id_mode = 1;
dev->command_state = 0;
break;
case SST_BYTE_PROGRAM:
if (!dev->is_39) {
memset(dev->page_buffer, 0xff, 128);
dev->page_bytes = 0;
timer_on_auto(&dev->page_write_timer, 210.0);
}
dev->command_state = 6;
break;
case SST_CLEAR_ID_MODE:
dev->id_mode = 0;
dev->command_state = 0;
break;
default:
dev->command_state = 0;
break;
}
}
static void
sst_sector_erase(sst_t *dev, uint32_t addr)
sst_page_write(void *priv)
{
memset(&dev->array[addr & (dev->mask & ~0xfff)], 0xff, 4096);
sst_t *dev = (sst_t *) priv;
memcpy(&(dev->array[dev->page_base]), dev->page_buffer, 128);
dev->dirty = 1;
dev->page_bytes = 0;
dev->command_state = 0;
}
@@ -148,6 +170,19 @@ sst_read_id(uint32_t addr, void *p)
}
static void
sst_buf_write(sst_t *dev, uint32_t addr, uint8_t val)
{
dev->page_buffer[addr & 0x0000007f] = val;
timer_disable(&dev->page_write_timer);
dev->page_bytes++;
if (dev->page_bytes >= 128)
sst_page_write(dev);
else
timer_set_delay_u64(&dev->page_write_timer, 210 * TIMER_USEC);
}
static void
sst_write(uint32_t addr, uint8_t val, void *p)
{
@@ -155,44 +190,55 @@ sst_write(uint32_t addr, uint8_t val, void *p)
switch (dev->command_state) {
case 0:
/* 1st Bus Write Cycle */
if ((val == 0xf0) && dev->is_39) {
case 3:
/* 1st and 4th Bus Write Cycle */
if ((val == 0xf0) && dev->is_39 && (dev->command_state == 0)) {
if (dev->id_mode)
dev->id_mode = 0;
} else if ((addr & 0xffff) == 0x5555 && val == 0xaa)
dev->command_state = 1;
else
dev->command_state = 0;
} else if (((addr & 0x7fff) == 0x5555) && (val == 0xaa))
dev->command_state++;
else {
if (!dev->is_39 && !dev->sdp && (dev->command_state == 0)) {
/* 29 series, software data protection off, start loading the page. */
dev->page_base = addr & dev->page_mask; /* First byte, A7 onwards of its address are the page mask. */
dev->command_state = 7;
sst_buf_write(dev, addr, val);
}
dev->command_state = 0;
}
break;
case 1:
/* 2nd Bus Write Cycle */
if ((addr & 0xffff) == 0x2aaa && val == 0x55)
dev->command_state = 2;
case 4:
/* 2nd and 5th Bus Write Cycle */
if (((addr & 0x7fff) == 0x2aaa) && (val == 0x55))
dev->command_state++;
else
dev->command_state = 0;
break;
case 2:
/* 3rd Bus Write Cycle */
if ((addr & 0xffff) == 0x5555)
sst_new_command(dev, val);
else if (dev->is_39 && (val == SST_SECTOR_ERASE) && dev->erase) {
sst_sector_erase(dev, addr);
dev->command_state = 0;
} else
case 5:
/* 3rd and 6th Bus Write Cycle */
if ((addr & 0x7fff) == 0x5555)
sst_new_command(dev, addr, val);
else
dev->command_state = 0;
break;
case 3:
dev->array[addr & dev->mask] = val;
if (!dev->is_39) {
timer_disable(&dev->page_load_timer);
if (dev->page_bytes == 0)
timer_set_delay_u64(&dev->page_load_timer, 100 * TIMER_USEC);
else
timer_set_delay_u64(&dev->page_load_timer, 200 * TIMER_USEC);
dev->page_bytes++;
} else
case 6:
/* Page Load Cycle (29) / Data Write Cycle (39SF) */
if (dev->is_39) {
dev->array[addr & dev->mask] = val;
dev->command_state = 0;
dev->dirty = 1;
dev->dirty = 1;
} else {
dev->page_base = addr & dev->page_mask; /* First byte, A7 onwards of its address are the page mask. */
dev->command_state++;
sst_buf_write(dev, addr, val);
}
break;
case 7:
if (!dev->is_39 && ((addr & dev->page_mask) == dev->page_base))
sst_buf_write(dev, addr, val);
break;
}
}
@@ -255,15 +301,6 @@ sst_readl(uint32_t addr, void *p)
}
static void
sst_page_load(void *priv)
{
sst_t *dev = (sst_t *) priv;
dev->command_state = 0;
}
static void
sst_add_mappings(sst_t *dev)
{
@@ -331,6 +368,8 @@ sst_init(const device_t *info)
else
dev->size = 0x20000;
dev->mask = dev->size - 1;
dev->page_mask = dev->mask & 0xffffff80; /* Filter out A0-A6. */
dev->sdp = 1;
sst_add_mappings(dev);
@@ -339,13 +378,14 @@ sst_init(const device_t *info)
if (fread(&(dev->array[0x00000]), 1, dev->size, f) != dev->size)
fatal("Less than %i bytes read from the SST Flash ROM file\n", dev->size);
fclose(f);
}
} else
dev->dirty = 1; /* It is by definition dirty on creation. */
free(flash_name);
free(machine_name);
if (!dev->is_39)
timer_add(&dev->page_load_timer, sst_page_load, dev, 0);
timer_add(&dev->page_write_timer, sst_page_write, dev, 0);
return dev;
}
@@ -357,9 +397,11 @@ sst_close(void *p)
FILE *f;
sst_t *dev = (sst_t *)p;
f = nvr_fopen(flash_path, L"wb");
fwrite(&(dev->array[0x00000]), dev->size, 1, f);
fclose(f);
if (dev->dirty) {
f = nvr_fopen(flash_path, L"wb");
fwrite(&(dev->array[0x00000]), dev->size, 1, f);
fclose(f);
}
free(dev->array);
dev->array = NULL;

BIN
src/video/86Box.exe
View File

Binary file not shown.

4876
src/video/vid_mga - Cópia.c
View File

File diff suppressed because it is too large Load Diff

2
src/video/vid_mga.c
View File

@@ -4765,7 +4765,7 @@ mystique_pci_write(int func, int addr, uint8_t val, void *p)
case 0x48: case 0x49: case 0x4a: case 0x4b:
addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) |
(addr & 3);
pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val);
/* pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val); */
mystique_ctrl_write_b(addr, val, mystique);
break;
}

3
src/win/86Box.rc
View File

@@ -474,6 +474,9 @@ BEGIN
CONTROL "ISABugger device",IDC_CHECK_BUGGER,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,80,94,10
CONTROL "POST card",IDC_CHECK_POSTCARD,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,147,80,94,10
LTEXT "ISA RTC",IDT_1767,7,99,48,10
COMBOBOX IDC_COMBO_ISARTC,64,98,155,120,
CBS_DROPDOWNLIST | WS_VSCROLL | WS_TABSTOP

3
src/win/Makefile.mingw
View File

@@ -597,7 +597,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \
@@ -605,6 +605,7 @@ DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_w83787f.o \
sio_w83877f.o sio_w83977f.o \
sio_um8669f.o \
smbus.o \
keyboard.o \
keyboard_xt.o keyboard_at.o \
gameport.o \

3
src/win/Makefile_ndr.mingw
View File

@@ -602,7 +602,7 @@ MCHOBJ := machine.o machine_table.o \
m_at_286_386sx.o m_at_386dx_486.o \
m_at_socket4_5.o m_at_socket7_s7.o
DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
DEVOBJ := bugger.o hwm.o hwm_w83781d.o ibm_5161.o isamem.o isartc.o lpt.o postcard.o $(SERIAL) \
sio_acc3221.o \
sio_fdc37c66x.o sio_fdc37c669.o \
sio_fdc37c93x.o \
@@ -610,6 +610,7 @@ DEVOBJ := bugger.o ibm_5161.o isamem.o isartc.o lpt.o $(SERIAL) \
sio_w83787f.o \
sio_w83877f.o sio_w83977f.o \
sio_um8669f.o \
smbus.o \
keyboard.o \
keyboard_xt.o keyboard_at.o \
gameport.o \

2
src/win/resource.h
View File

@@ -175,7 +175,7 @@
#define IDC_CHECK_IDE_QUA 1127
#define IDC_BUTTON_IDE_QUA 1128
#define IDC_CHECK_BUGGER 1129
#define IDC_CONFIGURE_BUGGER 1130
#define IDC_CHECK_POSTCARD 1130
#define IDC_COMBO_ISARTC 1131
#define IDC_CONFIGURE_ISARTC 1132
#define IDC_GROUP_ISAMEM 1140

10
src/win/win_settings.c
View File

@@ -97,6 +97,7 @@ static int temp_serial[2], temp_lpt[3];
/* Other peripherals category */
static int temp_hdc, temp_scsi_card, temp_ide_ter, temp_ide_qua;
static int temp_bugger;
static int temp_postcard;
static int temp_isartc;
static int temp_isamem[ISAMEM_MAX];
@@ -248,6 +249,7 @@ win_settings_init(void)
temp_ide_ter = ide_ter_enabled;
temp_ide_qua = ide_qua_enabled;
temp_bugger = bugger_enabled;
temp_postcard = postcard_enabled;
temp_isartc = isartc_type;
/* ISA memory boards. */
@@ -356,6 +358,7 @@ win_settings_changed(void)
i = i || (temp_ide_ter != ide_ter_enabled);
i = i || (temp_ide_qua != ide_qua_enabled);
i = i || (temp_bugger != bugger_enabled);
i = i || (temp_postcard != postcard_enabled);
i = i || (temp_isartc != isartc_type);
/* ISA memory boards. */
@@ -460,6 +463,7 @@ win_settings_save(void)
ide_ter_enabled = temp_ide_ter;
ide_qua_enabled = temp_ide_qua;
bugger_enabled = temp_bugger;
postcard_enabled = temp_postcard;
isartc_type = temp_isartc;
/* ISA memory boards. */
@@ -1594,6 +1598,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h=GetDlgItem(hdlg, IDC_CHECK_BUGGER);
SendMessage(h, BM_SETCHECK, temp_bugger, 0);
h=GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
SendMessage(h, BM_SETCHECK, temp_postcard, 0);
/* Populate the ISA RTC card dropdown. */
e = 0;
h = GetDlgItem(hdlg, IDC_COMBO_ISARTC);
@@ -1797,6 +1804,9 @@ win_settings_peripherals_proc(HWND hdlg, UINT message, WPARAM wParam, LPARAM lPa
h = GetDlgItem(hdlg, IDC_CHECK_BUGGER);
temp_bugger = SendMessage(h, BM_GETCHECK, 0, 0);
h = GetDlgItem(hdlg, IDC_CHECK_POSTCARD);
temp_postcard = SendMessage(h, BM_GETCHECK, 0, 0);
free(stransi);
free(lptsTemp);