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Merge branch 'master' into tandy-shake

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This commit is contained in:
pixel-jupiter
2025-09-30 15:41:02 +03:00
parent 3e7b3d32e8 c35bb9749f
commit 49a3eca742
399 changed files with 26924 additions and 18317 deletions
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1
.github/pull_request_template.md vendored
View File

@@ -5,6 +5,7 @@ _Briefly describe what you are submitting._
Checklist
=========
* [ ] Closes #xxx
* [ ] I have tested my changes locally and validated that the functionality works as intended
* [ ] I have discussed this with core contributors already
* [ ] This pull request requires changes to the ROM set
* [ ] I have opened a roms pull request - https://github.com/86Box/roms/pull/changeme/

6
.github/workflows/cmake_linux.yml vendored
View File

@@ -55,6 +55,7 @@ jobs:
- name: SDL GUI
qt: off
qt6: off
slug: -SDL
static: on
- name: Qt 5 GUI
qt: on
@@ -121,10 +122,9 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D USE_QT6=${{ matrix.ui.qt6 }}

109
.github/workflows/cmake_macos.yml vendored
View File

@@ -26,11 +26,11 @@ on:
jobs:
macos13-x86_64:
macos:
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, x86_64"
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.arch }}"
runs-on: macos-13
runs-on: ${{ matrix.environment.runner }}
strategy:
fail-fast: true
@@ -54,12 +54,27 @@ jobs:
ui:
- name: SDL GUI
qt: off
slug: -SDL
static: on
- name: Qt GUI
- name: Qt 5 GUI
qt: on
slug: -Qt
slug: -Qt5
packages: >-
qt@5
environment:
- arch: x86_64
toolchain: ./cmake/flags-gcc-x86_64.cmake
slug: -x86_64
runner: macos-13
- arch: arm64
toolchain: ./cmake/llvm-macos-aarch64.cmake
slug: -arm64
runner: macos-14
exclude:
- dynarec:
new: off
environment:
arch: arm64
steps:
- name: Install dependencies
@@ -81,10 +96,9 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ./cmake/flags-gcc-x86_64.cmake
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D Qt5_ROOT=$(brew --prefix qt@5)
-D Qt5LinguistTools_ROOT=$(brew --prefix qt@5)
@@ -100,82 +114,5 @@ jobs:
- name: Upload artifact
uses: actions/upload-artifact@v4
with:
name: '86Box${{ matrix.ui.slug }}${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-macOS-x86_64-gha${{ github.run_number }}'
path: build/artifacts/**
macos14-arm64:
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, arm64"
runs-on: macos-14
strategy:
fail-fast: true
matrix:
build:
# - name: Regular
# preset: regular
- name: Debug
preset: dev_debug
slug: -Debug
- name: Dev
preset: development
slug: -Dev
dynarec:
# - name: ODR
# new: off
# slug: -ODR
- name: NDR
new: on
slug: -NDR
ui:
- name: SDL GUI
qt: off
static: on
- name: Qt GUI
qt: on
slug: -Qt
packages: >-
qt@5
steps:
- name: Install dependencies
run: >-
brew install
sdl2
rtmidi
openal-soft
fluidsynth
libslirp
vde
libserialport
${{ matrix.ui.packages }}
- name: Checkout repository
uses: actions/checkout@v4
with:
fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ./cmake/llvm-macos-aarch64.cmake
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D Qt5_ROOT=$(brew --prefix qt@5)
-D Qt5LinguistTools_ROOT=$(brew --prefix qt@5)
-D OpenAL_ROOT=$(brew --prefix openal-soft)
-D LIBSERIALPORT_ROOT=$(brew --prefix libserialport)
- name: Build
run: cmake --build build
- name: Generate package
run: cmake --install build
- name: Upload artifact
uses: actions/upload-artifact@v4
with:
name: '86Box${{ matrix.ui.slug }}${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-macOS-arm64-gha${{ github.run_number }}'
name: '86Box${{ matrix.ui.slug }}${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-macOS${{ matrix.environment.slug }}-gha${{ github.run_number }}'
path: build/artifacts/**

24
.github/workflows/cmake_windows_msys2.yml vendored
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@@ -1,4 +1,4 @@
name: CMake (Windows, msys2)
name: CMake (Windows)
on:
@@ -26,9 +26,9 @@ on:
jobs:
msys2:
windows:
name: "${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }}"
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }}"
runs-on: ${{ matrix.environment.runner }}
@@ -56,14 +56,15 @@ jobs:
new: on
slug: -NDR
ui:
- name: Qt GUI
- name: Qt 5 GUI
qt: on
slug: -Qt5
static: on
slug: -Qt
packages: >-
qt5-base:p
qt5-tools:p
qt5-static:p
vulkan-headers:p
# qt5-base:p
# qt5-tools:p
environment:
# - msystem: MSYS
# toolchain: ./cmake/flags-gcc-x86_64.cmake
@@ -77,10 +78,12 @@ jobs:
# prefix: mingw-w64-clang-x86_64
# toolchain: ./cmake/llvm-win32-x86_64.cmake
# slug: "CLANG64"
# runner: windows-2022
# - msystem: UCRT64
# prefix: mingw-w64-ucrt-x86_64
# toolchain: ./cmake/flags-gcc-x86_64.cmake
# slug: "UCRT64"
# runner: windows-2022
- msystem: CLANGARM64
toolchain: ./cmake/flags-gcc-aarch64.cmake
slug: -arm64
@@ -112,8 +115,7 @@ jobs:
libslirp:p
fluidsynth:p
libserialport:p
qt5-static:p
vulkan-headers:p
${{ matrix.ui.packages }}
openmp:p
- name: Checkout repository
@@ -123,10 +125,10 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
- name: Build
run: cmake --build build

35
.github/workflows/codeql_linux.yml vendored
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@@ -33,7 +33,7 @@ jobs:
analyze-linux:
name: "Analyze (${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, x86_64)"
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.arch }}"
runs-on: ubuntu-22.04
@@ -68,10 +68,13 @@ jobs:
ui:
- name: SDL GUI
qt: off
qt6: off
slug: -SDL
static: on
- name: Qt GUI
- name: Qt 5 GUI
qt: on
slug: -Qt
qt6: off
slug: -Qt5
packages: >-
qtbase5-dev
qtbase5-private-dev
@@ -79,6 +82,20 @@ jobs:
qttranslations5-l10n
libevdev-dev
libxkbcommon-x11-dev
environment:
- arch: x86_64
toolchain: ./cmake/flags-gcc-x86_64.cmake
slug: "-x86_64"
runner: ubuntu-22.04
# - arch: arm64
# toolchain: ./cmake/flags-gcc-aarch64.cmake
# slug: -arm64
# runner: ubuntu-22.04-arm
# exclude:
# - dynarec:
# new: off
# environment:
# arch: arm64
steps:
- name: Install dependencies
@@ -104,7 +121,7 @@ jobs:
fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis
- name: Install Build Wrapper
uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v5
uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v6
- name: Initialize CodeQL
uses: github/codeql-action/init@v3
@@ -114,11 +131,11 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ./cmake/flags-gcc-x86_64.cmake
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D USE_QT6=${{ matrix.ui.qt6 }}
- name: Build
run: |
@@ -132,7 +149,7 @@ jobs:
- name: SonarQube Scan
if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != ''
# if: 0
uses: SonarSource/sonarqube-scan-action@v5
uses: SonarSource/sonarqube-scan-action@v6
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }}
@@ -140,4 +157,4 @@ jobs:
with:
# Consult https://docs.sonarsource.com/sonarqube-server/latest/analyzing-source-code/scanners/sonarscanner/ for more information and options
args: >
--define sonar.cfamily.compile-commands="${{ env.BUILD_WRAPPER_OUT_DIR }}/compile_commands.json"
--define sonar.cfamily.compile-commands=build/compile_commands.json

41
.github/workflows/codeql_macos.yml vendored
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@@ -31,11 +31,11 @@ on:
jobs:
analyze-macos13-x86_64:
analyze-macos:
name: "Analyze (${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, x86_64)"
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.arch }}"
runs-on: macos-13
runs-on: ${{ matrix.environment.runner }}
env:
BUILD_WRAPPER_OUT_DIR: build_wrapper_output_directory # Directory where build-wrapper output will be placed
@@ -66,13 +66,29 @@ jobs:
new: on
slug: -NDR
ui:
- name: SDL GUI
qt: off
- name: Qt GUI
# - name: SDL GUI
# qt: off
# slug: -SDL
# static: on
- name: Qt 5 GUI
qt: on
slug: -Qt
slug: -Qt5
packages: >-
qt@5
environment:
- arch: x86_64
toolchain: ./cmake/flags-gcc-x86_64.cmake
slug: -x86_64
runner: macos-13
# - arch: arm64
# toolchain: ./cmake/llvm-macos-aarch64.cmake
# slug: -arm64
# runner: macos-14
# exclude:
# - dynarec:
# new: off
# environment:
# arch: arm64
steps:
- name: Install dependencies
@@ -93,7 +109,7 @@ jobs:
fetch-depth: 0 # Shallow clones should be disabled for a better relevancy of analysis
- name: Install Build Wrapper
uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v5
uses: SonarSource/sonarqube-scan-action/install-build-wrapper@v6
- name: Initialize CodeQL
uses: github/codeql-action/init@v3
@@ -103,10 +119,9 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ./cmake/flags-gcc-x86_64.cmake
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D Qt5_ROOT=$(brew --prefix qt@5)
-D Qt5LinguistTools_ROOT=$(brew --prefix qt@5)
@@ -125,7 +140,7 @@ jobs:
- name: SonarQube Scan
# if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != ''
if: 0
uses: SonarSource/sonarqube-scan-action@v5
uses: SonarSource/sonarqube-scan-action@v6
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }}
@@ -133,4 +148,4 @@ jobs:
with:
# Consult https://docs.sonarsource.com/sonarqube-server/latest/analyzing-source-code/scanners/sonarscanner/ for more information and options
args: >
--define sonar.cfamily.compile-commands="${{ env.BUILD_WRAPPER_OUT_DIR }}/compile_commands.json"
--define sonar.cfamily.compile-commands=build/compile_commands.json

18
.github/workflows/codeql_windows_msys2.yml vendored
View File

@@ -1,4 +1,4 @@
name: CodeQL Analysis (Windows, msys2)
name: CodeQL Analysis (Windows)
on:
@@ -31,9 +31,9 @@ on:
jobs:
analyze-msys2:
analyze-windows:
name: "Analyze (${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }})"
name: "${{ matrix.ui.name }}, ${{ matrix.build.name }}, ${{ matrix.dynarec.name }}, ${{ matrix.environment.msystem }}"
runs-on: ${{ matrix.environment.runner }}
@@ -70,14 +70,15 @@ jobs:
new: on
slug: -NDR
ui:
- name: Qt GUI
- name: Qt 5 GUI
qt: on
slug: -Qt5
static: off
slug: -Qt
packages: >-
qt5-base:p
qt5-tools:p
vulkan-headers:p
# qt5-static:p
environment:
# - msystem: MSYS
# toolchain: ./cmake/flags-gcc-x86_64.cmake
@@ -147,10 +148,9 @@ jobs:
- name: Configure CMake
run: >-
cmake -G Ninja -S . -B build --preset ${{ matrix.build.preset }}
cmake -S . -B build --preset ${{ matrix.build.preset }}
--toolchain ${{ matrix.environment.toolchain }}
-D NEW_DYNAREC=${{ matrix.dynarec.new }}
-D CMAKE_INSTALL_PREFIX=./build/artifacts
-D QT=${{ matrix.ui.qt }}
-D STATIC_BUILD=${{ matrix.ui.static }}
@@ -169,7 +169,7 @@ jobs:
- name: SonarQube Scan
# if: matrix.build.preset == 'dev_debug' && matrix.dynarec.new == 'on' && matrix.ui.qt == 'on' && env.SONAR_TOKEN != ''
if: 0
uses: SonarSource/sonarqube-scan-action@v5
uses: SonarSource/sonarqube-scan-action@v6
env:
GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
SONAR_TOKEN: ${{ secrets.SONAR_TOKEN }}
@@ -177,4 +177,4 @@ jobs:
with:
# Consult https://docs.sonarsource.com/sonarqube-server/latest/analyzing-source-code/scanners/sonarscanner/ for more information and options
args: >
--define sonar.cfamily.compile-commands="${{ env.BUILD_WRAPPER_OUT_DIR }}/compile_commands.json"
--define sonar.cfamily.compile-commands=build/compile_commands.json

2
.gitignore vendored
View File

@@ -8,6 +8,8 @@ Makefile
/src/*.exe
/src/86Box
/src/include/86box/version.h
/src/.vs
/src/out
# Legacy Makefile
/src/*.o

1
CMakeLists.txt
View File

@@ -185,6 +185,7 @@ cmake_dependent_option(SIO_DETECT "Super I/O Detection Helper"
cmake_dependent_option(WACOM "Wacom Input Devices" ON "DEV_BRANCH" OFF)
cmake_dependent_option(XL24 "ATI VGA Wonder XL24 (ATI-28800-6)" ON "DEV_BRANCH" OFF)
cmake_dependent_option(NETSWITCH "Network Switch Support" ON "DEV_BRANCH" OFF)
cmake_dependent_option(VFIO "Virtual Function I/O" ON "DEV_BRANCH" OFF)
# Ditto but for Qt
if(QT)

8
sonar-project.properties
View File

@@ -1,12 +1,16 @@
sonar.projectKey=86Box_86Box
sonar.organization=86box
# This is the name and version displayed in the SonarCloud UI.
#sonar.projectName=86Box
sonar.projectName=86Box
#sonar.projectVersion=1.0
# Path is relative to the sonar-project.properties file. Replace "\" by "/" on Windows.
# Path is relative to the sonar-project.properties file. Defaults to .
#sonar.sources=.
# Encoding of the source code. Default is default system encoding
#sonar.sourceEncoding=UTF-8
sonar.cfamily.compile-commands=build/compile_commands.json

7
src/86box.c
View File

@@ -107,6 +107,7 @@
#include <86box/apm.h>
#include <86box/acpi.h>
#include <86box/nv/vid_nv_rivatimer.h>
#include <86box/vfio.h>
// Disable c99-designator to avoid the warnings about int ng
#ifdef __clang__
@@ -238,6 +239,7 @@ char monitor_edid_path[1024] = { 0 }; /* (C) Path to
double video_gl_input_scale = 1.0; /* (C) OpenGL 3.x input scale */
int video_gl_input_scale_mode = FULLSCR_SCALE_FULL; /* (C) OpenGL 3.x input stretch mode */
int color_scheme = 0; /* (C) Color scheme of UI (Windows-only) */
int fdd_sounds_enabled = 1; /* (C) Floppy drive sounds enabled */
// Accelerator key array
struct accelKey acc_keys[NUM_ACCELS];
@@ -1646,6 +1648,11 @@ pc_reset_hard_init(void)
the chances of the SCSI controller ending up on the bridge. */
video_voodoo_init();
#if defined(USE_VFIO) && defined(__linux__)
/* Initialize VFIO */
vfio_init();
#endif
/* installs first game port if no device provides one, must be late */
if (joystick_type[0])
gameport_update_joystick_type(0);

10
src/CMakeLists.txt
View File

@@ -103,6 +103,16 @@ if(VNC)
endif()
endif()
if(CMAKE_SYSTEM_NAME MATCHES "Linux")
if(VFIO)
include(CheckIncludeFile)
check_include_file("linux/vfio.h" VFIO_AVAILABLE)
if(VFIO_AVAILABLE)
add_compile_definitions(USE_VFIO)
endif()
endif()
endif()
if(INSTRUMENT)
add_compile_definitions(USE_INSTRUMENT)
endif()

16
src/acpi.c
View File

@@ -8,8 +8,6 @@
*
* ACPI emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.
@@ -1222,7 +1220,7 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *priv)
/* GPOREG - General Purpose Output Register (IO) */
if (size == 1) {
dev->regs.gporeg[addr & 3] = val;
if ((addr == 0x34) && !strcmp(machine_get_internal_name(), "cubx"))
if ((addr == 0x34) && (machines[machine].init == machine_at_cubx_init))
hdc_onboard_enabled = (val & 0x01);
}
break;
@@ -1749,7 +1747,7 @@ acpi_reg_write_sis_5595(int size, uint16_t addr, uint8_t val, void *priv)
break;
case 0x1c:
dev->regs.gpe_pin = ((dev->regs.gpe_pin & ~(0xff << shift32)) | ((val & 0xff) << shift32));
if (!strcmp(machine_get_internal_name(), "m747") && (val & 0x10) &&
if ((machines[machine].init == machine_at_m747_init) && (val & 0x10) &&
!(dev->regs.gpe_io & 0x00000010))
resetx86();
break;
@@ -2365,7 +2363,7 @@ acpi_reset(void *priv)
/* PC Chips M773:
- Bit 3: 80-conductor cable on unknown IDE channel (active low)
- Bit 1: 80-conductor cable on unknown IDE channel (active low) */
dev->regs.gpireg[0] = !strcmp(machine_get_internal_name(), "m773") ? 0xf5 : 0xff;
dev->regs.gpireg[0] = (machines[machine].init == machine_at_m773_init) ? 0xf5 : 0xff;
dev->regs.gpireg[1] = 0xff;
/* A-Trend ATC7020BXII:
- Bit 3: 80-conductor cable on secondary IDE channel (active low)
@@ -2399,9 +2397,9 @@ acpi_reset(void *priv)
- Bit 19: password cleared (active low).
*/
dev->regs.gpi_val = 0xfff57fc1;
if (!strcmp(machine_get_internal_name(), "ficva503a") || !strcmp(machine_get_internal_name(), "6via90ap"))
if ((machines[machine].init == machine_at_ficva503a_init) || (machines[machine].init == machine_at_6via90ap_init))
dev->regs.gpi_val |= 0x00000004;
else if (!strcmp(machine_get_internal_name(), "ficka6130"))
else if ((machines[machine].init == machine_at_ficka6130_init))
dev->regs.gpi_val |= 0x00080000;
/*
TriGem Delhi-III second GPI word:
@@ -2409,7 +2407,7 @@ acpi_reset(void *priv)
- Bit 6 = Password jumper (must be set);
- Bit 5 = Enable Setup (must be set).
*/
else if (!strcmp(machine_get_internal_name(), "delhi3"))
else if (machines[machine].init == machine_at_delhi3_init)
dev->regs.gpi_val |= 0x00008000;
}
@@ -2420,7 +2418,7 @@ acpi_reset(void *priv)
}
/* The Gateway Tomahawk requires the LID polarity bit to be set. */
if (!strcmp(machine_get_internal_name(), "tomahawk"))
if (machines[machine].init == machine_at_tomahawk_init)
dev->regs.glbctl |= 0x02000000;
acpi_rtc_status = 0;

2
src/apm.c
View File

@@ -8,8 +8,6 @@
*
* Advanced Power Management emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019 Miran Grca.

2
src/arch_detect.c
View File

@@ -8,8 +8,6 @@
*
* Configure-time architecture detection for the CMake build.
*
*
*
* Authors: David Hrdlička, <hrdlickadavid@outlook.com>
*
* Copyright 2020-2021 David Hrdlička.

2
src/cdrom/cdrom.c
View File

@@ -8,8 +8,6 @@
*
* Generic CD-ROM drive core.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2018-2021 Miran Grca.

14
src/cdrom/cdrom_image_viso.c
View File

@@ -880,7 +880,7 @@ viso_init(const uint8_t id, const char *dirname, int *error)
if (dirp) { /* create empty directory if opendir failed */
while ((readdir_entry = readdir(dirp))) {
/* Ignore . and .. pseudo-directories. */
if ((readdir_entry->d_name[0] == '.') && ((readdir_entry->d_name[1] == '\0') || (*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
if ((readdir_entry->d_name[0] == '.') && ((readdir_entry->d_name[1] == '\0') || (AS_U16(readdir_entry->d_name[1]) == '.')))
continue;
children_count++;
}
@@ -927,7 +927,7 @@ viso_init(const uint8_t id, const char *dirname, int *error)
/* Ignore . and .. pseudo-directories. */
if ((readdir_entry->d_name[0] == '.') &&
((readdir_entry->d_name[1] == '\0') ||
(*((uint16_t *) &readdir_entry->d_name[1]) == '.')))
(AS_U16(readdir_entry->d_name[1]) == '.')))
continue;
/* Add and fill entry. */
@@ -1245,8 +1245,8 @@ next_dir:
/* Calculate checksum. */
uint16_t eltorito_checksum = 0;
for (int i = 0; i < (p - data); i += 2)
eltorito_checksum -= le16_to_cpu(*((uint16_t *) &data[i]));
*((uint16_t *) &data[28]) = cpu_to_le16(eltorito_checksum);
eltorito_checksum -= le16_to_cpu(AS_U16(data[i]));
AS_U16(data[28]) = cpu_to_le16(eltorito_checksum);
/* Now fill the default boot entry. */
*p++ = 0x88; /* bootable flag */
@@ -1552,11 +1552,11 @@ next_entry:
uint32_t boot_size = entry->stats.st_size;
if (boot_size % 512) /* round up */
boot_size += 512 - (boot_size % 512);
*((uint16_t *) &data[0]) = cpu_to_le16(boot_size / 512);
AS_U16(data[0]) = cpu_to_le16(boot_size / 512);
} else { /* emulation */
*((uint16_t *) &data[0]) = cpu_to_le16(1);
AS_U16(data[0]) = cpu_to_le16(1);
}
*((uint32_t *) &data[2]) = cpu_to_le32(viso->all_sectors * base_factor);
AS_U32(data[2]) = cpu_to_le32(viso->all_sectors * base_factor);
viso_pwrite(data, eltorito_offset, 6, 1, viso->tf.fp);
} else {
p = data;

2
src/chipset/82c100.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of Chips&Technology's 82C100 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

1
src/chipset/CMakeLists.txt
View File

@@ -92,5 +92,6 @@ add_library(chipset OBJECT
via_apollo.c
via_pipc.c
vl82c480.c
vl82c59x.c
wd76c10.c
)

2
src/chipset/acc2168.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ACC 2046/2168 chipset
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Tiseno100
*

2
src/chipset/ali1409.c
View File

@@ -11,8 +11,6 @@
* Note: This chipset has no datasheet, everything were done via
* reverse engineering.
*
*
*
* Authors: Jose Phillips, <jose@latinol.com>
* Sarah Walker, <https://pcem-emulator.co.uk/>
*

2
src/chipset/ali1429.c
View File

@@ -11,8 +11,6 @@
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/ali1435.c
View File

@@ -7,8 +7,6 @@
* Emulation of ALi M1435 chipset that acts as both the
* southbridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.

2
src/chipset/ali1489.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M1489 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/ali1531.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M1531B CPU-to-PCI Bridge.
*
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.

2
src/chipset/ali1541.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M1541/2 CPU-to-PCI Bridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

2
src/chipset/ali1543.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M1543 Desktop South Bridge.
*
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.

2
src/chipset/ali1621.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M1621/2 CPU-to-PCI Bridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

2
src/chipset/ali6117.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ALi M6117 SoC.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/chipset/contaq_82c59x.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the Contaq/Cypress 82C596(A) and 597 chipsets.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

2
src/chipset/cs4031.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the Chips & Technologies CS4031 chipset.
*
*
*
* Authors: Tiseno100
*
* Copyright 2021 Tiseno100

2
src/chipset/cs8220.c
View File

@@ -160,7 +160,7 @@ cs8220_init(UNUSED(const device_t *info))
/*
Dell System 200: 640 kB soldered on-board, any other RAM is expansion.
*/
if (!strcmp(machine_get_internal_name(), "dells200")) switch (mem_size) {
if ((machines[machine].init == machine_at_dells200_init)) switch (mem_size) {
default:
dev->ram_banks[2].virt = 0x00100000;
dev->ram_banks[2].phys = 0x000a0000;

2
src/chipset/cs8230.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of C&T CS8230 ("386/AT") chipset.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2020 Sarah Walker.

2
src/chipset/et6000.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the ETEQ Cheetah ET6000 chipset.
*
*
*
* Authors: Tiseno100
*
* Copyright 2021 Tiseno100

2
src/chipset/gc100.c
View File

@@ -12,8 +12,6 @@
* GC100 chipset, the GC100A chipset has been reverese-engineered.
* Thus, its behavior may not be fully accurate.
*
*
*
* Authors: EngiNerd, <webmaster.crrc@yahoo.it>
*
* Copyright 2020-2021 EngiNerd.

1
src/chipset/grid1520.c
View File

@@ -9,6 +9,7 @@
* Implementation of the GRiD GRiDcase 1520
*
* The GRiDcase 1520 is a 286-based portable.
*
* These are HDDs supported by GRiD1520 (and probably other 15XX) BIOS
* "CP3022",5
* "CP3024",5, 615,4,17 BIOS table type 2

2
src/chipset/headland.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the HEADLAND AT286 chipset.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Fred N. van Kempen, <decwiz@yahoo.com>
* Original by GreatPsycho for PCem.

2
src/chipset/ims8848.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the IMS 8848/8849 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*

2
src/chipset/intel_420ex.c
View File

@@ -9,8 +9,6 @@
* Emulation of Intel 82420EX chipset that acts as both the
* northbridge and the southbridge.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.

4
src/chipset/intel_4x0.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the Intel PCISet chips from 420TX to 440GX.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019-2020 Miran Grca.
@@ -1549,7 +1547,7 @@ i4x0_read(int func, int addr, void *priv)
with the addition of bits 3 and 0. */
if ((func == 0) && (addr == 0x93) && ((dev->type == INTEL_440FX) || (dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)))
ret = (ret & 0xf9) | (pci_read(0x0cf9, NULL) & 0x06);
else if ((func == 0) && (addr == 0x52) && (dev->type == INTEL_430TX) && !strcmp(machine_get_internal_name(), "tomahawk"))
else if ((func == 0) && (addr == 0x52) && (dev->type == INTEL_430TX) && (machines[machine].init == machine_at_tomahawk_init))
ret = 0xb2;
}

2
src/chipset/intel_82335.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the Intel 82335(KU82335) chipset.
*
*
*
* Authors: Tiseno100
*
* Copyright 2021 Tiseno100.

4
src/chipset/intel_piix.c
View File

@@ -11,8 +11,6 @@
* word 0 - base address
* word 1 - bits 1-15 = byte count, bit 31 = end of transfer
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2020 Miran Grca.
@@ -1595,7 +1593,7 @@ piix_init(const device_t *info)
- Bit 4: CMOS clear jumper, must be clear;
- Bit 0: Password switch, must be clear.
*/
if (!strcmp(machine_get_internal_name(), "richmond"))
if (machines[machine].init == machine_at_richmond_init)
acpi_set_gpireg2_default(dev->acpi, 0xee);
else
acpi_set_gpireg2_default(dev->acpi, (dev->type > 4) ? 0xf1 : 0xdd);

4
src/chipset/intel_sio.c
View File

@@ -6,8 +6,6 @@
*
* Emulation of Intel System I/O PCI chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.
@@ -368,7 +366,7 @@ sio_config_read(uint16_t port, UNUSED(void *priv))
- 1, 0 = M;
- 1, 1 = M.
*/
if (!strcmp(machine_get_internal_name(), "opti560l"))
if (machines[machine].init == machine_at_opti560l_init)
ret = 0x20;
else
ret = 0xd3;

2
src/chipset/neat.c
View File

@@ -13,8 +13,6 @@
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2018 Fred N. van Kempen.

2
src/chipset/olivetti_eva.c
View File

@@ -11,8 +11,6 @@
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: EngiNerd <webmaster.crrc@yahoo.it>
*
* Copyright 2020-2021 EngiNerd

2
src/chipset/opti283.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the OPTi 82C283 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/opti291.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the OPTi 82C291 chipset.
*
*
*
* Authors: plant/nerd73, Tiseno100
*
* Copyright 2020 plant/nerd73.

2
src/chipset/opti391.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the OPTi 82C391/392 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

2
src/chipset/opti499.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the OPTi 82C493/82C499 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/opti822.c
View File

@@ -9,8 +9,6 @@
* Implementation of the OPTi 82C822 VESA Local Bus to PCI
* Bridge Interface.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2022 Miran Grca.

2
src/chipset/opti895.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the OPTi 82C802G/82C895 chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/scamp.c
View File

@@ -13,8 +13,6 @@
* 8MB of DRAM chips', because it works fine with bus-based
* memory expansion.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2020 Sarah Walker.

2
src/chipset/scat.c
View File

@@ -10,8 +10,6 @@
*
* Re-worked version based on the 82C235 datasheet and errata.
*
*
*
* Authors: Original by GreatPsycho for PCem.
* Fred N. van Kempen, <decwiz@yahoo.com>
*

2
src/chipset/sis_5571_old.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the SiS 5571 Chipset.
*
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.

2
src/chipset/sis_85c496.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the SiS 85c496/85c497 chip.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019-2020 Miran Grca.

6
src/chipset/sis_85c4xx.c
View File

@@ -9,8 +9,6 @@
* Emulation of the SiS 85c401/85c402, 85c460, 85c461, and
* 85c407/85c471 chipsets.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2019-2020 Miran Grca.
@@ -766,7 +764,7 @@ sis_85c4xx_reset(void *priv)
if (dev->is_471) {
dev->regs[0x09] = 0x40;
if (!strcmp(machine_get_internal_name(), "vli486sv2g")) {
if (machines[machine].init == machine_at_vli486sv2g_init) {
if (mem_size_mb == 64)
dev->regs[0x09] |= 0x1f;
else
@@ -784,7 +782,7 @@ sis_85c4xx_reset(void *priv)
dev->regs[0x09] |= 0x34;
else
dev->regs[0x09] |= 0x35;
} else if (!strcmp(machine_get_internal_name(), "tg486g"))
} else if (machines[machine].init == machine_at_tg486g_init)
dev->regs[0x09] |= ram_tg486g[mem_size_mb];
else
dev->regs[0x09] |= ram_471[mem_size_mb];

2
src/chipset/stpc.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the STMicroelectronics STPC series of SoCs.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/chipset/umc_8886.c
View File

@@ -11,8 +11,6 @@
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/via_apollo.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the VIA Apollo series of chips.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
* Tiseno100,

2
src/chipset/via_pipc.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the VIA PIPC southbridges.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
*

2
src/chipset/via_vt82c49x.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the VIA VT82C49X chipset.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/chipset/via_vt82c505.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the VIA VT82C505 VL/PCI Bridge Controller.
*
*
*
* Authors: Tiseno100,
* Miran Grca, <mgrca8@gmail.com>
*

16
src/chipset/vl82c480.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the VLSI VL82c480 chipset.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.
@@ -30,6 +28,8 @@
#include <86box/port_92.h>
#include <86box/chipset.h>
#define machine_at_prolineamt_init NULL /* checks for a removed machine */
typedef struct vl82c480_t {
uint8_t idx;
uint8_t regs[256];
@@ -132,8 +132,8 @@ vl82c480_write(uint16_t addr, uint8_t val, void *priv)
break;
case 0x02: case 0x03:
dev->regs[dev->idx] = val;
if (!strcmp(machine_get_internal_name(), "martin") ||
!strcmp(machine_get_internal_name(), "prolineamt"))
if ((machines[machine].init == machine_at_martin_init) ||
(machines[machine].init == machine_at_prolineamt_init))
vl82c480_recalc_banks(dev);
break;
case 0x04:
@@ -220,9 +220,9 @@ vl82c480_init(const device_t *info)
vl82c480_t *dev = (vl82c480_t *) calloc(1, sizeof(vl82c480_t));
uint32_t sizes[8] = { 0, 0, 1024, 2048, 4096, 8192, 16384, 32768 };
uint32_t ms = mem_size;
uint8_t min_i = !strcmp(machine_get_internal_name(), "prolineamt") ? 1 : 0;
uint8_t min_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 4 : 2;
uint8_t max_j = !strcmp(machine_get_internal_name(), "prolineamt") ? 8 : 7;
uint8_t min_i = (machines[machine].init == machine_at_prolineamt_init) ? 1 : 0;
uint8_t min_j = (machines[machine].init == machine_at_prolineamt_init) ? 4 : 2;
uint8_t max_j = (machines[machine].init == machine_at_prolineamt_init) ? 8 : 7;
dev->regs[0x00] = info->local;
dev->regs[0x01] = 0xff;
@@ -233,7 +233,7 @@ vl82c480_init(const device_t *info)
dev->regs[0x07] = 0x21;
dev->regs[0x08] = 0x38;
if (!strcmp(machine_get_internal_name(), "prolineamt")) {
if (machines[machine].init == machine_at_prolineamt_init) {
dev->banks[0] = 4096;
/* Bank 0 is ignored if 64 MB is installed. */

644
src/chipset/vl82c59x.c Normal file
View File

@@ -0,0 +1,644 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the VLSI SuperCore and Wildcat chipsets.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* win2kgamer
*
* Copyright 2020-2025 Miran Grca.
* Copyright 2025 win2kgamer
*/
#ifdef ENABLE_VL82C59X_LOG
#include <stdarg.h>
#endif
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/apm.h>
#include <86box/machine.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/pit_fast.h>
#include <86box/plat_unused.h>
#include <86box/mem.h>
#include <86box/nvr.h>
#include <86box/smram.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/spd.h>
#include <86box/keyboard.h>
#include <86box/chipset.h>
#include <86box/log.h>
#ifdef ENABLE_VL82C59X_LOG
int vl82c59x_do_log = ENABLE_VL82C59X_LOG;
static void
vl82c59x_log(void *priv, const char *fmt, ...)
{
if (vl82c59x_do_log) {
va_list ap;
va_start(ap, fmt);
log_out(priv, fmt, ap);
va_end(ap);
}
}
#else
# define vl82c59x_log(fmt, ...)
#endif
typedef struct vl82c59x_t {
uint8_t nb_slot;
uint8_t sb_slot;
uint8_t type;
uint8_t is_compaq;
uint8_t pci_conf[256];
uint8_t pci_conf_sb[256];
uint16_t pmio;
uint8_t pmio_set;
uint8_t pmreg;
smram_t *smram[4];
port_92_t *port_92;
nvr_t *nvr;
void * log; /* New logging system */
} vl82c59x_t;
static int
vl82c59x_shflags(uint8_t access)
{
int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
switch (access) {
default:
case 0x00:
ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
break;
case 0x01:
ret = MEM_READ_EXTANY | MEM_WRITE_INTERNAL;
break;
case 0x02:
ret = MEM_READ_INTERNAL | MEM_WRITE_EXTANY;
break;
case 0x03:
ret = MEM_READ_INTERNAL | MEM_WRITE_INTERNAL;
break;
}
return ret;
}
static void
vl82c59x_recalc(vl82c59x_t *dev)
{
uint32_t base;
uint8_t access;
shadowbios = 0;
shadowbios_write = 0;
for (uint8_t i = 0; i < 4; i++) {
for (uint8_t j = 0; j < 8; j += 2) {
base = 0x000c0000 + (i << 16) + (j << 13);
access = (dev->pci_conf[0x66 + i] >> j) & 3;
mem_set_mem_state_both(base, 0x4000, vl82c59x_shflags(access));
shadowbios |= ((base >= 0xe0000) && (access & 0x02));
shadowbios_write |= ((base >= 0xe0000) && (access & 0x01));
}
}
flushmmucache();
}
static void
vl82c59x_smram(vl82c59x_t *dev)
{
smram_disable_all();
/* A/B region SMRAM seems to not be controlled by 591 reg 0x7C/SMRAM enable */
/* Dell Dimension BIOS breaks if A0000 region is controlled by SMRAM enable */
if (dev->pci_conf[0x64] & 0x55) {
smram_enable(dev->smram[0], 0x000a0000, 0x000a0000, 0x10000, dev->pci_conf[0x64] & 0xAA, dev->pci_conf[0x64] & 0x55);
}
if (dev->pci_conf[0x65] & 0x55) {
smram_enable(dev->smram[1], 0x000b0000, 0x000b0000, 0x10000, dev->pci_conf[0x65] & 0xAA, dev->pci_conf[0x65] & 0x55);
}
/* Handle E region SMRAM */
if (dev->pci_conf[0x7C] & 0x80) {
if (dev->pci_conf[0x68] & 0x05) {
smram_enable(dev->smram[2], 0x000e0000, 0x000e0000, 0x8000, dev->pci_conf[0x68] & 0x0A, dev->pci_conf[0x68] & 0x05);
}
if (dev->pci_conf[0x68] & 0x50) {
smram_enable(dev->smram[3], 0x000e8000, 0x000e8000, 0x8000, dev->pci_conf[0x68] & 0xA0, dev->pci_conf[0x68] & 0x50);
}
}
flushmmucache();
}
static void
vl82c59x_pm_write(uint16_t addr, uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
vl82c59x_log(dev->log, "VL82c593 SMI I/O: [W] (%04X) = %02X\n", addr, val);
/* Verify SMI Global Enable and Software SMI Enable are set */
if ((dev->pci_conf_sb[0x6D] & 0x80) && (dev->pci_conf_sb[0x60] & 0x80)) {
dev->pci_conf_sb[0x61] = 0x80;
dev->pmreg = val;
smi_raise();
}
}
static uint8_t
vl82c59x_pm_read(uint16_t addr, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0x00;
ret = dev->pmreg;
vl82c59x_log(dev->log, "VL82c593 SMI I/O: [R] (%04X) = %02X\n", addr, ret);
return ret;
}
static void
vl82c59x_set_pm_io(void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t highbyte = dev->pci_conf_sb[0x62];
uint8_t lowbyte = dev->pci_conf_sb[0x63];
/* Check for existing I/O mapping and remove it */
if (dev->pmio_set == 1) {
vl82c59x_log(dev->log, "VL82c59x: Removing SMI IO handler for %04X\n", dev->pmio);
io_removehandler(dev->pmio, 0x0001, vl82c59x_pm_read, NULL, NULL, vl82c59x_pm_write, NULL, NULL, dev);
dev->pmio_set = 0;
}
if ((highbyte != 0x00) | (lowbyte != 0x00)) {
dev->pmio = ((highbyte << 8) + lowbyte);
vl82c59x_log(dev->log, "VL82c59x: Adding SMI IO handler for %04X\n", dev->pmio);
io_sethandler(dev->pmio, 0x0001, vl82c59x_pm_read, NULL, NULL, vl82c59x_pm_write, NULL, NULL, dev);
dev->pmio_set = 1;
}
}
static void
vl82c59x_write(int func, int addr, uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
vl82c59x_log(dev->log, "[%04X:%08X] VL82c591: [W] (%02X, %02X) = %02X\n", CS, cpu_state.pc, func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
case 0x05: /* PCI Command Register */
dev->pci_conf[addr] = val;
break;
case 0x54: /* Cache Control Register 1 */
dev->pci_conf[addr] = val;
cpu_cache_ext_enabled = (val & 0xc0);
cpu_update_waitstates();
break;
case 0x55: /* Cache Control Register 2 */
dev->pci_conf[addr] = val;
cpu_cache_int_enabled = (val & 0x40);
cpu_update_waitstates();
break;
case 0x58: /* RAMCFG0 */
case 0x59: /* RAMCFG1 */
dev->pci_conf[addr] = val;
break;
case 0x5A: /* Wildcat EDO RAM control */
if (dev->type == 0x01) {
dev->pci_conf[addr] = val;
}
break;
case 0x5C: /* RAMCTL0 */
case 0x5D: /* RAMCTL1 */
case 0x5E: /* RAMCTL2 */
case 0x5F:
case 0x60:
case 0x62:
/* Apricot XEN-PC Ruby/Jade BIOS requires bit 2 to be set or */
/* CMOS setup hangs on subsequent runs after NVRAM is initialized */
dev->pci_conf[addr] = val;
break;
case 0x64: /* A-B SMRAM regs */
case 0x65:
dev->pci_conf[addr] = val;
vl82c59x_smram(dev);
break;
case 0x66: /* Shadow RAM */
case 0x67:
case 0x68:
case 0x69:
dev->pci_conf[addr] = val;
vl82c59x_recalc(dev);
vl82c59x_smram(dev);
break;
case 0x6C: /* L2 Cacheability registers */
case 0x6D:
case 0x6E:
case 0x6F:
case 0x70:
case 0x71:
case 0x74: /* Suspected PMRA registers */
case 0x75:
case 0x76:
case 0x78:
case 0x79:
case 0x7A:
dev->pci_conf[addr] = val;
break;
case 0x7C: /* MISCSSET, bit 7 is SMRAM enable (for the E region) */
/* io.c logging shows BIOSes setting Bit 7 here */
dev->pci_conf[addr] = val;
vl82c59x_smram(dev);
break;
case 0x7D: /* Unknown but seems Wildcat-specific, Zeos and PB600 BIOSes hang if bit 3 is writable */
if (dev->type == 0x01) {
dev->pci_conf[addr] = val & 0xf7;
}
break;
default:
if (addr > 0x3F)
vl82c59x_log(dev->log, "VL82c591: Unknown reg [W] (%02X, %02X) = %02X\n", func, addr, val);
break;
}
}
static uint8_t
vl82c59x_read(int func, int addr, void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00) {
switch (addr) {
default:
ret = dev->pci_conf[addr];
break;
}
}
vl82c59x_log(dev->log, "[%04X:%08X] VL82c591: [R] (%02X, %02X) = %02X\n", CS, cpu_state.pc, func, addr, ret);
return ret;
}
static void
vl82c59x_sb_write(int func, int addr, uint8_t val, void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t irq;
const uint8_t irq_array[8] = { 3, 5, 9, 10, 11, 12, 14, 15 };
vl82c59x_log(dev->log, "[%04X:%08X] VL82c593: [W] (%02X, %02X) = %02X\n", CS, cpu_state.pc, func, addr, val);
if (func == 0x00)
switch (addr) {
case 0x04:
case 0x05: /* PCI Command Register */
dev->pci_conf_sb[addr] = val;
break;
case 0x50: /* MISCSETC */
case 0x51: /* MISCSETB */
case 0x52: /* MISCSETA */
case 0x53:
case 0x54:
case 0x55:
case 0x56:
case 0x57:
case 0x58:
case 0x59:
case 0x5A:
/* Has at least one GPIO bit. Compaq Presario 700/900 586 BIOS */
/* uses bit 2 as an output to set the onboard ES688's base I/O */
/* address. Bit 2 cleared = 220, bit 2 set = 240 */
case 0x5C: /* Interrupt Assertion Level Register */
case 0x5D:
dev->pci_conf_sb[addr] = val;
break;
case 0x60: /* SMI Enable Register */
dev->pci_conf_sb[addr] = val;
break;
case 0x61: /* SMI Status Register */
dev->pci_conf_sb[addr] = 0x00;
break;
case 0x62: /* SMI I/O port high byte */
case 0x63: /* SMI I/O port low byte */
dev->pci_conf_sb[addr] = val;
vl82c59x_set_pm_io(dev);
break;
case 0x64: /* System Event Enable Register 1 */
dev->pci_conf_sb[addr] = val;
break;
case 0x65: /* System Event Status Register 1 */
dev->pci_conf_sb[addr] = 0x00;
break;
case 0x66: /* System Event Enable Register 2 */
dev->pci_conf_sb[addr] = val;
break;
case 0x67: /* System Event Status Register 2 */
dev->pci_conf_sb[addr] = 0x00;
break;
case 0x68: /* System Event Enable Register 3 */
dev->pci_conf_sb[addr] = val;
break;
case 0x69: /* System Event Status Register 3 */
dev->pci_conf_sb[addr] = 0x00;
break;
case 0x6A: /* PCI Activity Control Register */
dev->pci_conf_sb[addr] = val & 0x0f; /* Top 4 bits are Read/Clear */
break;
case 0x6B: /* Programmable I/O Range Register High Byte */
dev->pci_conf_sb[addr] = val;
break;
case 0x6C: /* Programmable I/O Range Register Low Byte */
dev->pci_conf_sb[addr] = val;
break;
case 0x6D: /* System Event Control Register/SMI Global Enable */
dev->pci_conf_sb[addr] = val;
break;
case 0x6E:
case 0x6F:
case 0x70:
case 0x71:
case 0x72: /* GPIO */
/* Compaq Presario and Prolinea use bits 6-4 for setting ECP DMA */
/* 011 (0x03) = DMA 3 (Default) */
/* 100 (0x04) = DMA 0 */
/* 111 (0x07) = DMA disabled */
case 0x73: /* GPIO */
dev->pci_conf_sb[addr] = val;
break;
case 0x74: /* PCI Interrupt Connection Register (PCIINT0/1) */
dev->pci_conf_sb[addr] = val;
irq = irq_array[val & 0x07];
pci_set_irq_routing(PCI_INTA, (irq != 0) ? irq : PCI_IRQ_DISABLED);
irq = irq_array[(val & 0x70) >> 4];
pci_set_irq_routing(PCI_INTB, (irq != 0) ? irq : PCI_IRQ_DISABLED);
break;
case 0x75: /* PCI Interrupt Connection Register (PCIINT2/3) */
dev->pci_conf_sb[addr] = val;
irq = irq_array[val & 0x07];
pci_set_irq_routing(PCI_INTC, (irq != 0) ? irq : PCI_IRQ_DISABLED);
irq = irq_array[(val & 0x70) >> 4];
pci_set_irq_routing(PCI_INTD, (irq != 0) ? irq : PCI_IRQ_DISABLED);
break;
case 0x76: /* PCI Interrupt Connection Register (ISA/PCIINT) */
dev->pci_conf_sb[addr] = val;
break;
case 0x77:
case 0x78:
dev->pci_conf_sb[addr] = val;
break;
default:
if (addr > 0x3F)
vl82c59x_log(dev->log, "VL82c593: Unknown reg [W] (%02X, %02X) = %02X\n", func, addr, val);
break;
}
}
static uint8_t
vl82c59x_sb_read(int func, int addr, void *priv)
{
const vl82c59x_t *dev = (vl82c59x_t *) priv;
uint8_t ret = 0xff;
if (func == 0x00)
switch (addr) {
case 0x69: /* Lower two bits are a CPU speed readout per Compaq's Prolinea E series TRG */
/* Per the Prolinea TRG bits 5/3/1 of 593 reg 0x73 must be set to 1 to read the jumpers */
if (dev->is_compaq && (dev->pci_conf_sb[0x73] & 0x2A)) {
/* Set bit 2 to 1 as this is required for the Prolinea E to be properly identified
in Compaq Computer Setup. */
ret = (dev->pci_conf_sb[addr] | 0x04);
if (cpu_busspeed <= 50000000)
ret = (ret & 0xfd); /* 50MHz: Bit 1 = 0 */
else
ret = (ret | 0x02); /* 60MHz: Bit 1 = 1 */
if (cpu_dmulti <= 1.5)
ret = (ret | 0x01); /* 1.5x mult: Bit 0 = 1 */
else
ret = (ret & 0xfe); /* 2.0x mult: Bit 0 = 0 */
} else {
ret = dev->pci_conf_sb[addr];
}
break;
default:
ret = dev->pci_conf_sb[addr];
break;
}
vl82c59x_log(dev->log, "[%04X:%08X] VL82c593: [R] (%02X, %02X) = %02X\n", CS, cpu_state.pc, func, addr, ret);
return ret;
}
static void
vl82c59x_reset(void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
/* Northbridge (VLSI VL82c591) */
dev->pci_conf[0x00] = 0x04;
dev->pci_conf[0x01] = 0x10;
switch (dev->type) {
case 0: /* SuperCore */
dev->pci_conf[0x02] = 0x05;
dev->pci_conf[0x03] = 0x00;
break;
case 1: /* Wildcat */
dev->pci_conf[0x02] = 0x07;
dev->pci_conf[0x03] = 0x00;
break;
}
dev->pci_conf[0x08] = 0x00;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
/* Southbridge (VLSI VL82c593) */
dev->pci_conf_sb[0x00] = 0x04;
dev->pci_conf_sb[0x01] = 0x10;
switch (dev->type) {
case 0: /* SuperCore */
dev->pci_conf_sb[0x02] = 0x06;
dev->pci_conf_sb[0x03] = 0x00;
break;
case 1: /* Wildcat */
dev->pci_conf_sb[0x02] = 0x08;
dev->pci_conf_sb[0x03] = 0x00;
break;
}
dev->pci_conf_sb[0x08] = 0x00;
dev->pci_conf_sb[0x09] = 0x00;
dev->pci_conf_sb[0x0a] = 0x01;
dev->pci_conf_sb[0x0b] = 0x06;
/* Unsure on which register configures this (if any), per Compaq's
* Pentium-based Presario 700/900 Series and Prolinea E Series Desktop
* Technical Reference Guides the ISA bus runs at 8MHz while the
* Zeos Pantera Wildcat user manual says that the ISA bus runs at
* 7.5MHz on 90MHz (60MHz bus) systems and 8.25MHz on 100MHz (66MHz bus)
* systems.
*/
if (cpu_busspeed > 50000000)
cpu_set_isa_pci_div(4);
else
cpu_set_isa_pci_div(3);
pci_set_irq_routing(PCI_INTA, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTB, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTC, PCI_IRQ_DISABLED);
pci_set_irq_routing(PCI_INTD, PCI_IRQ_DISABLED);
vl82c59x_smram(dev);
/* Reset SMI IO port */
dev->pmio = 0x0000;
dev->pmio_set = 0;
cpu_cache_int_enabled = 1;
cpu_cache_ext_enabled = 1;
cpu_update_waitstates();
}
static void
vl82c59x_close(void *priv)
{
vl82c59x_t *dev = (vl82c59x_t *) priv;
smram_del(dev->smram[0]);
smram_del(dev->smram[1]);
smram_del(dev->smram[2]);
smram_del(dev->smram[3]);
if (dev->log != NULL) {
log_close(dev->log);
dev->log = NULL;
}
free(dev);
}
static void *
vl82c59x_init(UNUSED(const device_t *info))
{
vl82c59x_t *dev = (vl82c59x_t *) calloc(1, sizeof(vl82c59x_t));
dev->type = (info->local & 0x0f);
dev->is_compaq = (info->local >> 4);
dev->log = log_open("VL82c59x");
/* VL82c591 (Northbridge) */
pci_add_card(PCI_ADD_NORTHBRIDGE, vl82c59x_read, vl82c59x_write, dev, &dev->nb_slot);
/* VL82c593 (Southbridge) */
pci_add_card(PCI_ADD_SOUTHBRIDGE, vl82c59x_sb_read, vl82c59x_sb_write, dev, &dev->sb_slot);
dev->port_92 = device_add(&port_92_device);
/* NVR */
dev->nvr = device_add(&at_nvr_device);
dev->smram[0] = smram_add();
dev->smram[1] = smram_add();
dev->smram[2] = smram_add();
dev->smram[3] = smram_add();
vl82c59x_reset(dev);
return dev;
}
const device_t vl82c59x_device = {
.name = "VLSI VL82c59x (SuperCore)",
.internal_name = "vl82c59x",
.flags = DEVICE_PCI,
.local = 0,
.init = vl82c59x_init,
.close = vl82c59x_close,
.reset = vl82c59x_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t vl82c59x_compaq_device = {
.name = "VLSI VL82c59x (SuperCore with Compaq readout)",
.internal_name = "vl82c59x_compaq",
.flags = DEVICE_PCI,
.local = 0x10,
.init = vl82c59x_init,
.close = vl82c59x_close,
.reset = vl82c59x_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t vl82c59x_wildcat_device = {
.name = "VLSI VL82c59x (Wildcat)",
.internal_name = "vl82c59x_wildcat",
.flags = DEVICE_PCI,
.local = 1,
.init = vl82c59x_init,
.close = vl82c59x_close,
.reset = vl82c59x_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t vl82c59x_wildcat_compaq_device = {
.name = "VLSI VL82c59x (Wildcat with Compaq readout)",
.internal_name = "vl82c59x_wildcat_compaq",
.flags = DEVICE_PCI,
.local = 0x11,
.init = vl82c59x_init,
.close = vl82c59x_close,
.reset = vl82c59x_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

1
src/chipset/wd76c10.c
View File

@@ -11,7 +11,6 @@
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2024 Miran Grca.
*
*/
#include <stdarg.h>
#include <stdint.h>

25
src/config.c
View File

@@ -265,6 +265,7 @@ load_general(void)
do_auto_pause = ini_section_get_int(cat, "do_auto_pause", 0);
force_constant_mouse = ini_section_get_int(cat, "force_constant_mouse", 0);
fdd_sounds_enabled = ini_section_get_int(cat, "fdd_sounds_enabled", 1);
p = ini_section_get_string(cat, "uuid", NULL);
if (p != NULL)
@@ -572,7 +573,7 @@ load_input_devices(void)
p = ini_section_get_string(cat, "keyboard_type", NULL);
if (p != NULL)
keyboard_type = keyboard_get_from_internal_name(p);
else if (strstr(machine_get_internal_name(), "pc5086"))
else if (machines[machine].init == machine_xt_pc5086_init)
keyboard_type = KEYBOARD_TYPE_PC_XT;
else if (machine_has_bus(machine, MACHINE_BUS_PS2_PORTS)) {
if (machine_has_flags(machine, MACHINE_KEYBOARD_JIS))
@@ -1436,6 +1437,15 @@ load_floppy_and_cdrom_drives(void)
sprintf(temp, "fdd_%02i_check_bpb", c + 1);
ini_section_delete_var(cat, temp);
}
sprintf(temp, "fdd_%02i_audio", c + 1);
int def_prof = FDD_AUDIO_PROFILE_NONE;
int prof = ini_section_get_int(cat, temp, def_prof);
if (prof < 0 || prof >= FDD_AUDIO_PROFILE_MAX)
prof = def_prof;
fdd_set_audio_profile(c, prof);
if (prof == def_prof)
ini_section_delete_var(cat, temp);
for (int i = 0; i < MAX_PREV_IMAGES; i++) {
fdd_image_history[c][i] = (char *) calloc((MAX_IMAGE_PATH_LEN + 1) << 1, sizeof(char));
sprintf(temp, "fdd_%02i_image_history_%02i", c + 1, i + 1);
@@ -2479,6 +2489,11 @@ save_general(void)
else
ini_section_delete_var(cat, "force_constant_mouse");
if (fdd_sounds_enabled == 1)
ini_section_delete_var(cat, "fdd_sounds_enabled");
else
ini_section_set_int(cat, "fdd_sounds_enabled", fdd_sounds_enabled);
char cpu_buf[128] = { 0 };
plat_get_cpu_string(cpu_buf, 128);
ini_section_set_string(cat, "host_cpu", cpu_buf);
@@ -3416,6 +3431,14 @@ save_floppy_and_cdrom_drives(void)
else
save_image_file(cat, temp, fdd_image_history[c][i]);
}
sprintf(temp, "fdd_%02i_audio", c + 1);
int def_prof = FDD_AUDIO_PROFILE_NONE;
int prof = fdd_get_audio_profile(c);
if (prof == def_prof)
ini_section_delete_var(cat, temp);
else
ini_section_set_int(cat, temp, prof);
}
for (c = 0; c < CDROM_NUM; c++) {

2
src/cpu/386_common.h
View File

@@ -542,7 +542,7 @@ fastreadl_fetch(uint32_t a)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint32_t *) &pccache2[a]);
return AS_U32(pccache2[a]);
# endif
}
val = fastreadw_fetch(a);

6
src/cpu/cpu.c
View File

@@ -386,11 +386,7 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
return 1;
/* Cyrix 6x86MX on the NuPRO 592. */
if (((cpu_s->cyrix_id & 0xff00) == 0x0400) && (strstr(machine_s->internal_name, "nupro") != NULL))
return 0;
/* Cyrix 6x86MX or MII on the P5MMS98. */
if ((cpu_s->cpu_type == CPU_Cx6x86MX) && (strstr(machine_s->internal_name, "p5mms98") != NULL))
if (((cpu_s->cyrix_id & 0xff00) == 0x0400) && (machine_s->init == machine_at_nupro592_init))
return 0;
/* Check CPU blocklist. */

2
src/ddma.c
View File

@@ -8,8 +8,6 @@
*
* Distributed DMA emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.

2
src/device.c
View File

@@ -9,8 +9,6 @@
* Implementation of the generic device interface to handle
* all devices attached to the emulator.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* Sarah Walker, <https://pcem-emulator.co.uk/>

13
src/device/CMakeLists.txt
View File

@@ -18,6 +18,8 @@
add_library(dev OBJECT
access_bus.c
ast_nvr.c
ast_readout.c
bugger.c
cartridge.c
cassette.c
@@ -81,6 +83,17 @@ if(ISAMEM_BRAT)
target_compile_definitions(dev PRIVATE USE_ISAMEM_BRAT)
endif()
if(CMAKE_SYSTEM_NAME MATCHES "Linux")
if(VFIO)
include(CheckIncludeFile)
check_include_file("linux/vfio.h" VFIO_AVAILABLE)
if(VFIO_AVAILABLE)
add_compile_definitions(USE_VFIO)
target_sources(dev PRIVATE vfio.c)
endif()
endif()
endif()
if(LASERXT)
target_compile_definitions(dev PRIVATE USE_LASERXT)
endif()

180
src/device/ast_nvr.c Normal file
View File

@@ -0,0 +1,180 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the AST Bravo MS secondary NVR
*
*
*
* Authors: win2kgamer
*
* Copyright 2025 win2kgamer.
*/
#ifdef ENABLE_AST_NVR_LOG
#include <stdarg.h>
#endif
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/rom.h>
#include <86box/log.h>
#ifdef ENABLE_AST_NVR_LOG
int ast_nvr_do_log = ENABLE_AST_NVR_LOG;
static void
ast_nvr_log(void *priv, const char *fmt, ...)
{
if (ast_nvr_do_log) {
va_list ap;
va_start(ap, fmt);
log_out(priv, fmt, ap);
va_end(ap);
}
}
#else
# define ast_nvr_log(fmt, ...)
#endif
typedef struct ast_nvr_t {
int addr;
int bank;
uint8_t *ram;
int size;
char *fn;
void * log; // New logging system
} ast_nvr_t;
static uint8_t
ast_nvr_read(uint16_t port, void *priv)
{
ast_nvr_t *nvr = (ast_nvr_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x800 ... 0x8FF:
nvr->addr = ((nvr->bank << 8) + (port - 0x800));
ret = nvr->ram[nvr->addr];
break;
default:
break;
}
ast_nvr_log(nvr->log, "AST NVR Read [%02X:%02X] = %02X\n", nvr->bank, port, ret);
return ret;
}
static void
ast_nvr_write(uint16_t port, uint8_t val, void *priv)
{
ast_nvr_t *nvr = (ast_nvr_t *) priv;
ast_nvr_log(nvr->log, "AST NVR Write [%02X:%02X] = %02X\n", nvr->bank, port, val);
switch (port) {
case 0x800 ... 0x8FF:
nvr->addr = ((nvr->bank << 8) + (port - 0x800));
nvr->ram[nvr->addr] = val;
break;
case 0xC00:
nvr->bank = val;
default:
break;
}
}
static void *
ast_nvr_init(const device_t *info)
{
ast_nvr_t *nvr;
FILE *fp = NULL;
int c;
nvr = (ast_nvr_t *) calloc(1, sizeof(ast_nvr_t));
memset(nvr, 0x00, sizeof(ast_nvr_t));
nvr->log = log_open("ASTNVR");
nvr->size = 8192;
/* Set up the NVR file's name */
c = strlen(machine_get_internal_name()) + 9;
nvr->fn = (char *) calloc(1, (c + 1));
sprintf(nvr->fn, "%s_sec.nvr", machine_get_internal_name());
io_sethandler(0x0800, 0x100,
ast_nvr_read, NULL, NULL, ast_nvr_write, NULL, NULL, nvr);
io_sethandler(0x0C00, 0x01,
ast_nvr_read, NULL, NULL, ast_nvr_write, NULL, NULL, nvr);
fp = nvr_fopen(nvr->fn, "rb");
nvr->ram = (uint8_t *) calloc(1, nvr->size);
memset(nvr->ram, 0xff, nvr->size);
if (fp != NULL) {
if (fread(nvr->ram, 1, nvr->size, fp) != nvr->size)
fatal("ast_nvr_init(): Error reading EEPROM data\n");
fclose(fp);
}
return nvr;
}
static void
ast_nvr_close (void *priv)
{
ast_nvr_t *nvr = (ast_nvr_t *) priv;
FILE *fp = NULL;
fp = nvr_fopen(nvr->fn, "wb");
if (fp != NULL) {
(void) fwrite(nvr->ram, nvr->size, 1, fp);
fclose(fp);
}
if (nvr->ram != NULL)
free(nvr->ram);
if (nvr->log != NULL) {
log_close(nvr->log);
nvr->log = NULL;
}
free(nvr);
}
const device_t ast_nvr_device = {
.name = "AST Secondary NVRAM for Bravo MS",
.internal_name = "ast_nvr",
.flags = 0,
.local = 0,
.init = ast_nvr_init,
.close = ast_nvr_close,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

198
src/device/ast_readout.c Normal file
View File

@@ -0,0 +1,198 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the AST Bravo MS jumper readout.
*
*
*
* Authors: win2kgamer
*
* Copyright 2025 win2kgamer
*/
#ifdef ENABLE_AST_READOUT_LOG
#include <stdarg.h>
#endif
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/chipset.h>
#include <86box/plat_unused.h>
#include <86box/lpt.h>
#include <86box/machine.h>
#include <86box/log.h>
/*
The AST readout device has multiple indexed registers that handle
jumper readout, software ECP DMA configuration and other unknown functions.
Register 0x00:
Bits 6-4 = ECP DMA configuration
010 (0x02) = DMA 0
101 (0x05) = DMA 1
111 (0x07) = DMA 3
Register 0x03:
Bit 7 = Force flash
Bit 6 = Password disable
Bit 5 = Mono/Color primary video (0=Color/1=Mono)
Bit 4 = Setup disable (0=Enable Setup/1=Disable Setup)
Bit 3 = Enable onboard video (0=Enable/1=Disable)
Bit 2 = ????
Bit 1 = ????
Bit 0 = ????
*/
typedef struct ast_readout_t {
uint8_t index;
uint8_t jumper[4];
void * log; // New logging system
} ast_readout_t;
#ifdef ENABLE_AST_READOUT_LOG
int ast_readout_do_log = ENABLE_AST_READOUT_LOG;
static void
ast_readout_log(void *priv, const char *fmt, ...)
{
if (ast_readout_do_log) {
va_list ap;
va_start(ap, fmt);
log_out(priv, fmt, ap);
va_end(ap);
}
}
#else
# define ast_readout_log(fmt, ...)
#endif
static void
ast_readout_write(uint16_t port, uint8_t val, void *priv)
{
ast_readout_t *dev = (ast_readout_t *) priv;
switch (port) {
case 0xE0:
ast_readout_log(dev->log, "[%04X:%08X] AST Bravo Readout: Set Index %02X\n", CS, cpu_state.pc, val);
dev->index = val;
break;
case 0xE1:
ast_readout_log(dev->log, "[%04X:%08X] AST Bravo Readout: Write %02X:%02X\n", CS, cpu_state.pc, dev->index, val);
if ((dev->index == 0x00) && (!strcmp(machine_get_internal_name(), "bravoms586"))) {
uint8_t dmaval = ((val >> 4) & 0x07);
dev->jumper[dev->index] = val;
switch (dmaval) {
case 0x02:
ast_readout_log(dev->log, "ECP DMA set to 0\n");
lpt1_dma(0);
break;
case 0x05:
ast_readout_log(dev->log, "ECP DMA set to 1\n");
lpt1_dma(1);
break;
case 0x07:
ast_readout_log(dev->log, "ECP DMA set to 3\n");
lpt1_dma(3);
break;
default:
ast_readout_log(dev->log, "Unknown ECP DMA!\n");
break;
}
} else if (dev->index == 0x03) {
dev->jumper[dev->index] = (val & 0x07);
if (gfxcard[0] != 0x01)
dev->jumper[dev->index] |= 0x08;
}
else
dev->jumper[dev->index] = val;
break;
default:
break;
}
}
static uint8_t
ast_readout_read(uint16_t port, void *priv)
{
const ast_readout_t *dev = (ast_readout_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0xE0:
ast_readout_log(dev->log, "[%04X:%08X] AST Bravo Readout: Read Index %02X\n", CS, cpu_state.pc, dev->index);
ret = dev->index;
break;
case 0xE1:
ast_readout_log(dev->log, "[%04X:%08X] AST Bravo Readout: Read %02X:%02X\n", CS, cpu_state.pc, dev->index, dev->jumper[dev->index]);
ret = dev->jumper[dev->index];
break;
default:
break;
}
return ret;
}
static void
ast_readout_reset(void *priv)
{
ast_readout_t *dev = (ast_readout_t *) priv;
dev->jumper[0x03] = 0x06;
if (gfxcard[0] != 0x01)
dev->jumper[0x03] |= 0x08;
}
static void
ast_readout_close(void *priv)
{
ast_readout_t *dev = (ast_readout_t *) priv;
if (dev->log != NULL) {
log_close(dev->log);
dev->log = NULL;
}
free(dev);
}
static void *
ast_readout_init(const device_t *info)
{
ast_readout_t *dev = (ast_readout_t *) calloc(1, sizeof(ast_readout_t));
dev->log = log_open("AST Readout");
ast_readout_reset(dev);
io_sethandler(0x00E0, 0x0002, ast_readout_read, NULL, NULL, ast_readout_write, NULL, NULL, dev);
return dev;
}
const device_t ast_readout_device = {
.name = "AST Bravo MS Readout",
.internal_name = "ast_readout",
.flags = 0,
.local = 0,
.init = ast_readout_init,
.close = ast_readout_close,
.reset = ast_readout_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

3
src/device/bugger.c
View File

@@ -44,9 +44,8 @@
* configuration register (CTRL_SPCFG bit set) but have to
* remember that stuff first...
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 1989-2018 Fred N. van Kempen.
*/
#include <stdarg.h>

2
src/device/cartridge.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the PCjr cartridge emulation.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.

2
src/device/clock_ics9xxx.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the ICS9xxx series of clock generators.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/hasp.c
View File

@@ -12,8 +12,6 @@
* emulation is enough to satisfy that game, but not Aladdin's
* DiagnostiX utility.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
* Peter Ferrie
*

3
src/device/hwm.c
View File

@@ -8,13 +8,10 @@
*
* Common functions for hardware monitoring chips.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>

2
src/device/hwm_gl518sm.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the Genesys Logic GL518SM hardware monitoring chip.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/hwm_lm75.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the National Semiconductor LM75 temperature sensor chip.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/hwm_lm78.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the National Semiconductor LM78 hardware monitoring chip.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/hwm_vt82c686.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the VIA VT82C686A/B integrated hardware monitor.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/i2c.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the I2C bus and its operations.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/i2c_gpio.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of a GPIO-based I2C host controller.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/ibm_5161.c
View File

@@ -6,8 +6,6 @@
*
* Emulation of the IBM Expansion Unit (5161).
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

283
src/device/isapnp.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of ISA Plug and Play.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* RichardG, <richardg867@gmail.com>
*
@@ -27,6 +25,7 @@
#include <86box/io.h>
#include <86box/isapnp.h>
#include <86box/plat_unused.h>
#include "cpu.h"
#define CHECK_CURRENT_LD() \
if (!ld) { \
@@ -44,6 +43,11 @@ const uint8_t isapnp_init_key[32] = { 0x6A, 0xB5, 0xDA, 0xED, 0xF6, 0xFB
0xDF, 0x6F, 0x37, 0x1B, 0x0D, 0x86, 0xC3, 0x61,
0xB0, 0x58, 0x2C, 0x16, 0x8B, 0x45, 0xA2, 0xD1,
0xE8, 0x74, 0x3A, 0x9D, 0xCE, 0xE7, 0x73, 0x39 };
/* Required for the RTL8019AS. */
const uint8_t isapnp_init_key2[32] = { 0xDA, 0x6D, 0x36, 0x1B, 0x8D, 0x46, 0x23, 0x91,
0x48, 0xA4, 0xD2, 0x69, 0x34, 0x9A, 0x4D, 0x26,
0x13, 0x89, 0x44, 0xA2, 0x51, 0x28, 0x94, 0xCA,
0x65, 0x32, 0x19, 0x0C, 0x86, 0x43, 0xA1, 0x50 };
static const device_t isapnp_device;
#ifdef ENABLE_ISAPNP_LOG
@@ -73,6 +77,7 @@ enum {
typedef struct _isapnp_device_ {
uint8_t number;
uint8_t defs[256];
uint8_t regs[256];
uint8_t mem_upperlimit;
uint8_t irq_types;
@@ -87,11 +92,15 @@ typedef struct _isapnp_card_ {
uint8_t enable;
uint8_t state;
uint8_t csn;
uint8_t csnsav;
uint8_t ld;
uint8_t id_checksum;
uint8_t serial_read;
uint8_t serial_read_pair;
uint8_t serial_read_pos;
uint8_t is_rt;
uint8_t normal;
uint8_t multiple_lds;
uint8_t *rom;
uint16_t rom_pos;
uint16_t rom_size;
@@ -111,6 +120,7 @@ typedef struct _isapnp_card_ {
typedef struct {
uint8_t in_isolation;
uint8_t using_key2;
uint8_t reg;
uint8_t key_pos : 5;
uint16_t read_data_addr;
@@ -168,7 +178,7 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld)
}
for (uint8_t i = 0; i < 8; i++) {
reg_base = 0x60 + (2 * i);
if (ld->regs[0x31] & 0x02)
if (!(ld->regs[0x30] & 0x01) && (ld->regs[0x31] & 0x02))
card->config.io[i].base = 0; /* let us handle I/O range check reads */
else
card->config.io[i].base = (ld->regs[reg_base] << 8) | ld->regs[reg_base + 1];
@@ -176,7 +186,7 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld)
for (uint8_t i = 0; i < 2; i++) {
reg_base = 0x70 + (2 * i);
card->config.irq[i].irq = ld->regs[reg_base];
card->config.irq[i].level = ld->regs[reg_base + 1] & 0x02;
card->config.irq[i].level = !!(ld->regs[reg_base + 1] & 0x02);
card->config.irq[i].type = ld->regs[reg_base + 1] & 0x01;
}
for (uint8_t i = 0; i < 2; i++) {
@@ -258,17 +268,29 @@ isapnp_reset_ld_regs(isapnp_device_t *ld)
/* Set the default IRQ type bits. */
for (uint8_t i = 0; i < 2; i++) {
if (ld->irq_types & (0x1 << (4 * i)))
ld->regs[0x70 + (2 * i)] = 0x02;
ld->regs[0x71 + (2 * i)] = 0x02;
else if (ld->irq_types & (0x2 << (4 * i)))
ld->regs[0x70 + (2 * i)] = 0x00;
ld->regs[0x71 + (2 * i)] = 0x00;
else if (ld->irq_types & (0x4 << (4 * i)))
ld->regs[0x70 + (2 * i)] = 0x03;
ld->regs[0x71 + (2 * i)] = 0x03;
else if (ld->irq_types & (0x8 << (4 * i)))
ld->regs[0x70 + (2 * i)] = 0x01;
ld->regs[0x71 + (2 * i)] = 0x01;
}
/* Reset configuration registers to match the default configuration. */
isapnp_reset_ld_config(ld);
if (ld->defs[0x30] != 0x00)
ld->regs[0x30] = ld->defs[0x30];
if (ld->defs[0x60] != 0x00)
ld->regs[0x60] = ld->defs[0x60];
if (ld->defs[0x61] != 0x00)
ld->regs[0x61] = ld->defs[0x61];
if (ld->defs[0x70] != 0x00)
ld->regs[0x70] = ld->defs[0x70];
}
static uint8_t
@@ -290,7 +312,7 @@ isapnp_read_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uint
case 0x01: /* Serial Isolation */
card = dev->first_card;
while (card) {
if (card->enable && card->rom && (card->state == PNP_STATE_ISOLATION))
if (card->enable && (card->rom != NULL) && (card->state == PNP_STATE_ISOLATION))
break;
card = card->next;
}
@@ -376,6 +398,7 @@ vendor_defined:
default:
if (reg >= 0x30) {
CHECK_CURRENT_CARD();
CHECK_CURRENT_LD();
isapnp_log("ISAPnP: Read register %02X from CSN %02X device %02X\n", reg, card->csn, ld->number);
ret = ld->regs[reg];
@@ -399,7 +422,8 @@ isapnp_read_data(UNUSED(uint16_t addr), void *priv)
card = card->next;
}
isapnp_log("ISAPnP: read_data() => ");
// isapnp_log("ISAPnP: read_data() => ");
isapnp_log("[%04X:%08X] ISAPnP: read_data() => ", CS, cpu_state.pc);
return isapnp_read_common(dev, card, dev->current_ld, dev->reg);
}
@@ -434,26 +458,60 @@ isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv)
if (card->state == PNP_STATE_WAIT_FOR_KEY) { /* checking only the first card should be fine */
/* Check written value against LFSR key. */
if (val == isapnp_init_key[dev->key_pos]) {
if ((val == isapnp_init_key[dev->key_pos]) || (val == isapnp_init_key2[dev->key_pos])) {
dev->using_key2 = (val == isapnp_init_key2[dev->key_pos]);
dev->key_pos++;
if (!dev->key_pos) {
isapnp_log("ISAPnP: Key unlocked, putting cards to SLEEP\n");
while (card) {
if (card->enable && (card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY))
int match_rt = (dev->using_key2 && card->is_rt);
int match_normal = (!dev->using_key2 && card->normal);
if (card->enable && (match_rt || match_normal) &&
(card->enable != ISAPNP_CARD_NO_KEY) && (card->state == PNP_STATE_WAIT_FOR_KEY))
card->state = PNP_STATE_SLEEP;
card = card->next;
}
}
} else {
} else
dev->key_pos = 0;
}
}
}
static void
isapnp_ld_io_remove(isapnp_device_t *ld)
{
uint16_t io_addr;
for (uint8_t i = 0; i < 8; i++) {
if (!ld->io_len[i])
continue;
io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)];
io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld);
}
}
static void
isapnp_ld_io_set(isapnp_device_t *ld)
{
uint16_t io_addr;
for (uint8_t i = 0; i < 8; i++) {
if (!ld->io_len[i])
continue;
io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)];
int ior = !(ld->regs[0x30] & 0x01) && (ld->regs[0x31] & 0x02);
if (ior)
io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld);
}
}
static void
isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uint8_t reg, uint8_t val)
{
uint16_t io_addr;
uint16_t reset_cards = 0;
isapnp_log("ISAPnP: write_common(%02X, %02X)\n", reg, val);
@@ -495,6 +553,7 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin
card->state = PNP_STATE_WAIT_FOR_KEY;
card = card->next;
}
dev->key_pos = 0;
}
if (val & 0x04) {
isapnp_log("ISAPnP: Reset CSN\n");
@@ -515,8 +574,22 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin
if (card->csn == val) {
card->rom_pos = 0;
card->id_checksum = isapnp_init_key[0];
if (card->state == PNP_STATE_SLEEP)
if (card->state == PNP_STATE_SLEEP) {
card->state = (val == 0) ? PNP_STATE_ISOLATION : PNP_STATE_CONFIG;
if (!card->multiple_lds) {
ld = card->first_ld;
while (ld) {
if (ld->number == 0x00) {
isapnp_log("ISAPnP: Select CSN %02X device 00\n", card->csn);
dev->current_ld_card = card;
dev->current_ld = ld;
break;
}
ld = ld->next;
}
}
}
} else
card->state = PNP_STATE_SLEEP;
@@ -537,56 +610,47 @@ isapnp_write_common(isapnp_t *dev, isapnp_card_t *card, isapnp_device_t *ld, uin
break;
case 0x07: /* Logical Device Number */
CHECK_CURRENT_CARD();
if (card->multiple_lds) {
CHECK_CURRENT_CARD();
card->ld = val;
ld = card->first_ld;
while (ld) {
if (ld->number == val) {
isapnp_log("ISAPnP: Select CSN %02X device %02X\n", card->csn, val);
dev->current_ld_card = card;
dev->current_ld = ld;
break;
card->ld = val;
ld = card->first_ld;
while (ld) {
if (ld->number == val) {
isapnp_log("ISAPnP: Select CSN %02X device %02X\n", card->csn, val);
dev->current_ld_card = card;
dev->current_ld = ld;
break;
}
ld = ld->next;
}
ld = ld->next;
}
if (!ld) {
isapnp_log("ISAPnP: CSN %02X has no device %02X, creating one\n", card->csn, val);
dev->current_ld_card = card;
dev->current_ld = isapnp_create_ld(card);
dev->current_ld->number = val;
if (!ld) {
isapnp_log("ISAPnP: CSN %02X has no device %02X, creating one\n", card->csn, val);
dev->current_ld_card = card;
dev->current_ld = isapnp_create_ld(card);
dev->current_ld->number = val;
}
}
break;
case 0x30: /* Activate */
CHECK_CURRENT_LD();
isapnp_log("ISAPnP: %sctivate CSN %02X device %02X\n", (val & 0x01) ? "A" : "Dea", card->csn, ld->number);
ld->regs[reg] = val & 0x01;
isapnp_device_config_changed(card, ld);
break;
case 0x31: /* I/O Range Check */
CHECK_CURRENT_LD();
for (uint8_t i = 0; i < 8; i++) {
if (!ld->io_len[i])
continue;
isapnp_log("ISAPnP: %sctivate CSN %02X device %02X\n", (ld->regs[0x30] & 0x01) ? "A" : "Dea",
card->csn, ld->number);
io_addr = (ld->regs[0x60 + (2 * i)] << 8) | ld->regs[0x61 + (2 * i)];
if (ld->regs[reg] & 0x02)
io_removehandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld);
if (val & 0x02)
io_sethandler(io_addr, ld->io_len[i], isapnp_read_rangecheck, NULL, NULL, NULL, NULL, NULL, ld);
}
isapnp_ld_io_remove(ld);
if (reg == 0x30)
ld->regs[reg] = val & 0x01;
else
ld->regs[reg] = val & 0x03;
isapnp_ld_io_set(ld);
ld->regs[reg] = val & 0x03;
isapnp_device_config_changed(card, ld);
break;
case 0x20 ... 0x2f:
@@ -603,6 +667,7 @@ vendor_defined:
default:
if (reg >= 0x40) {
CHECK_CURRENT_CARD();
CHECK_CURRENT_LD();
isapnp_log("ISAPnP: Write %02X to register %02X on CSN %02X device %02X\n", val, reg, card->csn, ld->number);
@@ -651,7 +716,9 @@ vendor_defined:
break;
}
isapnp_ld_io_remove(ld);
ld->regs[reg] = val;
isapnp_ld_io_set(ld);
isapnp_device_config_changed(card, ld);
}
break;
@@ -672,7 +739,8 @@ isapnp_write_data(UNUSED(uint16_t addr), uint8_t val, void *priv)
}
}
isapnp_log("ISAPnP: write_data(%02X) => ", val);
// isapnp_log("ISAPnP: write_data(%02X) => ", val);
isapnp_log("[%04X:%08X] ISAPnP: write_data(%02X) => ", CS, cpu_state.pc, val);
isapnp_write_common(dev, card, dev->current_ld, dev->reg, val);
}
@@ -731,11 +799,13 @@ isapnp_add_card(uint8_t *rom, uint16_t rom_size,
isapnp_card_t *card = (isapnp_card_t *) calloc(1, sizeof(isapnp_card_t));
card->enable = 1;
card->normal = 1;
card->priv = priv;
card->config_changed = config_changed;
card->csn_changed = csn_changed;
card->read_vendor_reg = read_vendor_reg;
card->write_vendor_reg = write_vendor_reg;
card->multiple_lds = 1;
if (!dev->first_card) {
dev->first_card = card;
@@ -815,22 +885,22 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
isapnp_log("ISAPnP: >>%s Memory range %d with %d bytes at %06X-%06X to %06X-%06X, align %d",
/* %s */ in_df ? ">" : "",
/* %d */ mem_range,
/* %d */ *((uint16_t *) &card->rom[i + 8]),
/* %06X */ *((uint16_t *) &card->rom[i + 4]) << 8,
/* %d */ AS_U16(card->rom[i + 8]),
/* %06X */ AS_U16(card->rom[i + 4]) << 8,
/* %06X */ ((card->rom[i + 3] & 0x4) ?
/* High address. */
(*((uint16_t *) &card->rom[i + 10]) << 8) :
(AS_U16(card->rom[i + 10]) << 8) :
/* Range. */
(*((uint16_t *) &card->rom[i + 4]) << 8)) +
(*((uint16_t *) &card->rom[i + 10]) << 8),
/* %06X */ *((uint16_t *) &card->rom[i + 6]) << 8,
(AS_U16(card->rom[i + 4]) << 8)) +
(AS_U16(card->rom[i + 10]) << 8),
/* %06X */ AS_U16(card->rom[i + 6]) << 8,
/* %06X */ ((card->rom[i + 3] & 0x4) ?
/* High address. */
(*((uint16_t *) &card->rom[i + 10]) << 8) :
(AS_U16(card->rom[i + 10]) << 8) :
/* Range. */
(*((uint16_t *) &card->rom[i + 6]) << 8)) +
(*((uint16_t *) &card->rom[i + 10]) << 8),
/* %d */ *((uint16_t *) &card->rom[i + 8]));
(AS_U16(card->rom[i + 6]) << 8)) +
(AS_U16(card->rom[i + 10]) << 8),
/* %d */ AS_U16(card->rom[i + 8]));
res = 1 << mem_range;
mem_range++;
} else {
@@ -847,22 +917,22 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
isapnp_log("ISAPnP: >>%s 32-bit memory range %d with %d bytes at %08X-%08X, align %d",
/* %s */ in_df ? ">" : "",
/* %d */ mem_range_32,
/* %d */ *((uint32_t *) &card->rom[i + 12]),
/* %08X */ *((uint32_t *) &card->rom[i + 4]),
/* %d */ AS_U32(card->rom[i + 12]),
/* %08X */ AS_U32(card->rom[i + 4]),
/* %08X */ ((card->rom[i + 3] & 0x4) ?
/* High address. */
*((uint32_t *) &card->rom[i + 16]) :
AS_U32(card->rom[i + 16]) :
/* Range. */
*((uint32_t *) &card->rom[i + 4])) +
*((uint32_t *) &card->rom[i + 16]),
/* %08X */ *((uint32_t *) &card->rom[i + 8]),
AS_U32(card->rom[i + 4])) +
AS_U32(card->rom[i + 16]),
/* %08X */ AS_U32(card->rom[i + 8]),
/* %08X */ ((card->rom[i + 3] & 0x4) ?
/* High address. */
*((uint32_t *) &card->rom[i + 16]) :
AS_U32(card->rom[i + 16]) :
/* Range. */
*((uint32_t *) &card->rom[i + 8])) +
*((uint32_t *) &card->rom[i + 16]),
/* %d */ *((uint32_t *) &card->rom[i + 12]));
AS_U32(card->rom[i + 8])) +
AS_U32(card->rom[i + 16]),
/* %d */ AS_U32(card->rom[i + 12]));
res = 1 << (4 + mem_range_32);
mem_range_32++;
}
@@ -972,7 +1042,7 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
else /* specific */
res = card->rom[i + 3] & 0x0f;
isapnp_log("ISAPnP: >>%s IRQ index %d with mask %04X, types %01X\n", in_df ? ">" : "", irq, *((uint16_t *) &card->rom[i + 1]), res);
isapnp_log("ISAPnP: >>%s IRQ index %d with mask %04X, types %01X\n", in_df ? ">" : "", irq, AS_U16(card->rom[i + 1]), res);
ld->irq_types &= ~(0x0f << (4 * irq));
ld->irq_types |= res << (4 * irq);
@@ -1038,7 +1108,7 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
break;
}
isapnp_log("ISAPnP: >>%s I/O range %d with %d ports at %04X-%04X, align %d, %d-bit decode\n", in_df ? ">" : "", io, card->rom[i + 7], *((uint16_t *) &card->rom[i + 2]), *((uint16_t *) &card->rom[i + 4]), card->rom[i + 6], (card->rom[i + 1] & 0x01) ? 16 : 10);
isapnp_log("ISAPnP: >>%s I/O range %d with %d ports at %04X-%04X, align %d, %d-bit decode\n", in_df ? ">" : "", io, card->rom[i + 7], AS_U16(card->rom[i + 2]), AS_U16(card->rom[i + 4]), card->rom[i + 6], (card->rom[i + 1] & 0x01) ? 16 : 10);
if (card->rom[i + 1] & 0x01)
ld->io_16bit |= 1 << io;
@@ -1063,7 +1133,7 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
break;
}
isapnp_log("ISAPnP: >>%s Fixed I/O range %d with %d ports at %04X\n", in_df ? ">" : "", io, card->rom[i + 3], *((uint16_t *) &card->rom[i + 1]));
isapnp_log("ISAPnP: >>%s Fixed I/O range %d with %d ports at %04X\n", in_df ? ">" : "", io, card->rom[i + 3], AS_U16(card->rom[i + 1]));
/* Fixed I/O port ranges of this kind are always 10-bit. */
ld->io_16bit &= ~(1 << io);
@@ -1117,6 +1187,8 @@ isapnp_enable_card(void *priv, uint8_t enable)
/* Enable or disable the card. */
if (!!enable ^ !!card->enable)
card->state = (enable == ISAPNP_CARD_FORCE_CONFIG) ? PNP_STATE_CONFIG : PNP_STATE_WAIT_FOR_KEY;
if (enable == ISAPNP_CARD_FORCE_SLEEP)
card->state = PNP_STATE_SLEEP;
int old_enable = card->enable;
card->enable = enable;
@@ -1163,6 +1235,63 @@ isapnp_read_reg(void *priv, uint8_t ldn, uint8_t reg)
return isapnp_read_common(device_get_priv(&isapnp_device), card, ld, reg);
}
void
isapnp_set_rt(void *priv, uint8_t is_rt)
{
isapnp_card_t *card = (isapnp_card_t *) priv;
card->is_rt = is_rt;
}
void
isapnp_set_normal(void *priv, uint8_t normal)
{
isapnp_card_t *card = (isapnp_card_t *) priv;
card->normal = normal;
}
void
isapnp_activate(void *priv, uint16_t base, uint8_t irq, int active)
{
isapnp_card_t *card = (isapnp_card_t *) priv;
isapnp_device_t *ld = card->first_ld;
while (ld) {
if (ld->number == 0x00)
break;
ld = ld->next;
}
if (ld != NULL) {
ld->defs[0x30] = active;
ld->defs[0x60] = base >> 8;
if (!(ld->io_16bit & (1 << ((0x60 >> 1) & 0x07))))
ld->defs[0x60] &= 0x03;
ld->defs[0x61] = base & 0xff;
ld->defs[0x70] = irq;
isapnp_reset_ld_regs(ld);
}
}
void
isapnp_set_single_ld(void *priv)
{
isapnp_card_t *card = (isapnp_card_t *) priv;
card->multiple_lds = 0;
card->ld = 0x00;
}
uint8_t *
isapnp_get_csnsav(void *priv)
{
isapnp_card_t *card = (isapnp_card_t *) priv;
return &card->csnsav;
}
void
isapnp_write_reg(void *priv, uint8_t ldn, uint8_t reg, uint8_t val)
{

4
src/device/isartc.c
View File

@@ -26,8 +26,6 @@
* NOTE: The IRQ functionalities have been implemented, but not yet
* tested, as I need to write test software for them first :)
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
* Copyright 2018 Fred N. van Kempen.
@@ -523,7 +521,7 @@ isartc_init(const device_t *info)
{
rtcdev_t *dev;
int is_at = IS_AT(machine);
is_at = is_at || !strcmp(machine_get_internal_name(), "xi8088");
is_at = is_at || (machines[machine].init == machine_xt_xi8088_init);
/* Create a device instance. */
dev = (rtcdev_t *) calloc(1, sizeof(rtcdev_t));

12
src/device/kbc_at.c
View File

@@ -806,15 +806,15 @@ write_p2(atkbc_t *dev, uint8_t val)
cpu_set_edx();
flushmmucache();
if ((kbc_ven == KBC_VEN_ALI) ||
!strcmp(machine_get_internal_name(), "spc7700plw") ||
!strcmp(machine_get_internal_name(), "pl4600c"))
(machines[machine].init == machine_at_spc7700plw_init) ||
(machines[machine].init == machine_at_pl4600c_init))
smbase = 0x00030000;
/* Yes, this is a hack, but until someone gets ahold of the real PCD-2L
and can find out what they actually did to make it boot from FFFFF0
correctly despite A20 being gated when the CPU is reset, this will
have to do. */
if ((kbc_ven == KBC_VEN_SIEMENS) || !strcmp(machine_get_internal_name(), "acera1g"))
if ((kbc_ven == KBC_VEN_SIEMENS) || (machines[machine].init == machine_at_acera1g_init))
is486 ? loadcs(0xf000) : loadcs_2386(0xf000);
}
}
@@ -1187,7 +1187,7 @@ write_cmd_ami(void *priv, uint8_t val)
kbc_at_log("ATkbc: set KBC lines P22-P23 (P2 bits 2-3) low\n");
if (!(dev->flags & DEVICE_PCI))
write_p2(dev, dev->p2 & ~(4 << (val & 0x01)));
if (strstr(machine_get_internal_name(), "sb486pv") != NULL)
if (machines[machine].init == machine_at_sb486pv_init)
kbc_delay_to_ob(dev, 0x03, 0, 0x00);
else
kbc_delay_to_ob(dev, dev->ob, 0, 0x00);
@@ -2627,7 +2627,7 @@ kbc_at_process_cmd(void *priv)
if (dev->ib == 0xbb)
break;
if (strstr(machine_get_internal_name(), "pb41") != NULL)
if (machines[machine].init == machine_at_pb410a_init)
cpu_override_dynarec = 1;
if (dev->misc_flags & FLAG_PS2) {
@@ -2759,7 +2759,7 @@ kbc_at_port_1_read(uint16_t port, void *priv)
*/
if (!(dev->misc_flags & FLAG_PS2) && (dev->irq[0] != 0xffff))
picintclevel(1 << dev->irq[0], &dev->irq_state);
if ((strstr(machine_get_internal_name(), "pb41") != NULL) && (cpu_override_dynarec == 1))
if ((machines[machine].init == machine_at_pb410a_init) && (cpu_override_dynarec == 1))
cpu_override_dynarec = 0;
kbc_at_log("ATkbc: [%04X:%08X] read (%04X) = %02X\n", CS, cpu_state.pc, port, ret);

2
src/device/kbc_xt.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the XT-style keyboard.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>

2
src/device/keyboard.c
View File

@@ -8,8 +8,6 @@
*
* General keyboard driver interface.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>

2
src/device/keyboard_xt.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the XT-style keyboard.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>

2
src/device/mouse.c
View File

@@ -11,8 +11,6 @@
* TODO: Add the Genius bus- and serial mouse.
* Remove the '3-button' flag from mouse types.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*

2
src/device/mouse_bus.c
View File

@@ -57,8 +57,6 @@
* Microsoft Windows NT 3.1
* Microsoft Windows 98 SE
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*

2
src/device/mouse_microtouch_touchscreen.c
View File

@@ -8,8 +8,6 @@
*
* 3M MicroTouch Serial emulation.
*
*
*
* Authors: Cacodemon345, mourix
*
* Copyright 2024 Cacodemon345

2
src/device/nec_mate_unk.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the NEC Mate NX MA30D/23D Unknown Readout.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020-2023 Miran Grca.

2
src/device/novell_cardkey.c
View File

@@ -9,12 +9,10 @@
* Implementation of the Novell NetWare 2.x Key Card, which
* was used for anti-piracy protection.
*
*
* Authors: Cacodemon345
*
* Copyright 2024 Cacodemon345.
*/
#include <stdint.h>
#include <stdlib.h>
#include <stdio.h>

3
src/device/pci_bridge.c
View File

@@ -8,13 +8,10 @@
*
* Implementation of PCI-PCI and host-AGP bridges.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>

32
src/device/phoenix_486_jumper.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of the Phoenix 486 Jumper Readout.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Tiseno100,
*
@@ -42,6 +40,18 @@
Bit 0 = ????.
*/
/*
PB600 bit meanings:
Bit 7 = ???? (if 1 BIOS throws beep codes and won't POST)
Bit 6 = Super I/O chip: 1 = disabled, 0 = enabled
Bit 5 = ????
Bit 4 = ????
Bit 3 = ????
Bit 2 = ????
Bit 1 = Quick Boot: 1 = normal boot, 0 = quick boot/skip POST
Bit 0 = ????
*/
typedef struct phoenix_486_jumper_t {
uint8_t type;
uint8_t jumper;
@@ -72,6 +82,8 @@ phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
if (dev->type == 1)
dev->jumper = val & 0xbf;
else if (dev->type == 2) /* PB600 */
dev->jumper = ((val & 0xbf) | 0x02);
else
dev->jumper = val;
}
@@ -92,6 +104,8 @@ phoenix_486_jumper_reset(void *priv)
if (dev->type == 1)
dev->jumper = 0x00;
else if (dev->type == 2) /* PB600 */
dev->jumper = 0x02;
else {
dev->jumper = 0x9f;
if (gfxcard[0] != 0x01)
@@ -148,3 +162,17 @@ const device_t phoenix_486_jumper_pci_device = {
.force_redraw = NULL,
.config = NULL
};
const device_t phoenix_486_jumper_pci_pb600_device = {
.name = "Phoenix 486 Jumper Readout (PB600)",
.internal_name = "phoenix_486_jumper_pci_pb600",
.flags = 0,
.local = 2,
.init = phoenix_486_jumper_init,
.close = phoenix_486_jumper_close,
.reset = phoenix_486_jumper_reset,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};

2
src/device/postcard.c
View File

@@ -8,8 +8,6 @@
*
* Implementation of a port 80h POST diagnostic card.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

2
src/device/serial.c
View File

@@ -10,8 +10,6 @@
*
* Now passes all the AMIDIAG tests.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*

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