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Merge branch 'master' into tandy-shake

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This commit is contained in:
pixel-jupiter
2025-09-30 15:41:02 +03:00
parent 3e7b3d32e8 c35bb9749f
commit 49a3eca742
399 changed files with 26924 additions and 18317 deletions
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2
src/video/agpgart.c
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@@ -8,8 +8,6 @@
*
* AGP Graphics Address Remapping Table remapping emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2021 RichardG.

2
src/video/clockgen/vid_clockgen_av9194.c
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@@ -10,8 +10,6 @@
*
* Used by the S3 86c801 (V7-Mirage) card.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

2
src/video/clockgen/vid_clockgen_icd2061.c
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@@ -14,8 +14,6 @@
* Used by ET4000w32/p (Diamond Stealth 32) and the S3
* Vision964 family.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

2
src/video/clockgen/vid_clockgen_ics2494.c
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@@ -10,8 +10,6 @@
*
* Used by the AMI S3 924.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.

2
src/video/clockgen/vid_clockgen_ics2595.c
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@@ -8,8 +8,6 @@
*
* ICS2595 clock chip emulation. Used by ATI Mach64.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/nv/nv_rivatimer.c
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@@ -8,8 +8,6 @@
*
* Fast, high-frequency, CPU-independent timer.
*
*
*
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
*
* Copyright 2024-2025 starfrost

2
src/video/ramdac/vid_ramdac_ati68860.c
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@@ -28,8 +28,6 @@
* 7 If set can remove "snow" in some cases
* (A860_Delay_L ?) ??
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/ramdac/vid_ramdac_ati68875.c
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@@ -8,8 +8,6 @@
*
* Emulation of the Mach32-compatible ATI 68875 RAMDAC and clones.
*
*
*
* Authors: TheCollector1995.
*
* Copyright 2022-2023 TheCollector1995.

2
src/video/ramdac/vid_ramdac_att20c49x.c
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@@ -8,8 +8,6 @@
*
* Emulation of a AT&T 20c490/491 and 492/493 RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

2
src/video/ramdac/vid_ramdac_att2xc498.c
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@@ -8,8 +8,6 @@
*
* Emulation of a AT&T 2xc498 RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

2
src/video/ramdac/vid_ramdac_bt481.c
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@@ -9,8 +9,6 @@
* Emulation of the Brooktree BT481 true colour RAMDAC
* family.
*
*
*
* Authors: TheCollector1995.
*
* Copyright 2024 TheCollector1995.

2
src/video/ramdac/vid_ramdac_bt48x.c
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@@ -9,8 +9,6 @@
* Emulation of the Brooktree BT484-485A true colour RAMDAC
* family.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995,
*

2
src/video/ramdac/vid_ramdac_ibm_rgb528.c
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@@ -8,8 +8,6 @@
*
* Emulation of the IBM RGB 528 true colour RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2020 Miran Grca.

2
src/video/ramdac/vid_ramdac_sc1148x.c
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@@ -10,8 +10,6 @@
*
* Used by the S3 911 and 924 chips.
*
*
*
* Authors: TheCollector1995, <mariogplayer90@gmail.com>
*
* Copyright 2020 TheCollector1995.

2
src/video/ramdac/vid_ramdac_sc1502x.c
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@@ -10,8 +10,6 @@
*
* Used by the TLIVESA1 driver for ET4000.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/ramdac/vid_ramdac_sdac.c
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@@ -8,8 +8,6 @@
*
* 87C716 'SDAC' true colour RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/ramdac/vid_ramdac_stg1702.c
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@@ -8,8 +8,6 @@
*
* STG1702 true colour RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/ramdac/vid_ramdac_tkd8001.c
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@@ -8,8 +8,6 @@
*
* Trident TKD8001 RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

1
src/video/ramdac/vid_ramdac_tvp3026.c
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@@ -9,7 +9,6 @@
* Emulation of the Texas Instruments TVP3026 true colour RAMDAC
* family.
*
*
* TODO: Clock and other parts.
*
* Authors: TheCollector1995,

2
src/video/vid_8514a.c
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@@ -9,8 +9,6 @@
* Emulation of the 8514/A card from IBM for the MCA bus and
* ISA bus clones.
*
*
*
* Authors: TheCollector1995.
*
* Copyright 2022-2024 TheCollector1995.

2
src/video/vid_ati18800.c
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@@ -8,8 +8,6 @@
*
* ATI 18800 emulation (VGA Edge-16)
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_ati28800.c
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@@ -8,8 +8,6 @@
*
* ATI 28800 emulation (VGA Charger and Korean VGA)
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* greatpsycho,

2
src/video/vid_ati_eeprom.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the EEPROM on select ATI cards.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

338
src/video/vid_ati_mach64.c
View File

@@ -8,8 +8,6 @@
*
* ATi Mach64 graphics card emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
@@ -41,6 +39,7 @@
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/bswap.h>
#ifdef CLAMP
# undef CLAMP
@@ -82,6 +81,7 @@ enum {
typedef struct mach64_t {
mem_mapping_t linear_mapping;
mem_mapping_t mmio_mapping;
mem_mapping_t linear_mapping_big_endian;
mem_mapping_t mmio_linear_mapping;
mem_mapping_t mmio_linear_mapping_2;
@@ -100,6 +100,8 @@ typedef struct mach64_t {
uint8_t pci_slot;
uint8_t irq_state;
uint8_t on_board;
uint8_t pci_regs[256];
uint8_t int_line;
@@ -274,7 +276,7 @@ typedef struct mach64_t {
uint32_t cur_clr0;
uint32_t cur_clr1;
uint32_t overlay_dat[1024];
uint32_t overlay_dat[2048];
uint32_t overlay_graphics_key_clr;
uint32_t overlay_graphics_key_msk;
uint32_t overlay_video_key_clr;
@@ -288,12 +290,17 @@ typedef struct mach64_t {
uint32_t scaler_height_width;
int scaler_format;
int scaler_update;
int scaler_yuv_aper;
uint32_t buf_offset[2];
uint32_t buf_pitch[2];
int overlay_v_acc;
uint32_t overlay_uv_addr;
uint32_t overlay_cur_y;
uint32_t overlay_base;
uint8_t thread_run;
void *i2c;
void *ddc;
@@ -383,6 +390,9 @@ void mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv);
void mach64_ext_writew(uint32_t addr, uint16_t val, void *priv);
void mach64_ext_writel(uint32_t addr, uint32_t val, void *priv);
uint8_t mach64_readb_be(uint32_t addr, void *priv);
void mach64_writeb_be(uint32_t addr, uint8_t val, void *priv);
#ifdef ENABLE_MACH64_LOG
int mach64_do_log = ENABLE_MACH64_LOG;
@@ -593,6 +603,7 @@ mach64_updatemapping(mach64_t *mach64)
mach64_log("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->linear_mapping_big_endian);
mem_mapping_disable(&mach64->mmio_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping_2);
@@ -647,14 +658,16 @@ mach64_updatemapping(mach64_t *mach64)
}
} else {
/*2*8 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x4000), 0x4000);
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 4096);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 4096), 4096);
mem_mapping_set_addr(&mach64->linear_mapping_big_endian, mach64->linear_base + (8 << 20), (8 << 20) - 0x1000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x1000), 0x1000);
}
} else {
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping_2);
mem_mapping_disable(&mach64->linear_mapping_big_endian);
}
}
@@ -2312,8 +2325,11 @@ mach64_vblank_start(svga_t *svga)
svga->overlay.ena = (mach64->overlay_scale_cntl & OVERLAY_EN) && (overlay_cmp_mix != 1);
mach64->overlay_v_acc = 0;
mach64->scaler_update = 1;
mach64->overlay_v_acc = 0;
mach64->scaler_update = 1;
mach64->overlay_uv_addr = svga->overlay.addr;
mach64->overlay_cur_y = 0;
mach64->overlay_base = svga->overlay.addr;
}
uint8_t
@@ -2391,6 +2407,10 @@ mach64_ext_readb(uint32_t addr, void *priv)
case 0x4a:
ret = mach64->scaler_format;
break;
case 0x4b:
ret = mach64->scaler_yuv_aper;
break;
default:
ret = 0xff;
@@ -2560,7 +2580,7 @@ mach64_ext_readb(uint32_t addr, void *priv)
case 0xc7:
READ8(addr, mach64->dac_cntl);
if (mach64->type == MACH64_VT2) {
if (mach64->type >= MACH64_VT2) {
ret &= 0xf9;
if (i2c_gpio_get_scl(mach64->i2c))
ret |= 0x04;
@@ -2959,7 +2979,8 @@ mach64_ext_readw(uint32_t addr, void *priv)
if (!(addr & 0x400)) {
mach64_log("mach64_ext_readw: addr=%04x\n", addr);
ret = 0xffff;
ret = mach64_ext_readb(addr, priv);
ret |= mach64_ext_readb(addr + 1, priv) << 8;
} else
switch (addr & 0x3ff) {
case 0xb4:
@@ -2988,7 +3009,8 @@ mach64_ext_readl(uint32_t addr, void *priv)
if (!(addr & 0x400)) {
mach64_log("mach64_ext_readl: addr=%04x\n", addr);
ret = 0xffffffff;
ret = mach64_ext_readw(addr, priv);
ret |= mach64_ext_readw(addr + 2, priv) << 16;
} else
switch (addr & 0x3ff) {
case 0x18:
@@ -3089,6 +3111,10 @@ mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv)
case 0x4a:
mach64->scaler_format = val & 0xf;
break;
case 0x4b:
mach64->scaler_yuv_aper = val;
break;
case 0x80:
case 0x81:
@@ -4108,76 +4134,113 @@ mach64_int_hwcursor_draw(svga_t *svga, int displine)
} \
} while (0)
#define DECODE_VYUY422() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
y1 = src[0]; \
u = src[1] - 0x80; \
y2 = src[2]; \
v = src[3] - 0x80; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \
} \
#define DECODE_VYUY422() \
do { \
for (x = 0; x < src_w; x += 1) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
y1 = src[0]; \
u = src[1] - 0x80; \
y2 = src[2]; \
v = src[3] - 0x80; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_YVYU422() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
u = src[0] - 0x80; \
y1 = src[1]; \
v = src[2] - 0x80; \
y2 = src[3]; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \
} \
#define DECODE_YVYU422() \
do { \
for (x = 0; x < src_w; x += 1) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
u = src[0] - 0x80; \
y1 = src[1]; \
v = src[2] - 0x80; \
y2 = src[3]; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_YUV12_PACKED() \
do { \
for (x = 0; x < src_w; x += 1) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
u = uvsrc[3] - 0x80; \
y1 = src[0]; \
v = uvsrc[2] - 0x80; \
y2 = src[1]; \
src += 4; \
uvsrc += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x * 2] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[(x * 2) + 1] = (r << 16) | (g << 8) | b; \
} \
} while (0)
void
@@ -4187,11 +4250,13 @@ mach64_overlay_draw(svga_t *svga, int displine)
int x;
int h_acc = 0;
int h_max = (mach64->scaler_height_width >> 16) & 0x3ff;
int src_w = h_max;
int h_inc = mach64->overlay_scale_inc >> 16;
int v_max = mach64->scaler_height_width & 0x3ff;
int v_inc = mach64->overlay_scale_inc & 0xffff;
uint32_t *p;
uint8_t *src = &svga->vram[svga->overlay.addr];
uint8_t *uvsrc = src;
int old_y = mach64->overlay_v_acc;
int y_diff;
int video_key_fn = mach64->overlay_key_cntl & 5;
@@ -4200,6 +4265,11 @@ mach64_overlay_draw(svga_t *svga, int displine)
p = &buffer32->line[displine][svga->x_add + mach64->svga.overlay_latch.x];
if (mach64->overlay_cur_y >= 2) {
/* Avoid corrupt UV data on YUV12 packed modes */
uvsrc = &svga->vram[mach64->overlay_base + svga->overlay.pitch * 2 * (!(mach64->overlay_cur_y & 1) ? (mach64->overlay_cur_y + 1) : mach64->overlay_cur_y)];
}
if (mach64->scaler_update) {
switch (mach64->scaler_format) {
case 0x3:
@@ -4211,6 +4281,9 @@ mach64_overlay_draw(svga_t *svga, int displine)
case 0x6:
DECODE_ARGB8888();
break;
case 0xa:
DECODE_YUV12_PACKED();
break;
case 0xb:
DECODE_VYUY422();
break;
@@ -4219,7 +4292,7 @@ mach64_overlay_draw(svga_t *svga, int displine)
break;
default:
mach64_log("Unknown Mach64 scaler format %x\n", mach64->scaler_format);
pclog("Unknown Mach64 scaler format %x\n", mach64->scaler_format);
/*Fill buffer with something recognisably wrong*/
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++)
mach64->overlay_dat[x] = 0xff00ff;
@@ -4356,6 +4429,7 @@ mach64_overlay_draw(svga_t *svga, int displine)
svga->overlay.addr += svga->overlay.pitch * 2 * y_diff;
mach64->scaler_update = y_diff;
mach64->overlay_cur_y += y_diff;
}
static void
@@ -4391,7 +4465,7 @@ mach64_io_remove(mach64_t *mach64)
io_removehandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
io_removehandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
io_removehandler(mach64->block_decoded_io, 0x0100, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
}
static void
@@ -4431,7 +4505,7 @@ mach64_io_set(mach64_t *mach64)
io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (mach64->use_block_decoded_io && mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
io_sethandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
io_sethandler(mach64->block_decoded_io, 0x0100, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
}
static uint8_t
@@ -4480,7 +4554,6 @@ static void
mach64_write_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_b;
addr &= svga->decode_mask;
@@ -4509,10 +4582,38 @@ mach64_writew_linear(uint32_t addr, uint16_t val, void *priv)
static void
mach64_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
svga_t *svga = (svga_t *) priv;
mach64_t *mach64 = (mach64_t *) svga->priv;
cycles -= svga->monitor->mon_video_timing_write_l;
if (((mach64->scaler_yuv_aper >> 4) & 0xc) && !!(addr & 0x800000) == !(mach64->scaler_yuv_aper & 0x20)) {
uint32_t offset_from_base = addr & 0x7FFFFF;
if (addr & 0x800000) bswap32s(&val);
if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x4) { // Y plane
offset_from_base <<= 1;
svga->vram[offset_from_base & svga->vram_mask] = (val & 0xFF);
svga->vram[(offset_from_base + 1) & svga->vram_mask] = ((val >> 8) & 0xFF);
svga->vram[(offset_from_base + 4) & svga->vram_mask] = ((val >> 16) & 0xFF);
svga->vram[(offset_from_base + 5) & svga->vram_mask] = ((val >> 24) & 0xFF);
}
else if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x8 || ((mach64->scaler_yuv_aper >> 4) & 0xc) == 0xc) {
offset_from_base <<= 2;
if (((mach64->scaler_yuv_aper >> 4) & 0xc) == 0x8) { // U plane
svga->vram[(offset_from_base + 3) & svga->vram_mask] = (val & 0xFF);
svga->vram[(offset_from_base + 7) & svga->vram_mask] = ((val >> 8) & 0xFF);
svga->vram[(offset_from_base + 11) & svga->vram_mask] = ((val >> 16) & 0xFF);
svga->vram[(offset_from_base + 15) & svga->vram_mask] = ((val >> 24) & 0xFF);
} else { // V plane
svga->vram[(offset_from_base + 2) & svga->vram_mask] = (val & 0xFF);
svga->vram[(offset_from_base + 6) & svga->vram_mask] = ((val >> 8) & 0xFF);
svga->vram[(offset_from_base + 10) & svga->vram_mask] = ((val >> 16) & 0xFF);
svga->vram[(offset_from_base + 14) & svga->vram_mask] = ((val >> 24) & 0xFF);
}
}
return;
}
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
@@ -4521,6 +4622,42 @@ mach64_writel_linear(uint32_t addr, uint32_t val, void *priv)
*(uint32_t *) &svga->vram[addr] = val;
}
uint8_t
mach64_readb_be(uint32_t addr, void *priv)
{
return mach64_read_linear(addr, priv);
}
uint16_t
mach64_readw_be(uint32_t addr, void *priv)
{
return bswap16(mach64_readw_linear(addr, priv));
}
uint32_t
mach64_readl_be(uint32_t addr, void *priv)
{
return bswap32(mach64_readl_linear(addr, priv));
}
void
mach64_writeb_be(uint32_t addr, uint8_t val, void *priv)
{
return mach64_write_linear(addr, val, priv);
}
void
mach64_writew_be(uint32_t addr, uint16_t val, void *priv)
{
return mach64_writew_linear(addr, bswap16(val), priv);
}
void
mach64_writel_be(uint32_t addr, uint32_t val, void *priv)
{
return mach64_writel_linear(addr, bswap32(val), priv);
}
uint8_t
mach64_pci_read(UNUSED(int func), int addr, void *priv)
{
@@ -4566,30 +4703,31 @@ mach64_pci_read(UNUSED(int func), int addr, void *priv)
return mach64->linear_base >> 24;
case 0x14:
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
return 0x01; /*Block decoded IO address*/
return 0x00;
case 0x15:
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
return mach64->block_decoded_io >> 8;
return 0x00;
case 0x16:
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
return mach64->block_decoded_io >> 16;
return 0x00;
case 0x17:
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
return mach64->block_decoded_io >> 24;
return 0x00;
case 0x30:
return mach64->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
return (mach64->on_board) ? 0 : (mach64->pci_regs[0x30] & 0x01); /*BIOS ROM address*/
case 0x31:
return 0x00;
case 0x32:
return mach64->pci_regs[0x32];
return (mach64->on_board) ? 0 : mach64->pci_regs[0x32];
case 0x33:
return mach64->pci_regs[0x33];
return (mach64->on_board) ? 0 : mach64->pci_regs[0x33];
case 0x3c:
return mach64->int_line;
@@ -4621,7 +4759,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
break;
case 0x12:
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
val = 0;
mach64->linear_base = (mach64->linear_base & 0xff000000) | ((val & 0x80) << 16);
mach64_updatemapping(mach64);
@@ -4632,16 +4770,16 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
break;
case 0x15:
if (mach64->type == MACH64_VT2) {
if (mach64->type >= MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0xffff0000) | ((val & 0xfc) << 8);
mach64->block_decoded_io = (mach64->block_decoded_io & 0xffff0000) | ((val & 0xff) << 8);
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
}
break;
case 0x16:
if (mach64->type == MACH64_VT2) {
if (mach64->type >= MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0xff00fc00) | (val << 16);
@@ -4650,7 +4788,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
}
break;
case 0x17:
if (mach64->type == MACH64_VT2) {
if (mach64->type >= MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0x00fffc00) | (val << 24);
@@ -4662,6 +4800,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
case 0x30:
case 0x32:
case 0x33:
if (mach64->on_board) return;
mach64->pci_regs[addr] = val;
if (mach64->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (mach64->pci_regs[0x32] << 16) | (mach64->pci_regs[0x33] << 24);
@@ -4681,7 +4820,7 @@ mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->io_base = val & 0x03;
if (mach64->type == MACH64_VT2)
if (mach64->type >= MACH64_VT2)
mach64->use_block_decoded_io = val & 0x04;
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
@@ -4702,7 +4841,7 @@ mach64_common_init(const device_t *info)
svga = &mach64->svga;
mach64->type = info->local & 0xff;
mach64->vram_size = device_get_config_int("memory");
mach64->vram_size = (info->local & (1 << 20)) ? 4 : device_get_config_int("memory");
mach64->vram_mask = (mach64->vram_size << 20) - 1;
if (mach64->type > MACH64_GX)
@@ -4719,9 +4858,10 @@ mach64_common_init(const device_t *info)
mach64_overlay_draw);
mem_mapping_add(&mach64->linear_mapping, 0, 0, mach64_read_linear, mach64_readw_linear, mach64_readl_linear, mach64_write_linear, mach64_writew_linear, mach64_writel_linear, NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&mach64->linear_mapping_big_endian, 0, 0, mach64_readb_be, mach64_readw_be, mach64_readl_be, mach64_writeb_be, mach64_writew_be, mach64_writel_be, NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_add(&mach64->mmio_linear_mapping_2, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_add(&mach64->mmio_mapping, 0xbf000, 0x1000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_disable(&mach64->mmio_mapping);
mach64_io_set(mach64);

2
src/video/vid_ati_mach8.c
View File

@@ -9,8 +9,6 @@
* Emulation of the 8514/A-compatible Mach8 and Mach32 graphics
* chips from ATI for the ISA/VLB/MCA/PCI buses.
*
*
*
* Authors: TheCollector1995.
*
* Copyright 2022-2024 TheCollector1995.

1
src/video/vid_bochs_vbe.c
View File

@@ -23,7 +23,6 @@
*
* See https://gitlab.freedesktop.org/xorg/lib/libxcvt/-/blob/master/COPYING for libxcvt license details
*/
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>

2
src/video/vid_cga_colorplus.c
View File

@@ -8,8 +8,6 @@
*
* Plantronics ColorPlus emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_cga_comp.c
View File

@@ -9,8 +9,6 @@
* IBM CGA composite filter, borrowed from reenigne's DOSBox
* patch and ported to C.
*
*
*
* Authors: reenigne,
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_cga_compaq.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the Compaq CGA graphics cards.
*
*
*
* Authors: John Elliott, <jce@seasip.info>
* Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>

2
src/video/vid_cga_compaq_plasma.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the plasma displays on early Compaq Portables and laptops.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

3
src/video/vid_cga_ncr.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the NCR NGA (K511, K201) video cards.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -20,7 +18,6 @@
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2020 EngiNerd.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>

3
src/video/vid_cga_olivetti.c
View File

@@ -9,8 +9,6 @@
* Emulation of the Olivetti OGC 8-bit ISA (GO708) and
* M21/M24/M28 16-bit bus (GO317/318/380/709) video cards.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
@@ -21,7 +19,6 @@
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2020 EngiNerd.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>

2
src/video/vid_cga_toshiba_t1000.c
View File

@@ -9,8 +9,6 @@
* Implementation of the Toshiba T1000 plasma display, which
* has a fixed resolution of 640x200 pixels.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>

2
src/video/vid_cga_toshiba_t3100e.c
View File

@@ -22,8 +22,6 @@
* 61 50 52 0F 19 06 19 19 02 0D 0B 0C MONO
* 2D 28 22 0A 67 00 64 67 02 03 06 07 640x400
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>

2
src/video/vid_chips_69000.c
View File

@@ -8,8 +8,6 @@
*
* C&T 69000 emulation.
*
*
*
* Authors: Cacodemon345
*
* Copyright 2023-2024 Cacodemon345

4
src/video/vid_cl54xx.c
View File

@@ -9,8 +9,6 @@
* Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* tonioni,
* TheCollector1995,
@@ -4339,7 +4337,7 @@ gd54xx_init(const device_t *info)
case CIRRUS_ID_CLGD5436:
if ((info->local & 0x200) &&
!strstr(machine_get_internal_name(), "sb486pv")) {
(machines[machine].init != machine_at_sb486pv_init)) {
romfn = NULL;
gd54xx->has_bios = 0;
} else

2
src/video/vid_ddc.c
View File

@@ -8,8 +8,6 @@
*
* DDC monitor emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
* Copyright 2020 RichardG.

3
src/video/vid_ddc_edid_custom.c
View File

@@ -8,15 +8,12 @@
*
* Custom monitor EDID file loader.
*
*
*
* Authors: Cacodemon345,
* David Hrdlička, <hrdlickadavid@outlook.com>
*
* Copyright 2025 Cacodemon.
* Copyright 2025 David Hrdlička.
*/
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>

2
src/video/vid_ega.c
View File

@@ -9,8 +9,6 @@
* Emulation of the EGA and Chips & Technologies SuperEGA
* graphics cards.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_ega_render.c
View File

@@ -8,8 +8,6 @@
*
* EGA renderers.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_et3000.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the Tseng Labs ET3000.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.

2
src/video/vid_et4000.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the Tseng Labs ET4000.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* GreatPsycho, <greatpsycho@yahoo.com>

2
src/video/vid_et4000w32.c
View File

@@ -10,8 +10,6 @@
*
* Known bugs: Accelerator doesn't work in planar modes
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_genius.c
View File

@@ -8,8 +8,6 @@
*
* MDSI Genius VHR emulation.
*
*
*
* Authors: John Elliott, <jce@seasip.info>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_hercules.c
View File

@@ -8,8 +8,6 @@
*
* Hercules emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_hercules_incolor.c
View File

@@ -8,8 +8,6 @@
*
* Hercules InColor emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_hercules_plus.c
View File

@@ -8,8 +8,6 @@
*
* Hercules Plus emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_ht216.c
View File

@@ -8,8 +8,6 @@
*
* Video 7 VGA 1024i emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_im1024.c
View File

@@ -38,8 +38,6 @@
* This is implemented by holding a FIFO of unlimited depth in
* the IM1024 to receive the data.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* John Elliott, <jce@seasip.info>
*

2
src/video/vid_mda.c
View File

@@ -8,8 +8,6 @@
*
* IBM Monochrome Display and Printer Adapter emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Connor Hyde, <mario64crashed@gmail.com>

6
src/video/vid_mga.c
View File

@@ -8,8 +8,6 @@
*
* Matrox MGA graphics card emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.
@@ -3753,10 +3751,10 @@ blit_iload_iload(mystique_t *mystique, uint32_t data, int size)
case MACCESS_PWIDTH_24:
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t old_dst = *((uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]);
uint32_t old_dst = AS_U32(svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]);
dst = bitop(data64, old_dst, mystique->dwgreg.dwgctrl_running);
*((uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]) = (dst & 0xffffff) | (old_dst & 0xff000000);
AS_U32(svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]) = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount;
}

2
src/video/vid_oak_oti.c
View File

@@ -8,8 +8,6 @@
*
* Oak OTI037C/67/077 emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_paradise.c
View File

@@ -10,8 +10,6 @@
* PC2086, PC3086 use PVGA1A
* MegaPC uses W90C11A
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_pcjr.c
View File

@@ -8,7 +8,6 @@
*
* IBM PCjr video subsystem emulation
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Connor Hyde / starfrost <mario64crashed@gmail.com>
@@ -18,7 +17,6 @@
* Copyright 2017-2019 Fred N. van Kempen.
* Copyright 2025 starfrost
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>

2
src/video/vid_pgc.c
View File

@@ -44,8 +44,6 @@
*
* This is expected to be done shortly.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* John Elliott, <jce@seasip.info>
*

29
src/video/vid_ps55da2.c
View File

@@ -22,7 +22,6 @@
*
* Copyright 2024-2025 Akamaki.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
@@ -96,20 +95,20 @@
#define DA2_POSID_L 0xfe
/*
[Identification]
POS ID SYS ID
EFFFh * Display Adapter (PS/55 Model 5571-S0A) [Toledo]
E013h * Layout Display Terminal (PS/55-5571 RPQ model) [LDT]
EFFEh * Display Adapter II (I/O 3E0:0A = xx0x xxxx) [Atlas]
|- FFF2h Display Adapter B2 (I/O 3E0:0A = xx1x xxxx) (PS/55 Model 5530Z-SX)
|- FDFEh Display Adapter B2 (I/O 3E0:0A = xx1x xxxx) (PS/55 Model 5550-V2)
|- * Display Adapter III,V (I/O 3E0:0A = xx1x xxxx)
ECECh FF4Fh Display Adapter B1 (PS/55 Model 5531Z-SX) [Atlas-KENT]
|- * Display Adapter IV
ECCEh * Display Adapter IV
901Fh * Display Adapter A2
901Dh * Display Adapter A1 [Atlas II]
901Eh * Plasma Display Adapter
EFD8h * Display Adapter/J [Atlas-SP2]
POS ID SYS ID
EFFFh * Display Adapter (PS/55 Model 5571-S0A) [Toledo]
E013h * Layout Display Terminal (PS/55-5571 RPQ model) [LDT]
EFFEh * Display Adapter II (I/O 3E0:0A = xx0x xxxx) [Atlas]
|- FFF2h Display Adapter B2 (I/O 3E0:0A = xx1x xxxx) (PS/55 Model 5530Z-SX)
|- FDFEh Display Adapter B2 (I/O 3E0:0A = xx1x xxxx) (PS/55 Model 5550-V2)
|- * Display Adapter III,V (I/O 3E0:0A = xx1x xxxx)
ECECh FF4Fh Display Adapter B1 (PS/55 Model 5531Z-SX) [Atlas-KENT]
|- * Display Adapter IV
ECCEh * Display Adapter IV
901Fh * Display Adapter A2
901Dh * Display Adapter A1 [Atlas II]
901Eh * Plasma Display Adapter
EFD8h * Display Adapter/J [Atlas-SP2]
[Japanese DOS and Display Adapter compatibility]
| | | 5605JBK | 5605PAA | 5605PCA | 5605PDE | 5605PAW | 5605PXB |

2
src/video/vid_rtg310x.c
View File

@@ -8,8 +8,6 @@
*
* Emulation of the Realtek RTG series of VGA ISA chips.
*
*
*
* Authors: TheCollector1995, <mariogplayer90@gmail.com>
*
* Copyright 2021 TheCollector1995.

5
src/video/vid_s3.c
View File

@@ -8,8 +8,6 @@
*
* S3 emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
@@ -530,9 +528,8 @@ s3_queue(s3_t *s3, uint32_t addr, uint32_t val, uint32_t type)
if (FIFO_FULL) {
thread_reset_event(s3->fifo_not_full_event);
if (FIFO_FULL) {
if (FIFO_FULL)
thread_wait_event(s3->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
}
fifo->val = val;

26
src/video/vid_s3_virge.c
View File

@@ -8,8 +8,6 @@
*
* S3 ViRGE emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
@@ -1954,9 +1952,9 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv)
break;
case 0x8190:
virge->streams.sec_ctrl = val;
virge->streams.dda_horiz_accumulator = val & 0xfff;
if (val & 0x1000)
virge->streams.dda_horiz_accumulator |= ~0xfff;
virge->streams.dda_horiz_accumulator = val & 0x7ff;
if (val & 0x800)
virge->streams.dda_horiz_accumulator |= ~0x7ff;
virge->streams.sdif = (val >> 24) & 7;
break;
@@ -1969,9 +1967,9 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv)
if (val & 0x800)
virge->streams.k1_horiz_scale |= ~0x7ff;
virge->streams.k2_horiz_scale = (val >> 16) & 0x7ff;
if ((val >> 16) & 0x800)
virge->streams.k2_horiz_scale |= ~0x7ff;
virge->streams.k2_horiz_scale = (val >> 16) & 0x3ff;
if ((val >> 16) & 0x400)
virge->streams.k2_horiz_scale |= ~0x3ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
@@ -2027,14 +2025,14 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv)
virge->streams.k1_vert_scale |= ~0x7ff;
break;
case 0x81e4:
virge->streams.k2_vert_scale = val & 0x7ff;
if (val & 0x800)
virge->streams.k2_vert_scale |= ~0x7ff;
virge->streams.k2_vert_scale = val & 0x3ff;
if (val & 0x400)
virge->streams.k2_vert_scale |= ~0x3ff;
break;
case 0x81e8:
virge->streams.dda_vert_accumulator = val & 0xfff;
if (val & 0x1000)
virge->streams.dda_vert_accumulator |= ~0xfff;
virge->streams.dda_vert_accumulator = val & 0x7ff;
if (val & 0x800)
virge->streams.dda_vert_accumulator |= ~0x7ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;

2
src/video/vid_sigma.c
View File

@@ -8,8 +8,6 @@
*
* Sigma Color 400 emulation.
*
*
*
* Authors: John Elliott,
*
* Copyright 2018 John Elliott.

2
src/video/vid_svga.c
View File

@@ -11,8 +11,6 @@
* This is intended to be used by another SVGA driver,
* and not as a card in its own right.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

6
src/video/vid_svga_render.c
View File

@@ -8,8 +8,6 @@
*
* SVGA renderers.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
@@ -157,7 +155,7 @@ svga_render_text_40(svga_t *svga)
svga->lastline_draw = svga->displine;
if (svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
p = &svga->monitor->target_buffer->line[(svga->displine + svga->y_add) & 2047][(svga->x_add) & 2047];
xinc = (svga->seqregs[1] & 1) ? 16 : 18;
for (int x = 0; x < (svga->hdisp + svga->scrollcache); x += xinc) {
@@ -240,7 +238,7 @@ svga_render_text_80(svga_t *svga)
svga->lastline_draw = svga->displine;
if (svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
p = &svga->monitor->target_buffer->line[(svga->displine + svga->y_add) & 2047][(svga->x_add) & 2047];
xinc = (svga->seqregs[1] & 1) ? 8 : 9;
static uint32_t col = 0x00000000;

2
src/video/vid_table.c
View File

@@ -8,8 +8,6 @@
*
* Define all known video cards.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*

2
src/video/vid_tandy.c
View File

@@ -8,8 +8,6 @@
*
* Tandy 1000 video emulation
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Connor Hyde / starfrost, <mario64crashed@gmail.com>

2
src/video/vid_tgui9440.c
View File

@@ -47,8 +47,6 @@
* access size or host data has any affect, but the Windows 3.1
* driver always reads bytes and write words of 0xffff.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_ti_cf62011.c
View File

@@ -42,8 +42,6 @@
* which are the same as the XGA. It supports up to 1MB of VRAM,
* but we lock it down to 512K. The PS/1 2122 had 256K.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>

2
src/video/vid_tvga.c
View File

@@ -8,8 +8,6 @@
*
* Trident TVGA (8900D) emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_vga.c
View File

@@ -8,8 +8,6 @@
*
* IBM VGA emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

2
src/video/vid_voodoo.c
View File

@@ -8,8 +8,6 @@
*
* Voodoo Graphics, 2, Banshee, 3 emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* leilei
*

2
src/video/vid_voodoo_banshee.c
View File

@@ -8,8 +8,6 @@
*
* Voodoo Banshee and 3 specific emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

14
src/video/vid_voodoo_banshee_blitter.c
View File

@@ -1,3 +1,17 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.
*/
/*Current issues :
- missing YUV blits (YUV -> 32-bit, 24-bit, or 16-bit RGB now done)
- missing wait for vsync

2
src/video/vid_voodoo_blitter.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_display.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_fb.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_fifo.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_reg.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_render.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_setup.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_voodoo_texture.c
View File

@@ -8,8 +8,6 @@
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
*
* Copyright 2008-2020 Sarah Walker.

2
src/video/vid_wy700.c
View File

@@ -8,8 +8,6 @@
*
* Wyse-700 emulation.
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*

8
src/video/vid_xga.c
View File

@@ -8,8 +8,6 @@
*
* IBM XGA emulation.
*
*
*
* Authors: TheCollector1995.
*
* Copyright 2022 TheCollector1995.
@@ -2718,15 +2716,15 @@ xga_hwcursor_draw(svga_t *svga, int displine)
if (x >= idx) {
switch (comb) {
case 0x00:
/* Cursor Color 1 */
/* Cursor Color 1 */
p[x_pos] = xga->hwc_color0;
break;
case 0x01:
/* Cursor Color 2 */
/* Cursor Color 2 */
p[x_pos] = xga->hwc_color1;
break;
case 0x03:
/* Complement */
/* Complement */
p[x_pos] ^= 0xffffff;
break;

2
src/video/video.c
View File

@@ -40,8 +40,6 @@
* W = 3 bus clocks
* L = 4 bus clocks
*
*
*
* Authors: Sarah Walker, <https://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*