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Merge remote-tracking branch 'refs/remotes/OBattler/master'

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basic2004
2017-07-17 22:56:34 +09:00
parent 2988d5285b d3baa03d05
commit 4ac5b13a99
71 changed files with 2092 additions and 781 deletions
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4
README.md
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@@ -1,5 +1,5 @@
# 86Box [![Build Status](http://dome.rol.im/job/86Box/badge/icon)](http://dome.rol.im/job/86Box)
86Box (formerly PCem Unofficial, PCem Experimental, or PCem-X) is an unofficial branch of the PCem emulator, which aims to emulate IBM compatible machines from 1981-2000 period. This branch adds several emulated motherboards.
# 86Box [![Build Status](http://ci.86box.net/job/86Box/badge/icon)](http://ci.86box.net/job/86Box)
86Box (formerly PCem Unofficial, PCem Experimental, or PCem-X) is a fork of the PCem emulator, which aims to emulate IBM compatible machines from 1981-2000 period. This branch adds several emulated motherboards.
---
Keep in touch with the 86Box community:

32
src/CPU/386_dynarec.c
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@@ -265,6 +265,38 @@ void x86_int_sw(int num)
CPU_BLOCK_END();
}
int x86_int_sw_rm(int num)
{
uint32_t addr;
uint16_t new_pc, new_cs;
flags_rebuild();
cycles -= timing_int;
addr = num << 2;
new_pc = readmemw(0, addr);
new_cs = readmemw(0, addr + 2);
if (cpu_state.abrt) return 1;
writememw(ss,((SP-2)&0xFFFF),flags); if (cpu_state.abrt) {pclog("abrt5\n"); return 1; }
writememw(ss,((SP-4)&0xFFFF),CS);
writememw(ss,((SP-6)&0xFFFF),cpu_state.pc); if (cpu_state.abrt) {pclog("abrt6\n"); return 1; }
SP-=6;
eflags &= ~VIF_FLAG;
flags &= ~T_FLAG;
cpu_state.pc = new_pc;
loadcs(new_cs);
oxpc=cpu_state.pc;
cycles -= timing_int_rm;
trap = 0;
CPU_BLOCK_END();
return 0;
}
void x86illegal()
{
x86_int(6);

2
src/CPU/808x.c
View File

@@ -547,7 +547,7 @@ void dumpregs(int force)
if (is386)
{
printf("386 in %s mode stack in %s mode\n",(use32)?"32-bit":"16-bit",(stack32)?"32-bit":"16-bit");
printf("CR0=%08X CR2=%08X CR3=%08X\n",cr0,cr2,cr3);
printf("CR0=%08X CR2=%08X CR3=%08X CR4=%08x\n",cr0,cr2,cr3, cr4);
}
printf("Entries in readlookup : %i writelookup : %i\n",readlnum,writelnum);
for (c=0;c<1024*1024;c++)

4
src/CPU/codegen_ops_misc.h
View File

@@ -16,11 +16,15 @@ static uint32_t ropSTD(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
static uint32_t ropCLI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
return 0;
CLEAR_BITS((uintptr_t)&flags, I_FLAG);
return op_pc;
}
static uint32_t ropSTI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
if (!IOPLp && (cr4 & (CR4_VME | CR4_PVI)))
return 0;
SET_BITS((uintptr_t)&flags, I_FLAG);
return op_pc;
}

61
src/CPU/cpu.c
View File

@@ -71,6 +71,8 @@ OpFn *x86_opcodes_df_a32;
enum
{
CPUID_FPU = (1 << 0),
CPUID_VME = (1 << 1),
CPUID_PSE = (1 << 3),
CPUID_TSC = (1 << 4),
CPUID_MSR = (1 << 5),
CPUID_CMPXCHG8B = (1 << 8),
@@ -90,6 +92,7 @@ int cpu_busspeed;
int cpu_hasrdtsc;
int cpu_hasMMX, cpu_hasMSR;
int cpu_hasCR4;
int cpu_hasVME;
int cpu_use_dynarec;
int cpu_cyrix_alignment;
@@ -365,8 +368,8 @@ CPU cpus_i486[] =
{"i486DX2/40", CPU_i486DX, 4, 40000000, 2, 20000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"i486DX2/50", CPU_i486DX, 5, 50000000, 2, 25000000, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 8,8,6,6},
{"i486DX2/66", CPU_i486DX, 6, 66666666, 2, 33333333, 0x430, 0, 0, CPU_SUPPORTS_DYNAREC, 12,12,6,6},
{"iDX4/75", CPU_i486DX, 7, 75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_i486DX,10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"iDX4/75", CPU_iDX4, 7, 75000000, 3, 25000000, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 12,12,9,9}, /*CPUID available on DX4, >= 75 MHz*/
{"iDX4/100", CPU_iDX4, 10, 100000000, 3, 33333333, 0x481, 0x481, 0, CPU_SUPPORTS_DYNAREC, 18,18,9,9}, /*Is on some real Intel DX2s, limit here is pretty arbitary*/
{"Pentium OverDrive/63", CPU_PENTIUM, 6, 62500000, 3, 25000000, 0x1531, 0x1531, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 10,10,7,7},
{"Pentium OverDrive/83", CPU_PENTIUM, 8, 83333333, 3, 33333333, 0x1532, 0x1532, 0, CPU_SUPPORTS_DYNAREC | CPU_REQUIRES_DYNAREC, 15,15,8,8},
{"", -1, 0, 0, 0}
@@ -991,6 +994,10 @@ void cpu_set()
timing_misaligned = 3;
break;
case CPU_iDX4:
cpu_hasCR4 = 1;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_VME;
case CPU_i486SX:
case CPU_i486DX:
x86_setopcodes(ops_386, ops_486_0f, dynarec_ops_386, dynarec_ops_486_0f);
@@ -1204,7 +1211,8 @@ void cpu_set()
cpu_hasMMX = 0;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_pentium);
break;
@@ -1244,7 +1252,8 @@ void cpu_set()
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_pentium);
break;
@@ -1443,7 +1452,8 @@ void cpu_set()
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_pentium);
break;
@@ -1476,7 +1486,8 @@ void cpu_set()
cpu_hasMMX = 0;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_686);
break;
@@ -1510,7 +1521,8 @@ void cpu_set()
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE;
codegen_timing_set(&codegen_timing_686);
break;
#endif
@@ -1544,7 +1556,8 @@ void cpu_set()
cpu_hasMMX = 1;
cpu_hasMSR = 1;
cpu_hasCR4 = 1;
cpu_CR4_mask = CR4_TSD | CR4_DE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
cpu_hasVME = 1;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PCE | CR4_OSFXSR;
codegen_timing_set(&codegen_timing_686);
break;
@@ -1575,6 +1588,24 @@ void cpu_CPUID()
EAX = 0;
break;
case CPU_iDX4:
if (!EAX)
{
EAX = 0x00000001;
EBX = 0x756e6547;
EDX = 0x49656e69;
ECX = 0x6c65746e;
}
else if (EAX == 1)
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME;
}
else
EAX = 0;
break;
case CPU_Am486SX:
if (!EAX)
{
@@ -1651,7 +1682,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
}
else
EAX = 0;
@@ -1739,7 +1770,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B;
}
else if (EAX == 0x80000000)
{
@@ -1750,7 +1781,7 @@ void cpu_CPUID()
{
EAX = CPUID + 0x100;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_AMDSEP;
}
else if (EAX == 0x80000002)
{
@@ -1801,7 +1832,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX;
}
else
EAX = 0;
@@ -1896,7 +1927,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_SEP | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -1917,7 +1948,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_CMOV;
}
else if (EAX == 2)
{
@@ -1941,7 +1972,7 @@ void cpu_CPUID()
{
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
}
else if (EAX == 2)
{

32
src/CPU/cpu.h
View File

@@ -44,26 +44,27 @@ extern int cpu, cpu_manufacturer;
#define CPU_i486DX 11
#define CPU_Am486DX 12
#define CPU_Cx486DX 13
#define CPU_Cx5x86 14
#define CPU_iDX4 14
#define CPU_Cx5x86 15
/*586 class CPUs*/
#define CPU_WINCHIP 15
#define CPU_PENTIUM 16
#define CPU_PENTIUMMMX 17
#define CPU_Cx6x86 18
#define CPU_Cx6x86MX 19
#define CPU_Cx6x86L 20
#define CPU_CxGX1 21
#define CPU_K5 22
#define CPU_5K86 23
#define CPU_K6 24
#define CPU_WINCHIP 16
#define CPU_PENTIUM 17
#define CPU_PENTIUMMMX 18
#define CPU_Cx6x86 19
#define CPU_Cx6x86MX 20
#define CPU_Cx6x86L 21
#define CPU_CxGX1 22
#define CPU_K5 23
#define CPU_5K86 24
#define CPU_K6 25
/*686 class CPUs*/
#define CPU_PENTIUMPRO 25
#define CPU_PENTIUMPRO 26
/*
#define CPU_PENTIUM2 26
#define CPU_PENTIUM2D 27 */
#define CPU_PENTIUM2D 26
#define CPU_PENTIUM2 27
#define CPU_PENTIUM2D 28 */
#define CPU_PENTIUM2D 27
#define MANU_INTEL 0
#define MANU_AMD 1
@@ -144,6 +145,7 @@ extern int cpu_hasrdtsc;
extern int cpu_hasMSR;
extern int cpu_hasMMX;
extern int cpu_hasCR4;
extern int cpu_hasVME;
#define CR4_TSD (1 << 2)
#define CR4_DE (1 << 3)

118
src/CPU/x86_ops_flag.h
View File

@@ -27,8 +27,16 @@ static int opCLI(uint32_t fetchdat)
{
if (!IOPLp)
{
x86gpf(NULL,0);
return 1;
if ((!(eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((eflags & VM_FLAG) && (cr4 & CR4_VME)))
{
eflags &= ~VIF_FLAG;
}
else
{
x86gpf(NULL,0);
return 1;
}
}
else
flags &= ~I_FLAG;
@@ -57,8 +65,22 @@ static int opSTI(uint32_t fetchdat)
{
if (!IOPLp)
{
x86gpf(NULL,0);
return 1;
if ((!(eflags & VM_FLAG) && (cr4 & CR4_PVI)) ||
((eflags & VM_FLAG) && (cr4 & CR4_VME)))
{
if (eflags & VIP_FLAG)
{
x86gpf(NULL,0);
return 1;
}
else
eflags |= VIF_FLAG;
}
else
{
x86gpf(NULL,0);
return 1;
}
}
else
flags |= I_FLAG;
@@ -94,11 +116,27 @@ static int opPUSHF(uint32_t fetchdat)
{
if ((eflags & VM_FLAG) && (IOPL < 3))
{
x86gpf(NULL,0);
return 1;
if (cr4 & CR4_VME)
{
uint16_t temp;
flags_rebuild();
temp = (flags & ~I_FLAG) | 0x3000;
if (eflags & VIF_FLAG)
temp |= I_FLAG;
PUSH_W(temp);
}
else
{
x86gpf(NULL,0);
return 1;
}
}
flags_rebuild();
PUSH_W(flags);
else
{
flags_rebuild();
PUSH_W(flags);
}
CLOCK_CYCLES(4);
PREFETCH_RUN(4, 1, -1, 0,0,1,0, 0);
return cpu_state.abrt;
@@ -111,8 +149,9 @@ static int opPUSHFD(uint32_t fetchdat)
x86gpf(NULL, 0);
return 1;
}
if (CPUID) tempw = eflags & 0x24;
else tempw = eflags & 4;
if (cpu_CR4_mask & CR4_VME) tempw = eflags & 0x3c;
else if (CPUID) tempw = eflags & 0x24;
else tempw = eflags & 4;
flags_rebuild();
PUSH_L(flags | (tempw << 16));
CLOCK_CYCLES(4);
@@ -151,15 +190,49 @@ static int opPOPF(uint32_t fetchdat)
if ((eflags & VM_FLAG) && (IOPL < 3))
{
x86gpf(NULL, 0);
return 1;
}
tempw = POP_W(); if (cpu_state.abrt) return 1;
if (cr4 & CR4_VME)
{
uint32_t old_esp = ESP;
if (!(CPL) || !(msw & 1)) flags = (tempw & 0x7fd5) | 2;
else if (IOPLp) flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
else flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
tempw = POP_W();
if (cpu_state.abrt)
{
ESP = old_esp;
return 1;
}
if ((tempw & T_FLAG) || ((tempw & I_FLAG) && (eflags & VIP_FLAG)))
{
ESP = old_esp;
x86gpf(NULL, 0);
return 1;
}
if (tempw & I_FLAG)
eflags |= VIF_FLAG;
else
eflags &= ~VIF_FLAG;
flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
}
else
{
x86gpf(NULL, 0);
return 1;
}
}
else
{
tempw = POP_W();
if (cpu_state.abrt)
return 1;
if (!(CPL) || !(msw & 1))
flags = (tempw & 0x7fd5) | 2;
else if (IOPLp)
flags = (flags & 0x3000) | (tempw & 0x4fd5) | 2;
else
flags = (flags & 0x3200) | (tempw & 0x4dd5) | 2;
}
flags_extract();
CLOCK_CYCLES(5);
@@ -185,11 +258,12 @@ static int opPOPFD(uint32_t fetchdat)
else if (IOPLp) flags = (flags & 0x3000) | (templ & 0x4fd5) | 2;
else flags = (flags & 0x3200) | (templ & 0x4dd5) | 2;
templ &= is486 ? 0x240000 : 0;
templ &= is486 ? 0x3c0000 : 0;
templ |= ((eflags&3) << 16);
if (CPUID) eflags = (templ >> 16) & 0x27;
else if (is486) eflags = (templ >> 16) & 7;
else eflags = (templ >> 16) & 3;
if (cpu_CR4_mask & CR4_VME) eflags = (templ >> 16) & 0x3f;
else if (CPUID) eflags = (templ >> 16) & 0x27;
else if (is486) eflags = (templ >> 16) & 7;
else eflags = (templ >> 16) & 3;
flags_extract();

64
src/CPU/x86_ops_int.h
View File

@@ -29,47 +29,39 @@ static int opINT1(uint32_t fetchdat)
static int opINT(uint32_t fetchdat)
{
int cycles_old = cycles; UNUSED(cycles_old);
uint8_t temp;
/*if (msw&1) pclog("INT %i %i %i\n",cr0&1,eflags&VM_FLAG,IOPL);*/
uint8_t temp = getbytef();
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
if (cr4 & CR4_VME)
{
uint16_t t;
uint8_t d;
cpl_override = 1;
t = readmemw(tr.base, 0x66) - 32;
cpl_override = 0;
if (cpu_state.abrt) return 1;
t += (temp >> 3);
if (t <= tr.limit)
{
cpl_override = 1;
d = readmemb(tr.base, t);// + (temp >> 3));
cpl_override = 0;
if (cpu_state.abrt) return 1;
if (!(d & (1 << (temp & 7))))
{
x86_int_sw_rm(temp);
PREFETCH_RUN(cycles_old-cycles, 2, -1, 0,0,0,0, 0);
return 1;
}
}
}
x86gpf(NULL,0);
return 1;
}
temp = getbytef();
// /*if (temp == 0x10 && AH == 0xe) */pclog("INT %02X : %04X %04X %04X %04X %c %04X:%04X\n", temp, AX, BX, CX, DX, (AL < 32) ? ' ' : AL, CS, pc);
// if (CS == 0x0028 && pc == 0xC03813C0)
// output = 3;
/* if (pc == 0x8028009A)
output = 3;
if (pc == 0x80282B6F)
{
__times++;
if (__times == 2)
fatal("WRONG\n");
}
if (pc == 0x802809CE)
fatal("RIGHT\n");*/
// if (CS == 0x0028 && pc == 0x80037FE9)
// output = 3;
//if (CS == 0x9087 && pc == 0x3763)
// fatal("Here\n");
//if (CS==0x9087 && pc == 0x0850)
// output = 1;
/* if (output && pc == 0x80033008)
{
__times++;
if (__times == 2)
fatal("WRONG\n");
}*/
/* if (output && pc == 0x80D8)
{
__times++;
if (__times == 2)
fatal("RIGHT\n");
}*/
x86_int_sw(temp);
PREFETCH_RUN(cycles_old-cycles, 2, -1, 0,0,0,0, 0);

10
src/CPU/x86_ops_pmode.h
View File

@@ -212,6 +212,9 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
access = readmemb(0, addr + 5);
granularity = readmemb(0, addr + 6) & 0x80;
if (cpu_state.abrt) return 1;
access |= 2;
writememb(0, addr + 5, access);
if (cpu_state.abrt) return 1;
tr.seg = sel;
tr.limit = limit;
tr.access = access;
@@ -365,7 +368,12 @@ static int op0F01_common(uint32_t fetchdat, int is32, int is286, int ea32)
}
tempw = geteaw(); if (cpu_state.abrt) return 1;
if (msw & 1) tempw |= 1;
if (!is386) tempw &= 0xF;
if (is386)
{
tempw &= ~0x10;
tempw |= (msw & 0x10);
}
else tempw &= 0xF;
msw = tempw;
PREFETCH_RUN(2, 2, rmdat, 0,0,(cpu_mod == 3) ? 0:1,0, ea32);
break;

80
src/CPU/x86_ops_ret.h
View File

@@ -141,35 +141,67 @@ static int opIRET(uint32_t fetchdat)
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
return 1;
}
if (msw&1)
{
optype = IRET;
pmodeiret(0);
optype = 0;
}
else
{
uint16_t new_cs;
oxpc = cpu_state.pc;
if (stack32)
if (cr4 & CR4_VME)
{
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
uint16_t new_pc, new_cs, new_flags;
new_pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
new_flags = readmemw(ss, ((SP + 4) & 0xffff));
if (cpu_state.abrt)
return 1;
if ((new_flags & T_FLAG) || ((new_flags & I_FLAG) && (eflags & VIP_FLAG)))
{
x86gpf(NULL, 0);
return 1;
}
SP += 6;
if (new_flags & I_FLAG)
eflags |= VIF_FLAG;
else
eflags &= ~VIF_FLAG;
flags = (flags & 0x3300) | (new_flags & 0x4cd5) | 2;
loadcs(new_cs);
cpu_state.pc = new_pc;
cycles -= timing_iret_rm;
}
else
{
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
SP += 6;
x86gpf(NULL,0);
return 1;
}
}
else
{
if (msw&1)
{
optype = IRET;
pmodeiret(0);
optype = 0;
}
else
{
uint16_t new_cs;
oxpc = cpu_state.pc;
if (stack32)
{
cpu_state.pc = readmemw(ss, ESP);
new_cs = readmemw(ss, ESP + 2);
flags = (readmemw(ss, ESP + 4) & 0xffd5) | 2;
ESP += 6;
}
else
{
cpu_state.pc = readmemw(ss, SP);
new_cs = readmemw(ss, ((SP + 2) & 0xffff));
flags = (readmemw(ss, ((SP + 4) & 0xffff)) & 0xffd5) | 2;
SP += 6;
}
loadcs(new_cs);
cycles -= timing_iret_rm;
}
loadcs(new_cs);
cycles -= timing_iret_rm;
}
flags_extract();
nmi_enable = 1;

261
src/CPU/x86seg.c
View File

@@ -628,8 +628,8 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
return;
}
type=segdat[2]&0xF00;
if (type==0x400) newpc=segdat[0];
else newpc=segdat[0]|(segdat[3]<<16);
newpc=segdat[0];
if (type&0x800) newpc|=segdat[3]<<16;
switch (type)
{
case 0x400: /*Call gate*/
@@ -737,6 +737,7 @@ void loadcsjmp(uint16_t seg, uint32_t oxpc)
case 0x100: /*286 Task gate*/
case 0x900: /*386 Task gate*/
cpu_state.pc=oxpc;
optype=JMP;
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
flags &= ~NT_FLAG;
@@ -874,8 +875,8 @@ void loadcscall(uint16_t seg)
segdat[2]=readmemw(0,addr+4);
segdat[3]=readmemw(0,addr+6); cpl_override=0; if (cpu_state.abrt) return;
type=segdat[2]&0xF00;
if (type==0x400) newpc=segdat[0];
else newpc=segdat[0]|(segdat[3]<<16);
newpc=segdat[0];
if (type&0x800) newpc|=segdat[3]<<16;
if (csout) pclog("Code seg call - %04X - %04X %04X %04X\n",seg,segdat[0],segdat[1],segdat[2]);
if (segdat[2]&0x1000)
@@ -900,7 +901,7 @@ void loadcscall(uint16_t seg)
}
if (!(segdat[2]&0x8000))
{
x86np("Load CS call not present", seg & 0xfffc);
x86ss("Load CS call not present", seg & 0xfffc);
return;
}
set_use32(segdat[3]&0x40);
@@ -1191,6 +1192,14 @@ void loadcscall(uint16_t seg)
}
break;
case 0x100: /*286 Task gate*/
case 0x900: /*386 Task gate*/
cpu_state.pc=oxpc;
cpl_override=1;
taskswitch286(seg,segdat,segdat[2]&0x800);
cpl_override=0;
break;
default:
x86gpf(NULL,seg&~3);
return;
@@ -1593,7 +1602,7 @@ void pmodeint(int num, int soft)
}
else
{
addr = 2 + tr.base + (DPL2 * 8);
addr = 2 + tr.base + (DPL2 * 4);
newss=readmemw(0,addr+2);
newsp=readmemw(0,addr);
}
@@ -2127,43 +2136,32 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
base=segdat[1]|((segdat[2]&0xFF)<<16);
limit=segdat[0];
if (is32)
if(is386)
{
base |= (segdat[3]>>8)<<24;
limit |= (segdat[3]&0xF)<<16;
}
new_cr3=readmeml(base,0x1C);
new_pc=readmeml(base,0x20);
new_flags=readmeml(base,0x24);
new_eax=readmeml(base,0x28);
new_ecx=readmeml(base,0x2C);
new_edx=readmeml(base,0x30);
new_ebx=readmeml(base,0x34);
new_esp=readmeml(base,0x38);
new_ebp=readmeml(base,0x3C);
new_esi=readmeml(base,0x40);
new_edi=readmeml(base,0x44);
new_es=readmemw(base,0x48);
new_cs=readmemw(base,0x4C);
new_ss=readmemw(base,0x50);
new_ds=readmemw(base,0x54);
new_fs=readmemw(base,0x58);
new_gs=readmemw(base,0x5C);
new_ldt=readmemw(base,0x60);
if (cpu_state.abrt) return;
if (optype==JMP || optype==OPTYPE_INT)
if (is32)
{
if (limit < 103)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
if (cpu_state.abrt) return;
tempw&=~0x200;
if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
else writememw(gdt.base,(tr.seg&~7)+4,tempw);
pclog("32-bit TSS %04X limit less than 103.\n", seg);
x86ts(NULL, seg);
return;
}
if (optype==JMP || optype==CALL || optype==OPTYPE_INT)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
else tempw=readmemw(gdt.base,(seg&~7)+4);
if (cpu_state.abrt) return;
tempw|=0x200;
if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
else writememw(gdt.base,(seg&~7)+4,tempw);
}
if (cpu_state.abrt) return;
if (optype==IRET) flags&=~NT_FLAG;
cpu_386_flags_rebuild();
@@ -2186,26 +2184,48 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
writememl(tr.base,0x54,DS);
writememl(tr.base,0x58,FS);
writememl(tr.base,0x5C,GS);
writememl(tr.base,0x60,ldt.seg);
if (optype==OPTYPE_INT)
if (optype==JMP || optype==IRET)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
if (cpu_state.abrt) return;
tempw&=~0x200;
if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
else writememw(gdt.base,(tr.seg&~7)+4,tempw);
}
if (cpu_state.abrt) return;
if (optype==OPTYPE_INT || optype==CALL)
{
writememl(base,0,tr.seg);
new_flags|=NT_FLAG;
}
if (cpu_state.abrt) return;
if (optype==JMP || optype==OPTYPE_INT)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
else tempw=readmemw(gdt.base,(seg&~7)+4);
if (cpu_state.abrt) return;
tempw|=0x200;
if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
else writememw(gdt.base,(seg&~7)+4,tempw);
}
new_cr3=readmeml(base,0x1C);
new_pc=readmeml(base,0x20);
new_flags=readmeml(base,0x24);
new_eax=readmeml(base,0x28);
new_ecx=readmeml(base,0x2C);
new_edx=readmeml(base,0x30);
new_ebx=readmeml(base,0x34);
new_esp=readmeml(base,0x38);
new_ebp=readmeml(base,0x3C);
new_esi=readmeml(base,0x40);
new_edi=readmeml(base,0x44);
new_es=readmemw(base,0x48);
new_cs=readmemw(base,0x4C);
new_ss=readmemw(base,0x50);
new_ds=readmemw(base,0x54);
new_fs=readmemw(base,0x58);
new_gs=readmemw(base,0x5C);
new_ldt=readmemw(base,0x60);
cr0 |= 8;
cr3=new_cr3;
flushmmucache();
@@ -2232,7 +2252,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if (!(new_cs&~3))
{
x86gpf(NULL,0);
x86ts(NULL,0);
return;
}
addr=new_cs&~7;
@@ -2240,7 +2260,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
{
if (addr>=ldt.limit)
{
x86gpf(NULL,0);
x86ts(NULL,new_cs&~3);
return;
}
addr+=ldt.base;
@@ -2249,7 +2269,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
{
if (addr>=gdt.limit)
{
x86gpf(NULL,0);
x86ts(NULL,new_cs&~3);
return;
}
addr+=gdt.base;
@@ -2268,19 +2288,19 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
case 0x1800: case 0x1900: case 0x1A00: case 0x1B00: /*Non-conforming*/
if ((new_cs&3) != DPL2)
{
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
break;
case 0x1C00: case 0x1D00: case 0x1E00: case 0x1F00: /*Conforming*/
if ((new_cs&3) < DPL2)
{
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
break;
default:
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
@@ -2313,35 +2333,24 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
}
else
{
new_pc=readmemw(base,0x0E);
new_flags=readmemw(base,0x10);
new_eax=readmemw(base,0x12);
new_ecx=readmemw(base,0x14);
new_edx=readmemw(base,0x16);
new_ebx=readmemw(base,0x18);
new_esp=readmemw(base,0x1A);
new_ebp=readmemw(base,0x1C);
new_esi=readmemw(base,0x1E);
new_edi=readmemw(base,0x20);
new_es=readmemw(base,0x22);
new_cs=readmemw(base,0x24);
new_ss=readmemw(base,0x26);
new_ds=readmemw(base,0x28);
new_ldt=readmemw(base,0x2A);
if (cpu_state.abrt) return;
if (optype==JMP || optype==OPTYPE_INT)
if (limit < 43)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
if (cpu_state.abrt) return;
tempw&=~0x200;
if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
else writememw(gdt.base,(tr.seg&~7)+4,tempw);
pclog("16-bit TSS %04X limit less than 43.\n", seg);
x86ts(NULL, seg);
return;
}
if (optype==JMP || optype==CALL || optype==OPTYPE_INT)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
else tempw=readmemw(gdt.base,(seg&~7)+4);
if (cpu_state.abrt) return;
tempw|=0x200;
if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
else writememw(gdt.base,(seg&~7)+4,tempw);
}
if (cpu_state.abrt) return;
if (optype==IRET) flags&=~NT_FLAG;
cpu_386_flags_rebuild();
@@ -2361,24 +2370,46 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
writememw(tr.base,0x24,CS);
writememw(tr.base,0x26,SS);
writememw(tr.base,0x28,DS);
writememw(tr.base,0x2A,ldt.seg);
if (optype==OPTYPE_INT)
if (optype==JMP || optype==IRET)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(tr.seg&~7)+4);
else tempw=readmemw(gdt.base,(tr.seg&~7)+4);
if (cpu_state.abrt) return;
tempw&=~0x200;
if (tr.seg&4) writememw(ldt.base,(tr.seg&~7)+4,tempw);
else writememw(gdt.base,(tr.seg&~7)+4,tempw);
}
if (cpu_state.abrt) return;
if (optype==OPTYPE_INT || optype==CALL)
{
writememw(base,0,tr.seg);
new_flags|=NT_FLAG;
}
if (cpu_state.abrt) return;
if (optype==JMP || optype==OPTYPE_INT)
{
if (tr.seg&4) tempw=readmemw(ldt.base,(seg&~7)+4);
else tempw=readmemw(gdt.base,(seg&~7)+4);
if (cpu_state.abrt) return;
tempw|=0x200;
if (tr.seg&4) writememw(ldt.base,(seg&~7)+4,tempw);
else writememw(gdt.base,(seg&~7)+4,tempw);
}
new_pc=readmemw(base,0x0E);
new_flags=readmemw(base,0x10);
new_eax=readmemw(base,0x12);
new_ecx=readmemw(base,0x14);
new_edx=readmemw(base,0x16);
new_ebx=readmemw(base,0x18);
new_esp=readmemw(base,0x1A);
new_ebp=readmemw(base,0x1C);
new_esi=readmemw(base,0x1E);
new_edi=readmemw(base,0x20);
new_es=readmemw(base,0x22);
new_cs=readmemw(base,0x24);
new_ss=readmemw(base,0x26);
new_ds=readmemw(base,0x28);
new_ldt=readmemw(base,0x2A);
msw |= 8;
cpu_state.pc=new_pc;
flags=new_flags;
cpu_386_flags_extract();
@@ -2387,11 +2418,20 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
templ=(ldt.seg&~7)+gdt.base;
ldt.limit=readmemw(0,templ);
ldt.base=(readmemw(0,templ+2))|(readmemb(0,templ+4)<<16);
if (is386)
{
if (readmemb(0,templ+6)&0x80)
{
ldt.limit<<=12;
ldt.limit|=0xFFF;
}
ldt.base|=(readmemb(0,templ+7)<<24);
}
if (!(new_cs&~3))
{
pclog("TS loading null CS\n");
x86gpf(NULL,0);
x86ts(NULL,0);
return;
}
addr=new_cs&~7;
@@ -2400,7 +2440,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if (addr>=ldt.limit)
{
pclog("Bigger than LDT limit %04X %04X %04X TS\n",new_cs,ldt.limit,addr);
x86gpf(NULL,0);
x86ts(NULL,new_cs&~3);
return;
}
addr+=ldt.base;
@@ -2410,7 +2450,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if (addr>=gdt.limit)
{
pclog("Bigger than GDT limit %04X %04X TS\n",new_cs,gdt.limit);
x86gpf(NULL,0);
x86ts(NULL,new_cs&~3);
return;
}
addr+=gdt.base;
@@ -2431,7 +2471,7 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if ((new_cs&3) != DPL2)
{
pclog("TS load CS non-conforming RPL != DPL");
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
break;
@@ -2439,13 +2479,13 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if ((new_cs&3) < DPL2)
{
pclog("TS load CS non-conforming RPL < DPL");
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
break;
default:
pclog("TS load CS not code segment\n");
x86gpf(NULL,new_cs&~3);
x86ts(NULL,new_cs&~3);
return;
}
@@ -2454,14 +2494,14 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
if (CPL==3 && oldcpl!=3) flushmmucache_cr3();
set_use32(0);
AX=new_eax;
CX=new_ecx;
DX=new_edx;
BX=new_ebx;
SP=new_esp;
BP=new_ebp;
SI=new_esi;
DI=new_edi;
EAX=new_eax | 0xFFFF0000;
ECX=new_ecx | 0xFFFF0000;
EDX=new_edx | 0xFFFF0000;
EBX=new_ebx | 0xFFFF0000;
ESP=new_esp | 0xFFFF0000;
EBP=new_ebp | 0xFFFF0000;
ESI=new_esi | 0xFFFF0000;
EDI=new_edi | 0xFFFF0000;
if (output) pclog("Load ES %04X\n",new_es);
loadseg(new_es,&_es);
@@ -2469,6 +2509,11 @@ void taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
loadseg(new_ss,&_ss);
if (output) pclog("Load DS %04X\n",new_ds);
loadseg(new_ds,&_ds);
if (is386)
{
loadseg(0,&_fs);
loadseg(0,&_gs);
}
if (output) pclog("Resuming at %04X:%08X\n",CS,cpu_state.pc);
}

2
src/Makefile.mingw
View File

@@ -165,7 +165,7 @@ DEVOBJ = bugger.o lpt.o serial.o \
mouse.o mouse_serial.o mouse_ps2.o mouse_bus.o \
fdd.o fdc.o fdi2raw.o \
hdd.o hdd_image.o \
mfm_at.o mfm_xebec.o hdd_esdi.o ide.o xtide.o piix.o \
esdi_at.o mfm_at.o mfm_xebec.o hdd_esdi.o ide.o xtide.o piix.o \
disc.o \
disc_86f.o disc_fdi.o disc_imd.o disc_img.o \
disc_random.o disc_td0.o \

14
src/NETWORK/net_ne2000.c
View File

@@ -722,13 +722,13 @@ page0_write(nic_t *dev, uint32_t off, uint32_t val, unsigned len)
case 0x07: /* ISR */
val &= 0x7f; /* clear RST bit - status-only bit */
/* All other values are cleared iff the ISR bit is 1 */
dev->ISR.pkt_rx &= ~((int)((val & 0x01) == 0x01));
dev->ISR.pkt_tx &= ~((int)((val & 0x02) == 0x02));
dev->ISR.rx_err &= ~((int)((val & 0x04) == 0x04));
dev->ISR.tx_err &= ~((int)((val & 0x08) == 0x08));
dev->ISR.overwrite &= ~((int)((val & 0x10) == 0x10));
dev->ISR.cnt_oflow &= ~((int)((val & 0x20) == 0x20));
dev->ISR.rdma_done &= ~((int)((val & 0x40) == 0x40));
dev->ISR.pkt_rx &= !((int)((val & 0x01) == 0x01));
dev->ISR.pkt_tx &= !((int)((val & 0x02) == 0x02));
dev->ISR.rx_err &= !((int)((val & 0x04) == 0x04));
dev->ISR.tx_err &= !((int)((val & 0x08) == 0x08));
dev->ISR.overwrite &= !((int)((val & 0x10) == 0x10));
dev->ISR.cnt_oflow &= !((int)((val & 0x20) == 0x20));
dev->ISR.rdma_done &= !((int)((val & 0x40) == 0x40));
val = ((dev->ISR.rdma_done << 6) |
(dev->ISR.cnt_oflow << 5) |
(dev->ISR.overwrite << 4) |

1
src/SOUND/midi.c
View File

@@ -26,6 +26,7 @@ static MIDI_DEVICE devices[] =
{"None", "none", NULL},
{SYSTEM_MIDI_NAME, SYSTEM_MIDI_INTERNAL_NAME, &system_midi_device},
{"Roland MT-32 Emulation", "mt32", &mt32_device},
{"Roland CM-32L Emulation", "cm32l", &cm32l_device},
{"", "", NULL}
};

44
src/SOUND/midi_mt32.c
View File

@@ -54,7 +54,7 @@ static const mt32emu_report_handler_i_v0 handler_v0 = {
static const mt32emu_report_handler_i handler = { &handler_v0 };
static mt32emu_context context = NULL;
static int roms_present = -1;
static int roms_present[2] = {-1, -1};
mt32emu_return_code mt32_check(const char* func, mt32emu_return_code ret, mt32emu_return_code expected)
{
@@ -68,9 +68,16 @@ mt32emu_return_code mt32_check(const char* func, mt32emu_return_code ret, mt32em
int mt32_available()
{
if (roms_present < 0)
roms_present = (rom_present(L"roms/mt32/mt32_control.rom") && rom_present(L"roms/mt32/mt32_pcm.rom"));
return roms_present;
if (roms_present[0] < 0)
roms_present[0] = (rom_present(L"roms/sound/mt32/mt32_control.rom") && rom_present(L"roms/sound/mt32/mt32_pcm.rom"));
return roms_present[0];
}
int cm32l_available()
{
if (roms_present[1] < 0)
roms_present[1] = (rom_present(L"roms/sound/cm32l/cm32l_control.rom") && rom_present(L"roms/sound/cm32l/cm32l_pcm.rom"));
return roms_present[1];
}
static thread_t *thread_h = NULL;
@@ -138,15 +145,15 @@ void mt32_sysex(uint8_t* data, unsigned int len)
if (context) mt32_check("mt32emu_play_sysex", mt32emu_play_sysex(context, data, len), MT32EMU_RC_OK);
}
void* mt32_init()
void* mt32emu_init(wchar_t *control_rom, wchar_t *pcm_rom)
{
wchar_t s[512];
char fn[512];
context = mt32emu_create_context(handler, NULL);
if (!rom_getfile(L"roms/mt32/mt32_control.rom", s, 512)) return 0;
if (!rom_getfile(control_rom, s, 512)) return 0;
wcstombs(fn, s, (wcslen(s) << 1) + 2);
if (!mt32_check("mt32emu_add_rom_file", mt32emu_add_rom_file(context, fn), MT32EMU_RC_ADDED_CONTROL_ROM)) return 0;
if (!rom_getfile(L"roms/mt32/mt32_pcm.rom", s, 512)) return 0;
if (!rom_getfile(pcm_rom, s, 512)) return 0;
wcstombs(fn, s, (wcslen(s) << 1) + 2);
if (!mt32_check("mt32emu_add_rom_file", mt32emu_add_rom_file(context, fn), MT32EMU_RC_ADDED_PCM_ROM)) return 0;
@@ -193,6 +200,16 @@ void* mt32_init()
return dev;
}
void *mt32_init()
{
return mt32emu_init(L"roms/sound/mt32/mt32_control.rom", L"roms/sound/mt32/mt32_pcm.rom");
}
void *cm32l_init()
{
return mt32emu_init(L"roms/sound/cm32l/cm32l_control.rom", L"roms/sound/cm32l/cm32l_pcm.rom");
}
void mt32_close(void* p)
{
if (!p) return;
@@ -321,3 +338,16 @@ device_t mt32_device =
NULL,
mt32_config
};
device_t cm32l_device =
{
"Roland CM-32L Emulation",
0,
cm32l_init,
mt32_close,
cm32l_available,
NULL,
NULL,
NULL,
mt32_config
};

1
src/SOUND/midi_mt32.h
View File

@@ -1 +1,2 @@
extern device_t mt32_device;
extern device_t cm32l_device;

4
src/SOUND/snd_emu8k.c
View File

@@ -696,9 +696,9 @@ void emu8k_init(emu8k_t *emu8k, int onboard_ram)
int c;
double out;
f = romfopen(L"roms/awe32.raw", L"rb");
f = romfopen(L"roms/sound/awe32.raw", L"rb");
if (!f)
fatal("ROMS/AWE32.RAW not found\n");
fatal("ROMS/SOUND/AWE32.RAW not found\n");
if (onboard_ram)
{

2
src/SOUND/snd_sb.c
View File

@@ -680,7 +680,7 @@ void *sb_16_init()
int sb_awe32_available()
{
return rom_present(L"roms/awe32.raw");
return rom_present(L"roms/sound/awe32.raw");
}
void *sb_awe32_init()

4
src/VIDEO/vid_ati18800.c
View File

@@ -163,7 +163,7 @@ void *ati18800_init()
ati18800_t *ati18800 = malloc(sizeof(ati18800_t));
memset(ati18800, 0, sizeof(ati18800_t));
rom_init(&ati18800->bios_rom, L"roms/vga88.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ati18800->bios_rom, L"roms/video/ati18800/vga88.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
svga_init(&ati18800->svga, ati18800, 1 << 19, /*512kb*/
NULL,
@@ -183,7 +183,7 @@ void *ati18800_init()
static int ati18800_available()
{
return rom_present(L"roms/vga88.BIN");
return rom_present(L"roms/video/ati18800/vga88.BIN");
}
void ati18800_close(void *p)

16
src/VIDEO/vid_ati28800.c
View File

@@ -362,19 +362,19 @@ void *ati28800_init()
if (gfxcard == GFX_VGAWONDERXL)
{
rom_init_interleaved(&ati28800->bios_rom,
L"roms/XLEVEN.BIN",
L"roms/XLODD.BIN",
L"roms/video/ati28800/XLEVEN.BIN",
L"roms/video/ati28800/XLODD.BIN",
0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
}
else if (gfxcard == GFX_VGAWONDERXL24)
{
rom_init_interleaved(&ati28800->bios_rom,
L"roms/112-14318-102.bin",
L"roms/112-14319-102.bin",
L"roms/video/ati28800/112-14318-102.bin",
L"roms/video/ati28800/112-14319-102.bin",
0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
}
else
rom_init(&ati28800->bios_rom, L"roms/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ati28800->bios_rom, L"roms/video/ati28800/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga_init(&ati28800->svga, ati28800, memory, /*512kb*/
ati28800_recalctimings,
@@ -394,17 +394,17 @@ void *ati28800_init()
static int ati28800_available()
{
return rom_present(L"roms/bios.bin");
return rom_present(L"roms/video/ati28800/bios.bin");
}
static int compaq_ati28800_available()
{
return (rom_present(L"roms/XLEVEN.bin") && rom_present(L"roms/XLODD.bin"));
return (rom_present(L"roms/video/ati28800/XLEVEN.bin") && rom_present(L"roms/video/ati28800/XLODD.bin"));
}
static int ati28800_wonderxl24_available()
{
return (rom_present(L"roms/112-14318-102.bin") && rom_present(L"roms/112-14319-102.bin"));
return (rom_present(L"roms/video/ati28800/112-14318-102.bin") && rom_present(L"roms/video/ati28800/112-14319-102.bin"));
}
void ati28800_close(void *p)

8
src/VIDEO/vid_ati_mach64.c
View File

@@ -3349,7 +3349,7 @@ static void *mach64gx_init()
ati_eeprom_load(&mach64->eeprom, L"mach64.nvr", 1);
rom_init(&mach64->bios_rom, L"roms/mach64gx/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&mach64->bios_rom, L"roms/video/mach64/bios.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return mach64;
}
@@ -3367,7 +3367,7 @@ static void *mach64vt2_init()
ati_eeprom_load(&mach64->eeprom, L"mach64vt.nvr", 1);
rom_init(&mach64->bios_rom, L"roms/atimach64vt2pci.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&mach64->bios_rom, L"roms/video/mach64/atimach64vt2pci.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga->vblank_start = mach64_vblank_start;
@@ -3376,11 +3376,11 @@ static void *mach64vt2_init()
int mach64gx_available()
{
return rom_present(L"roms/mach64gx/bios.bin");
return rom_present(L"roms/video/mach64/bios.bin");
}
int mach64vt2_available()
{
return rom_present(L"roms/atimach64vt2pci.bin");
return rom_present(L"roms/video/mach64/atimach64vt2pci.bin");
}
void mach64_close(void *p)

36
src/VIDEO/vid_cl_gd.c
View File

@@ -881,92 +881,92 @@ void *clgd_common_init(wchar_t *romfn, uint8_t id)
void *gd6235_init()
{
return clgd_common_init(L"roms/vga6235.rom", CIRRUS_ID_CLGD6235);
return clgd_common_init(L"roms/video/cirruslogic/vga6235.rom", CIRRUS_ID_CLGD6235);
}
void *gd5422_init()
{
return clgd_common_init(L"roms/CL5422.ROM", CIRRUS_ID_CLGD5422);
return clgd_common_init(L"roms/video/cirruslogic/CL5422.ROM", CIRRUS_ID_CLGD5422);
}
void *gd5429_init()
{
return clgd_common_init(L"roms/5429.vbi", CIRRUS_ID_CLGD5429);
return clgd_common_init(L"roms/video/cirruslogic/5429.vbi", CIRRUS_ID_CLGD5429);
}
void *gd5430_init()
{
return clgd_common_init(L"roms/pci.BIN", CIRRUS_ID_CLGD5430);
return clgd_common_init(L"roms/video/cirruslogic/pci.BIN", CIRRUS_ID_CLGD5430);
}
void *dia5430_init()
{
return clgd_common_init(L"roms/diamondvlbus.BIN", CIRRUS_ID_CLGD5430);
return clgd_common_init(L"roms/video/cirruslogic/diamondvlbus.BIN", CIRRUS_ID_CLGD5430);
}
void *gd5434_init()
{
return clgd_common_init(L"roms/japan.BIN", CIRRUS_ID_CLGD5434);
return clgd_common_init(L"roms/video/cirruslogic/japan.BIN", CIRRUS_ID_CLGD5434);
}
void *gd5436_init()
{
return clgd_common_init(L"roms/5436.VBI", CIRRUS_ID_CLGD5436);
return clgd_common_init(L"roms/video/cirruslogic/5436.VBI", CIRRUS_ID_CLGD5436);
}
void *gd5440_init()
{
return clgd_common_init(L"roms/5440BIOS.BIN", CIRRUS_ID_CLGD5440);
return clgd_common_init(L"roms/video/cirruslogic/5440BIOS.BIN", CIRRUS_ID_CLGD5440);
}
void *gd5446_init()
{
return clgd_common_init(L"roms/5446BV.VBI", CIRRUS_ID_CLGD5446);
return clgd_common_init(L"roms/video/cirruslogic/5446BV.VBI", CIRRUS_ID_CLGD5446);
}
static int gd5422_available()
{
return rom_present(L"roms/CL5422.ROM");
return rom_present(L"roms/video/cirruslogic/CL5422.ROM");
}
static int gd5429_available()
{
return rom_present(L"roms/5429.vbi");
return rom_present(L"roms/video/cirruslogic/5429.vbi");
}
static int gd5430_available()
{
return rom_present(L"roms/pci.BIN");
return rom_present(L"roms/video/cirruslogic/pci.BIN");
}
static int dia5430_available()
{
return rom_present(L"roms/diamondvlbus.BIN");
return rom_present(L"roms/video/cirruslogic/diamondvlbus.BIN");
}
static int gd5434_available()
{
return rom_present(L"roms/japan.BIN");
return rom_present(L"roms/video/cirruslogic/japan.BIN");
}
static int gd5436_available()
{
return rom_present(L"roms/5436.VBI");
return rom_present(L"roms/video/cirruslogic/5436.VBI");
}
static int gd5440_available()
{
return rom_present(L"roms/5440BIOS.BIN");
return rom_present(L"roms/video/cirruslogic/5440BIOS.BIN");
}
static int gd5446_available()
{
return rom_present(L"roms/5446BV.VBI");
return rom_present(L"roms/video/cirruslogic/5446BV.VBI");
}
static int gd6235_available()
{
return rom_present(L"roms/vga6235.rom");
return rom_present(L"roms/video/cirruslogic/vga6235.rom");
}
void clgd_close(void *p)

16
src/VIDEO/vid_ega.c
View File

@@ -998,7 +998,7 @@ void *ega_standalone_init()
overscan_x = 16;
overscan_y = 28;
rom_init(&ega->bios_rom, L"roms/ibm_6277356_ega_card_u44_27128.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ega->bios_rom, L"roms/video/ega/ibm_6277356_ega_card_u44_27128.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (ega->bios_rom.rom[0x3ffe] == 0xaa && ega->bios_rom.rom[0x3fff] == 0x55)
{
@@ -1036,7 +1036,7 @@ void *cpqega_standalone_init()
overscan_x = 16;
overscan_y = 28;
rom_init(&ega->bios_rom, L"roms/108281-001.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ega->bios_rom, L"roms/video/ega/108281-001.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (ega->bios_rom.rom[0x3ffe] == 0xaa && ega->bios_rom.rom[0x3fff] == 0x55)
{
@@ -1072,7 +1072,7 @@ void *sega_standalone_init()
overscan_x = 16;
overscan_y = 28;
rom_init(&ega->bios_rom, L"roms/lega.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&ega->bios_rom, L"roms/video/ega/lega.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (ega->bios_rom.rom[0x3ffe] == 0xaa && ega->bios_rom.rom[0x3fff] == 0x55)
{
@@ -1198,8 +1198,8 @@ void *jega_standalone_init()
{
ega_t *ega = (ega_t *) sega_standalone_init();
LoadFontxFile(L"roms/JPNHN19X.FNT");
LoadFontxFile(L"roms/JPNZN16X.FNT");
LoadFontxFile(L"roms/video/ega/JPNHN19X.FNT");
LoadFontxFile(L"roms/video/ega/JPNZN16X.FNT");
ega->is_jega = 1;
@@ -1208,17 +1208,17 @@ void *jega_standalone_init()
static int ega_standalone_available()
{
return rom_present(L"roms/ibm_6277356_ega_card_u44_27128.bin");
return rom_present(L"roms/video/ega/ibm_6277356_ega_card_u44_27128.bin");
}
static int cpqega_standalone_available()
{
return rom_present(L"roms/108281-001.bin");
return rom_present(L"roms/video/ega/108281-001.bin");
}
static int sega_standalone_available()
{
return rom_present(L"roms/lega.vbi");
return rom_present(L"roms/video/ega/lega.vbi");
}
void ega_close(void *p)

4
src/VIDEO/vid_et4000.c
View File

@@ -144,7 +144,7 @@ void *et4000_init()
et4000_t *et4000 = malloc(sizeof(et4000_t));
memset(et4000, 0, sizeof(et4000_t));
rom_init(&et4000->bios_rom, L"roms/et4000.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&et4000->bios_rom, L"roms/video/et4000/et4000.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
io_sethandler(0x03c0, 0x0020, et4000_in, NULL, NULL, et4000_out, NULL, NULL, et4000);
@@ -159,7 +159,7 @@ void *et4000_init()
static int et4000_available()
{
return rom_present(L"roms/et4000.BIN");
return rom_present(L"roms/video/et4000/et4000.BIN");
}
void et4000_close(void *p)

4
src/VIDEO/vid_et4000w32.c
View File

@@ -1152,7 +1152,7 @@ void *et4000w32p_init()
et4000w32p_hwcursor_draw,
NULL);
rom_init(&et4000->bios_rom, L"roms/et4000w32.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&et4000->bios_rom, L"roms/video/et4000w32/et4000w32.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&et4000->bios_rom.mapping);
@@ -1187,7 +1187,7 @@ void *et4000w32p_init()
int et4000w32p_available()
{
return rom_present(L"roms/et4000w32.bin");
return rom_present(L"roms/video/et4000w32/et4000w32.bin");
}
void et4000w32p_close(void *p)

2
src/VIDEO/vid_genius.c
View File

@@ -607,7 +607,7 @@ void genius_close(void *p)
static int genius_available()
{
return rom_present(L"roms/8x12.bin");
return rom_present(L"roms/video/genius/8x12.bin");
}
void genius_speed_changed(void *p)

16
src/VIDEO/vid_nv_riva128.c
View File

@@ -2716,7 +2716,7 @@ static void *riva128_init()
riva128_in, riva128_out,
NULL, NULL);
rom_init(&riva128->bios_rom, L"roms/Diamond_V330_rev-e.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&riva128->bios_rom, L"roms/video/nv_riva128/Diamond_V330_rev-e.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&riva128->bios_rom.mapping);
@@ -2813,7 +2813,7 @@ static void riva128_close(void *p)
static int riva128_available()
{
return rom_present(L"roms/Diamond_V330_rev-e.vbi");
return rom_present(L"roms/video/nv_riva128/Diamond_V330_rev-e.vbi");
}
static void riva128_speed_changed(void *p)
@@ -3017,7 +3017,7 @@ static void *rivatnt_init()
riva128_in, riva128_out,
NULL, NULL);
rom_init(&riva128->bios_rom, L"roms/NV4_diamond_revB.rom", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&riva128->bios_rom, L"roms/video/nv_riva128/NV4_diamond_revB.rom", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&riva128->bios_rom.mapping);
@@ -3098,7 +3098,7 @@ static void rivatnt_close(void *p)
static int rivatnt_available()
{
return rom_present(L"roms/NV4_diamond_revB.rom");
return rom_present(L"roms/video/nv_riva128/NV4_diamond_revB.rom");
}
static void rivatnt_speed_changed(void *p)
@@ -3220,13 +3220,13 @@ static void *rivatnt2_init()
switch(model)
{
case 0:
rom_init(&riva128->bios_rom, L"roms/NV5diamond.bin", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&riva128->bios_rom, L"roms/video/nv_riva128/NV5diamond.bin", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
break;
case 1:
rom_init(&riva128->bios_rom, L"roms/inno3d64bit.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&riva128->bios_rom, L"roms/video/nv_riva128/inno3d64bit.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
break;
case 2:
rom_init(&riva128->bios_rom, L"roms/creative.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&riva128->bios_rom, L"roms/video/nv_riva128/creative.BIN", 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
break;
}
if (PCI)
@@ -3309,7 +3309,7 @@ static void rivatnt2_close(void *p)
static int rivatnt2_available()
{
return rom_present(L"roms/NV5diamond.bin") || rom_present(L"roms/inno3d64bit.BIN") || rom_present(L"roms/creative.BIN");
return rom_present(L"roms/video/nv_riva128/NV5diamond.bin") || rom_present(L"roms/video/nv_riva128/inno3d64bit.BIN") || rom_present(L"roms/video/nv_riva128/creative.BIN");
}
static void rivatnt2_speed_changed(void *p)

8
src/VIDEO/vid_oti067.c
View File

@@ -186,23 +186,23 @@ void *oti067_common_init(wchar_t *bios_fn, int vram_size, int chip_id)
void *oti067_init()
{
int vram_size = device_get_config_int("memory");
return oti067_common_init(L"roms/oti067/bios.bin", vram_size, 2);
return oti067_common_init(L"roms/video/oti/bios.bin", vram_size, 2);
}
void *oti077_init()
{
int vram_size = device_get_config_int("memory");
return oti067_common_init(L"roms/oti077.vbi", vram_size, 5);
return oti067_common_init(L"roms/video/oti/oti077.vbi", vram_size, 5);
}
static int oti067_available()
{
return rom_present(L"roms/oti067/bios.bin");
return rom_present(L"roms/video/oti/bios.bin");
}
static int oti077_available()
{
return rom_present(L"roms/oti077.vbi");
return rom_present(L"roms/video/oti/oti077.vbi");
}
void oti067_close(void *p)

10
src/VIDEO/vid_paradise.c
View File

@@ -324,7 +324,7 @@ static void *paradise_pvga1a_pc2086_init()
paradise_t *paradise = paradise_pvga1a_init();
if (paradise)
rom_init(&paradise->bios_rom, L"roms/pc2086/40186.ic171", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&paradise->bios_rom, L"roms/machines/pc2086/40186.ic171", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
@@ -333,7 +333,7 @@ static void *paradise_pvga1a_pc3086_init()
paradise_t *paradise = paradise_pvga1a_init();
if (paradise)
rom_init(&paradise->bios_rom, L"roms/pc3086/c000.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&paradise->bios_rom, L"roms/machines/pc3086/c000.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
@@ -344,8 +344,8 @@ static void *paradise_wd90c11_megapc_init()
if (paradise)
rom_init_interleaved(&paradise->bios_rom,
L"roms/megapc/41651-bios lo.u18",
L"roms/megapc/211253-bios hi.u19",
L"roms/machines/megapc/41651-bios lo.u18",
L"roms/machines/megapc/211253-bios hi.u19",
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
@@ -353,7 +353,7 @@ static void *paradise_wd90c11_megapc_init()
static int paradise_wd90c11_standalone_available()
{
return rom_present(L"roms/megapc/41651-bios lo.u18") && rom_present(L"roms/megapc/211253-bios hi.u19");
return rom_present(L"roms/machines/megapc/41651-bios lo.u18") && rom_present(L"roms/machines/megapc/211253-bios hi.u19");
}
void paradise_close(void *p)

2
src/VIDEO/vid_pc1640.c
View File

@@ -126,7 +126,7 @@ void *pc1640_init()
ega_t *ega = &pc1640->ega;
memset(pc1640, 0, sizeof(pc1640_t));
rom_init(&pc1640->bios_rom, L"roms/pc1640/40100", 0xc0000, 0x8000, 0x7fff, 0, 0);
rom_init(&pc1640->bios_rom, L"roms/machines/pc1640/40100", 0xc0000, 0x8000, 0x7fff, 0, 0);
ega_init(&pc1640->ega);
pc1640->cga.vram = pc1640->ega.vram;

28
src/VIDEO/vid_s3.c
View File

@@ -1676,8 +1676,6 @@ void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
if (cpu_input/* && (s3->accel.multifunc[0xa] & 0xc0) == 0x80*/) return;
if (s3->accel.sy < 0)
{
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
return;
}
}
@@ -1746,8 +1744,6 @@ void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat
if (s3->accel.sy < 0)
{
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
return;
}
}
@@ -2218,29 +2214,29 @@ void *s3_vision864_init(wchar_t *bios_fn)
void *s3_bahamas64_init()
{
s3_t *s3 = s3_vision864_init(L"roms/bahamas64.BIN");
s3_t *s3 = s3_vision864_init(L"roms/video/s3/bahamas64.BIN");
return s3;
}
void *s3_phoenix_vision864_init()
{
s3_t *s3 = s3_vision864_init(L"roms/86c864p.bin");
s3_t *s3 = s3_vision864_init(L"roms/video/s3/86c864p.bin");
return s3;
}
int s3_bahamas64_available()
{
return rom_present(L"roms/bahamas64.BIN");
return rom_present(L"roms/video/s3/bahamas64.BIN");
}
int s3_phoenix_vision864_available()
{
return rom_present(L"roms/86c864p.bin");
return rom_present(L"roms/video/s3/86c864p.bin");
}
void *s3_phoenix_trio32_init()
{
s3_t *s3 = s3_init(L"roms/86C732P.bin", S3_TRIO32);
s3_t *s3 = s3_init(L"roms/video/s3/86C732P.bin", S3_TRIO32);
s3->id = 0xe1; /*Trio32*/
s3->id_ext = 0x10;
@@ -2255,7 +2251,7 @@ void *s3_phoenix_trio32_init()
int s3_phoenix_trio32_available()
{
return rom_present(L"roms/86C732P.bin");
return rom_present(L"roms/video/s3/86C732P.bin");
}
void *s3_trio64_init(wchar_t *bios_fn)
@@ -2274,35 +2270,35 @@ void *s3_trio64_init(wchar_t *bios_fn)
void *s3_9fx_init()
{
s3_t *s3 = s3_trio64_init(L"roms/s3_764.bin");
s3_t *s3 = s3_trio64_init(L"roms/video/s3/s3_764.bin");
return s3;
}
void *s3_phoenix_trio64_init()
{
s3_t *s3 = s3_trio64_init(L"roms/86C764X1.bin");
s3_t *s3 = s3_trio64_init(L"roms/video/s3/86C764X1.bin");
return s3;
}
void *s3_diamond_stealth64_init()
{
s3_t *s3 = s3_trio64_init(L"roms/STEALT64.BIN");
s3_t *s3 = s3_trio64_init(L"roms/video/s3/STEALT64.BIN");
return s3;
}
int s3_9fx_available()
{
return rom_present(L"roms/s3_764.bin");
return rom_present(L"roms/video/s3/s3_764.bin");
}
int s3_phoenix_trio64_available()
{
return rom_present(L"roms/86c764x1.bin");
return rom_present(L"roms/video/s3/86c764x1.bin");
}
int s3_diamond_stealth64_available()
{
return rom_present(L"roms/STEALT64.BIN");
return rom_present(L"roms/video/s3/STEALT64.BIN");
}
void s3_close(void *p)

16
src/VIDEO/vid_s3_virge.c
View File

@@ -3750,7 +3750,7 @@ static void *s3_virge_init()
s3_virge_overlay_draw);
virge->svga.vblank_start = s3_virge_vblank_start;
rom_init(&virge->bios_rom, L"roms/s3virge.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&virge->bios_rom, L"roms/video/s3virge/s3virge.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&virge->bios_rom.mapping);
@@ -3845,7 +3845,7 @@ static void *s3_virge_988_init()
s3_virge_hwcursor_draw,
s3_virge_overlay_draw);
rom_init(&virge->bios_rom, L"roms/diamondstealth3000.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&virge->bios_rom, L"roms/video/s3virge/diamondstealth3000.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (PCI)
mem_mapping_disable(&virge->bios_rom.mapping);
@@ -4023,12 +4023,12 @@ static void *s3_virge_375_init(wchar_t *romfn)
static void *s3_virge_375_1_init()
{
return s3_virge_375_init(L"roms/86c375_1.bin");
return s3_virge_375_init(L"roms/video/s3virge/86c375_1.bin");
}
static void *s3_virge_375_4_init()
{
return s3_virge_375_init(L"roms/86c375_4.bin");
return s3_virge_375_init(L"roms/video/s3virge/86c375_4.bin");
}
static void s3_virge_close(void *p)
@@ -4056,22 +4056,22 @@ static void s3_virge_close(void *p)
static int s3_virge_available()
{
return rom_present(L"roms/s3virge.bin");
return rom_present(L"roms/video/s3virge/s3virge.bin");
}
static int s3_virge_988_available()
{
return rom_present(L"roms/diamondstealth3000.VBI");
return rom_present(L"roms/video/s3virge/diamondstealth3000.VBI");
}
static int s3_virge_375_1_available()
{
return rom_present(L"roms/86c375_1.bin");
return rom_present(L"roms/video/s3virge/86c375_1.bin");
}
static int s3_virge_375_4_available()
{
return rom_present(L"roms/86c375_4.bin");
return rom_present(L"roms/video/s3virge/86c375_4.bin");
}
static void s3_virge_speed_changed(void *p)

4
src/VIDEO/vid_tgui9440.c
View File

@@ -511,7 +511,7 @@ void *tgui9440_init()
tgui->vram_size = device_get_config_int("memory") << 20;
tgui->vram_mask = tgui->vram_size - 1;
rom_init(&tgui->bios_rom, L"roms/9440.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&tgui->bios_rom, L"roms/video/tgui9440/9440.vbi", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga_init(&tgui->svga, tgui, tgui->vram_size,
tgui_recalctimings,
@@ -537,7 +537,7 @@ void *tgui9440_init()
static int tgui9440_available()
{
return rom_present(L"roms/9440.vbi");
return rom_present(L"roms/video/tgui9440/9440.vbi");
}
void tgui_close(void *p)

4
src/VIDEO/vid_tvga.c
View File

@@ -286,7 +286,7 @@ void *tvga8900d_init()
tvga->vram_size = device_get_config_int("memory") << 10;
tvga->vram_mask = tvga->vram_size - 1;
rom_init(&tvga->bios_rom, L"roms/TRIDENT.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&tvga->bios_rom, L"roms/video/tvga/TRIDENT.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga_init(&tvga->svga, tvga, tvga->vram_size,
tvga_recalctimings,
@@ -301,7 +301,7 @@ void *tvga8900d_init()
static int tvga8900d_available()
{
return rom_present(L"roms/TRIDENT.BIN");
return rom_present(L"roms/video/tvga/TRIDENT.BIN");
}
void tvga_close(void *p)

6
src/VIDEO/vid_vga.c
View File

@@ -85,7 +85,7 @@ void *vga_init()
vga_t *vga = malloc(sizeof(vga_t));
memset(vga, 0, sizeof(vga_t));
rom_init(&vga->bios_rom, L"roms/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0x2000, MEM_MAPPING_EXTERNAL);
rom_init(&vga->bios_rom, L"roms/video/vga/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0x2000, MEM_MAPPING_EXTERNAL);
svga_init(&vga->svga, vga, 1 << 18, /*256kb*/
NULL,
@@ -107,7 +107,7 @@ void *trigem_unk_init()
vga_t *vga = malloc(sizeof(vga_t));
memset(vga, 0, sizeof(vga_t));
rom_init(&vga->bios_rom, L"roms/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0x2000, MEM_MAPPING_EXTERNAL);
rom_init(&vga->bios_rom, L"roms/video/vga/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0x2000, MEM_MAPPING_EXTERNAL);
svga_init(&vga->svga, vga, 1 << 18, /*256kb*/
NULL,
@@ -150,7 +150,7 @@ void *ps1vga_init()
static int vga_available()
{
return rom_present(L"roms/ibm_vga.bin");
return rom_present(L"roms/video/vga/ibm_vga.bin");
}
void vga_close(void *p)

16
src/VIDEO/video.c
View File

@@ -17,6 +17,7 @@
#include "video.h"
#include "vid_svga.h"
#ifndef __unix
# include "../win/win.h" /*YUCK*/
# include "../win/win_cgapal.h" /*YUCK*/
#endif
@@ -692,6 +693,15 @@ time_t now;
struct tm *info;
wchar_t screenshot_fn_partial[2048];
wchar_t screenshot_fn[4096];
wchar_t screenshot_path[4096];
BOOL DirectoryExists(LPCTSTR szPath)
{
DWORD dwAttrib = GetFileAttributes(szPath);
return (dwAttrib != INVALID_FILE_ATTRIBUTES &&
(dwAttrib & FILE_ATTRIBUTE_DIRECTORY));
}
void take_screenshot()
{
@@ -700,7 +710,13 @@ void take_screenshot()
info = localtime(&now);
memset(screenshot_fn, 0, 8192);
memset(screenshot_fn_partial, 0, 4096);
memset(screenshot_path, 0, 8192);
pclog("Video API is: %i\n", vid_api);
append_filename_w(screenshot_path, pcempath, L"screenshots", 4095);
if (!DirectoryExists(screenshot_path))
{
CreateDirectory(screenshot_path, NULL);
}
if (vid_api == 1)
{
wcsftime(screenshot_fn_partial, 2048, L"screenshots\\%Y%m%d_%H%M%S.png", info);

1
src/WIN/86Box.rc
View File

@@ -46,6 +46,7 @@ BEGIN
BEGIN
MENUITEM "&Hard Reset", IDM_ACTION_HRESET
MENUITEM "&Ctrl+Alt+Del\tCtrl+F12", IDM_ACTION_RESET_CAD
MENUITEM "&Ctrl+Alt+Esc", IDM_ACTION_CTRL_ALT_ESC
MENUITEM SEPARATOR
MENUITEM "E&xit", IDM_ACTION_EXIT
END

1
src/WIN/resource.h
View File

@@ -388,6 +388,7 @@
#define IDM_ACTION_HRESET 40012
#define IDM_ACTION_RESET_CAD 40013
#define IDM_ACTION_EXIT 40014
#define IDM_ACTION_CTRL_ALT_ESC 40015
#define IDM_CONFIG 40020
#define IDM_CONFIG_LOAD 40021
#define IDM_CONFIG_SAVE 40022

7
src/WIN/win.c
View File

@@ -1836,6 +1836,10 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
PostQuitMessage (0); /* send a WM_QUIT to the message queue */
break;
case IDM_ACTION_CTRL_ALT_ESC:
ctrl_alt_esc();
break;
case IDM_CONFIG:
win_settings_open(hwnd);
break;
@@ -1897,6 +1901,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
endblit();
saveconfig();
device_force_redraw();
cgapal_rebuild();
break;
case IDM_VID_FULLSCREEN:
@@ -1919,6 +1924,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
endblit();
saveconfig();
device_force_redraw();
cgapal_rebuild();
}
break;
@@ -2248,6 +2254,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
mouse_init();
endblit();
device_force_redraw();
cgapal_rebuild();
break;
case WM_KEYDOWN:

2
src/WIN/win.h
View File

@@ -107,6 +107,8 @@ extern int find_status_bar_part(int tag);
extern void cdrom_close(uint8_t id);
extern void update_tip(int meaning);
extern BOOL DirectoryExists(LPCTSTR szPath);
#ifdef __cplusplus
}
#endif

27
src/WIN/win_d3d.cc
View File

@@ -95,7 +95,8 @@ int d3d_init(HWND h)
d3dpp.BackBufferWidth = 0;
d3dpp.BackBufferHeight = 0;
d3d->CreateDevice(D3DADAPTER_DEFAULT, D3DDEVTYPE_HAL, h, D3DCREATE_SOFTWARE_VERTEXPROCESSING, &d3dpp, &d3ddev);
if (FAILED(d3d->CreateDevice(D3DADAPTER_DEFAULT, D3DDEVTYPE_HAL, h, D3DCREATE_SOFTWARE_VERTEXPROCESSING, &d3dpp, &d3ddev)))
fatal("CreateDevice failed\n");
d3d_init_objects();
@@ -125,14 +126,16 @@ void d3d_init_objects()
int y;
RECT r;
d3ddev->CreateVertexBuffer(12*sizeof(CUSTOMVERTEX),
if (FAILED(d3ddev->CreateVertexBuffer(12*sizeof(CUSTOMVERTEX),
0,
D3DFVF_XYZRHW | D3DFVF_DIFFUSE | D3DFVF_TEX1,
D3DPOOL_MANAGED,
&v_buffer,
NULL);
NULL)))
fatal("CreateVertexBuffer failed\n");
d3ddev->CreateTexture(2048, 2048, 1, 0, D3DFMT_X8R8G8B8, D3DPOOL_MANAGED, &d3dTexture, NULL);
if (FAILED(d3ddev->CreateTexture(2048, 2048, 1, 0, D3DFMT_X8R8G8B8, D3DPOOL_MANAGED, &d3dTexture, NULL)))
fatal("CreateTexture failed\n");
r.top = r.left = 0;
r.bottom = r.right = 2047;
@@ -244,19 +247,23 @@ void d3d_blit_memtoscreen(int x, int y, int y1, int y2, int w, int h)
r.bottom = y2;
r.right = 2047;
hr = d3dTexture->LockRect(0, &dr, &r, 0);
if (hr == D3D_OK)
{
if (FAILED(d3dTexture->LockRect(0, &dr, &r, 0)))
fatal("LockRect failed\n");
for (yy = y1; yy < y2; yy++)
memcpy((void *)((uintptr_t)dr.pBits + ((yy - y1) * dr.Pitch)), &(((uint32_t *)buffer32->line[yy + y])[x]), w * 4);
{
if ((y + yy) >= 0 && (y + yy) < buffer32->h)
memcpy((void *)((uintptr_t)dr.pBits + ((yy - y1) * dr.Pitch)), &(((uint32_t *)buffer32->line[yy + y])[x]), w * 4);
}
video_blit_complete();
d3dTexture->UnlockRect(0);
}
else
{
video_blit_complete();
return;
}
d3d_verts[0].tu = d3d_verts[2].tu = d3d_verts[3].tu = 0;//0.5 / 2048.0;
d3d_verts[0].tv = d3d_verts[3].tv = d3d_verts[4].tv = 0;//0.5 / 2048.0;
@@ -334,11 +341,9 @@ void d3d_blit_memtoscreen_8(int x, int y, int w, int h)
r.bottom = h;
r.right = 2047;
hr = d3dTexture->LockRect(0, &dr, &r, 0);
if (hr == D3D_OK)
{
if (FAILED(d3dTexture->LockRect(0, &dr, &r, 0)))
fatal("LockRect failed\n");
for (yy = 0; yy < h; yy++)
{
uint32_t *p = (uint32_t *)((uintptr_t)dr.pBits + (yy * dr.Pitch));

67
src/WIN/win_d3d_fs.cc
View File

@@ -213,7 +213,8 @@ int d3d_fs_init(HWND h)
d3dpp.BackBufferWidth = d3d_fs_w;
d3dpp.BackBufferHeight = d3d_fs_h;
d3d->CreateDevice(D3DADAPTER_DEFAULT, D3DDEVTYPE_HAL, h, D3DCREATE_SOFTWARE_VERTEXPROCESSING, &d3dpp, &d3ddev);
if (FAILED(d3d->CreateDevice(D3DADAPTER_DEFAULT, D3DDEVTYPE_HAL, h, D3DCREATE_SOFTWARE_VERTEXPROCESSING, &d3dpp, &d3ddev)))
fatal("CreateDevice failed\n");
d3d_fs_init_objects();
@@ -243,14 +244,16 @@ static void d3d_fs_init_objects()
int y;
RECT r;
d3ddev->CreateVertexBuffer(12*sizeof(CUSTOMVERTEX),
if (FAILED(d3ddev->CreateVertexBuffer(12*sizeof(CUSTOMVERTEX),
0,
D3DFVF_XYZRHW | D3DFVF_DIFFUSE | D3DFVF_TEX1,
D3DPOOL_MANAGED,
&v_buffer,
NULL);
NULL)))
fatal("CreateVertexBuffer failed\n");
d3ddev->CreateTexture(2048, 2048, 1, 0, D3DFMT_X8R8G8B8, D3DPOOL_MANAGED, &d3dTexture, NULL);
if (FAILED(d3ddev->CreateTexture(2048, 2048, 1, 0, D3DFMT_X8R8G8B8, D3DPOOL_MANAGED, &d3dTexture, NULL)))
fatal("CreateTexture failed\n");
r.top = r.left = 0;
r.bottom = r.right = 2047;
@@ -392,9 +395,9 @@ static void d3d_fs_blit_memtoscreen(int x, int y, int y1, int y2, int w, int h)
D3DLOCKED_RECT dr;
RECT window_rect;
int yy;
double l, t, r, b;
double l = 0, t = 0, r = 0, b = 0;
if (y1 == y2)
if (y1 == y2)
{
video_blit_complete();
return; /*Nothing to do*/
@@ -409,14 +412,20 @@ static void d3d_fs_blit_memtoscreen(int x, int y, int y1, int y2, int w, int h)
lock_rect.bottom = y2;
lock_rect.right = 2047;
if (FAILED(d3dTexture->LockRect(0, &dr, &lock_rect, 0)))
fatal("LockRect failed\n");
for (yy = y1; yy < y2; yy++)
memcpy((void *)((uintptr_t)dr.pBits + ((yy - y1) * dr.Pitch)), &(((uint32_t *)buffer32->line[yy + y])[x]), w * 4);
hr = d3dTexture->LockRect(0, &dr, &lock_rect, 0);
if (hr == D3D_OK)
{
for (yy = y1; yy < y2; yy++)
memcpy((void *)((uintptr_t)dr.pBits + ((yy - y1) * dr.Pitch)), &(((uint32_t *)buffer32->line[yy + y])[x]), w * 4);
video_blit_complete();
d3dTexture->UnlockRect(0);
video_blit_complete();
d3dTexture->UnlockRect(0);
}
else
{
video_blit_complete();
return;
}
}
else
video_blit_complete();
@@ -498,7 +507,7 @@ static void d3d_fs_blit_memtoscreen_8(int x, int y, int w, int h)
D3DLOCKED_RECT dr;
RECT window_rect;
int xx, yy;
double l, t, r, b;
double l = 0, t = 0, r = 0, b = 0;
if (!h)
{
@@ -515,23 +524,27 @@ static void d3d_fs_blit_memtoscreen_8(int x, int y, int w, int h)
lock_rect.bottom = 2047;
lock_rect.right = 2047;
if (FAILED(d3dTexture->LockRect(0, &dr, &lock_rect, 0)))
fatal("LockRect failed\n");
for (yy = 0; yy < h; yy++)
hr = d3dTexture->LockRect(0, &dr, &lock_rect, 0);
if (hr == D3D_OK)
{
uint32_t *p = (uint32_t *)((uintptr_t)dr.pBits + (yy * dr.Pitch));
if ((y + yy) >= 0 && (y + yy) < buffer->h)
for (yy = 0; yy < h; yy++)
{
for (xx = 0; xx < w; xx++)
p[xx] = pal_lookup[buffer->line[y + yy][x + xx]];
uint32_t *p = (uint32_t *)((uintptr_t)dr.pBits + (yy * dr.Pitch));
if ((y + yy) >= 0 && (y + yy) < buffer->h)
{
for (xx = 0; xx < w; xx++)
p[xx] = pal_lookup[buffer->line[y + yy][x + xx]];
}
}
video_blit_complete();
d3dTexture->UnlockRect(0);
}
video_blit_complete();
d3dTexture->UnlockRect(0);
}
else
{
video_blit_complete();
return;
}
}
else
video_blit_complete();

2
src/WIN/win_serial.c
View File

@@ -379,7 +379,7 @@ bhtty_close(BHTTY *pp)
BHTTY *
bhtty_open(char *port, int tmo)
{
char temp[64];
char temp[84];
COMMTIMEOUTS to;
COMMCONFIG conf;
BHTTY *pp;

28
src/WIN/win_settings.c
View File

@@ -729,10 +729,10 @@ static void recalc_vid_list(HWND hdlg)
EnableWindow(h, models[temp_model].fixed_gfxcard ? FALSE : TRUE);
h = GetDlgItem(hdlg, IDC_CHECK_VOODOO);
EnableWindow(h, (models[model].flags & MODEL_PCI) ? TRUE : FALSE);
EnableWindow(h, (models[temp_model].flags & MODEL_PCI) ? TRUE : FALSE);
h = GetDlgItem(hdlg, IDC_BUTTON_VOODOO);
EnableWindow(h, ((models[model].flags & MODEL_PCI) && temp_voodoo) ? TRUE : FALSE);
EnableWindow(h, ((models[temp_model].flags & MODEL_PCI) && temp_voodoo) ? TRUE : FALSE);
}
@@ -2538,6 +2538,7 @@ static BOOL CALLBACK win_settings_hard_disks_add_proc(HWND hdlg, UINT message, W
char *big_buf;
int b = 0;
uint64_t r = 0;
int j = 0;
switch (message)
{
@@ -2852,24 +2853,31 @@ hdd_add_file_open_error:
fseeko64(f, 0, SEEK_END);
size = ftello64(f);
fclose(f);
if (((size % 17) == 0) && (size <= 133693440))
if (((size % 17) == 0) && (size <= 142606336))
{
spt = 17;
if (size <= 26738688)
{
hpc = 4;
}
else if (size <= 53477376)
else if (((size % 3072) == 0) && (size <= 53477376))
{
hpc = 6;
}
else if (size <= 71303168)
{
hpc = 8;
}
else
{
hpc = 15;
for (j = 0; j < 16; j++)
{
if (((size % (i << 9)) == 0) && (size <= ((i * 17) << 19)))
{
break;
}
if (i == 5)
{
i++;
}
}
hpc = i;
}
}
else
@@ -2907,7 +2915,7 @@ hdd_add_file_open_error:
chs_enabled = 1;
no_update = 0;
}
}
else
{
fclose(f);

4
src/cdrom_ioctl.c
View File

@@ -796,7 +796,7 @@ static void ioctl_read_capacity(uint8_t id, uint8_t *b)
const UCHAR cdb[] = { 0x25, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
UCHAR buf[16];
if (!cdrom_ioctl[id].capacity_read)
if (!cdrom_ioctl[id].capacity_read || (b == NULL))
{
SCSICommand(id, cdb, buf, &len, 1);
@@ -1198,7 +1198,7 @@ static int ioctl_readtoc_raw(uint8_t id, uint8_t *b, int maxlen)
static uint32_t ioctl_size(uint8_t id)
{
uint8_t capacity_buffer[8];
uint8_t capacity_buffer[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
uint32_t capacity = 0;
ioctl_read_capacity(id, capacity_buffer);
capacity = ((uint32_t) capacity_buffer[0]) << 24;

11
src/config.c
View File

@@ -835,6 +835,7 @@ static void loadconfig_machine(void)
{
char *cat = "Machine";
wchar_t *wp;
wchar_t last;
char *p;
p = config_get_string(cat, "model", NULL);
@@ -883,6 +884,16 @@ static void loadconfig_machine(void)
path_len = wcslen(nvr_path);
#ifndef __unix
last = nvr_path[wcslen(nvr_path) - 1];
nvr_path[wcslen(nvr_path) - 1] = 0;
if (!DirectoryExists(nvr_path))
{
CreateDirectory(nvr_path, NULL);
}
nvr_path[wcslen(nvr_path)] = last;
#endif
cpu_use_dynarec = !!config_get_int(cat, "cpu_use_dynarec", 0);
enable_external_fpu = !!config_get_int(cat, "cpu_enable_fpu", 0);

853
src/esdi_at.c Normal file
View File

@@ -0,0 +1,853 @@
#define _LARGEFILE_SOURCE
#define _LARGEFILE64_SOURCE
#define _GNU_SOURCE
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <sys/types.h>
#include "ibm.h"
#include "device.h"
#include "hdd_image.h"
#include "io.h"
#include "mem.h"
#include "pic.h"
#include "rom.h"
#include "timer.h"
#include "esdi_at.h"
#define IDE_TIME (TIMER_USEC*10)
#define STAT_ERR 0x01
#define STAT_INDEX 0x02
#define STAT_CORRECTED_DATA 0x04
#define STAT_DRQ 0x08 /* Data request */
#define STAT_DSC 0x10
#define STAT_SEEK_COMPLETE 0x20
#define STAT_READY 0x40
#define STAT_BUSY 0x80
#define ERR_DAM_NOT_FOUND 0x01 /*Data Address Mark not found*/
#define ERR_TR000 0x02 /*Track 0 not found*/
#define ERR_ABRT 0x04 /*Command aborted*/
#define ERR_ID_NOT_FOUND 0x10 /*ID not found*/
#define ERR_DATA_CRC 0x40 /*Data CRC error*/
#define ERR_BAD_BLOCK 0x80 /*Bad Block detected*/
#define CMD_NOP 0x00
#define CMD_RESTORE 0x10
#define CMD_READ 0x20
#define CMD_WRITE 0x30
#define CMD_VERIFY 0x40
#define CMD_FORMAT 0x50
#define CMD_SEEK 0x70
#define CMD_DIAGNOSE 0x90
#define CMD_SET_PARAMETERS 0x91
#define CMD_READ_PARAMETERS 0xec
extern char ide_fn[4][512];
typedef struct esdi_drive_t
{
int cfg_spt;
int cfg_hpc;
int current_cylinder;
int real_spt;
int real_hpc;
int real_tracks;
int present;
int hdc_num;
} esdi_drive_t;
typedef struct esdi_t
{
uint8_t status;
uint8_t error;
int secount,sector,cylinder,head,cylprecomp;
uint8_t command;
uint8_t fdisk;
int pos;
int drive_sel;
int reset;
uint16_t buffer[256];
int irqstat;
int callback;
esdi_drive_t drives[2];
rom_t bios_rom;
} esdi_t;
uint16_t esdi_readw(uint16_t port, void *p);
void esdi_writew(uint16_t port, uint16_t val, void *p);
static inline void esdi_irq_raise(esdi_t *esdi)
{
if (!(esdi->fdisk&2))
picint(1 << 14);
esdi->irqstat=1;
}
static inline void esdi_irq_lower(esdi_t *esdi)
{
picintc(1 << 14);
}
void esdi_irq_update(esdi_t *esdi)
{
if (esdi->irqstat && !((pic2.pend|pic2.ins)&0x40) && !(esdi->fdisk & 2))
picint(1 << 14);
}
/*
* Return the sector offset for the current register values
*/
int esdi_get_sector(esdi_t *esdi, off64_t *addr)
{
esdi_drive_t *drive = &esdi->drives[esdi->drive_sel];
int heads = drive->cfg_hpc;
int sectors = drive->cfg_spt;
if (esdi->head > heads)
{
pclog("esdi_get_sector: past end of configured heads\n");
return 1;
}
if (esdi->sector >= sectors+1)
{
pclog("esdi_get_sector: past end of configured sectors\n");
return 1;
}
if (drive->cfg_spt == drive->real_spt && drive->cfg_hpc == drive->real_hpc)
{
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) *
sectors) + (esdi->sector - 1);
}
else
{
/*When performing translation, the firmware seems to leave 1
sector per track inaccessible (spare sector)*/
int c, h, s;
*addr = ((((off64_t) esdi->cylinder * heads) + esdi->head) *
sectors) + (esdi->sector - 1);
s = *addr % (drive->real_spt - 1);
h = (*addr / (drive->real_spt - 1)) % drive->real_hpc;
c = (*addr / (drive->real_spt - 1)) / drive->real_hpc;
*addr = ((((off64_t) c * drive->real_hpc) + h) *
drive->real_spt) + s;
}
return 0;
}
/**
* Move to the next sector using CHS addressing
*/
void esdi_next_sector(esdi_t *esdi)
{
esdi_drive_t *drive = &esdi->drives[esdi->drive_sel];
esdi->sector++;
if (esdi->sector == (drive->cfg_spt + 1))
{
esdi->sector = 1;
esdi->head++;
if (esdi->head == drive->cfg_hpc)
{
esdi->head = 0;
esdi->cylinder++;
if (drive->current_cylinder < drive->real_tracks)
drive->current_cylinder++;
}
}
}
void esdi_write(uint16_t port, uint8_t val, void *p)
{
esdi_t *esdi = (esdi_t *)p;
switch (port)
{
case 0x1F0: /* Data */
esdi_writew(port, val | (val << 8), p);
return;
case 0x1F1: /* Write precompenstation */
esdi->cylprecomp = val;
return;
case 0x1F2: /* Sector count */
esdi->secount = val;
return;
case 0x1F3: /* Sector */
esdi->sector = val;
return;
case 0x1F4: /* Cylinder low */
esdi->cylinder = (esdi->cylinder & 0xFF00) | val;
return;
case 0x1F5: /* Cylinder high */
esdi->cylinder = (esdi->cylinder & 0xFF) | (val << 8);
return;
case 0x1F6: /* Drive/Head */
esdi->head = val & 0xF;
esdi->drive_sel = (val & 0x10) ? 1 : 0;
if (esdi->drives[esdi->drive_sel].present)
esdi->status = 0;
else
esdi->status = STAT_READY | STAT_DSC;
return;
case 0x1F7: /* Command register */
esdi_irq_lower(esdi);
esdi->command = val;
esdi->error = 0;
switch (val & 0xf0)
{
case CMD_RESTORE:
esdi->command &= ~0x0f; /*Mask off step rate*/
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
case CMD_SEEK:
esdi->command &= ~0x0f; /*Mask off step rate*/
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
default:
switch (val)
{
case CMD_NOP:
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
case CMD_READ: case CMD_READ+1:
case CMD_READ+2: case CMD_READ+3:
esdi->command &= ~3;
if (val & 2)
fatal("Read with ECC\n");
case 0xa0:
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
case CMD_WRITE: case CMD_WRITE+1:
case CMD_WRITE+2: case CMD_WRITE+3:
esdi->command &= ~3;
if (val & 2)
fatal("Write with ECC\n");
esdi->status = STAT_DRQ | STAT_DSC;
esdi->pos=0;
break;
case CMD_VERIFY: case CMD_VERIFY+1:
esdi->command &= ~1;
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200 * IDE_TIME;
timer_update_outstanding();
break;
case CMD_FORMAT:
esdi->status = STAT_DRQ;
esdi->pos=0;
break;
case CMD_SET_PARAMETERS: /* Initialize Drive Parameters */
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 30*IDE_TIME;
timer_update_outstanding();
break;
case CMD_DIAGNOSE: /* Execute Drive Diagnostics */
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
case 0xe0: /*???*/
case CMD_READ_PARAMETERS:
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
default:
pclog("Bad esdi command %02X\n", val);
case 0xe8: /*???*/
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 200*IDE_TIME;
timer_update_outstanding();
break;
}
}
break;
case 0x3F6: /* Device control */
if ((esdi->fdisk & 4) && !(val & 4))
{
timer_process();
esdi->callback = 500*IDE_TIME;
timer_update_outstanding();
esdi->reset = 1;
esdi->status = STAT_BUSY;
}
if (val & 4)
{
/*Drive held in reset*/
timer_process();
esdi->callback = 0;
timer_update_outstanding();
esdi->status = STAT_BUSY;
}
esdi->fdisk = val;
esdi_irq_update(esdi);
return;
}
}
void esdi_writew(uint16_t port, uint16_t val, void *p)
{
esdi_t *esdi = (esdi_t *)p;
esdi->buffer[esdi->pos >> 1] = val;
esdi->pos += 2;
if (esdi->pos >= 512)
{
esdi->pos = 0;
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 6*IDE_TIME;
timer_update_outstanding();
}
}
uint8_t esdi_read(uint16_t port, void *p)
{
esdi_t *esdi = (esdi_t *)p;
uint8_t temp = 0xff;
switch (port)
{
case 0x1F0: /* Data */
temp = esdi_readw(port, esdi) & 0xff;
break;
case 0x1F1: /* Error */
temp = esdi->error;
break;
case 0x1F2: /* Sector count */
temp = (uint8_t)esdi->secount;
break;
case 0x1F3: /* Sector */
temp = (uint8_t)esdi->sector;
break;
case 0x1F4: /* Cylinder low */
temp = (uint8_t)(esdi->cylinder&0xFF);
break;
case 0x1F5: /* Cylinder high */
temp = (uint8_t)(esdi->cylinder>>8);
break;
case 0x1F6: /* Drive/Head */
temp = (uint8_t)(esdi->head | (esdi->drive_sel ? 0x10 : 0) | 0xa0);
break;
case 0x1F7: /* Status */
esdi_irq_lower(esdi);
temp = esdi->status;
break;
}
return temp;
}
uint16_t esdi_readw(uint16_t port, void *p)
{
esdi_t *esdi = (esdi_t *)p;
uint16_t temp;
temp = esdi->buffer[esdi->pos >> 1];
esdi->pos += 2;
if (esdi->pos >= 512)
{
esdi->pos=0;
esdi->status = STAT_READY | STAT_DSC;
if (esdi->command == CMD_READ || esdi->command == 0xa0)
{
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount)
{
esdi_next_sector(esdi);
esdi->status = STAT_BUSY;
timer_process();
esdi->callback = 6*IDE_TIME;
timer_update_outstanding();
}
}
}
return temp;
}
void esdi_callback(void *p)
{
esdi_t *esdi = (esdi_t *)p;
esdi_drive_t *drive = &esdi->drives[esdi->drive_sel];
off64_t addr;
esdi->callback = 0;
if (esdi->reset)
{
esdi->status = STAT_READY | STAT_DSC;
esdi->error = 1;
esdi->secount = 1;
esdi->sector = 1;
esdi->head = 0;
esdi->cylinder = 0;
esdi->reset = 0;
return;
}
switch (esdi->command)
{
case CMD_RESTORE:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
drive->current_cylinder = 0;
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case CMD_SEEK:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case CMD_READ:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
if (esdi_get_sector(esdi, &addr))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
if (hdd_image_read_ex(drive->hdc_num, addr, 1, (uint8_t *) esdi->buffer))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
update_status_bar_icon(SB_HDD | HDD_BUS_RLL, 1);
}
break;
case CMD_WRITE:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
if (esdi_get_sector(esdi, &addr))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
if (hdd_image_write_ex(drive->hdc_num, addr, 1, (uint8_t *) esdi->buffer))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
esdi_irq_raise(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount)
{
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
esdi->pos = 0;
esdi_next_sector(esdi);
}
else
esdi->status = STAT_READY | STAT_DSC;
update_status_bar_icon(SB_HDD | HDD_BUS_RLL, 1);
}
break;
case CMD_VERIFY:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
if (esdi_get_sector(esdi, &addr))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
if (hdd_image_read_ex(drive->hdc_num, addr, 1, (uint8_t *) esdi->buffer))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
update_status_bar_icon(SB_HDD | HDD_BUS_RLL, 1);
esdi_next_sector(esdi);
esdi->secount = (esdi->secount - 1) & 0xff;
if (esdi->secount)
esdi->callback = 6*IDE_TIME;
else
{
esdi->pos = 0;
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
}
break;
case CMD_FORMAT:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
if (esdi_get_sector(esdi, &addr))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
if (hdd_image_zero_ex(drive->hdc_num, addr, esdi->secount))
{
esdi->error = ERR_ID_NOT_FOUND;
esdi->status = STAT_READY | STAT_DSC | STAT_ERR;
esdi_irq_raise(esdi);
break;
}
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
update_status_bar_icon(SB_HDD | HDD_BUS_RLL, 1);
}
break;
case CMD_DIAGNOSE:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
esdi->error = 1; /*No error detected*/
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case CMD_SET_PARAMETERS: /* Initialize Drive Parameters */
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
drive->cfg_spt = esdi->secount;
drive->cfg_hpc = esdi->head+1;
pclog("Parameters: spt=%i hpc=%i\n", drive->cfg_spt,drive->cfg_hpc);
if (!esdi->secount)
fatal("secount=0\n");
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case CMD_NOP:
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
break;
case 0xe0:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
switch (esdi->cylinder >> 8)
{
case 0x31:
esdi->cylinder = drive->real_tracks;
break;
case 0x33:
esdi->cylinder = drive->real_hpc;
break;
case 0x35:
esdi->cylinder = 0x200;
break;
case 0x36:
esdi->cylinder = drive->real_spt;
break;
default:
pclog("EDSI Bad read config %02x\n", esdi->cylinder >> 8);
}
esdi->status = STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case 0xa0:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
memset(esdi->buffer, 0, 512);
memset(&esdi->buffer[3], 0xff, 512-6);
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
case CMD_READ_PARAMETERS:
if (!drive->present)
{
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
}
else
{
memset(esdi->buffer, 0, 512);
esdi->buffer[0] = 0x44; /* general configuration */
esdi->buffer[1] = drive->real_tracks; /* number of non-removable cylinders */
esdi->buffer[2] = 0; /* number of removable cylinders */
esdi->buffer[3] = drive->real_hpc; /* number of heads */
esdi->buffer[5] = esdi->buffer[4] * drive->real_spt; /* number of unformatted bytes/sector */
esdi->buffer[4] = 600; /* number of unformatted bytes/track */
esdi->buffer[6] = drive->real_spt; /* number of sectors */
esdi->buffer[7] = 0; /*minimum bytes in inter-sector gap*/
esdi->buffer[8] = 0; /* minimum bytes in postamble */
esdi->buffer[9] = 0; /* number of words of vendor status */
/* controller info */
esdi->buffer[20] = 2; /* controller type */
esdi->buffer[21] = 1; /* sector buffer size, in sectors */
esdi->buffer[22] = 0; /* ecc bytes appended */
esdi->buffer[27] = 'W' | ('D' << 8);
esdi->buffer[28] = '1' | ('0' << 8);
esdi->buffer[29] = '0' | ('7' << 8);
esdi->buffer[30] = 'V' | ('-' << 8);
esdi->buffer[31] = 'S' | ('E' << 8);
esdi->buffer[32] = '1';
esdi->buffer[47] = 0; /* sectors per interrupt */
esdi->buffer[48] = 0;/* can use double word read/write? */
esdi->pos = 0;
esdi->status = STAT_DRQ | STAT_READY | STAT_DSC;
esdi_irq_raise(esdi);
}
break;
default:
pclog("ESDI Callback on unknown command %02x\n", esdi->command);
case 0xe8:
esdi->status = STAT_READY | STAT_ERR | STAT_DSC;
esdi->error = ERR_ABRT;
esdi_irq_raise(esdi);
break;
}
update_status_bar_icon(SB_HDD | HDD_BUS_RLL, 0);
}
static void esdi_rom_write(uint32_t addr, uint8_t val, void *p)
{
rom_t *rom = (rom_t *)p;
addr &= rom->mask;
if (addr >= 0x1f00 && addr < 0x2000)
rom->rom[addr] = val;
}
static void loadhd(esdi_t *esdi, int hdc_num, int d, const wchar_t *fn)
{
esdi_drive_t *drive = &esdi->drives[d];
int ret = 0;
ret = hdd_image_load(hdc_num);
if (!ret)
{
drive->present = 0;
return;
}
drive->cfg_spt = drive->real_spt = hdc[hdc_num].spt;
drive->cfg_hpc = drive->real_hpc = hdc[hdc_num].hpc;
drive->real_tracks = hdc[hdc_num].tracks;
drive->hdc_num = hdc_num;
drive->present = 1;
}
void *wd1007vse1_init()
{
int i = 0;
int c = 0;
esdi_t *esdi = malloc(sizeof(esdi_t));
memset(esdi, 0, sizeof(esdi_t));
esdi->drives[0].present = esdi->drives[1].present = 0;
for (i = 0; i < HDC_NUM; i++)
{
if ((hdc[i].bus == HDD_BUS_RLL) && (hdc[i].rll_channel < RLL_NUM))
{
loadhd(esdi, i, hdc[i].rll_channel, hdc[i].fn);
c++;
if (c >= RLL_NUM) break;
}
}
esdi->status = STAT_READY | STAT_DSC;
esdi->error = 1; /*No errors*/
rom_init(&esdi->bios_rom, L"roms/hdd/esdi_at/62-000279-061.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_set_handler(&esdi->bios_rom.mapping,
rom_read, rom_readw, rom_readl,
esdi_rom_write, NULL, NULL);
io_sethandler(0x01f0, 0x0001, esdi_read, esdi_readw, NULL, esdi_write, esdi_writew, NULL, esdi);
io_sethandler(0x01f1, 0x0007, esdi_read, NULL, NULL, esdi_write, NULL, NULL, esdi);
io_sethandler(0x03f6, 0x0001, NULL, NULL, NULL, esdi_write, NULL, NULL, esdi);
timer_add(esdi_callback, &esdi->callback, &esdi->callback, esdi);
return esdi;
}
void wd1007vse1_close(void *p)
{
esdi_t *esdi = (esdi_t *)p;
esdi_drive_t *drive;
int d;
esdi->drives[0].present = esdi->drives[1].present = 0;
for (d = 0; d < 2; d++)
{
drive = &esdi->drives[d];
hdd_image_close(drive->hdc_num);
}
free(esdi);
}
static int wd1007vse1_available()
{
return rom_present(L"roms/hdd/esdi_at/62-000279-061.bin");
}
device_t wd1007vse1_device =
{
"Western Digital WD1007V-SE1 (ESDI)",
DEVICE_AT,
wd1007vse1_init,
wd1007vse1_close,
wd1007vse1_available,
NULL,
NULL,
NULL,
NULL
};

1
src/esdi_at.h Normal file
View File

@@ -0,0 +1 @@
extern device_t wd1007vse1_device;

2
src/fdc.c
View File

@@ -1491,7 +1491,7 @@ void fdc_callback(void *priv)
case -1: /*Reset*/
fdc_int();
fdc.fintr = 0;
memset(fdc.pcn, 0, 4);
memset(fdc.pcn, 0, 4 * sizeof(int));
fdc_reset_stat = 4;
return;
case 1: /*Mode*/

20
src/hdd.c
View File

@@ -4,6 +4,7 @@
#include "hdd.h"
#include "model.h"
#include "esdi_at.h"
#include "hdd_esdi.h"
#include "mfm_at.h"
#include "mfm_xebec.h"
@@ -25,15 +26,16 @@ static struct
int is_mfm;
} hdd_controllers[] =
{
{"None", "none", &null_hdd_device, 0},
{"AT Fixed Disk Adapter", "mfm_at", &mfm_at_device, 1},
{"DTC 5150X", "dtc5150x", &dtc_5150x_device, 1},
{"Fixed Disk Adapter (Xebec)", "mfm_xebec", &mfm_xebec_device, 1},
{"IBM ESDI Fixed Disk Adapter (MCA)", "esdi_mca", &hdd_esdi_device, 1},
{"XTIDE", "xtide", &xtide_device, 0},
{"XTIDE (AT)", "xtide_at", &xtide_at_device, 0},
{"XTIDE (PS/2)", "xtide_ps2",&xtide_ps2_device,0},
{"XTIDE (AT) (PS/2)", "xtide_at_ps2",&xtide_at_ps2_device,0},
{"None", "none", &null_hdd_device, 0},
{"[MFM] AT Fixed Disk Adapter", "mfm_at", &mfm_at_device, 1},
{"[MFM] DTC 5150X", "dtc5150x", &dtc_5150x_device, 1},
{"[MFM] Fixed Disk Adapter (Xebec)", "mfm_xebec", &mfm_xebec_device, 1},
{"[ESDI] IBM ESDI Fixed Disk Adapter", "esdi_mca", &hdd_esdi_device, 1},
{"[ESDI] Western Digital WD1007V-SE1", "wd1007vse1", &wd1007vse1_device, 0},
{"[IDE] XTIDE", "xtide", &xtide_device, 0},
{"[IDE] XTIDE (Acculogic)", "xtide_ps2", &xtide_ps2_device, 0},
{"[IDE] XTIDE (AT)", "xtide_at", &xtide_at_device, 0},
{"[IDE] XTIDE (AT) (1.1.5)", "xtide_at_ps2", &xtide_at_ps2_device, 0},
{"", "", NULL, 0}
};

12
src/hdd_esdi.c
View File

@@ -816,9 +816,11 @@ static void *esdi_init()
esdi_t *esdi = malloc(sizeof(esdi_t));
memset(esdi, 0, sizeof(esdi_t));
rom_init_interleaved(&esdi->bios_rom, L"roms/90x8970.bin", L"roms/90x8969.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init_interleaved(&esdi->bios_rom, L"roms/hdd/esdi/90x8970.bin", L"roms/hdd/esdi/90x8969.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&esdi->bios_rom.mapping);
esdi->drives[0].present = esdi->drives[1].present = 0;
for (i = 0; i < HDC_NUM; i++)
{
if ((hdc[i].bus == HDD_BUS_RLL) && (hdc[i].rll_channel < RLL_NUM))
@@ -846,11 +848,15 @@ static void *esdi_init()
static void esdi_close(void *p)
{
esdi_t *esdi = (esdi_t *)p;
esdi_drive_t *drive;
int d;
esdi->drives[0].present = esdi->drives[1].present = 0;
for (d = 0; d < 2; d++)
{
esdi_drive_t *drive = &esdi->drives[d];
drive = &esdi->drives[d];
hdd_image_close(drive->hdc_num);
}
@@ -860,7 +866,7 @@ static void esdi_close(void *p)
static int esdi_available()
{
return rom_present(L"roms/90x8969.bin") && rom_present(L"roms/90x8970.bin");
return rom_present(L"roms/hdd/esdi/90x8969.bin") && rom_present(L"roms/hdd/esdi/90x8970.bin");
}
device_t hdd_esdi_device =

77
src/hdd_image.c
View File

@@ -361,6 +361,33 @@ void hdd_image_read(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer
fread(buffer, 1, count, hdd_images[id].file);
}
uint32_t hdd_sectors(uint8_t id)
{
fseeko64(hdd_images[id].file, 0, SEEK_END);
return (uint32_t) (ftello64(hdd_images[id].file) >> 9);
}
int hdd_image_read_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
{
transfer_sectors = sectors - sector;
}
hdd_image_seek(id, sector);
memset(buffer, 0, transfer_sectors << 9);
fread(buffer, 1, transfer_sectors << 9, hdd_images[id].file);
if (count != transfer_sectors)
{
return 1;
}
return 0;
}
void hdd_image_write(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
count <<= 9;
@@ -369,6 +396,27 @@ void hdd_image_write(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffe
fwrite(buffer, 1, count, hdd_images[id].file);
}
int hdd_image_write_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer)
{
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
{
transfer_sectors = sectors - sector;
}
hdd_image_seek(id, sector);
memset(buffer, 0, transfer_sectors << 9);
fwrite(buffer, 1, transfer_sectors << 9, hdd_images[id].file);
if (count != transfer_sectors)
{
return 1;
}
return 0;
}
void hdd_image_zero(uint8_t id, uint32_t sector, uint32_t count)
{
int i = 0;
@@ -386,6 +434,35 @@ void hdd_image_zero(uint8_t id, uint32_t sector, uint32_t count)
free(b);
}
int hdd_image_zero_ex(uint8_t id, uint32_t sector, uint32_t count)
{
int i = 0;
uint8_t *b;
uint32_t transfer_sectors = count;
uint32_t sectors = hdd_sectors(id);
if ((sectors - sector) < transfer_sectors)
{
transfer_sectors = sectors - sector;
}
b = (uint8_t *) malloc(512);
memset(b, 0, 512);
hdd_image_seek(id, sector);
for (i = 0; i < transfer_sectors; i++)
{
fwrite(b, 1, 512, hdd_images[id].file);
}
if (count != transfer_sectors)
{
return 1;
}
return 0;
}
uint32_t hdd_image_get_last_sector(uint8_t id)
{
return hdd_images[id].last_sector;

3
src/hdd_image.h
View File

@@ -1,8 +1,11 @@
extern int hdd_image_load(int id);
extern void hdd_image_seek(uint8_t id, uint32_t sector);
extern void hdd_image_read(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer);
extern int hdd_image_read_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer);
extern void hdd_image_write(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer);
extern int hdd_image_write_ex(uint8_t id, uint32_t sector, uint32_t count, uint8_t *buffer);
extern void hdd_image_zero(uint8_t id, uint32_t sector, uint32_t count);
extern int hdd_image_zero_ex(uint8_t id, uint32_t sector, uint32_t count);
extern uint32_t hdd_image_get_last_sector(uint8_t id);
extern uint8_t hdd_image_get_type(uint8_t id);
extern void hdd_image_specify(uint8_t id, uint64_t hpc, uint64_t spt);

8
src/ibm.h
View File

@@ -256,9 +256,15 @@ extern uint32_t dr[8];
#define V_FLAG 0x0800
#define NT_FLAG 0x4000
#define VM_FLAG 0x0002 /*In EFLAGS*/
#define VIF_FLAG 0x0008 /*In EFLAGS*/
#define VIP_FLAG 0x0010 /*In EFLAGS*/
#define WP_FLAG 0x10000 /*In CR0*/
#define CR4_VME (1 << 0)
#define CR4_PVI (1 << 1)
#define CR4_PSE (1 << 4)
#define IOPL ((flags>>12)&3)
#define IOPLp ((!(msw&1)) || (CPL<=IOPL))
@@ -672,6 +678,7 @@ extern int infocus;
extern void onesec(void);
extern void resetpc_cad(void);
extern void ctrl_alt_esc(void);
extern int dump_on_exit;
extern int start_in_fullscreen;
@@ -775,6 +782,7 @@ extern void softresetx86(void);
extern void speedchanged(void);
extern void trc_reset(uint8_t val);
extern void x86_int_sw(int num);
extern int x86_int_sw_rm(int num);
extern void x86gpf(char *s, uint16_t error);
extern void x86np(char *s, uint16_t error);
extern void x86ss(char *s, uint16_t error);

2
src/keyboard.c
View File

@@ -422,7 +422,7 @@ static int scorder[272] = {0x38, 0xB8, 0x1D, 0x9D, 0xFF, 0x2A, 0x36,0x103, 0x00,
0xFE,0x100,0x101,0x102,0x104,0x105,0x106,0x107,0x108,0x109,0x10A,0x10B,0x10C,0x10D,0x10E,0x10F};
/* bit 0 = repeat, bit 1 = makes break code? */
int set3_flags[272];
uint8_t set3_flags[272];
uint8_t set3_all_repeat = 0;
uint8_t set3_all_break = 0;

2
src/keyboard.h
View File

@@ -24,6 +24,6 @@ extern int pcem_key[272];
extern uint8_t mode;
void keyboard_process();
extern int set3_flags[272];
extern uint8_t set3_flags[272];
extern uint8_t set3_all_repeat;
extern uint8_t set3_all_break;

270
src/mem.c
View File

@@ -63,7 +63,7 @@ int shadowbios,shadowbios_write;
int mem_a20_state;
static unsigned char isram[0x10000];
unsigned char isram[0x10000];
static uint8_t ff_array[0x1000];
@@ -82,7 +82,7 @@ uint32_t ram_mapped_addr[64];
static void mem_load_atide115_bios()
{
FILE *f;
f=romfopen(L"roms/ide_at_1_1_5.bin",L"rb");
f=romfopen(L"roms/hdd/xtide/ide_at_1_1_5.bin",L"rb");
if (f)
{
@@ -97,8 +97,8 @@ int loadbios()
FILE *f=NULL,*ff=NULL;
int c;
loadfont(L"roms/mda.rom", 0);
loadfont(L"roms/wy700.rom", 3);
loadfont(L"roms/graphics/mda/mda.rom", 0);
loadfont(L"roms/graphics/wyse700/wy700.rom", 3);
biosmask = 0xffff;
@@ -114,8 +114,8 @@ int loadbios()
switch (romset)
{
case ROM_PC1512:
f=romfopen(L"roms/pc1512/40043.v1",L"rb");
ff=romfopen(L"roms/pc1512/40044.v1",L"rb");
f=romfopen(L"roms/machines/pc1512/40043.v1",L"rb");
ff=romfopen(L"roms/machines/pc1512/40044.v1",L"rb");
if (!f || !ff) break;
for (c=0xC000;c<0x10000;c+=2)
{
@@ -124,11 +124,11 @@ int loadbios()
}
fclose(ff);
fclose(f);
loadfont(L"roms/pc1512/40078.ic127", 2);
loadfont(L"roms/machines/pc1512/40078.ic127", 2);
return 1;
case ROM_PC1640:
f=romfopen(L"roms/pc1640/40044.v3",L"rb");
ff=romfopen(L"roms/pc1640/40043.v3",L"rb");
f=romfopen(L"roms/machines/pc1640/40044.v3",L"rb");
ff=romfopen(L"roms/machines/pc1640/40043.v3",L"rb");
if (!f || !ff) break;
for (c=0xC000;c<0x10000;c+=2)
{
@@ -137,13 +137,13 @@ int loadbios()
}
fclose(ff);
fclose(f);
f=romfopen(L"roms/pc1640/40100",L"rb");
f=romfopen(L"roms/machines/pc1640/40100",L"rb");
if (!f) break;
fclose(f);
return 1;
case ROM_PC200:
f=romfopen(L"roms/pc200/pc20v2.1",L"rb");
ff=romfopen(L"roms/pc200/pc20v2.0",L"rb");
f=romfopen(L"roms/machines/pc200/pc20v2.1",L"rb");
ff=romfopen(L"roms/machines/pc200/pc20v2.0",L"rb");
if (!f || !ff) break;
for (c=0xC000;c<0x10000;c+=2)
{
@@ -152,24 +152,24 @@ int loadbios()
}
fclose(ff);
fclose(f);
loadfont(L"roms/pc200/40109.bin", 1);
loadfont(L"roms/machines/pc200/40109.bin", 1);
return 1;
case ROM_TANDY:
f=romfopen(L"roms/tandy/tandy1t1.020",L"rb");
f=romfopen(L"roms/machines/tandy/tandy1t1.020",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_TANDY1000HX:
f = romfopen(L"roms/tandy1000hx/v020000.u12", L"rb");
f = romfopen(L"roms/machines/tandy1000hx/v020000.u12", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
biosmask = 0x1ffff;
return 1;
case ROM_TANDY1000SL2:
f = romfopen(L"roms/tandy1000sl2/8079047.hu1" ,L"rb");
ff = romfopen(L"roms/tandy1000sl2/8079048.hu2",L"rb");
f = romfopen(L"roms/machines/tandy1000sl2/8079047.hu1" ,L"rb");
ff = romfopen(L"roms/machines/tandy1000sl2/8079048.hu2",L"rb");
if (!f || !ff) break;
fseek(f, 0x30000/2, SEEK_SET);
fseek(ff, 0x30000/2, SEEK_SET);
@@ -182,11 +182,11 @@ int loadbios()
fclose(f);
return 1;
case ROM_IBMXT:
f=romfopen(L"roms/ibmxt/xt.rom",L"rb");
f=romfopen(L"roms/machines/ibmxt/xt.rom",L"rb");
if (!f)
{
f = romfopen(L"roms/ibmxt/5000027.u19", L"rb");
ff = romfopen(L"roms/ibmxt/1501512.u18", L"rb");
f = romfopen(L"roms/machines/ibmxt/5000027.u19", L"rb");
ff = romfopen(L"roms/machines/ibmxt/1501512.u18", L"rb");
if (!f || !ff) break;
fread(rom, 0x8000, 1, f);
fread(rom + 0x8000, 0x8000, 1, ff);
@@ -203,22 +203,22 @@ int loadbios()
break;
case ROM_IBMPCJR:
f = romfopen(L"roms/ibmpcjr/bios.rom", L"rb");
f = romfopen(L"roms/machines/ibmpcjr/bios.rom", L"rb");
if (!f) break;
fread(rom, 0x10000, 1, f);
fclose(f);
return 1;
case ROM_PORTABLE:
f=romfopen(L"roms/portable/Compaq Portable Plus 100666-001 Rev C u47.bin",L"rb");
f=romfopen(L"roms/machines/portable/Compaq Portable Plus 100666-001 Rev C u47.bin",L"rb");
if (!f) break;
fread(rom+0xE000,8192,1,f);
fclose(f);
return 1;
case ROM_PORTABLEII:
f = romfopen(L"roms/portableii/62x0820.u27", L"rb");
ff =romfopen(L"roms/portableii/62x0821.u47", L"rb");
f = romfopen(L"roms/machines/portableii/62x0820.u27", L"rb");
ff =romfopen(L"roms/machines/portableii/62x0821.u47", L"rb");
if (!f || !ff) break;
for (c=0x0000;c<0x10000;c+=2)
{
@@ -230,9 +230,9 @@ int loadbios()
return 1;
case ROM_PORTABLEIII:
case ROM_PORTABLEIII386:
f = romfopen(L"roms/portableiii/62x0820.u27", L"rb");
ff =romfopen(L"roms/portableiii/62x0821.u47", L"rb");
case ROM_PORTABLEIII386:
f = romfopen(L"roms/machines/portableiii/62x0820.u27", L"rb");
ff =romfopen(L"roms/machines/portableiii/62x0821.u47", L"rb");
if (!f || !ff) break;
for (c=0x0000;c<0x10000;c+=2)
{
@@ -244,20 +244,20 @@ int loadbios()
return 1;
case ROM_GENXT:
f=romfopen(L"roms/genxt/pcxt.rom",L"rb");
f=romfopen(L"roms/machines/genxt/pcxt.rom",L"rb");
if (!f) break;
fread(rom+0xE000,8192,1,f);
fclose(f);
return 1;
case ROM_DTKXT:
f=romfopen(L"roms/dtk/DTK_ERSO_2.42_2764.bin",L"rb");
f=romfopen(L"roms/machines/dtk/DTK_ERSO_2.42_2764.bin",L"rb");
if (!f) break;
fread(rom+0xE000,8192,1,f);
fclose(f);
return 1;
case ROM_OLIM24:
f = romfopen(L"roms/olivetti_m24/olivetti_m24_version_1.43_low.bin" ,L"rb");
ff = romfopen(L"roms/olivetti_m24/olivetti_m24_version_1.43_high.bin",L"rb");
f = romfopen(L"roms/machines/olivetti_m24/olivetti_m24_version_1.43_low.bin" ,L"rb");
ff = romfopen(L"roms/machines/olivetti_m24/olivetti_m24_version_1.43_high.bin",L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x4000; c += 2)
{
@@ -269,8 +269,8 @@ int loadbios()
return 1;
case ROM_PC2086:
f = romfopen(L"roms/pc2086/40179.ic129" ,L"rb");
ff = romfopen(L"roms/pc2086/40180.ic132",L"rb");
f = romfopen(L"roms/machines/pc2086/40179.ic129" ,L"rb");
ff = romfopen(L"roms/machines/pc2086/40180.ic132",L"rb");
if (!f || !ff) break;
pclog("Loading BIOS\n");
for (c = 0x0000; c < 0x4000; c += 2)
@@ -281,26 +281,26 @@ int loadbios()
pclog("%02X %02X %02X\n", rom[0xfff0], rom[0xfff1], rom[0xfff2]);
fclose(ff);
fclose(f);
f = romfopen(L"roms/pc2086/40186.ic171", L"rb");
f = romfopen(L"roms/machines/pc2086/40186.ic171", L"rb");
if (!f) break;
fclose(f);
biosmask = 0x3fff;
return 1;
case ROM_PC3086:
f = romfopen(L"roms/pc3086/fc00.bin", L"rb");
f = romfopen(L"roms/machines/pc3086/fc00.bin", L"rb");
if (!f) break;
fread(rom, 0x4000, 1, f);
fclose(f);
f = romfopen(L"roms/pc3086/c000.bin", L"rb");
f = romfopen(L"roms/machines/pc3086/c000.bin", L"rb");
if (!f) break;
fclose(f);
biosmask = 0x3fff;
return 1;
case ROM_IBMAT:
f = romfopen(L"roms/ibmat/62x0820.u27", L"rb");
ff =romfopen(L"roms/ibmat/62x0821.u47", L"rb");
f = romfopen(L"roms/machines/ibmat/62x0820.u27", L"rb");
ff =romfopen(L"roms/machines/ibmat/62x0821.u47", L"rb");
if (!f || !ff) break;
for (c=0x0000;c<0x10000;c+=2)
{
@@ -310,9 +310,10 @@ int loadbios()
fclose(ff);
fclose(f);
return 1;
case ROM_CMDPC30:
f = romfopen(L"roms/cmdpc30/commodore pc 30 iii even.bin", L"rb");
ff = romfopen(L"roms/cmdpc30/commodore pc 30 iii odd.bin", L"rb");
f = romfopen(L"roms/machines/cmdpc30/commodore pc 30 iii even.bin", L"rb");
ff = romfopen(L"roms/machines/cmdpc30/commodore pc 30 iii odd.bin", L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x8000; c += 2)
{
@@ -323,68 +324,69 @@ int loadbios()
fclose(f);
biosmask = 0x7fff;
return 1;
case ROM_AMI386SX:
f=romfopen(L"roms/ami386/ami386.bin",L"rb");
f=romfopen(L"roms/machines/ami386/ami386.bin",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_AMI386DX_OPTI495: /*This uses the OPTi 82C495 chipset*/
f=romfopen(L"roms/ami386dx/OPT495SX.AMI",L"rb");
f=romfopen(L"roms/machines/ami386dx/OPT495SX.AMI",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_MR386DX_OPTI495: /*This uses the OPTi 82C495 chipset*/
f=romfopen(L"roms/mr386dx/OPT495SX.MR",L"rb");
f=romfopen(L"roms/machines/mr386dx/OPT495SX.MR",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_AMI286:
f=romfopen(L"roms/ami286/amic206.bin",L"rb");
f=romfopen(L"roms/machines/ami286/amic206.bin",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_AWARD286:
f=romfopen(L"roms/award286/award.bin",L"rb");
f=romfopen(L"roms/machines/award286/award.bin",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_EUROPC:
f=romfopen(L"roms/europc/50145",L"rb");
f=romfopen(L"roms/machines/europc/50145",L"rb");
if (!f) break;
fread(rom+0x8000,32768,1,f);
fclose(f);
return 1;
case ROM_IBMPC:
f=romfopen(L"roms/ibmpc/pc102782.bin",L"rb");
f=romfopen(L"roms/machines/ibmpc/pc102782.bin",L"rb");
if (!f) break;
fread(rom+0xE000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ibmpc/ibm-basic-1.10.rom",L"rb");
if (!f)
{
f=romfopen(L"roms/ibmpc/basicc11.f6",L"rb");
f=romfopen(L"roms/machines/ibmpc/basicc11.f6",L"rb");
if (!f) return 1; /*I don't really care if BASIC is there or not*/
fread(rom+0x6000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ibmpc/basicc11.f8",L"rb");
f=romfopen(L"roms/machines/ibmpc/basicc11.f8",L"rb");
if (!f) break; /*But if some of it is there, then all of it must be*/
fread(rom+0x8000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ibmpc/basicc11.fa",L"rb");
f=romfopen(L"roms/machines/ibmpc/basicc11.fa",L"rb");
if (!f) break;
fread(rom+0xA000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ibmpc/basicc11.fc",L"rb");
f=romfopen(L"roms/machines/ibmpc/basicc11.fc",L"rb");
if (!f) break;
fread(rom+0xC000,8192,1,f);
fclose(f);
@@ -399,8 +401,8 @@ int loadbios()
case ROM_MEGAPC:
case ROM_MEGAPCDX:
f = romfopen(L"roms/megapc/41651-bios lo.u18", L"rb");
ff = romfopen(L"roms/megapc/211253-bios hi.u19", L"rb");
f = romfopen(L"roms/machines/megapc/41651-bios lo.u18", L"rb");
ff = romfopen(L"roms/machines/megapc/211253-bios hi.u19", L"rb");
if (!f || !ff) break;
fseek(f, 0x8000, SEEK_SET);
fseek(ff, 0x8000, SEEK_SET);
@@ -414,21 +416,21 @@ int loadbios()
return 1;
case ROM_AMI486:
f=romfopen(L"roms/ami486/ami486.BIN",L"rb");
f=romfopen(L"roms/machines/ami486/ami486.BIN",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_WIN486:
f=romfopen(L"roms/win486/ALI1429G.AMW",L"rb");
f=romfopen(L"roms/machines/win486/ALI1429G.AMW",L"rb");
if (!f) break;
fread(rom,65536,1,f);
fclose(f);
return 1;
case ROM_SIS496:
f = romfopen(L"roms/sis496/SIS496_3.AWA", L"rb");
f = romfopen(L"roms/machines/sis496/SIS496_3.AWA", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -438,7 +440,7 @@ int loadbios()
#if 0
case ROM_430VX:
f = romfopen(L"roms/430vx/55XWUQ0E.BIN", L"rb");
f = romfopen(L"roms/machines/430vx/55XWUQ0E.BIN", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -447,12 +449,12 @@ int loadbios()
#endif
case ROM_REVENGE:
f = romfopen(L"roms/revenge/1009AF2_.BIO", L"rb");
f = romfopen(L"roms/machines/revenge/1009AF2_.BIO", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom + 0x10000, 0x10000, 1, f);
fclose(f);
f = romfopen(L"roms/revenge/1009AF2_.BI1", L"rb");
f = romfopen(L"roms/machines/revenge/1009AF2_.BI1", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom, 0xc000, 1, f);
@@ -460,12 +462,12 @@ int loadbios()
biosmask = 0x1ffff;
return 1;
case ROM_ENDEAVOR:
f = romfopen(L"roms/endeavor/1006CB0_.BIO", L"rb");
f = romfopen(L"roms/machines/endeavor/1006CB0_.BIO", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom + 0x10000, 0x10000, 1, f);
fclose(f);
f = romfopen(L"roms/endeavor/1006CB0_.BI1", L"rb");
f = romfopen(L"roms/machines/endeavor/1006CB0_.BI1", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom, 0xd000, 1, f);
@@ -474,7 +476,7 @@ int loadbios()
return 1;
case ROM_IBMPS1_2011:
f = romfopen(L"roms/ibmps1es/f80000.bin", L"rb");
f = romfopen(L"roms/machines/ibmps1es/f80000.bin", L"rb");
if (!f) break;
fseek(f, 0x60000, SEEK_SET);
fread(rom, 0x20000, 1, f);
@@ -484,7 +486,7 @@ int loadbios()
case ROM_IBMPS1_2121:
case ROM_IBMPS1_2121_ISA:
f = romfopen(L"roms/ibmps1_2121/fc0000.bin", L"rb");
f = romfopen(L"roms/machines/ibmps1_2121/fc0000.bin", L"rb");
if (!f) break;
fseek(f, 0x20000, SEEK_SET);
fread(rom, 0x20000, 1, f);
@@ -497,7 +499,7 @@ int loadbios()
return 1;
case ROM_IBMPS1_2133:
f = romfopen(L"roms/ibmps1_2133/PS1_2133_52G2974_ROM.bin", L"rb");
f = romfopen(L"roms/machines/ibmps1_2133/PS1_2133_52G2974_ROM.bin", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -505,8 +507,8 @@ int loadbios()
return 1;
case ROM_DESKPRO_386:
f=romfopen(L"roms/deskpro386/109592-005.U11.bin",L"rb");
ff=romfopen(L"roms/deskpro386/109591-005.U13.bin",L"rb");
f=romfopen(L"roms/machines/deskpro386/109592-005.U11.bin",L"rb");
ff=romfopen(L"roms/machines/deskpro386/109591-005.U13.bin",L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x8000; c += 2)
{
@@ -519,33 +521,33 @@ int loadbios()
return 1;
case ROM_AMIXT:
f = romfopen(L"roms/amixt/AMI_8088_BIOS_31JAN89.BIN", L"rb");
f = romfopen(L"roms/machines/amixt/AMI_8088_BIOS_31JAN89.BIN", L"rb");
if (!f) break;
fread(rom + 0xE000, 8192, 1, f);
fclose(f);
return 1;
case ROM_LTXT:
f = romfopen(L"roms/ltxt/27C64.bin", L"rb");
f = romfopen(L"roms/machines/ltxt/27C64.bin", L"rb");
if (!f) break;
fread(rom + 0xE000, 8192, 1, f);
fclose(f);
f=romfopen(L"roms/ltxt/ibm-basic-1.10.rom",L"rb");
if (!f)
{
f=romfopen(L"roms/ltxt/basicc11.f6",L"rb");
f=romfopen(L"roms/machines/ltxt/basicc11.f6",L"rb");
if (!f) return 1; /*I don't really care if BASIC is there or not*/
fread(rom+0x6000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ltxt/basicc11.f8",L"rb");
f=romfopen(L"roms/machines/ltxt/basicc11.f8",L"rb");
if (!f) break; /*But if some of it is there, then all of it must be*/
fread(rom+0x8000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ltxt/basicc11.fa",L"rb");
f=romfopen(L"roms/machines/ltxt/basicc11.fa",L"rb");
if (!f) break;
fread(rom+0xA000,8192,1,f);
fclose(f);
f=romfopen(L"roms/ltxt/basicc11.fc",L"rb");
f=romfopen(L"roms/machines/ltxt/basicc11.fc",L"rb");
if (!f) break;
fread(rom+0xC000,8192,1,f);
fclose(f);
@@ -559,26 +561,26 @@ int loadbios()
return 1;
case ROM_LXT3:
f = romfopen(L"roms/lxt3/27C64D.bin", L"rb");
f = romfopen(L"roms/machines/lxt3/27C64D.bin", L"rb");
if (!f) break;
fread(rom + 0xE000, 8192, 1, f);
fclose(f);
f=romfopen(L"roms/lxt3/ibm-basic-1.10.rom",L"rb");
f=romfopen(L"roms/machines/lxt3/ibm-basic-1.10.rom",L"rb");
if (!f)
{
f=romfopen(L"roms/lxt3/basicc11.f6",L"rb");
f=romfopen(L"roms/machines/lxt3/basicc11.f6",L"rb");
if (!f) return 1; /*I don't really care if BASIC is there or not*/
fread(rom+0x6000,8192,1,f);
fclose(f);
f=romfopen(L"roms/lxt3/basicc11.f8",L"rb");
f=romfopen(L"roms/machines/lxt3/basicc11.f8",L"rb");
if (!f) break; /*But if some of it is there, then all of it must be*/
fread(rom+0x8000,8192,1,f);
fclose(f);
f=romfopen(L"roms/lxt3/basicc11.fa",L"rb");
f=romfopen(L"roms/machines/lxt3/basicc11.fa",L"rb");
if (!f) break;
fread(rom+0xA000,8192,1,f);
fclose(f);
f=romfopen(L"roms/lxt3/basicc11.fc",L"rb");
f=romfopen(L"roms/machines/lxt3/basicc11.fc",L"rb");
if (!f) break;
fread(rom+0xC000,8192,1,f);
fclose(f);
@@ -592,42 +594,42 @@ int loadbios()
return 1;
case ROM_SPC4200P: /*Samsung SPC-4200P*/
f = romfopen(L"roms/spc4200p/U8.01", L"rb");
f = romfopen(L"roms/machines/spc4200p/U8.01", L"rb");
if (!f) break;
fread(rom, 65536, 1, f);
fclose(f);
return 1;
case ROM_SUPER286TR: /*Hyundai Super-286TR*/
f = romfopen(L"roms/super286tr/hyundai_award286.bin", L"rb");
f = romfopen(L"roms/machines/super286tr/hyundai_award286.bin", L"rb");
if (!f) break;
fread(rom, 65536, 1, f);
fclose(f);
return 1;
case ROM_DTK386: /*Uses NEAT chipset*/
f = romfopen(L"roms/dtk386/3cto001.bin", L"rb");
f = romfopen(L"roms/machines/dtk386/3cto001.bin", L"rb");
if (!f) break;
fread(rom, 65536, 1, f);
fclose(f);
return 1;
case ROM_PXXT:
f = romfopen(L"roms/pxxt/000p001.bin", L"rb");
f = romfopen(L"roms/machines/pxxt/000p001.bin", L"rb");
if (!f) break;
fread(rom + 0xE000, 8192, 1, f);
fclose(f);
return 1;
case ROM_JUKOPC:
f = romfopen(L"roms/jukopc/000o001.bin", L"rb");
f = romfopen(L"roms/machines/jukopc/000o001.bin", L"rb");
if (!f) break;
fread(rom + 0xE000, 8192, 1, f);
fclose(f);
return 1;
case ROM_IBMPS2_M30_286:
f = romfopen(L"roms/ibmps2_m30_286/33f5381a.bin", L"rb");
f = romfopen(L"roms/machines/ibmps2_m30_286/33f5381a.bin", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -639,14 +641,14 @@ int loadbios()
return 1;
case ROM_DTK486:
f = romfopen(L"roms/dtk486/4siw005.bin", L"rb");
f = romfopen(L"roms/machines/dtk486/4siw005.bin", L"rb");
if (!f) break;
fread(rom, 0x10000, 1, f);
fclose(f);
return 1;
case ROM_R418:
f = romfopen(L"roms/r418/r418i.bin", L"rb");
f = romfopen(L"roms/machines/r418/r418i.bin", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -656,7 +658,7 @@ int loadbios()
#if 0
case ROM_586MC1:
f = romfopen(L"roms/586mc1/IS.34", L"rb");
f = romfopen(L"roms/machines/586mc1/IS.34", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -665,12 +667,12 @@ int loadbios()
#endif
case ROM_PLATO:
f = romfopen(L"roms/plato/1016AX1_.BIO", L"rb");
f = romfopen(L"roms/machines/plato/1016AX1_.BIO", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom + 0x10000, 0x10000, 1, f);
fclose(f);
f = romfopen(L"roms/plato/1016AX1_.BI1", L"rb");
f = romfopen(L"roms/machines/plato/1016AX1_.BI1", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom, 0xd000, 1, f);
@@ -679,7 +681,7 @@ int loadbios()
return 1;
case ROM_MB500N:
f = romfopen(L"roms/mb500n/031396S.BIN", L"rb"); /* Works */
f = romfopen(L"roms/machines/mb500n/031396S.BIN", L"rb"); /* Works */
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -687,7 +689,7 @@ int loadbios()
return 1;
case ROM_AP53:
f = romfopen(L"roms/ap53/AP53R2C0.ROM", L"rb"); /* Works */
f = romfopen(L"roms/machines/ap53/AP53R2C0.ROM", L"rb"); /* Works */
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -695,7 +697,7 @@ int loadbios()
return 1;
case ROM_P55T2S:
f = romfopen(L"roms/p55t2s/S6Y08T.ROM", L"rb"); /* Works */
f = romfopen(L"roms/machines/p55t2s/S6Y08T.ROM", L"rb"); /* Works */
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -703,7 +705,7 @@ int loadbios()
return 1;
case ROM_PRESIDENT:
f = romfopen(L"roms/president/BIOS.BIN", L"rb");
f = romfopen(L"roms/machines/president/BIOS.BIN", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -711,7 +713,7 @@ int loadbios()
return 1;
case ROM_P54TP4XE:
f = romfopen(L"roms/p54tp4xe/T15I0302.AWD", L"rb");
f = romfopen(L"roms/machines/p54tp4xe/T15I0302.AWD", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -719,15 +721,15 @@ int loadbios()
return 1;
case ROM_ACERM3A:
f = romfopen(L"roms/acerm3a/r01-b3.bin", L"rb");
f = romfopen(L"roms/machines/acerm3a/r01-b3.bin", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
biosmask = 0x1ffff;
return 1;
case ROM_ACERV35N:
f = romfopen(L"roms/acerv35n/V35ND1S1.BIN", L"rb");
case ROM_ACERV35N:
f = romfopen(L"roms/machines/acerv35n/V35ND1S1.BIN", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -735,7 +737,7 @@ int loadbios()
return 1;
case ROM_P55VA:
f = romfopen(L"roms/p55va/VA021297.BIN", L"rb");
f = romfopen(L"roms/machines/p55va/VA021297.BIN", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -743,7 +745,7 @@ int loadbios()
return 1;
case ROM_P55T2P4:
f = romfopen(L"roms/p55t2p4/0207_J2.BIN", L"rb");
f = romfopen(L"roms/machines/p55t2p4/0207_J2.BIN", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -751,7 +753,7 @@ int loadbios()
return 1;
case ROM_P55TVP4:
f = romfopen(L"roms/p55tvp4/TV5I0204.AWD", L"rb");
f = romfopen(L"roms/machines/p55tvp4/TV5I0204.AWD", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -759,7 +761,7 @@ int loadbios()
return 1;
case ROM_440FX:
f = romfopen(L"roms/440fx/NTMAW501.BIN", L"rb"); /* Working Tyan BIOS. */
f = romfopen(L"roms/machines/440fx/NTMAW501.BIN", L"rb"); /* Working Tyan BIOS. */
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -767,7 +769,7 @@ int loadbios()
return 1;
case ROM_S1668:
f = romfopen(L"roms/tpatx/S1668P.ROM", L"rb"); /* Working Tyan BIOS. */
f = romfopen(L"roms/machines/tpatx/S1668P.ROM", L"rb"); /* Working Tyan BIOS. */
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -775,12 +777,12 @@ int loadbios()
return 1;
case ROM_THOR:
f = romfopen(L"roms/thor/1006CN0_.BIO", L"rb");
f = romfopen(L"roms/machines/thor/1006CN0_.BIO", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom + 0x10000, 0x10000, 1, f);
fclose(f);
f = romfopen(L"roms/thor/1006CN0_.BI1", L"rb");
f = romfopen(L"roms/machines/thor/1006CN0_.BI1", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom, 0x10000, 1, f);
@@ -789,7 +791,7 @@ int loadbios()
return 1;
case ROM_MRTHOR:
f = romfopen(L"roms/mrthor/MR_ATX.BIO", L"rb");
f = romfopen(L"roms/machines/mrthor/MR_ATX.BIO", L"rb");
if (!f) break;
fread(rom, 0x20000, 1, f);
fclose(f);
@@ -797,12 +799,12 @@ int loadbios()
return 1;
case ROM_ZAPPA:
f = romfopen(L"roms/zappa/1006BS0_.BIO", L"rb");
f = romfopen(L"roms/machines/zappa/1006BS0_.BIO", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom + 0x10000, 0x10000, 1, f);
fclose(f);
f = romfopen(L"roms/zappa/1006BS0_.BI1", L"rb");
f = romfopen(L"roms/machines/zappa/1006BS0_.BI1", L"rb");
if (!f) break;
fseek(f, 0x80, SEEK_SET);
fread(rom, 0x10000, 1, f);
@@ -811,8 +813,8 @@ int loadbios()
return 1;
case ROM_IBMPS2_M50:
f=romfopen(L"roms/i8550021/90x7423.zm14",L"rb");
ff=romfopen(L"roms/i8550021/90x7426.zm16",L"rb");
f=romfopen(L"roms/machines/ibmps2_m50/90x7423.zm14",L"rb");
ff=romfopen(L"roms/machines/ibmps2_m50/90x7426.zm16",L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x10000; c += 2)
{
@@ -821,8 +823,8 @@ int loadbios()
}
fclose(ff);
fclose(f);
f=romfopen(L"roms/i8550021/90x7420.zm13",L"rb");
ff=romfopen(L"roms/i8550021/90x7429.zm18",L"rb");
f=romfopen(L"roms/machines/ibmps2_m50/90x7420.zm13",L"rb");
ff=romfopen(L"roms/machines/ibmps2_m50/90x7429.zm18",L"rb");
if (!f || !ff) break;
for (c = 0x10000; c < 0x20000; c += 2)
{
@@ -835,8 +837,8 @@ int loadbios()
return 1;
case ROM_IBMPS2_M55SX:
f=romfopen(L"roms/i8555081/33f8146.zm41",L"rb");
ff=romfopen(L"roms/i8555081/33f8145.zm40",L"rb");
f=romfopen(L"roms/machines/ibmps2_m55sx/33f8146.zm41",L"rb");
ff=romfopen(L"roms/machines/ibmps2_m55sx/33f8145.zm40",L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x20000; c += 2)
{
@@ -849,8 +851,8 @@ int loadbios()
return 1;
case ROM_IBMPS2_M80:
f=romfopen(L"roms/i8580111/15f6637.bin",L"rb");
ff=romfopen(L"roms/i8580111/15f6639.bin",L"rb");
f=romfopen(L"roms/machines/ibmps2_m80/15f6637.bin",L"rb");
ff=romfopen(L"roms/machines/ibmps2_m80/15f6639.bin",L"rb");
if (!f || !ff) break;
for (c = 0x0000; c < 0x20000; c += 2)
{
@@ -1059,9 +1061,30 @@ uint32_t mmutranslate(uint32_t addr, int rw, int is_abrt)
/* First check the flags of the page directory entry. */
table_flags = ((uint32_t *)ram)[table_addr >> 2];
if (mmu_page_fault_check(addr, rw, table_flags & 7, 1, is_abrt) == -1)
if ((table_flags & 0x80) && (cr4 & CR4_PSE))
{
return -1;
/* Do a PDE-style page fault check. */
if (mmu_page_fault_check(addr, rw, table_flags & 7, 0, is_abrt) == -1)
{
return -1;
}
/* Since PSE is not enabled, there is no page table, so we do a slightly modified skip to the end. */
if (is_abrt)
{
mmu_perm = table_flags & 4;
((uint32_t *)ram)[table_addr >> 2] |= (rw ? PAGE_DIRTY_AND_ACCESSED : PAGE_ACCESSED);
}
return (table_flags & ~0x3FFFFF) + (addr & 0x3FFFFF);
}
else
{
/* Do a non-PDE-style page fault check. */
if (mmu_page_fault_check(addr, rw, table_flags & 7, 1, is_abrt) == -1)
{
return -1;
}
}
page_addr = table_flags & ~0xfff;
@@ -2293,16 +2316,19 @@ static uint8_t port_92_read(uint16_t port, void *priv)
static void port_92_write(uint16_t port, uint8_t val, void *priv)
{
if (val & 1)
if ((mem_a20_alt ^ val) & 2)
{
mem_a20_alt = val & 2;
mem_a20_recalc();
}
if ((~port_92_reg & val) & 1)
{
softresetx86();
cpu_set_edx();
}
port_92_reg = val & ~-1;
mem_a20_alt = val & 2;
mem_a20_recalc();
port_92_reg = val;
}
void port_92_clear_reset()

1
src/mem.h
View File

@@ -38,6 +38,7 @@ extern int readlnum,writelnum;
extern int memspeed[11];
extern int nopageerrors;
extern uint32_t biosmask;
extern unsigned char isram[0x10000];
#define MEM_MAP_TO_SHADOW_RAM_MASK 1
#define MEM_MAP_TO_RAM_ADDR_MASK 2

8
src/mfm_xebec.c
View File

@@ -823,7 +823,7 @@ static void *xebec_init()
xebec_set_switches(xebec);
rom_init(&xebec->bios_rom, L"roms/ibm_xebec_62x0822_1985.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&xebec->bios_rom, L"roms/hdd/mfm_xebec/ibm_xebec_62x0822_1985.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
io_sethandler(0x0320, 0x0004, xebec_read, NULL, NULL, xebec_write, NULL, NULL, xebec);
@@ -849,7 +849,7 @@ static void xebec_close(void *p)
static int xebec_available()
{
return rom_present(L"roms/ibm_xebec_62x0822_1985.bin");
return rom_present(L"roms/hdd/mfm_xebec/ibm_xebec_62x0822_1985.bin");
}
device_t mfm_xebec_device =
@@ -890,7 +890,7 @@ static void *dtc_5150x_init()
xebec->drives[1].cfg_cyl = xebec->drives[1].tracks;
xebec->drives[1].cfg_hpc = xebec->drives[1].hpc;
rom_init(&xebec->bios_rom, L"roms/dtc_cxd21a.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&xebec->bios_rom, L"roms/hdd/mfm_xebec/dtc_cxd21a.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
io_sethandler(0x0320, 0x0004, xebec_read, NULL, NULL, xebec_write, NULL, NULL, xebec);
@@ -900,7 +900,7 @@ static void *dtc_5150x_init()
}
static int dtc_5150x_available()
{
return rom_present(L"roms/dtc_cxd21a.bin");
return rom_present(L"roms/hdd/mfm_xebec/dtc_cxd21a.bin");
}
device_t dtc_5150x_device =

149
src/model.c
View File

@@ -140,76 +140,88 @@ int romset;
MODEL models[] =
{
{"IBM PC", ROM_IBMPC, "ibmpc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 32, 0, xt_init, NULL },
{"IBM XT", ROM_IBMXT, "ibmxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"Compaq Portable", ROM_PORTABLE, "portable", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 128, 640, 128, 0, xt_init, NULL },
{"IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, pcjr_init, &pcjr_device },
{"Generic XT clone", ROM_GENXT, "genxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"AMI XT clone", ROM_AMIXT, "amixt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"DTK XT clone", ROM_DTKXT, "dtk", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL },
{"VTech Laser XT3", ROM_LXT3, "lxt3", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL },
{"Phoenix XT clone", ROM_PXXT, "pxxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"Juko XT clone", ROM_JUKOPC, "jukopc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"Tandy 1000", ROM_TANDY, "tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, tandy1k_init, &tandy1000_device },
{"Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 256, 640, 128, 0, tandy1k_init, &tandy1000hx_device },
{"Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 512, 768, 128, 0, tandy1ksl2_init, NULL },
{"Amstrad PC1512", ROM_PC1512, "pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL },
{"Sinclair PC200", ROM_PC200, "pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL },
{"Schneider EuroPC", ROM_EUROPC, "europc", {{"", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 512, 640, 128, 0, europc_init, NULL },
{"Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_OLIM24, 128, 640, 128, 0, olim24_init, NULL },
{"Amstrad PC1640", ROM_PC1640, "pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"Amstrad PC2086", ROM_PC2086, "pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"Amstrad PC3086", ROM_PC3086, "pc3086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 256,15872, 128, 63, ibm_at_init, NULL },
{"Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 640,16384, 128, 127, cmdpc30_init, NULL },
{"AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
{"Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 512,16384, 512, 127, ps1_m2011_init, NULL },
{"IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps2_m30_286_init, NULL },
{"IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 16, 1, 63, ps2_model_50_init, NULL },
{"IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
{"IBM PS/1 m.2121 + ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
{"IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 8, 1, 63, ps2_model_55sx_init, NULL },
{"DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
{"Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
{"AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_headland_init, NULL },
{"Compaq Deskpro 386", ROM_DESKPRO_386, "dekspro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, deskpro386_init, NULL },
{"Compaq Portable III 386", ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"IBM PS/2 Model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 12, 1, 63, ps2_model_80_init, NULL },
{"Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
{"MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
{"AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
{"IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 64, 1, 127, ps1_m2133_init, NULL },
{"AMI 486 clone", ROM_AMI486, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
{"AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
{"DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_dtk486_init, NULL },
{"Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 64, 1, 127, at_r418_init, NULL },
{"Intel Premiere/PCI", ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_batman_init, NULL },
{"[8088] AMI XT clone", ROM_AMIXT, "amixt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] Compaq Portable", ROM_PORTABLE, "portable", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 128, 640, 128, 0, xt_init, NULL },
{"[8088] DTK XT clone", ROM_DTKXT, "dtk", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] IBM PC", ROM_IBMPC, "ibmpc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 32, 0, xt_init, NULL },
{"[8088] IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, pcjr_init, &pcjr_device },
{"[8088] IBM XT", ROM_IBMXT, "ibmxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] Generic XT clone", ROM_GENXT, "genxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] Juko XT clone", ROM_JUKOPC, "jukopc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] Phoenix XT clone", ROM_PXXT, "pxxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL },
{"[8088] Schneider EuroPC", ROM_EUROPC, "europc", {{"", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 512, 640, 128, 0, europc_init, NULL },
{"[8088] Tandy 1000", ROM_TANDY, "tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, tandy1k_init, &tandy1000_device },
{"[8088] Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 256, 640, 128, 0, tandy1k_init, &tandy1000hx_device },
{"[8088] VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL },
{"[8088] VTech Laser XT3", ROM_LXT3, "lxt3", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL },
{"[8086] Amstrad PC1512", ROM_PC1512, "pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL },
{"[8086] Amstrad PC1640", ROM_PC1640, "pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"[8086] Amstrad PC2086", ROM_PC2086, "pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"[8086] Amstrad PC3086", ROM_PC3086, "pc3086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL },
{"[8086] Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_OLIM24, 128, 640, 128, 0, olim24_init, NULL },
{"[8086] Sinclair PC200", ROM_PC200, "pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL },
{"[8086] Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 512, 768, 128, 0, tandy1ksl2_init, NULL },
{"[286] AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
{"[286] Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"[286] Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"[286] Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"[286] Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 640,16384, 128, 127, cmdpc30_init, NULL },
{"[286] Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"[286] IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 256,15872, 128, 63, ibm_at_init, NULL },
{"[286] IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 512,16384, 512, 127, ps1_m2011_init, NULL },
{"[286] IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps2_m30_286_init, NULL },
{"[286] IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 16, 1, 63, ps2_model_50_init, NULL },
{"[286] Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 512,16384, 128, 127, at_scat_init, NULL },
{"[386SX] AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_headland_init, NULL },
{"[386SX] Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
{"[386SX] DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 512,16384, 128, 127, at_neat_init, NULL },
{"[386SX] IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
{"[386SX] IBM PS/1 m.2121+ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL },
{"[386SX] IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 8, 1, 63, ps2_model_55sx_init, NULL },
{"[386DX] AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
{"[386DX] Amstrad MegaPC 386DX",ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL },
{"[386DX] Compaq Deskpro 386", ROM_DESKPRO_386, "dekspro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, deskpro386_init, NULL },
{"[386DX] Compaq Portable III 386",ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL },
{"[386DX] IBM PS/2 Model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 12, 1, 63, ps2_model_80_init, NULL },
{"[386DX] MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL },
{"[486] AMI 486 clone", ROM_AMI486, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
{"[486] AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL },
{"[486] DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_dtk486_init, NULL },
{"[486] IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 64, 1, 127, ps1_m2133_init, NULL },
{"[486] Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 64, 1, 127, at_r418_init, NULL },
{"[Socket 4 LX] Intel Premiere/PCI",ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_batman_init, NULL },
#if 0
{"Micro Star 586MC1", ROM_586MC1, "586mc1", {{"Intel", cpus_Pentium5V50}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_586mc1_init, NULL },
{"[Socket 4 LX] Micro Star 586MC1",ROM_586MC1, "586mc1", {{"Intel", cpus_Pentium5V50}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_586mc1_init, NULL },
#endif
{"Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_plato_init, NULL },
{"Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL },
{"Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL },
{"PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_mb500n_init, NULL },
{"President Award 430FX PCI", ROM_PRESIDENT, "president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_president_init, NULL },
{"ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p54tp4xe_init, NULL },
{"Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL },
{"MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL },
{"AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_ap53_init, NULL },
{"ASUS P/I-P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2s_init, NULL },
{"Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerm3a_init, NULL },
{"Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerv35n_init, NULL },
{"ASUS P/I-P55T2P4", ROM_P55T2P4, "p55r2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2p4_init, NULL },
{"Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55va_init, NULL },
{"ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55tvp4_init, NULL },
{"Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_i440fx_init, NULL },
{"Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_s1668_init, NULL },
{"[Socket 5 NX] Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_plato_init, NULL },
{"[Socket 5 FX] ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p54tp4xe_init, NULL },
{"[Socket 5 FX] Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL },
{"[Socket 5 FX] Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL },
{"[Socket 5 FX] PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_mb500n_init, NULL },
{"[Socket 5 FX] President Award 430FX PCI",ROM_PRESIDENT,"president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_president_init, NULL },
{"[Socket 7 FX] Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL },
{"[Socket 7 FX] MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL },
{"[Socket 7 HX] Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerm3a_init, NULL },
{"[Socket 7 HX] Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerv35n_init, NULL },
{"[Socket 7 HX] AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_ap53_init, NULL },
{"[Socket 7 HX] ASUS P/I-P55T2P4", ROM_P55T2P4, "p55r2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2p4_init, NULL },
{"[Socket 7 HX] ASUS P/I-P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2s_init, NULL },
{"[Socket 7 VX] ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55tvp4_init, NULL },
{"[Socket 7 VX] Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55va_init, NULL },
{"[Socket 8 FX] Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_i440fx_init, NULL },
{"[Socket 8 FX] Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_s1668_init, NULL },
{"", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0,0, 0 }
};
@@ -403,6 +415,7 @@ void xt_laserxt_init(void)
void at_init(void)
{
AT = 1;
mem_a20_key = mem_a20_alt = 0;
common_init();
if (lpt_enabled)
{

2
src/model.h
View File

@@ -33,7 +33,7 @@
typedef struct {
char name[32];
char name[64];
int id;
char internal_name[24];
struct {

11
src/pc.c
View File

@@ -470,6 +470,17 @@ void resetpc_cad(void)
pc_keyboard_send(211); /* Delete key released */
}
void ctrl_alt_esc(void)
{
pc_keyboard_send(29); /* Ctrl key pressed */
pc_keyboard_send(56); /* Alt key pressed */
pc_keyboard_send(1); /* Esc key pressed */
pc_keyboard_send(157); /* Ctrl key released */
pc_keyboard_send(184); /* Alt key released */
pc_keyboard_send(129); /* Esc key released */
}
int suppress_overscan = 0;
void resetpchard_close(void)

10
src/ps1.c
View File

@@ -141,7 +141,7 @@ void ps1mb_init(void)
if (!enable_xtide)
{
rom_init(&ps1_high_rom,
L"roms/ibmps1es/f80000_shell.bin",
L"roms/machines/ibmps1es/f80000_shell.bin",
0xf80000,
0x80000,
0x7ffff,
@@ -149,8 +149,8 @@ void ps1mb_init(void)
MEM_MAPPING_EXTERNAL);
}
/* rom_init_interleaved(&ps1_high_rom,
L"roms/ibmps1es/ibm_1057757_24-05-90.bin",
L"roms/ibmps1es/ibm_1057757_29-15-90.bin",
L"roms/machines/ibmps1es/ibm_1057757_24-05-90.bin",
L"roms/machines/ibmps1es/ibm_1057757_29-15-90.bin",
0xfc0000,
0x40000,
0x3ffff,
@@ -294,12 +294,13 @@ void ps1mb_m2121_init(void)
io_sethandler(0x0190, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
rom_init(&ps1_high_rom,
L"roms/ibmps1_2121/fc0000_shell.bin",
L"roms/machines/ibmps1_2121/fc0000_shell.bin",
0xfc0000,
0x40000,
0x3ffff,
0,
MEM_MAPPING_EXTERNAL);
ps1_92 = 0;
ps1_190 = 0;
lpt1_init(0x3bc);
@@ -315,6 +316,7 @@ void ps1mb_m2133_init(void)
io_sethandler(0x0102, 0x0004, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_m2121_read, NULL, NULL, ps1_m2121_write, NULL, NULL, NULL);
ps1_92 = 0;
ps1_190 = 0;
lpt1_init(0x3bc);

1
src/ps2.c
View File

@@ -131,6 +131,7 @@ void ps2board_init(void)
io_sethandler(0x0322, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps2_read, NULL, NULL, ps2_write, NULL, NULL, NULL);
ps2_92 = 0;
ps2_190 = 0;
lpt1_init(0x3bc);

2
src/rom.c
View File

@@ -59,7 +59,7 @@ int rom_present(wchar_t *fn)
}
static uint8_t rom_read(uint32_t addr, void *p)
uint8_t rom_read(uint32_t addr, void *p)
{
rom_t *rom = (rom_t *)p;
#ifdef ROM_TRACE

4
src/rom.h
View File

@@ -15,3 +15,7 @@ typedef struct rom_t
int rom_init(rom_t *rom, wchar_t *fn, uint32_t address, int size, int mask, int file_offset, uint32_t flags);
int rom_init_interleaved(rom_t *rom, wchar_t *fn_low, wchar_t *fn_high, uint32_t address, int size, int mask, int file_offset, uint32_t flags);
uint8_t rom_read(uint32_t addr, void *p);
uint16_t rom_readw(uint32_t addr, void *p);
uint32_t rom_readl(uint32_t addr, void *p);

291
src/scat.c
View File

@@ -1,64 +1,35 @@
/* Copyright holders: Greatpsycho
see COPYING for more details
*/
/*This is the chipset used in the Award 286 clone model*/
#include "ibm.h"
#include "cpu/cpu.h"
#include "CPU/cpu.h"
#include "io.h"
#include "mem.h"
#include "device.h"
#include "model.h"
#define SCAT_DMA_WAIT_STATE_CONTROL 0x01
#define SCAT_VERSION 0x40
#define SCAT_CLOCK_CONTROL 0x41
#define SCAT_PERIPHERAL_CONTROL 0x44
#define SCAT_MISCELLANEOUS_STATUS 0x45
#define SCAT_POWER_MANAGEMENT 0x46
#define SCAT_ROM_ENABLE 0x48
#define SCAT_RAM_WRITE_PROTECT 0x49
#define SCAT_SHADOW_RAM_ENABLE_1 0x4A
#define SCAT_SHADOW_RAM_ENABLE_2 0x4B
#define SCAT_SHADOW_RAM_ENABLE_3 0x4C
#define SCAT_DRAM_CONFIGURATION 0x4D
#define SCAT_EXTENDED_BOUNDARY 0x4E
#define SCAT_EMS_CONTROL 0x4F
typedef struct {
uint8_t regs_2x8;
uint8_t regs_2x9;
} scat_t;
#include "scat.h"
#include "CPU/x86.h"
#include "CPU/cpu.h"
static uint8_t scat_regs[256];
static int scat_index;
static uint8_t scat_port_92 = 0;
static uint8_t scat_ems_reg_2xA = 0;
static mem_mapping_t scat_mapping[32];
static mem_mapping_t scat_high_mapping[16];
static scat_t scat_stat[32];
static uint32_t scat_xms_bound;
static mem_mapping_t scat_shadowram_mapping;
static mem_mapping_t scat_512k_clip_mapping;
static mem_mapping_t scat_4000_9FFF_mapping[24];
static mem_mapping_t scat_A000_BFFF_mapping;
uint8_t scat_read(uint16_t port, void *priv);
void scat_write(uint16_t port, uint8_t val, void *priv);
static void scat_shadow_state_update(void)
void scat_shadow_state_update()
{
int i, val;
for (i = 0; i < 24; i++)
{
if((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1)
{
val = MEM_READ_INTERNAL;
ram_mapped_addr[i + 40] |= 1;
}
else
{
val = MEM_READ_EXTERNAL;
ram_mapped_addr[i + 40] &= ~1;
}
val = ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_READ_INTERNAL : MEM_READ_EXTERNAL;
if (i < 8)
{
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
@@ -74,14 +45,13 @@ static void scat_shadow_state_update(void)
val |= ((scat_regs[SCAT_SHADOW_RAM_ENABLE_1 + (i >> 3)] >> (i & 7)) & 1) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTERNAL;
}
}
mem_set_mem_state((i + 40) << 14, 0x4000, val);
mem_set_mem_state((i + 40) << 14, 0x4000, val);
}
flushmmucache();
}
static void scat_set_xms_bound(uint8_t val)
void scat_set_xms_bound(uint8_t val)
{
uint32_t max_xms_size = (mem_size >= 16384) ? 0xFC0000 : mem_size << 10;
@@ -155,8 +125,7 @@ static void scat_set_xms_bound(uint8_t val)
}
}
static uint32_t get_scat_addr(uint32_t addr, scat_t *p)
uint32_t get_scat_addr(uint32_t addr, scat_t *p)
{
if (p && (scat_regs[SCAT_EMS_CONTROL] & 0x80) && (p->regs_2x9 & 0x80))
{
@@ -170,8 +139,33 @@ static uint32_t get_scat_addr(uint32_t addr, scat_t *p)
return addr;
}
void scat_set_global_EMS_state(int state)
{
int i;
uint32_t base_addr, virt_addr;
static void scat_write(uint16_t port, uint8_t val, void *priv)
for(i=0; i<32; i++)
{
base_addr = (i + 16) << 14;
if(i >= 24)
base_addr += 0x30000;
if(state && (scat_stat[i].regs_2x9 & 0x80))
{
virt_addr = get_scat_addr(base_addr, &scat_stat[i]);
if(i < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[i]);
mem_mapping_set_exec(&scat_mapping[i], ram + virt_addr);
mem_mapping_enable(&scat_mapping[i]);
}
else
{
mem_mapping_set_exec(&scat_mapping[i], ram + base_addr);
mem_mapping_disable(&scat_mapping[i]);
if(i < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
}
}
void scat_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t scat_reg_valid = 0, scat_shadow_update = 0, index;
uint32_t base_addr, virt_addr;
@@ -187,11 +181,32 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
{
case SCAT_CLOCK_CONTROL:
case SCAT_PERIPHERAL_CONTROL:
scat_reg_valid = 1;
break;
case SCAT_EMS_CONTROL:
if(val & 0x40)
{
if(val & 1)
{
io_sethandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
else
{
io_sethandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
}
else
{
io_removehandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_removehandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
}
scat_set_global_EMS_state(val & 0x80);
scat_reg_valid = 1;
break;
case SCAT_POWER_MANAGEMENT:
val &= 0x40; /* TODO - Only use AUX parity disable bit for this version. Other bits should be implemented later. */
val &= 0x40;
scat_reg_valid = 1;
break;
case SCAT_DRAM_CONFIGURATION:
@@ -212,6 +227,10 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
}
}
flushmmucache();
cpu_waitstates = (val & 0x70) == 0 ? 1 : 2;
cpu_update_waitstates();
scat_reg_valid = 1;
break;
case SCAT_EXTENDED_BOUNDARY:
@@ -235,7 +254,6 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
scat_regs[scat_index] = val;
if (scat_shadow_update)
scat_shadow_state_update();
pclog("Write SCAT Register %02X to %02X at %04X:%04X\n", scat_index, val, CS, cpu_state.pc);
break;
case 0x92:
@@ -247,7 +265,7 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
if ((~scat_port_92 & val) & 1)
{
softresetx86();
cpu_set_edx();
cpu_set_edx();
}
scat_port_92 = val;
break;
@@ -255,17 +273,11 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
if((scat_regs[SCAT_EMS_CONTROL] & 0x80) && (scat_stat[index].regs_2x9 & 0x80))
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
@@ -273,25 +285,29 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
ram_mapped_addr[base_addr >> 14] &= 1;
if (val & 0x80)
if (scat_regs[SCAT_EMS_CONTROL] & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
if (val & 0x80)
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(index < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
mem_mapping_enable(&scat_mapping[index]);
}
else
{
mem_mapping_set_exec(&scat_mapping[index], ram + base_addr);
mem_mapping_disable(&scat_mapping[index]);
if(index < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[index]);
}
flushmmucache();
}
else
{
pclog("Unmap page %d(address %06X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -302,7 +318,6 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
@@ -310,17 +325,11 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x8 = val;
base_addr = (index + 16) << 14;
if(index >= 24)
base_addr += 0x30000;
if(scat_stat[index].regs_2x9 & 0x80)
if((scat_regs[SCAT_EMS_CONTROL] & 0x80) && (scat_stat[index].regs_2x9 & 0x80))
{
ram_mapped_addr[base_addr >> 14] &= 0xFFC000FF;
ram_mapped_addr[base_addr >> 14] |= val << 14;
flushmmucache();
}
}
@@ -328,24 +337,31 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
scat_stat[index].regs_2x9 = val;
base_addr = (index + 16) << 14;
if (index >= 24)
base_addr += 0x30000;
if (val & 0x80)
if (scat_regs[SCAT_EMS_CONTROL] & 0x80)
{
virt_addr = (((scat_stat[index].regs_2x9 & 3) << 8) | scat_stat[index].regs_2x8) << 14;
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
ram_mapped_addr[base_addr >> 14] |= virt_addr | 2;
if (val & 0x80)
{
virt_addr = get_scat_addr(base_addr, &scat_stat[index]);
if(index < 24) mem_mapping_disable(&scat_4000_9FFF_mapping[index]);
mem_mapping_set_exec(&scat_mapping[index], ram + virt_addr);
mem_mapping_enable(&scat_mapping[index]);
pclog("Map page %d(address %05X) to address %06X\n", scat_ems_reg_2xA & 0x1f, base_addr, virt_addr);
}
else
{
mem_mapping_set_exec(&scat_mapping[index], ram + base_addr);
mem_mapping_disable(&scat_mapping[index]);
if(index < 24) mem_mapping_enable(&scat_4000_9FFF_mapping[index]);
pclog("Unmap page %d(address %05X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
}
else
{
pclog("Unmap page %d(address %05X)\n", scat_ems_reg_2xA & 0x1f, base_addr);
}
flushmmucache();
if (scat_ems_reg_2xA & 0x80)
{
@@ -356,15 +372,13 @@ static void scat_write(uint16_t port, uint8_t val, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Write SCAT EMS Control Port %04X to %02X at %04X:%04X\n", port, val, CS, cpu_state.pc);
scat_ems_reg_2xA = val;
}
break;
}
}
static uint8_t scat_read(uint16_t port, void *priv)
uint8_t scat_read(uint16_t port, void *priv)
{
uint8_t val = 0xff, index;
switch (port)
@@ -375,11 +389,13 @@ static uint8_t scat_read(uint16_t port, void *priv)
case SCAT_MISCELLANEOUS_STATUS:
val = (scat_regs[scat_index] & 0xbf) | ((mem_a20_key & 2) << 5);
break;
case SCAT_DRAM_CONFIGURATION:
val = (scat_regs[scat_index] & 0x8f) | (cpu_waitstates == 1 ? 0 : 0x10);
break;
default:
val = scat_regs[scat_index];
break;
}
pclog("Read SCAT Register %02X at %04X:%04X\n", scat_index, CS, cpu_state.pc);
break;
case 0x92:
@@ -389,7 +405,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x208:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@@ -397,7 +412,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x209:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@@ -405,7 +419,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x20A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x40)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;
@@ -413,7 +426,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x218:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x8;
}
@@ -421,7 +433,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x219:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
index = scat_ems_reg_2xA & 0x1F;
val = scat_stat[index].regs_2x9;
}
@@ -429,7 +440,6 @@ static uint8_t scat_read(uint16_t port, void *priv)
case 0x21A:
if ((scat_regs[SCAT_EMS_CONTROL] & 0x41) == 0x41)
{
pclog("Read SCAT EMS Control Port %04X at %04X:%04X\n", port, CS, cpu_state.pc);
val = scat_ems_reg_2xA;
}
break;
@@ -437,8 +447,7 @@ static uint8_t scat_read(uint16_t port, void *priv)
return val;
}
static uint8_t mem_read_scatems(uint32_t addr, void *priv)
uint8_t mem_read_scatems(uint32_t addr, void *priv)
{
uint8_t val = 0xff;
scat_t *stat = (scat_t *)priv;
@@ -450,34 +459,7 @@ static uint8_t mem_read_scatems(uint32_t addr, void *priv)
return val;
}
static uint16_t mem_read_scatemsw(uint32_t addr, void *priv)
{
uint16_t val = 0xffff;
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
val = mem_read_ramw(addr, priv);
return val;
}
static uint32_t mem_read_scatemsl(uint32_t addr, void *priv)
{
uint32_t val = 0xffffffff;
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
val = mem_read_raml(addr, priv);
return val;
}
static void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
@@ -486,46 +468,18 @@ static void mem_write_scatems(uint32_t addr, uint8_t val, void *priv)
mem_write_ram(addr, val, priv);
}
static void mem_write_scatemsw(uint32_t addr, uint16_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
mem_write_ramw(addr, val, priv);
}
static void mem_write_scatemsl(uint32_t addr, uint32_t val, void *priv)
{
scat_t *stat = (scat_t *)priv;
addr = get_scat_addr(addr, stat);
if (addr < (mem_size << 10))
mem_write_raml(addr, val, priv);
}
void scat_init(void)
void scat_init()
{
int i;
io_sethandler(0x0022, 0x0002, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0208, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
io_sethandler(0x0218, 0x0003, scat_read, NULL, NULL, scat_write, NULL, NULL, NULL);
for (i = 0; i < 256; i++)
{
scat_regs[i] = 0xff;
}
for (i = 0; i < 64; i++)
{
ram_mapped_addr[i] = 0;
}
scat_regs[SCAT_DMA_WAIT_STATE_CONTROL] = 0;
scat_regs[SCAT_VERSION] = 10;
scat_regs[SCAT_CLOCK_CONTROL] = 2;
@@ -537,17 +491,35 @@ void scat_init(void)
scat_regs[SCAT_SHADOW_RAM_ENABLE_1] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_2] = 0;
scat_regs[SCAT_SHADOW_RAM_ENABLE_3] = 0;
scat_regs[SCAT_DRAM_CONFIGURATION] = 2;
scat_regs[SCAT_DRAM_CONFIGURATION] = cpu_waitstates == 1 ? 2 : 0x12;
scat_regs[SCAT_EXTENDED_BOUNDARY] = 0;
scat_regs[SCAT_EMS_CONTROL] = 0;
scat_port_92 = 0;
mem_mapping_set_addr(&ram_low_mapping, 0, 0x40000);
for (i = 0; i < 24; i++)
{
if(mem_size > 256 + (i << 4))
{
mem_mapping_add(&scat_4000_9FFF_mapping[i], 0x40000 + (i << 14), 0x4000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0x40000 + (i << 14), MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_4000_9FFF_mapping[i]);
}
}
mem_mapping_add(&scat_A000_BFFF_mapping, 0xA0000, 0x20000, mem_read_ram, mem_read_ramw, mem_read_raml, mem_write_ram, mem_write_ramw, mem_write_raml, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_enable(&scat_A000_BFFF_mapping);
for (i = 0; i < 32; i++)
{
scat_stat[i].regs_2x8 = 0xff;
scat_stat[i].regs_2x9 = 0x03;
mem_mapping_add(&scat_mapping[i], (i + (i >= 24 ? 28 : 16)) << 14, 0x04000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + ((i + (i >= 24 ? 28 : 16)) << 14), 0, &scat_stat[i]);
mem_mapping_disable(&scat_mapping[i]);
}
/* TODO - Only normal CPU accessing address FF0000 to FFFFFF mapped to ROM. Normal CPU accessing address FC0000 to FEFFFF map to ROM should be implemented later. */
for(i=4;i<10;i++) isram[i] = 0;
for (i = 12; i < 16; i++)
{
mem_mapping_add(&scat_high_mapping[i], (i << 14) + 0xFC0000, 0x04000, mem_read_bios, mem_read_biosw, mem_read_biosl, mem_write_null, mem_write_nullw, mem_write_nulll, rom + (i << 14), 0, NULL);
@@ -555,14 +527,11 @@ void scat_init(void)
if (mem_size == 1024)
{
mem_mapping_add(&scat_shadowram_mapping, 0x100000, 0x60000, mem_read_scatems, mem_read_scatemsw, mem_read_scatemsl, mem_write_scatems, mem_write_scatemsw, mem_write_scatemsl, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&scat_shadowram_mapping, 0x100000, 0x60000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram + 0xA0000, MEM_MAPPING_INTERNAL, NULL);
}
/* Need to RAM 512kb clipping emulation if only 256KB or 64KB modules installed in memory bank.
TODO - 512KB clipping should be applied all RAM refer. */
mem_mapping_add(&scat_512k_clip_mapping, 0x80000, 0x20000, mem_read_scatems, mem_read_scatemsw, mem_read_scatemsl, mem_write_scatems, mem_write_scatemsw, mem_write_scatemsl, ram, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_add(&scat_512k_clip_mapping, 0x80000, 0x20000, mem_read_scatems, NULL, NULL, mem_write_scatems, NULL, NULL, ram, MEM_MAPPING_INTERNAL, NULL);
mem_mapping_disable(&scat_512k_clip_mapping);
/* --- */
scat_set_xms_bound(0);
scat_shadow_state_update();

22
src/scat.h Normal file
View File

@@ -0,0 +1,22 @@
#define SCAT_DMA_WAIT_STATE_CONTROL 0x01
#define SCAT_VERSION 0x40
#define SCAT_CLOCK_CONTROL 0x41
#define SCAT_PERIPHERAL_CONTROL 0x44
#define SCAT_MISCELLANEOUS_STATUS 0x45
#define SCAT_POWER_MANAGEMENT 0x46
#define SCAT_ROM_ENABLE 0x48
#define SCAT_RAM_WRITE_PROTECT 0x49
#define SCAT_SHADOW_RAM_ENABLE_1 0x4A
#define SCAT_SHADOW_RAM_ENABLE_2 0x4B
#define SCAT_SHADOW_RAM_ENABLE_3 0x4C
#define SCAT_DRAM_CONFIGURATION 0x4D
#define SCAT_EXTENDED_BOUNDARY 0x4E
#define SCAT_EMS_CONTROL 0x4F
typedef struct scat_t
{
uint8_t regs_2x8;
uint8_t regs_2x9;
} scat_t;
void scat_init();

10
src/scsi_aha154x.c
View File

@@ -47,12 +47,12 @@
#if AHA == AHA154xB
# define ROMFILE L"roms/adaptec/aha1540b310.bin"
# define ROMFILE L"roms/scsi/adaptec/aha1540b310.bin"
# define AHA_BID 'A' /* AHA-154x B */
#endif
#if AHA == AHA154xC
# define ROMFILE L"roms/adaptec/aha1542c101.bin"
# define ROMFILE L"roms/scsi/adaptec/aha1542c101.bin"
# define AHA_BID 'D' /* AHA-154x C */
# define ROM_FWHIGH 0x0022 /* firmware version (hi/lo) */
# define ROM_SHRAM 0x3F80 /* shadow RAM address base */
@@ -62,7 +62,7 @@
#endif
#if AHA == AHA154xCF
# define ROMFILE L"roms/adaptec/aha1542cf201.bin"
# define ROMFILE L"roms/scsi/adaptec/aha1542cf201.bin"
# define AHA_BID 'E' /* AHA-154x CF */
# define ROM_FWHIGH 0x0022 /* firmware version (hi/lo) */
# define ROM_SHRAM 0x3F80 /* shadow RAM address base */
@@ -72,7 +72,7 @@
#endif
#if AHA == AHA154xCP
# define ROMFILE L"roms/adaptec/aha1542cp102.bin"
# define ROMFILE L"roms/scsi/adaptec/aha1542cp102.bin"
# define AHA_BID 'F' /* AHA-154x CP */
# define ROM_FWHIGH 0x0055 /* firmware version (hi/lo) */
# define ROM_SHRAM 0x3F80 /* shadow RAM address base */
@@ -2462,4 +2462,4 @@ device_t aha1640_device = {
NULL,
NULL,
NULL
};
};

4
src/tandy_rom.c
View File

@@ -53,8 +53,8 @@ void *tandy_rom_init()
tandy_rom = malloc(0x80000);
f = romfopen(L"roms/tandy1000sl2/8079047.hu1", L"rb");
ff = romfopen(L"roms/tandy1000sl2/8079048.hu2", L"rb");
f = romfopen(L"roms/machines/tandy1000sl2/8079047.hu1", L"rb");
ff = romfopen(L"roms/machines/tandy1000sl2/8079048.hu2", L"rb");
for (c = 0x0000; c < 0x80000; c += 2)
{
tandy_rom[c] = getc(f);

22
src/xtide.c
View File

@@ -25,8 +25,8 @@
#include "xtide.h"
#define XTIDE_ROM_PATH L"roms/ide_xt.bin"
#define ATIDE_ROM_PATH L"roms/ide_at.bin"
#define XTIDE_ROM_PATH L"roms/hdd/xtide/ide_xt.bin"
#define ATIDE_ROM_PATH L"roms/hdd/xtide/ide_at.bin"
typedef struct xtide_t
@@ -120,7 +120,7 @@ static void *xtide_ps2_init(void)
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0, sizeof(xtide_t));
rom_init(&xtide->bios_rom, L"roms/SIDE1V12.BIN", 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&xtide->bios_rom, L"roms/hdd/xtide/SIDE1V12.BIN", 0xc8000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
ide_xtide_init();
io_sethandler(0x0360, 0x0010, xtide_read, NULL, NULL, xtide_write, NULL, NULL, xtide);
@@ -133,7 +133,7 @@ static void *xtide_at_ps2_init(void)
xtide_t *xtide = malloc(sizeof(xtide_t));
memset(xtide, 0, sizeof(xtide_t));
rom_init(&xtide->bios_rom, L"roms/ide_at_1_1_5.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
rom_init(&xtide->bios_rom, L"roms/hdd/xtide/ide_at_1_1_5.bin", 0xc8000, 0x4000, 0x3fff, 0, MEM_MAPPING_EXTERNAL);
ide_init();
return xtide;
@@ -150,25 +150,25 @@ static void xtide_close(void *p)
static int xtide_available(void)
{
return rom_present(L"roms/ide_xt.bin");
return rom_present(L"roms/hdd/xtide/ide_xt.bin");
}
static int xtide_at_available(void)
{
return rom_present(L"roms/ide_at.bin");
return rom_present(L"roms/hdd/xtide/ide_at.bin");
}
static int xtide_ps2_available(void)
{
return rom_present(L"roms/SIDE1V12.BIN");
return rom_present(L"roms/hdd/xtide/SIDE1V12.BIN");
}
static int xtide_at_ps2_available(void)
{
return rom_present(L"roms/ide_at_1_1_5.bin");
return rom_present(L"roms/hdd/xtide/ide_at_1_1_5.bin");
}
@@ -199,8 +199,8 @@ device_t xtide_at_device =
device_t xtide_ps2_device =
{
"XTIDE (PS/2)",
DEVICE_PS2,
"XTIDE (Acculogic)",
0,
xtide_ps2_init,
xtide_close,
xtide_ps2_available,
@@ -212,7 +212,7 @@ device_t xtide_ps2_device =
device_t xtide_at_ps2_device =
{
"XTIDE (AT) (PS/2)",
"XTIDE (AT) (1.1.5)",
DEVICE_PS2,
xtide_at_ps2_init,
xtide_close,