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standardise on "ramin" over "pramin", add cache status registers

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starfrost013
2025-01-28 23:35:25 +00:00
parent 04d91e2b1c
commit 5b3617efe6
5 changed files with 127 additions and 98 deletions
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135
src/include/86box/nv/vid_nv3.h
View File

@@ -14,7 +14,7 @@
* Also check the doc folder for some more notres
*
* vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
* Last updated: 2 January 2025 (STILL WORKING ON IT!!!)
* Last updated: 28 January 2025 (STILL WORKING ON IT!!!)
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
@@ -231,8 +231,8 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_RUNOUT_STATUS 0x2400
#define NV3_PFIFO_RUNOUT_STATUS_RANOUT 0 // 1 if we fucked up
#define NV3_PFIFO_RUNOUT_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_RUNOUT_STATUS_HIGH_MARK 8
#define NV3_PFIFO_RUNOUT_STATUS_EMPTY 4 // 1 if ramro is empty
#define NV3_PFIFO_RUNOUT_STATUS_FULL 8
#define NV3_PFIFO_RUNOUT_PUT 0x2410
#define NV3_PFIFO_RUNOUT_PUT_ADDRESS 3 // 9:3 if small ramfc(?) otherwise 12:3
#define NV3_PFIFO_RUNOUT_GET 0x2420
@@ -247,9 +247,8 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE0_PUSH_CHANNEL_ID 0x3004
#define NV3_PFIFO_CACHE0_PUT 0x3010
#define NV3_PFIFO_CACHE0_STATUS 0x3014
#define NV3_PFIFO_CACHE0_STATUS_RANOUT 0 // 1 if we fucked up
#define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8
#define NV3_PFIFO_CACHE0_STATUS_EMPTY 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE0_STATUS_FULL 8
#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit
#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040
#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0
@@ -268,8 +267,8 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE1_PUT_ADDRESS 2 // 6:2
#define NV3_PFIFO_CACHE1_STATUS 0x3214
#define NV3_PFIFO_CACHE1_STATUS_RANOUT 0 // 1 if we fucked up
#define NV3_PFIFO_CACHE1_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE1_STATUS_HIGH_MARK 8
#define NV3_PFIFO_CACHE1_STATUS_EMPTY 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE1_STATUS_FULL 8
#define NV3_PFIFO_CACHE1_DMA_STATUS 0x3218
#define NV3_PFIFO_CACHE1_DMA_CONFIG_0 0x3220
#define NV3_PFIFO_CACHE1_DMA_CONFIG_1 0x3224
@@ -583,32 +582,30 @@ extern const device_config_t nv3_config[];
// control structures for dma'd in graphics objects from pfifo
// these all have configurable sizes, define them here
#define NV3_PRAMIN_START 0x1C00000
#define NV3_RAMIN_START 0x1C00000
#define NV3_PRAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects
#define NV3_PRAMIN_RAMHT_END 0x1C00FFF
#define NV3_PRAMIN_RAMHT_SIZE_0 0xFFF
#define NV3_PRAMIN_RAMHT_SIZE_1 0x1FFF
#define NV3_PRAMIN_RAMHT_SIZE_2 0x3FFF
#define NV3_PRAMIN_RAMHT_SIZE_3 0x7FFF
#define NV3_RAMIN_RAMHT_START 0x1C00000 // Hashtable for storing submitted objects
#define NV3_RAMIN_RAMHT_END 0x1C00FFF
#define NV3_RAMIN_RAMHT_SIZE_0 0xFFF
#define NV3_RAMIN_RAMHT_SIZE_1 0x1FFF
#define NV3_RAMIN_RAMHT_SIZE_2 0x3FFF
#define NV3_RAMIN_RAMHT_SIZE_3 0x7FFF
/* OBSOLETE AREA for AUDIO probably. DO NOT USE! */
#define NV3_PRAMIN_RAMAU_START 0x1C01000
#define NV3_PRAMIN_RAMAU_END 0x1C01BFF
#define NV3_PRAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels
#define NV3_PRAMIN_RAMFC_END 0x1C01DFF
#define NV3_PRAMIN_RAMFC_SIZE_0 0x1FF
#define NV3_PRAMIN_RAMFC_SIZE_1 0xFFF
#define NV3_PRAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions
#define NV3_PRAMIN_RAMRO_SIZE_0 0x1FF
#define NV3_PRAMIN_RAMRO_SIZE_1 0x1FFF
#define NV3_PRAMIN_RAMRO_END 0x1C01FFF
#define NV3_PRAMIN_RAMRM_START 0x1C02000
#define NV3_PRAMIN_RAMRM_END 0x1C02FFF
#define NV3_RAMIN_RAMAU_START 0x1C01000
#define NV3_RAMIN_RAMAU_END 0x1C01BFF
#define NV3_RAMIN_RAMFC_START 0x1C01C00 // context for unused PFIFO DMA channels
#define NV3_RAMIN_RAMFC_END 0x1C01DFF
#define NV3_RAMIN_RAMFC_SIZE_0 0x1FF
#define NV3_RAMIN_RAMFC_SIZE_1 0xFFF
#define NV3_RAMIN_RAMRO_START 0x1C01E00 // Runout area for invalid submissions
#define NV3_RAMIN_RAMRO_SIZE_0 0x1FF
#define NV3_RAMIN_RAMRO_SIZE_1 0x1FFF
#define NV3_RAMIN_RAMRO_END 0x1C01FFF
#define NV3_RAMIN_RAMRM_START 0x1C02000
#define NV3_RAMIN_RAMRM_END 0x1C02FFF
#define NV3_PRAMIN_END 0x1FFFFFF
#define NV3_RAMIN_END 0x1FFFFFF
// not done
@@ -821,13 +818,19 @@ typedef struct nv3_pfifo_s
uint32_t ramht_config; // RAMHT config
uint32_t ramfc_config; // RAMFC config
uint32_t ramro_config; // RAMRO config
// Runout stuff
uint32_t runout_put;
uint32_t runout_get;
// Cache stuff
uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0?
nv3_pfifo_cache_t cache0_settings;
nv3_pfifo_cache_t cache1_settings;
nv3_pfifo_cache_entry_t cache0_entries[1];
nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS
} nv3_pfifo_t;
// create_object(uint32_t type) here
@@ -1047,7 +1050,7 @@ typedef struct nv3_ptimer_s
uint32_t alarm; // The value of time when there should be an alarm
} nv3_ptimer_t;
typedef struct nv3_pramin_name_s
typedef struct nv3_ramin_name_s
{
union
{
@@ -1062,9 +1065,9 @@ typedef struct nv3_pramin_name_s
};
};
} nv3_pramin_name_t;
} nv3_ramin_name_t;
typedef struct nv3_pramin_context_s
typedef struct nv3_ramin_context_s
{
union
{
@@ -1080,27 +1083,27 @@ typedef struct nv3_pramin_context_s
};
};
} nv3_pramin_context_t;
} nv3_ramin_context_t;
// Graphics object hashtable for specific DMA [channel, subchannel] pair
typedef struct nv3_pramin_ramht_subchannel_s
typedef struct nv3_ramin_ramht_subchannel_s
{
nv3_pramin_name_t name; // must be >4096
nv3_ramin_name_t name; // must be >4096
// Contextual information.
// See the above union.
nv3_pramin_context_t context;
} nv3_pramin_ramht_subchannel_t;
nv3_ramin_context_t context;
} nv3_ramin_ramht_subchannel_t;
// Graphics object hashtable
typedef struct nv3_pramin_ramht_s
typedef struct nv3_ramin_ramht_s
{
nv3_pramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL];
} nv3_pramin_ramht_t;
nv3_ramin_ramht_subchannel_t subchannels[NV3_DMA_CHANNELS][NV3_DMA_SUBCHANNELS_PER_CHANNEL];
} nv3_ramin_ramht_t;
uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel);
uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel);
typedef enum nv3_pramin_ramro_reason_e
typedef enum nv3_ramin_ramro_reason_e
{
nv3_runout_reason_illegal_access = 0,
@@ -1117,37 +1120,40 @@ typedef enum nv3_pramin_ramro_reason_e
// Access reserved by pagetable
nv3_runout_reason_reserved_access = 5,
} nv3_pramin_ramro_reason;
} nv3_ramin_ramro_reason;
/* This is a gigantic error handling system */
typedef struct nv3_pramin_ramro_entry_s
typedef struct nv3_ramin_ramro_entry_s
{
//todo
} nv3_pramin_ramro_entry_t;
} nv3_ramin_ramro_entry_t;
// Anti-fuckup device
typedef struct nv3_pramin_ramro_s
typedef struct nv3_ramin_ramro_s
{
} nv3_pramin_ramro_t;
} nv3_ramin_ramro_t;
// context for unused channels
typedef struct nv3_pramin_ramfc_s
typedef struct nv3_ramin_ramfc_s
{
} nv3_pramin_ramfc_t;
} nv3_ramin_ramfc_t;
// ????? ram auxillary
typedef struct nv_pramin_ramau_s
// RAM for AUDIO - RevisionA ONLY
typedef struct nv_ramin_ramau_s
{
} nv3_pramin_ramau_t;
} nv3_ramin_ramau_t;
typedef struct nv3_pramin_s
typedef struct nv3_ramin_s
{
} nv3_pramin_t;
} nv3_ramin_t;
// RAMIN functions
void nv3_ramin_find_object(uint32_t name, uint32_t cache_id, uint32_t channel_id, uint32_t subchannel_id);
typedef struct nv3_pvideo_s
{
@@ -1179,11 +1185,11 @@ typedef struct nv3_s
nv3_pgraph_t pgraph; // 2D/3D Graphics
nv3_pextdev_t pextdev; // Chip configuration
nv3_ptimer_t ptimer; // programmable interval timer
nv3_pramin_ramht_t ramht; // hashtable for PGRAPH objects
nv3_pramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission
nv3_pramin_ramfc_t ramfc; // context for unused channels
nv3_pramin_ramau_t ramau; // auxillary weirdnes
nv3_pramin_t pramin; // Ram for INput of DMA objects. Very important!
nv3_ramin_ramht_t ramht; // hashtable for PGRAPH objects
nv3_ramin_ramro_t ramro; // anti-fuckup mechanism for idiots who fucked up the FIFO submission
nv3_ramin_ramfc_t ramfc; // context for unused channels
nv3_ramin_ramau_t ramau; // auxillary weirdnes
nv3_ramin_t pramin; // Ram for INput of DMA objects. Very important!
nv3_pvideo_t pvideo; // Video overlay
nv3_pme_t pme; // Mediaport - external MPEG decoder and video interface
//more here
@@ -1222,8 +1228,8 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv);
void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv); // Write 16-bit RAMIN
void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv); // Write 32-bit RAMIN
bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin
bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin
bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value); // Read arbitration so we can read/write to the structures in the first 64k of ramin
bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value); // Write arbitration so we can read/write to the structures in the first 64k of ramin
uint32_t nv3_ramfc_read(uint32_t address);
void nv3_ramfc_write(uint32_t address, uint32_t value);
@@ -1284,7 +1290,7 @@ uint32_t nv3_user_read(uint32_t address);
void nv3_user_write(uint32_t address, uint32_t value);
#define nv3_object_submit_start nv3_user_read
#define nv3_object_submit_end nv3_user_write
// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_pramin_*
// TODO: RAMHT, RAMFC...or maybe handle it inside of nv3_ramin_*
// GPU subsystems
@@ -1311,6 +1317,7 @@ void nv3_pfifo_cache1_push();
void nv3_pfifo_cache1_pull();
uint32_t nv3_pfifo_cache1_normal2gray(uint32_t val);
uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val);
bool nv3_pfifo_cache1_is_free();
// NV3 PFB
void nv3_pfb_init();

8
src/video/nv/nv3/nv3_core_arbiter.c
View File

@@ -104,8 +104,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address)
else if (address >= NV3_USER_START && address <= NV3_USER_END)
ret = nv3_user_read(address);
// RAMIN is handled by a separate memory mapping in PCI BAR1
//else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END)
//ret = nv3_pramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function
//else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END)
//ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function
else
{
nv_log("NV3: MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address);
@@ -167,8 +167,8 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value)
nv3_vram_write(address, value);
else if (address >= NV3_USER_START && address <= NV3_USER_END)
nv3_user_write(address, value);
else if (address >= NV3_PRAMIN_START && address <= NV3_PRAMIN_END)
nv3_pramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions
else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END)
nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions
else
{
nv_log("NV3: MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address);

40
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -158,10 +158,28 @@ uint32_t nv3_pfifo_read(uint32_t address)
ret = nv3->pfifo.cache1_settings.channel_id;
break;
case NV3_PFIFO_CACHE0_STATUS:
/* Todo: Return values based on runout put/get*/
ret = nv3->pfifo.cache0_settings.status;
uint32_t ret = 0x00;
// CACHE0 has only one entry so it can only ever be empty or full
if (nv3->pfifo.cache0_settings.put_address == nv3->pfifo.cache1_settings.get_address)
ret |= 1 << NV3_PFIFO_CACHE0_STATUS_EMPTY;
else
ret |= 1 << NV3_PFIFO_CACHE0_STATUS_FULL;
break;
case NV3_PFIFO_CACHE1_STATUS:
if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address)
ret |= 1 << NV3_PFIFO_CACHE1_STATUS_EMPTY;
// Check if Cache1 (0x7C bytes in size depending on gpu?) is full
// Based on how the drivers do it
if (!nv3_pfifo_cache1_is_free())
ret |= 1 << NV3_PFIFO_CACHE1_STATUS_FULL;
if (nv3->pfifo.runout_put == nv3->pfifo.runout_get)
ret |= 1 << NV3_PFIFO_CACHE1_STATUS_RANOUT;
ret = nv3->pfifo.cache1_settings.status;
break;
case NV3_PFIFO_CACHE0_METHOD:
@@ -338,13 +356,7 @@ void nv3_pfifo_write(uint32_t address, uint32_t value)
case NV3_PFIFO_CACHE1_PUSH_CHANNEL_ID:
nv3->pfifo.cache1_settings.channel_id = value;
break;
case NV3_PFIFO_CACHE0_STATUS:
/* Todo: Return values based on runout put/get*/
nv3->pfifo.cache0_settings.status = value;
break;
case NV3_PFIFO_CACHE1_STATUS:
nv3->pfifo.cache1_settings.status = value;
break;
// CACHE0_STATUS and CACHE1_STATUS are not writable
case NV3_PFIFO_CACHE0_METHOD:
nv3->pfifo.cache0_settings.method_subchannel = (value >> 13) & 0x07;
nv3->pfifo.cache0_settings.method_address = (value >> 2) & 0x7FF;
@@ -432,4 +444,14 @@ void nv3_pfifo_cache1_push()
void nv3_pfifo_cache1_pull()
{
}
bool nv3_pfifo_cache1_is_free()
{
// convert to gray code
uint32_t real_get_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.get_address);
uint32_t real_put_address = nv3_pfifo_cache1_normal2gray(nv3->pfifo.cache1_settings.put_address);
// There is no hope of being able to understand it. Nobody can understand
return (real_get_address - real_put_address - 4) & 0x7C; // there are 64 entries what
}

40
src/video/nv/nv3/subsystems/nv3_pramin.c
View File

@@ -52,7 +52,7 @@ uint8_t nv3_ramin_read8(uint32_t addr, void* priv)
uint32_t val = 0x00;
if (!nv3_pramin_arbitrate_read(addr, &val)) // Oh well
if (!nv3_ramin_arbitrate_read(addr, &val)) // Oh well
{
val = (uint8_t)nv3->nvbase.svga.vram[addr];
nv_log("NV3: Read byte from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
@@ -78,7 +78,7 @@ uint16_t nv3_ramin_read16(uint32_t addr, void* priv)
uint32_t val = 0x00;
if (!nv3_pramin_arbitrate_read(addr, &val))
if (!nv3_ramin_arbitrate_read(addr, &val))
{
val = (uint16_t)vram_16bit[addr];
nv_log("NV3: Read word from PRAMIN addr=0x%08x (raw address=0x%08x)\n", addr, raw_addr);
@@ -104,7 +104,7 @@ uint32_t nv3_ramin_read32(uint32_t addr, void* priv)
uint32_t val = 0x00;
if (!nv3_pramin_arbitrate_read(addr, &val))
if (!nv3_ramin_arbitrate_read(addr, &val))
{
val = vram_32bit[addr];
@@ -130,7 +130,7 @@ void nv3_ramin_write8(uint32_t addr, uint8_t val, void* priv)
uint32_t val32 = 0x00;
if (!nv3_pramin_arbitrate_write(addr, val32))
if (!nv3_ramin_arbitrate_write(addr, val32))
{
nv3->nvbase.svga.vram[addr] = val;
nv_log("NV3: Write byte to PRAMIN addr=0x%08x val=0x%02x (raw address=0x%08x)\n", addr, val, raw_addr);
@@ -156,7 +156,7 @@ void nv3_ramin_write16(uint32_t addr, uint16_t val, void* priv)
uint32_t val32 = 0x00;
if (!nv3_pramin_arbitrate_write(addr, val32))
if (!nv3_ramin_arbitrate_write(addr, val32))
{
vram_16bit[addr] = val;
nv_log("NV3: Write word to PRAMIN addr=0x%08x val=0x%04x (raw address=0x%08x)\n", addr, val, raw_addr);
@@ -182,7 +182,7 @@ void nv3_ramin_write32(uint32_t addr, uint32_t val, void* priv)
uint32_t val32 = 0x00;
if (!nv3_pramin_arbitrate_write(addr, val32))
if (!nv3_ramin_arbitrate_write(addr, val32))
{
vram_32bit[addr] = val;
nv_log("NV3: Write dword to PRAMIN addr=0x%08x val=0x%08x (raw address=0x%08x)\n", addr, val, raw_addr);
@@ -198,7 +198,7 @@ and generic RAMIN
Takes a pointer to a result integer. This is because we need to check its result in our normal write function.
Returns true if a valid "non-generic" address was found (e.g. RAMFC/RAMRO/RAMHT). False if the specified address is a generic RAMIN address
*/
bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value)
bool nv3_ramin_arbitrate_read(uint32_t address, uint32_t* value)
{
if (!nv3) return 0x00;
@@ -220,26 +220,26 @@ bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value)
switch (ramht_size)
{
case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3;
break;
}
switch (ramro_size)
{
case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B:
ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0;
ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0;
break;
case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K:
ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1;
ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1;
break;
}
@@ -266,7 +266,7 @@ bool nv3_pramin_arbitrate_read(uint32_t address, uint32_t* value)
return false;
}
bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value)
bool nv3_ramin_arbitrate_write(uint32_t address, uint32_t value)
{
if (!nv3) return 0x00;
@@ -288,26 +288,26 @@ bool nv3_pramin_arbitrate_write(uint32_t address, uint32_t value)
switch (ramht_size)
{
case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_0;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_0;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_1;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_1;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_2;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_2;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K:
ramht_end = ramht_start + NV3_PRAMIN_RAMHT_SIZE_3;
ramht_end = ramht_start + NV3_RAMIN_RAMHT_SIZE_3;
break;
}
switch (ramro_size)
{
case NV3_PFIFO_CONFIG_RAMRO_SIZE_512B:
ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_0;
ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_0;
break;
case NV3_PFIFO_CONFIG_RAMRO_SIZE_8K:
ramro_end = ramro_start + NV3_PRAMIN_RAMRO_SIZE_1;
ramro_end = ramro_start + NV3_RAMIN_RAMRO_SIZE_1;
break;
}

2
src/video/nv/nv3/subsystems/nv3_pramin_ramht.c
View File

@@ -32,7 +32,7 @@
It is used to get the offset within RAMHT of a graphics object.
*/
uint32_t nv3_ramht_hash(nv3_pramin_name_t name, uint32_t channel)
uint32_t nv3_ramht_hash(nv3_ramin_name_t name, uint32_t channel)
{
uint32_t hash = (name.byte_high ^ name.byte_mid2 ^ name.byte_mid1 ^ name.byte_low ^ (uint8_t)channel);
nv_log("NV3: Generating RAMHT hash (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", name, channel);