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Macro Cleaning

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This commit is contained in:
Jasmine Iwanek
2025-02-01 03:29:03 -05:00
parent 34fbecb377
commit 5b894c32e6
26 changed files with 1384 additions and 1236 deletions
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3
src/codegen_new/codegen.c
View File

@@ -21,8 +21,7 @@
#define MAX_INSTRUCTION_COUNT 50
static struct
{
static struct {
uint32_t pc;
int op_ssegs;
x86seg *op_ea_seg;

3
src/codegen_new/codegen_accumulate.c
View File

@@ -8,8 +8,7 @@
#include "codegen_accumulate.h"
#include "codegen_ir.h"
static struct
{
static struct {
int count;
int dest_reg;
} acc_regs[] = {

45
src/codegen_new/codegen_ops_3dnow.c
View File

@@ -16,28 +16,29 @@
#include "codegen_ops_3dnow.h"
#include "codegen_ops_helpers.h"
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
codegen_mark_code_present(block, cs + op_pc + 1, 1); \
return op_pc + 2; \
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
codegen_mark_code_present(block, cs + op_pc + 1, 1); \
return op_pc + 2; \
}
// clang-format off

85
src/codegen_new/codegen_ops_branch.c
View File

@@ -815,41 +815,56 @@ ropJNLE_common(codeblock_t *block, ir_data_t *ir, uint32_t dest_addr, uint32_t n
}
}
#define ropJ(cond) \
uint32_t ropJ##cond##_8(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), uint32_t op_32, uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc); \
uint32_t dest_addr = op_pc + 1 + offset; \
int ret; \
\
if (!(op_32 & 0x100)) \
dest_addr &= 0xffff; \
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 1); \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
return ret ? dest_addr : (op_pc + 1); \
} \
uint32_t ropJ##cond##_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int16_t) fastreadw(cs + op_pc); \
uint32_t dest_addr = (op_pc + 2 + offset) & 0xffff; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 2); \
\
codegen_mark_code_present(block, cs + op_pc, 2); \
return ret ? dest_addr : (op_pc + 2); \
} \
uint32_t ropJ##cond##_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
uint32_t dest_addr = op_pc + 4 + offset; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 4); \
\
codegen_mark_code_present(block, cs + op_pc, 4); \
return ret ? dest_addr : (op_pc + 4); \
#define ropJ(cond) \
uint32_t ropJ##cond##_8(codeblock_t *block, \
ir_data_t *ir, \
UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), \
uint32_t op_32, \
uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int8_t) fastreadb(cs + op_pc); \
uint32_t dest_addr = op_pc + 1 + offset; \
int ret; \
\
if (!(op_32 & 0x100)) \
dest_addr &= 0xffff; \
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 1); \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
return ret ? dest_addr : (op_pc + 1); \
} \
uint32_t ropJ##cond##_16(codeblock_t *block, \
ir_data_t *ir, \
UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), \
UNUSED(uint32_t op_32), \
uint32_t op_pc) \
{ \
uint32_t offset = (int32_t) (int16_t) fastreadw(cs + op_pc); \
uint32_t dest_addr = (op_pc + 2 + offset) & 0xffff; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 2); \
\
codegen_mark_code_present(block, cs + op_pc, 2); \
return ret ? dest_addr : (op_pc + 2); \
} \
uint32_t ropJ##cond##_32(codeblock_t *block, \
ir_data_t *ir, \
UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), \
UNUSED(uint32_t op_32), \
uint32_t op_pc) \
{ \
uint32_t offset = fastreadl(cs + op_pc); \
uint32_t dest_addr = op_pc + 4 + offset; \
int ret; \
\
ret = ropJ##cond##_common(block, ir, dest_addr, op_pc + 4); \
\
codegen_mark_code_present(block, cs + op_pc, 4); \
return ret ? dest_addr : (op_pc + 4); \
}
// clang-format off

528
src/codegen_new/codegen_ops_fpu_arith.c
View File

@@ -300,131 +300,139 @@ ropFUCOMPP(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uin
return op_pc;
}
#define ropF_arith_mem(name, load_uop) \
uint32_t ropFADD##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
if ((cpu_state.npxc >> 10) & 3) \
return 0; \
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFCOM##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFCOMP##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFDIV##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFDIVR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFMUL##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUB##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUBR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
#define ropF_arith_mem(name, load_uop) \
uint32_t ropFADD##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
if ((cpu_state.npxc >> 10) & 3) \
return 0; \
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFCOM##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFCOMP##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFDIV##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFDIVR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFMUL##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUB##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFSUBR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
load_uop(ir, IREG_temp0_D, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
}
// clang-format off
@@ -432,137 +440,145 @@ ropF_arith_mem(s, uop_MEM_LOAD_SINGLE)
ropF_arith_mem(d, uop_MEM_LOAD_DOUBLE)
// clang-format on
#define ropFI_arith_mem(name, temp_reg) \
uint32_t ropFIADD##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFICOM##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFICOMP##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIV##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIVR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIMUL##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUB##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUBR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
#define ropFI_arith_mem(name, temp_reg) \
uint32_t ropFIADD##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FADD(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFICOM##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
\
return op_pc + 1; \
} \
uint32_t ropFICOMP##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FCOM(ir, IREG_temp1_W, IREG_ST(0), IREG_temp0_D); \
uop_AND_IMM(ir, IREG_NPXS, IREG_NPXS, ~(FPU_SW_C0 | FPU_SW_C2 | FPU_SW_C3)); \
uop_OR(ir, IREG_NPXS, IREG_NPXS, IREG_temp1_W); \
fpu_POP(block, ir); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIV##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIDIVR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FDIV(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFIMUL##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FMUL(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUB##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_ST(0), IREG_temp0_D); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
} \
uint32_t ropFISUBR##name(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg; \
\
uop_FP_ENTER(ir); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
op_pc--; \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, temp_reg, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MOV_DOUBLE_INT(ir, IREG_temp0_D, temp_reg); \
uop_FSUB(ir, IREG_ST(0), IREG_temp0_D, IREG_ST(0)); \
uop_MOV_IMM(ir, IREG_tag(0), TAG_VALID); \
\
return op_pc + 1; \
}
// clang-format off

92
src/codegen_new/codegen_ops_misc.c
View File

@@ -519,57 +519,61 @@ ropCWDE(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSE
return op_pc;
}
#define ropLxS(name, seg) \
uint32_t rop##name##_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg = NULL; \
int dest_reg = (fetchdat >> 3) & 7; \
\
if ((fetchdat & 0xc0) == 0xc0) \
return 0; \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2); \
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
uop_MOV(ir, IREG_16(dest_reg), IREG_temp0_W); \
\
if (seg == &cpu_state.seg_ss) \
CPU_BLOCK_END(); \
\
return op_pc + 1; \
} \
uint32_t rop##name##_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg = NULL; \
int dest_reg = (fetchdat >> 3) & 7; \
\
if ((fetchdat & 0xc0) == 0xc0) \
return 0; \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4); \
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
uop_MOV(ir, IREG_32(dest_reg), IREG_temp0); \
\
if (seg == &cpu_state.seg_ss) \
CPU_BLOCK_END(); \
\
return op_pc + 1; \
#define ropLxS(name, seg) \
uint32_t rop##name##_16(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg = NULL; \
int dest_reg = (fetchdat >> 3) & 7; \
\
if ((fetchdat & 0xc0) == 0xc0) \
return 0; \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 2); \
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
uop_MOV(ir, IREG_16(dest_reg), IREG_temp0_W); \
\
if (seg == &cpu_state.seg_ss) \
CPU_BLOCK_END(); \
\
return op_pc + 1; \
} \
uint32_t rop##name##_32(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
x86seg *target_seg = NULL; \
int dest_reg = (fetchdat >> 3) & 7; \
\
if ((fetchdat & 0xc0) == 0xc0) \
return 0; \
\
codegen_mark_code_present(block, cs + op_pc, 1); \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_MEM_LOAD_REG_OFFSET(ir, IREG_temp1_W, ireg_seg_base(target_seg), IREG_eaaddr, 4); \
uop_LOAD_SEG(ir, seg, IREG_temp1_W); \
uop_MOV(ir, IREG_32(dest_reg), IREG_temp0); \
\
if (seg == &cpu_state.seg_ss) \
CPU_BLOCK_END(); \
\
return op_pc + 1; \
}
// clang-format off
ropLxS(LDS, &cpu_state.seg_ds)
ropLxS(LES, &cpu_state.seg_es)
ropLxS(LFS, &cpu_state.seg_fs)
ropLxS(LGS, &cpu_state.seg_gs)
ropLxS(LSS, &cpu_state.seg_ss)
// clang-format on
uint32_t
ropCLC(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc)

43
src/codegen_new/codegen_ops_mmx_arith.c
View File

@@ -16,27 +16,28 @@
#include "codegen_ops_mmx_arith.h"
#include "codegen_ops_helpers.h"
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
#define ropParith(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
}
// clang-format off

43
src/codegen_new/codegen_ops_mmx_cmp.c
View File

@@ -16,27 +16,28 @@
#include "codegen_ops_mmx_cmp.h"
#include "codegen_ops_helpers.h"
#define ropPcmp(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
#define ropPcmp(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
}
// clang-format off

43
src/codegen_new/codegen_ops_mmx_pack.c
View File

@@ -16,27 +16,28 @@
#include "codegen_ops_mmx_pack.h"
#include "codegen_ops_helpers.h"
#define ropPpack(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
#define ropPpack(func) \
uint32_t rop##func(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), \
uint32_t fetchdat, uint32_t op_32, uint32_t op_pc) \
{ \
int dest_reg = (fetchdat >> 3) & 7; \
\
uop_MMX_ENTER(ir); \
codegen_mark_code_present(block, cs + op_pc, 1); \
if ((fetchdat & 0xc0) == 0xc0) { \
int src_reg = fetchdat & 7; \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_MM(src_reg)); \
} else { \
x86seg *target_seg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
target_seg = codegen_generate_ea(ir, op_ea_seg, fetchdat, op_ssegs, &op_pc, op_32, 0); \
codegen_check_seg_read(block, ir, target_seg); \
uop_MEM_LOAD_REG(ir, IREG_temp0_Q, ireg_seg_base(target_seg), IREG_eaaddr); \
uop_##func(ir, IREG_MM(dest_reg), IREG_MM(dest_reg), IREG_temp0_Q); \
} \
\
return op_pc + 1; \
}
// clang-format off

110
src/codegen_new/codegen_ops_stack.c
View File

@@ -196,61 +196,65 @@ ropPOP_L(codeblock_t *block, ir_data_t *ir, UNUSED(uint8_t opcode), uint32_t fet
return op_pc + 1;
}
#define ROP_PUSH_SEG(seg) \
uint32_t ropPUSH_##seg##_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_##seg##_seg_W); \
SUB_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPUSH_##seg##_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4); \
uop_MOVZX(ir, IREG_temp0, IREG_##seg##_seg_W); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_temp0); \
SUB_SP(ir, 4); \
\
return op_pc; \
#define ROP_PUSH_SEG(seg) \
uint32_t ropPUSH_##seg##_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -2); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_##seg##_seg_W); \
SUB_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPUSH_##seg##_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
int sp_reg; \
\
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
sp_reg = LOAD_SP_WITH_OFFSET(ir, -4); \
uop_MOVZX(ir, IREG_temp0, IREG_##seg##_seg_W); \
uop_MEM_STORE_REG(ir, IREG_SS_base, sp_reg, IREG_temp0); \
SUB_SP(ir, 4); \
\
return op_pc; \
}
#define ROP_POP_SEG(seg, rseg) \
uint32_t ropPOP_##seg##_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPOP_##seg##_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 4); \
\
return op_pc; \
#define ROP_POP_SEG(seg, rseg) \
uint32_t ropPOP_##seg##_16(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 2); \
\
return op_pc; \
} \
uint32_t ropPOP_##seg##_32(UNUSED(codeblock_t *block), ir_data_t *ir, UNUSED(uint8_t opcode), \
UNUSED(uint32_t fetchdat), UNUSED(uint32_t op_32), uint32_t op_pc) \
{ \
uop_MOV_IMM(ir, IREG_oldpc, cpu_state.oldpc); \
\
if (stack32) \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_ESP); \
else { \
uop_MOVZX(ir, IREG_eaaddr, IREG_SP); \
uop_MEM_LOAD_REG(ir, IREG_temp0_W, IREG_SS_base, IREG_eaaddr); \
} \
uop_LOAD_SEG(ir, &rseg, IREG_temp0_W); \
ADD_SP(ir, 4); \
\
return op_pc; \
}
// clang-format off

96
src/video/CMakeLists.txt
View File

@@ -13,23 +13,72 @@
# Copyright 2020-2021 David Hrdlička.
#
add_library(vid OBJECT agpgart.c video.c vid_table.c vid_cga.c vid_cga_comp.c
vid_compaq_cga.c vid_mda.c vid_hercules.c vid_herculesplus.c
vid_incolor.c vid_colorplus.c vid_genius.c vid_pgc.c vid_im1024.c
vid_sigma.c vid_wy700.c vid_ega.c vid_ega_render.c vid_svga.c vid_8514a.c
vid_svga_render.c vid_ddc.c vid_vga.c vid_ati_eeprom.c vid_ati18800.c
vid_ati28800.c vid_ati_mach8.c vid_ati_mach64.c vid_ati68875_ramdac.c
vid_ati68860_ramdac.c vid_bt481_ramdac.c vid_bt48x_ramdac.c vid_chips_69000.c
vid_av9194.c vid_icd2061.c vid_ics2494.c vid_ics2595.c vid_cl54xx.c
vid_et3000.c vid_et4000.c vid_sc1148x_ramdac.c vid_sc1502x_ramdac.c
vid_et4000w32.c vid_stg_ramdac.c vid_ht216.c vid_oak_oti.c vid_paradise.c
vid_rtg310x.c vid_f82c425.c vid_ti_cf62011.c vid_tvga.c vid_tgui9440.c
vid_tkd8001_ramdac.c vid_att20c49x_ramdac.c vid_s3.c vid_s3_virge.c
vid_ibm_rgb528_ramdac.c vid_sdac_ramdac.c vid_ogc.c vid_mga.c vid_nga.c
vid_tvp3026_ramdac.c vid_att2xc498_ramdac.c vid_xga.c
add_library(vid OBJECT
agpgart.c
video.c
vid_table.c
vid_cga.c
vid_cga_comp.c
vid_compaq_cga.c
vid_mda.c
vid_hercules.c
vid_herculesplus.c
vid_incolor.c
vid_colorplus.c
vid_genius.c
vid_pgc.c
vid_im1024.c
vid_sigma.c
vid_wy700.c
vid_ega.c
vid_ega_render.c
vid_svga.c
vid_8514a.c
vid_svga_render.c
vid_ddc.c
vid_vga.c
vid_ati_eeprom.c
vid_ati18800.c
vid_ati28800.c
vid_ati_mach8.c
vid_ati_mach64.c
vid_ati68875_ramdac.c
vid_ati68860_ramdac.c
vid_bt481_ramdac.c
vid_bt48x_ramdac.c
vid_chips_69000.c
vid_av9194.c
vid_icd2061.c
vid_ics2494.c
vid_ics2595.c
vid_cl54xx.c
vid_et3000.c
vid_et4000.c
vid_sc1148x_ramdac.c
vid_sc1502x_ramdac.c
vid_et4000w32.c
vid_stg_ramdac.c
vid_ht216.c
vid_oak_oti.c
vid_paradise.c
vid_rtg310x.c
vid_f82c425.c
vid_ti_cf62011.c
vid_tvga.c vid_tgui9440.c
vid_tkd8001_ramdac.c
vid_att20c49x_ramdac.c
vid_s3.c vid_s3_virge.c
vid_ibm_rgb528_ramdac.c
vid_sdac_ramdac.c
vid_ogc.c
vid_mga.c
vid_nga.c
vid_tvp3026_ramdac.c
vid_att2xc498_ramdac.c
vid_xga.c
vid_bochs_vbe.c
nv/nv_rivatimer.c
)
)
if(G100)
target_compile_definitions(vid PRIVATE USE_G100)
@@ -39,10 +88,19 @@ if(XL24)
target_compile_definitions(vid PRIVATE USE_XL24)
endif()
add_library(voodoo OBJECT vid_voodoo.c vid_voodoo_banshee.c
vid_voodoo_banshee_blitter.c vid_voodoo_blitter.c vid_voodoo_display.c
vid_voodoo_fb.c vid_voodoo_fifo.c vid_voodoo_reg.c vid_voodoo_render.c
vid_voodoo_setup.c vid_voodoo_texture.c)
add_library(voodoo OBJECT
vid_voodoo.c
vid_voodoo_banshee.c
vid_voodoo_banshee_blitter.c
vid_voodoo_blitter.c
vid_voodoo_display.c
vid_voodoo_fb.c
vid_voodoo_fifo.c
vid_voodoo_reg.c
vid_voodoo_render.c
vid_voodoo_setup.c
vid_voodoo_texture.c
)
if(NOT MSVC AND (ARCH STREQUAL "i386" OR ARCH STREQUAL "x86_64"))
target_compile_options(voodoo PRIVATE "-msse2")

259
src/video/vid_8514a.c
View File

@@ -47,7 +47,6 @@
# undef CLAMP
#endif
#define BIOS_MACH8_ROM_PATH "roms/video/mach8/11301113140_4k.BIN"
static void ibm8514_accel_outb(uint16_t port, uint8_t val, void *priv);
@@ -84,14 +83,14 @@ CLAMP(int16_t in, int16_t min, int16_t max)
return in;
}
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
}
#define READ8(addr, var) \
@@ -105,139 +104,139 @@ CLAMP(int16_t in, int16_t min, int16_t max)
}
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd <= 1) || (cmd == 5)) { \
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd <= 1) || (cmd == 5)) { \
temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} else { \
temp = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[(dev->accel.dest + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else { \
temp = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[(dev->accel.dest + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
#define READ(addr, dat) \
if (dev->bpp) \
#define READ(addr, dat) \
if (dev->bpp) \
dat = vram_w[(addr) & (dev->vram_mask >> 1)]; \
else \
else \
dat = (dev->vram[(addr) & (dev->vram_mask)]); \
#define READ_HIGH(addr, dat) \
#define READ_HIGH(addr, dat) \
dat |= (dev->vram[(addr) & (dev->vram_mask)] << 8);
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) >> 1; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) >> 1; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) >> 1; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
if (dev->bpp) \
dest_dat = MIN(0xffff, (dest_dat + src_dat)); \
else \
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
if (dev->bpp) \
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) >> 1; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) >> 1; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) >> 1; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
if (dev->bpp) \
dest_dat = MIN(0xffff, (dest_dat + src_dat)); \
else \
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
if (dev->bpp) \
dest_dat = (0xffff < (src_dat + dest_dat)) ? 0xffff : ((src_dat + dest_dat) / 2); \
else \
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
break; \
} \
else \
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
break; \
} \
}
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask >> 1)) >> 11] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
}
int ibm8514_active = 0;

66
src/video/vid_ati_mach64.c
View File

@@ -1508,16 +1508,16 @@ mach64_start_line(mach64_t *mach64)
mach64->accel.op = OP_LINE;
}
#define READ(addr, dat, width) \
if (width == 0) \
dat = svga->vram[((addr)) & mach64->vram_mask]; \
else if (width == 1) \
dat = *(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask]; \
else if (width == 2) \
dat = *(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask]; \
else if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> ((addr) &7)) & 1; \
else \
#define READ(addr, dat, width) \
if (width == 0) \
dat = svga->vram[((addr)) & mach64->vram_mask]; \
else if (width == 1) \
dat = *(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask]; \
else if (width == 2) \
dat = *(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask]; \
else if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> ((addr) &7)) & 1; \
else \
dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> (7 - ((addr) &7))) & 1;
#define MIX \
@@ -1575,29 +1575,29 @@ mach64_start_line(mach64_t *mach64)
break; \
}
#define WRITE(addr, width) \
if (width == 0) { \
svga->vram[(addr) &mach64->vram_mask] = dest_dat; \
svga->changedvram[((addr) &mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 1) { \
*(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 1) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 2) { \
*(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 2) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else { \
if (dest_dat & 1) { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << ((addr) &7); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << (7 - ((addr) &7)); \
} else { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << ((addr) &7)); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << (7 - ((addr) &7))); \
} \
svga->changedvram[(((addr) >> 3) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
#define WRITE(addr, width) \
if (width == 0) { \
svga->vram[(addr) &mach64->vram_mask] = dest_dat; \
svga->changedvram[((addr) &mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 1) { \
*(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 1) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 2) { \
*(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 2) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else { \
if (dest_dat & 1) { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << ((addr) &7); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << (7 - ((addr) &7)); \
} else { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << ((addr) &7)); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << (7 - ((addr) &7))); \
} \
svga->changedvram[(((addr) >> 3) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
}
void

414
src/video/vid_ati_mach8.c
View File

@@ -49,10 +49,10 @@
#define BIOS_MACH32_MCA_ROM_PATH "roms/video/mach32/MACH32MCA_Olivetti.BIN"
#define BIOS_MACH32_PCI_ROM_PATH "roms/video/mach32/intelopt_00000.rom"
static video_timings_t timing_gfxultra_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_mach32_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_gfxultra_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_mach32_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static void mach_accel_outb(uint16_t port, uint8_t val, void *priv);
static void mach_accel_outw(uint16_t port, uint16_t val, void *priv);
@@ -88,14 +88,14 @@ mach_log(const char *fmt, ...)
# define mach_log(fmt, ...)
#endif
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
}
#define READ8(addr, var) \
@@ -110,166 +110,164 @@ mach_log(const char *fmt, ...)
#define READ_PIXTRANS_BYTE_IO(cx, n) \
if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
if (dev->bpp) { \
if (n == 0)\
if (dev->bpp) { \
if (n == 0) \
mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] & 0xff; \
else \
mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] >> 8; \
\
} else \
mach->accel.pix_trans[(n)] = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
\
else \
mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] >> 8; \
} else \
mach->accel.pix_trans[(n)] = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
}
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd == 0) || (cmd == 1) || (cmd == 5) || (mach->accel.cmd_type == -1)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.cy * dev->pitch) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.dest) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.dest) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.dest) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 3) || (mach->accel.cmd_type == 4)) { \
if (dev->bpp) \
temp = vram_w[((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & dev->vram_mask]; \
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd == 0) || (cmd == 1) || (cmd == 5) || (mach->accel.cmd_type == -1)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.cy * dev->pitch) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.dest) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.dest) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.dest) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 3) || (mach->accel.cmd_type == 4)) { \
if (dev->bpp) \
temp = vram_w[((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} \
}
#define READ(addr, dat) \
if (dev->bpp) \
#define READ(addr, dat) \
if (dev->bpp) \
dat = vram_w[(addr) & (dev->vram_mask >> 1)]; \
else \
else \
dat = (dev->vram[(addr) & (dev->vram_mask)]);
#define READ_HIGH(addr, dat) \
#define READ_HIGH(addr, dat) \
dat |= (dev->vram[(addr) & (dev->vram_mask)] << 8);
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) / 2; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) / 2; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) / 2; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
if (dev->bpp) \
dest_dat = MIN(0xffff, (dest_dat + src_dat)); \
else \
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
if (dev->bpp) \
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) / 2; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) / 2; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) / 2; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
if (dev->bpp) \
dest_dat = MIN(0xffff, (dest_dat + src_dat)); \
else \
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
if (dev->bpp) \
dest_dat = (0xffff < (src_dat + dest_dat)) ? 0xffff : ((src_dat + dest_dat) / 2); \
else \
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
break; \
} \
else \
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
break; \
} \
}
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask >> 1)) >> 11] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
}
static int
@@ -338,7 +336,9 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
}
if ((dev->accel_bpp == 8) || (dev->accel_bpp == 15) || (dev->accel_bpp == 16) || (dev->accel_bpp == 24))
mach_log("RdMask=%04x, DPCONFIG=%04x, Clipping: l=%d, r=%d, t=%d, b=%d, LineDrawOpt=%04x, BPP=%d, CMDType = %d, offs=%08x, cnt = %d, input = %d, mono_src = %d, frgdsel = %d, d(%d,%d), dstxend = %d, pitch = %d, extcrt = %d, rw = %x, monpattern = %x.\n", dev->accel.rd_mask, mach->accel.dp_config, clip_l, clip_r, clip_t, clip_b, mach->accel.linedraw_opt, dev->accel_bpp, cmd_type, mach->accel.ge_offset, count, cpu_input, mono_src, frgd_sel, dev->accel.cur_x, dev->accel.cur_y, mach->accel.dest_x_end, dev->ext_pitch, dev->ext_crt_pitch, mach->accel.dp_config & 1, mach->accel.mono_pattern_enable);
mach_log("RdMask=%04x, DPCONFIG=%04x, Clipping: l=%d, r=%d, t=%d, b=%d, LineDrawOpt=%04x, BPP=%d, CMDType = %d, offs=%08x, cnt = %d, input = %d, mono_src = %d, frgdsel = %d, d(%d,%d), dstxend = %d, pitch = %d, extcrt = %d, rw = %x, monpattern = %x.\n",
dev->accel.rd_mask, mach->accel.dp_config, clip_l, clip_r, clip_t, clip_b, mach->accel.linedraw_opt, dev->accel_bpp, cmd_type, mach->accel.ge_offset, count, cpu_input, mono_src, frgd_sel, dev->accel.cur_x, dev->accel.cur_y,
mach->accel.dest_x_end, dev->ext_pitch, dev->ext_crt_pitch, mach->accel.dp_config & 1, mach->accel.mono_pattern_enable);
switch (cmd_type) {
case 1: /*Extended Raw Linedraw from bres_count register (0x96ee)*/
@@ -366,7 +366,9 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
mach->accel.stepx = (mach->accel.linedraw_opt & 0x20) ? 1 : -1;
mach->accel.stepy = (mach->accel.linedraw_opt & 0x80) ? 1 : -1;
mach_log("Extended bresenham, CUR(%d,%d), DEST(%d,%d), width = %d, options = %04x, dpconfig = %04x, opt_ena = %03x.\n", dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy, mach->accel.width, mach->accel.linedraw_opt, mach->accel.dp_config, mach->accel.max_waitstates & 0x100);
mach_log("Extended bresenham, CUR(%d,%d), DEST(%d,%d), width = %d, options = %04x, dpconfig = %04x, opt_ena = %03x.\n",
dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy, mach->accel.width, mach->accel.linedraw_opt,
mach->accel.dp_config, mach->accel.max_waitstates & 0x100);
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
@@ -853,11 +855,14 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
mach->accel.stepx = -1;
if (dev->accel.dx > 0)
dev->accel.dx--;
mach_log("BitBLT: Dst Negative X, dxstart = %d, end = %d, width = %d, dx = %d, dpconfig = %04x.\n", mach->accel.dest_x_start, mach->accel.dest_x_end, mach->accel.width, dev->accel.dx, mach->accel.dp_config);
mach_log("BitBLT: Dst Negative X, dxstart = %d, end = %d, width = %d, dx = %d, dpconfig = %04x.\n",
mach->accel.dest_x_start, mach->accel.dest_x_end, mach->accel.width, dev->accel.dx,
mach->accel.dp_config);
} else {
mach->accel.stepx = 1;
mach->accel.width = 0;
mach_log("BitBLT: Dst Indeterminate X, dpconfig = %04x, destxend = %d, destxstart = %d.\n", mach->accel.dp_config, mach->accel.dest_x_end, mach->accel.dest_x_start);
mach_log("BitBLT: Dst Indeterminate X, dpconfig = %04x, destxend = %d, destxstart = %d.\n",
mach->accel.dp_config, mach->accel.dest_x_end, mach->accel.dest_x_start);
}
dev->accel.sx = 0;
@@ -914,17 +919,23 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
if (mach->accel.sx_end > mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_end - mach->accel.sx_start);
mach->accel.src_stepx = 1;
mach_log("BitBLT: Src Positive X: wh(%d,%d), srcwidth = %d, coordinates: %d,%d px, start: %d, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.width, mach->accel.height, mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_start, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
mach_log("BitBLT: Src Positive X: wh(%d,%d), srcwidth = %d, coordinates: %d,%d px, start: %d, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
mach->accel.width, mach->accel.height, mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_start, mach->accel.src_x_end,
mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
} else if (mach->accel.sx_end < mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_start - mach->accel.sx_end);
mach->accel.src_stepx = -1;
if (dev->accel.cx > 0)
dev->accel.cx--;
mach_log("BitBLT: Src Negative X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
mach_log("BitBLT: Src Negative X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config
mach->accel.src_width & 1);
} else {
mach->accel.src_stepx = 1;
mach->accel.src_width = 0;
mach_log("BitBLT: Src Indeterminate X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
mach_log("BitBLT: Src Indeterminate X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n",
mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx,
mach->accel.dp_config, mach->accel.src_width & 1);
}
mach->accel.sx = 0;
if (mach->accel.patt_data_idx < 16)
@@ -996,7 +1007,8 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
if (cpu_input) {
if (mach->accel.dp_config == 0x3251) {
mach_log("DPCONFIG 3251: monosrc=%d, frgdsel=%d, bkgdsel=%d, pitch=%d.\n", mono_src, frgd_sel, bkgd_sel, dev->pitch);
mach_log("DPCONFIG 3251: monosrc=%d, frgdsel=%d, bkgdsel=%d, pitch=%d.\n",
mono_src, frgd_sel, bkgd_sel, dev->pitch);
if (dev->accel.sy == mach->accel.height) {
mach_log("No Blit on DPCONFIG=3251.\n");
dev->accel.cmd_back = 1;
@@ -1156,7 +1168,10 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
cpu_dat >>= 8;
if (mach->accel.dp_config == 0x2071 || (mach->accel.dp_config == 0x2011))
mach_log("FontBlit: SX=%d, C(%d,%d), SRCWidth=%d, frgdmix=%d, bkgdmix=%d, rdmask=%04x, D(%d,%d), geoffset=%x, addr=%08x,.\n", mach->accel.sx, dev->accel.cx, dev->accel.cy, mach->accel.src_width, dev->accel.frgd_mix & 0x1f, dev->accel.bkgd_mix & 0x1f, rd_mask, dev->accel.dx, dev->accel.dy, dev->accel.ge_offset, (dev->accel.src + dev->accel.cx) & dev->vram_mask);
mach_log("FontBlit: SX=%d, C(%d,%d), SRCWidth=%d, frgdmix=%d, bkgdmix=%d, rdmask=%04x, D(%d,%d), geoffset=%x, addr=%08x,.\n",
mach->accel.sx, dev->accel.cx, dev->accel.cy, mach->accel.src_width, dev->accel.frgd_mix & 0x1f,
dev->accel.bkgd_mix & 0x1f, rd_mask, dev->accel.dx, dev->accel.dy, dev->accel.ge_offset,
(dev->accel.src + dev->accel.cx) & dev->vram_mask);
if ((mono_src == 3) || (frgd_sel == 3) || (bkgd_sel == 3) || (mach->accel.dp_config & 0x02)) {
dev->accel.cx += mach->accel.src_stepx;
@@ -1248,7 +1263,9 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
dev->accel.sx = 0;
mach_log("Linedraw: c(%d,%d), d(%d,%d), cend(%d,%d), bounds: l=%d, r=%d, t=%d, b=%d.\n", dev->accel.cur_x, dev->accel.cur_y, dev->accel.dx, dev->accel.dy, mach->accel.cx_end_line, mach->accel.cy_end_line, mach->accel.bleft, mach->accel.bright, mach->accel.btop, mach->accel.bbottom);
mach_log("Linedraw: c(%d,%d), d(%d,%d), cend(%d,%d), bounds: l=%d, r=%d, t=%d, b=%d.\n",
dev->accel.cur_x, dev->accel.cur_y, dev->accel.dx, dev->accel.dy, mach->accel.cx_end_line,
mach->accel.cy_end_line, mach->accel.bleft, mach->accel.bright, mach->accel.btop, mach->accel.bbottom);
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
@@ -1944,7 +1961,9 @@ mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint3
else
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
mach_log("ScanToX=%04x, MonoSRC=%d, FrgdSel=%d, BkgdSel=%d, Pitch=%d, C(%d,%d), SRCWidth=%d, WH(%d,%d), colorpattidx=%d, pattlen=%d.\n", mach->accel.dp_config, mono_src, frgd_sel, bkgd_sel, dev->ext_pitch, dev->accel.cx, dev->accel.cy, mach->accel.src_width, mach->accel.width, mach->accel.height, mach->accel.color_pattern_idx, mach->accel.patt_len);
mach_log("ScanToX=%04x, MonoSRC=%d, FrgdSel=%d, BkgdSel=%d, Pitch=%d, C(%d,%d), SRCWidth=%d, WH(%d,%d), colorpattidx=%d, pattlen=%d.\n",
mach->accel.dp_config, mono_src, frgd_sel, bkgd_sel, dev->ext_pitch, dev->accel.cx, dev->accel.cy, mach->accel.src_width,
mach->accel.width, mach->accel.height, mach->accel.color_pattern_idx, mach->accel.patt_len);
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
@@ -2197,9 +2216,11 @@ mach_out(uint16_t addr, uint8_t val, void *priv)
if (((dev->disp_cntl & 0x60) == 0x20) && ((dev->local & 0xff) >= 0x02)) {
if ((addr >= 0x3c6) && (addr <= 0x3c9)) {
mach_log("VGA DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n", addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
mach_log("VGA DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n",
addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
} else if ((addr >= 0x2ea) && (addr <= 0x2ed))
mach_log("8514/A DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n", addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
mach_log("8514/A DAC write regs=%03x, on=%d, display control=%02x, on1=%x, clocksel=%02x.\n",
addr, dev->on, dev->disp_cntl & 0x60, dev->accel.advfunc_cntl & 0x01, mach->accel.clock_sel & 0x01);
}
switch (addr) {
@@ -2609,7 +2630,8 @@ ati8514_recalctimings(svga_t *svga)
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
mach->accel.ge_offset = dev->accel.ge_offset;
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x.\n", dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x05, mach->accel.clock_sel & 0x01);
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x.\n",
dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x05, mach->accel.clock_sel & 0x01);
if (mach->accel.clock_sel & 0x01) {
dev->h_disp = dev->hdisp;
@@ -2637,7 +2659,9 @@ ati8514_recalctimings(svga_t *svga)
if (dev->interlace)
dev->dispend >>= 1;
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n", dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset, mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n",
dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset,
mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
if (dev->vram_512k_8514) {
if (dev->h_disp == 640) {
dev->ext_pitch = 640;
@@ -2713,7 +2737,9 @@ mach_recalctimings(svga_t *svga)
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
mach->accel.ge_offset = dev->accel.ge_offset;
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x, interlace=%x.\n", dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x04, mach->accel.clock_sel & 0xfe, dev->interlace);
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x, interlace=%x.\n",
dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x04,
mach->accel.clock_sel & 0xfe, dev->interlace);
if ((dev->local & 0xff) >= 0x02) {
if (dev->bpp || ((mach->accel.ext_ge_config & 0x30) == 0x30) || (mach->accel.clock_sel & 0x01)) {
dev->h_disp = dev->hdisp;
@@ -2788,7 +2814,9 @@ mach_recalctimings(svga_t *svga)
}
svga->render8514 = ibm8514_render_blank;
mach_log("hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, bpp=%d, shadow=%x, vgahdisp=%d.\n", dev->h_disp, dev->dispend, dev->pitch, dev->ext_crt_pitch, mach->accel.ext_ge_config & 0xcec0, dev->accel_bpp, mach->shadow_set & 3, svga->hdisp);
mach_log("hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, bpp=%d, shadow=%x, vgahdisp=%d.\n",
dev->h_disp, dev->dispend, dev->pitch, dev->ext_crt_pitch, mach->accel.ext_ge_config & 0xcec0,
dev->accel_bpp, mach->shadow_set & 3, svga->hdisp);
switch (dev->accel_bpp) {
case 8:
svga->render8514 = ibm8514_render_8bpp;
@@ -2814,7 +2842,9 @@ mach_recalctimings(svga_t *svga)
}
} else {
svga->render8514 = ibm8514_render_blank;
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n", dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset, mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n",
dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset,
mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
if (dev->vram_512k_8514) {
if (dev->h_disp == 640) {
dev->ext_pitch = 640;
@@ -2829,7 +2859,8 @@ mach_recalctimings(svga_t *svga)
}
} else {
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
mach_log("GDCREG5=%02x, ATTR10=%02x, ATI B0 bit 5=%02x, ON=%d.\n", svga->gdcreg[5] & 0x60, svga->attrregs[0x10] & 0x40, mach->regs[0xb0] & 0x20, dev->on);
mach_log("GDCREG5=%02x, ATTR10=%02x, ATI B0 bit 5=%02x, ON=%d.\n",
svga->gdcreg[5] & 0x60, svga->attrregs[0x10] & 0x40, mach->regs[0xb0] & 0x20, dev->on);
if ((svga->gdcreg[6] & 0x01) || (svga->attrregs[0x10] & 0x01)) {
if ((svga->gdcreg[5] & 0x40) || (svga->attrregs[0x10] & 0x40) || (mach->regs[0xb0] & 0x20)) {
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clock_sel, svga->clock_gen);
@@ -3405,7 +3436,8 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8
} else if (((mach->shadow_set & 0x03) == 0x00) && !(mach->accel.clock_sel & 0x01))
dev->hdisp2 = (val + 1) << 3;
}
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): hdisp=0x%02x, shadowcntl=%02x, shadowset=%02x.\n", CS, cpu_state.pc, port, val, mach->shadow_cntl & 0x08, mach->shadow_set & 0x03);
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): hdisp=0x%02x, shadowcntl=%02x, shadowset=%02x.\n",
CS, cpu_state.pc, port, val, mach->shadow_cntl & 0x08, mach->shadow_set & 0x03);
svga_recalctimings(svga);
break;
@@ -3475,7 +3507,8 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8
dev->interlace = !!(dev->disp_cntl & 0x10);
}
}
mach_log("ATI 8514/A: DISP_CNTL write %04x=%02x, written=%02x, interlace=%d.\n", port, val & 0x70, dev->disp_cntl & 0x70, dev->interlace);
mach_log("ATI 8514/A: DISP_CNTL write %04x=%02x, written=%02x, interlace=%d.\n",
port, val & 0x70, dev->disp_cntl & 0x70, dev->interlace);
svga_recalctimings(svga);
break;
@@ -3483,7 +3516,8 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8
dev->accel.advfunc_cntl = val;
dev->on = dev->accel.advfunc_cntl & 0x01;
dev->vendor_mode = 0;
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): ON=%d, shadow crt=%x, hdisp=%d, vdisp=%d.\n", CS, cpu_state.pc, port, val & 0x01, dev->accel.advfunc_cntl & 0x04, dev->hdisp, dev->vdisp);
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): ON=%d, shadow crt=%x, hdisp=%d, vdisp=%d.\n",
CS, cpu_state.pc, port, val & 0x01, dev->accel.advfunc_cntl & 0x04, dev->hdisp, dev->vdisp);
if ((dev->local & 0xff) < 0x02) {
dev->ext_crt_pitch = 128;
@@ -3630,8 +3664,10 @@ mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8
WRITE8(port, mach->accel.clock_sel, val);
dev->on = mach->accel.clock_sel & 0x01;
dev->vendor_mode = 1;
mach_log("ATI 8514/A: (0x%04x): ON=%d, val=%04x, hdisp=%d, vdisp=%d.\n", port, mach->accel.clock_sel & 0x01, val, dev->hdisp, dev->vdisp);
mach_log("Vendor ATI mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
mach_log("ATI 8514/A: (0x%04x): ON=%d, val=%04x, hdisp=%d, vdisp=%d.\n",
port, mach->accel.clock_sel & 0x01, val, dev->hdisp, dev->vdisp);
mach_log("Vendor ATI mode set %s resolution.\n",
(dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
svga_recalctimings(svga);
if ((dev->local & 0xff) >= 0x01)
mach32_updatemapping(mach, svga);
@@ -5160,7 +5196,8 @@ mach32_ap_writeb(uint32_t addr, uint8_t val, void *priv)
mach_accel_outb(0x02e8 + (addr & 1) + (port_dword << 8), val, mach);
}
} else {
mach_log("Linear WORDB Write=%08x, val=%02x, ON=%x, dpconfig=%04x, apsize=%08x.\n", addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
mach_log("Linear WORDB Write=%08x, val=%02x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
if (dev->on)
mach32_write_common(addr, val, 1, mach, svga);
else
@@ -5186,7 +5223,8 @@ mach32_ap_writew(uint32_t addr, uint16_t val, void *priv)
mach_accel_outw(0x02e8 + (port_dword << 8), val, mach);
}
} else {
mach_log("Linear WORDW Write=%08x, val=%04x, ON=%x, dpconfig=%04x, apsize=%08x.\n", addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
mach_log("Linear WORDW Write=%08x, val=%04x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
if (dev->on)
mach32_writew_linear(addr, val, mach);
else
@@ -5214,7 +5252,8 @@ mach32_ap_writel(uint32_t addr, uint32_t val, void *priv)
mach_accel_outw(0x02e8 + (port_dword << 8) + 4, val >> 16, mach);
}
} else {
mach_log("Linear WORDL Write=%08x, val=%08x, ON=%x, dpconfig=%04x, apsize=%08x.\n", addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
mach_log("Linear WORDL Write=%08x, val=%08x, ON=%x, dpconfig=%04x, apsize=%08x.\n",
addr & dev->vram_mask, val, dev->on, mach->accel.dp_config, mach->ap_size << 20);
if (dev->on)
mach32_writel_linear(addr, val, mach);
else
@@ -5354,7 +5393,8 @@ mach32_updatemapping(mach_t *mach, svga_t *svga)
}
}
mach_log("Linear base = %08x, aperture = %04x, localcntl = %02x svgagdc = %x.\n", mach->linear_base, mach->memory_aperture, mach->local_cntl, svga->gdcreg[6] & 0x0c);
mach_log("Linear base = %08x, aperture = %04x, localcntl = %02x svgagdc = %x.\n",
mach->linear_base, mach->memory_aperture, mach->local_cntl, svga->gdcreg[6] & 0x0c);
if (mach->linear_base) {
if (((mach->memory_aperture & 3) == 1) && !mach->pci_bus) {
/*1 MB aperture*/
@@ -5832,7 +5872,8 @@ mach_mca_write(int port, uint8_t val, void *priv)
return;
mach->pos_regs[port & 7] = val;
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n", CS, port & 7, mach->pos_regs[port & 7], (((mach->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n",
CS, port & 7, mach->pos_regs[port & 7], (((mach->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mem_mapping_disable(&mach->bios_rom.mapping);
mem_mapping_disable(&mach->bios_rom2.mapping);
if (mach->pos_regs[2] & 0x01) {
@@ -5882,7 +5923,8 @@ ati8514_mca_write(int port, uint8_t val, void *priv)
return;
dev->pos_regs[port & 7] = val;
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n", CS, port & 7, dev->pos_regs[port & 7], (((dev->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n",
CS, port & 7, dev->pos_regs[port & 7], (((dev->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mem_mapping_disable(&dev->bios_rom.mapping);
if (dev->pos_regs[2] & 0x01)

32
src/video/vid_cga_comp.c
View File

@@ -44,22 +44,22 @@ static const double tau = 6.28318531; /* == 2*pi */
static unsigned char chroma_multiplexer[256] = {
// clang-format off
2, 2, 2, 2, 114,174, 4, 3, 2, 1,133,135, 2,113,150, 4,
133, 2, 1, 99, 151,152, 2, 1, 3, 2, 96,136, 151,152,151,152,
2, 56, 62, 4, 111,250,118, 4, 0, 51,207,137, 1,171,209, 5,
140, 50, 54,100, 133,202, 57, 4, 2, 50,153,149, 128,198,198,135,
32, 1, 36, 81, 147,158, 1, 42, 33, 1,210,254, 34,109,169, 77,
177, 2, 0,165, 189,154, 3, 44, 33, 0, 91,197, 178,142,144,192,
4, 2, 61, 67, 117,151,112, 83, 4, 0,249,255, 3,107,249,117,
147, 1, 50,162, 143,141, 52, 54, 3, 0,145,206, 124,123,192,193,
72, 78, 2, 0, 159,208, 4, 0, 53, 58,164,159, 37,159,171, 1,
248,117, 4, 98, 212,218, 5, 2, 54, 59, 93,121, 176,181,134,130,
1, 61, 31, 0, 160,255, 34, 1, 1, 58,197,166, 0,177,194, 2,
162,111, 34, 96, 205,253, 32, 1, 1, 57,123,125, 119,188,150,112,
78, 4, 0, 75, 166,180, 20, 38, 78, 1,143,246, 42,113,156, 37,
252, 4, 1,188, 175,129, 1, 37, 118, 4, 88,249, 202,150,145,200,
61, 59, 60, 60, 228,252,117, 77, 60, 58,248,251, 81,212,254,107,
198, 59, 58,169, 250,251, 81, 80, 100, 58,154,250, 251,252,252,252
2, 2, 2, 2, 114, 174, 4, 3, 2, 1, 133, 135, 2, 113, 150, 4,
133, 2, 1, 99, 151, 152, 2, 1, 3, 2, 96, 136, 151, 152, 151, 152,
2, 56, 62, 4, 111, 250, 118, 4, 0, 51, 207, 137, 1, 171, 209, 5,
140, 50, 54, 100, 133, 202, 57, 4, 2, 50, 153, 149, 128, 198, 198, 135,
32, 1, 36, 81, 147, 158, 1, 42, 33, 1, 210, 254, 34, 109, 169, 77,
177, 2, 0, 165, 189, 154, 3, 44, 33, 0, 91, 197, 178, 142, 144, 192,
4, 2, 61, 67, 117, 151, 112, 83, 4, 0, 249, 255, 3, 107, 249, 117,
147, 1, 50, 162, 143, 141, 52, 54, 3, 0, 145, 206, 124, 123, 192, 193,
72, 78, 2, 0, 159, 208, 4, 0, 53, 58, 164, 159, 37, 159, 171, 1,
248, 117, 4, 98, 212, 218, 5, 2, 54, 59, 93, 121, 176, 181, 134, 130,
1, 61, 31, 0, 160, 255, 34, 1, 1, 58, 197, 166, 0, 177, 194, 2,
162, 111, 34, 96, 205, 253, 32, 1, 1, 57, 123, 125, 119, 188, 150, 112,
78, 4, 0, 75, 166, 180, 20, 38, 78, 1, 143, 246, 42, 113, 156, 37,
252, 4, 1, 188, 175, 129, 1, 37, 118, 4, 88, 249, 202, 150, 145, 200,
61, 59, 60, 60, 228, 252, 117, 77, 60, 58, 248, 251, 81, 212, 254, 107,
198, 59, 58, 169, 250, 251, 81, 80, 100, 58, 154, 250, 251, 252, 252, 252
// clang-format on
};

4
src/video/vid_et4000.c
View File

@@ -82,8 +82,8 @@ typedef struct {
rom_t bios_rom;
uint8_t banking;
uint32_t vram_size,
vram_mask;
uint32_t vram_size;
uint32_t vram_mask;
uint8_t port_22cb_val;
uint8_t port_32cb_val;

21
src/video/vid_mga.c
View File

@@ -427,8 +427,7 @@ enum {
DMA_STATE_SEC
};
typedef struct
{
typedef struct {
uint32_t addr_type;
uint32_t val;
} fifo_entry_t;
@@ -484,13 +483,11 @@ typedef struct mystique_t {
event_t *wake_fifo_thread, *fifo_not_full_event;
struct
{
struct {
int m, n, p, s;
} xpixpll[3];
struct
{
struct {
uint8_t funcnt : 7, stylelen,
dmamod;
@@ -521,27 +518,23 @@ typedef struct mystique_t {
uint64_t extended_dr[4];
struct
{
struct {
int sdydxl, scanleft, sdxl, sdy,
sdxr;
} sgn;
} dwgreg;
struct
{
struct {
uint8_t r, g, b;
} lut[256];
struct
{
struct {
uint16_t pos_x, pos_y,
addr;
uint32_t col[3];
} cursor;
struct
{
struct {
atomic_int pri_state, sec_state, iload_state, state;
atomic_uint primaddress, primend, secaddress, secend,

2
src/video/vid_paradise.c
View File

@@ -68,7 +68,7 @@ typedef struct paradise_t {
} paradise_t;
static video_timings_t timing_paradise_pvga1a = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
static video_timings_t timing_paradise_wd90c = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_paradise_wd90c = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
void paradise_remap(paradise_t *paradise);

34
src/video/vid_s3.c
View File

@@ -537,15 +537,15 @@ static void s3_visionx68_video_engine_op(uint32_t cpu_dat, s3_t *s3);
#define READ_PIXTRANS_BYTE_MM \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask];
#define READ_PIXTRANS_WORD \
if ((s3->bpp == 0) && !s3->color_16bit) { \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask]; \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 1)) & s3->vram_mask] << 8); \
} else \
#define READ_PIXTRANS_WORD \
if ((s3->bpp == 0) && !s3->color_16bit) { \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask]; \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 1)) & s3->vram_mask] << 8); \
} else \
temp = vram_w[dword_remap_w(svga, (s3->accel.dest + s3->accel.cx - s3->accel.minus)) & (s3->vram_mask >> 1)];
#define READ_PIXTRANS_LONG \
if ((s3->bpp == 0) && !s3->color_16bit) { \
if ((s3->bpp == 0) && !s3->color_16bit) { \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask]; \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 1)) & s3->vram_mask] << 8); \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 2)) & s3->vram_mask] << 16); \
@@ -6583,9 +6583,9 @@ polygon_setup(s3_t *s3)
#define READ(addr, dat) \
if (((s3->bpp == 0) && !s3->color_16bit) || (s3->bpp == 2)) \
dat = svga->vram[dword_remap(svga, addr) & s3->vram_mask]; \
else if ((s3->bpp == 1) || s3->color_16bit) \
else if ((s3->bpp == 1) || s3->color_16bit) \
dat = vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)]; \
else \
else \
dat = vram_l[dword_remap_l(svga, addr) & (s3->vram_mask >> 2)];
#define MIX_READ \
@@ -6642,11 +6642,11 @@ polygon_setup(s3_t *s3)
} \
}
#define MIX \
{ \
old_dest_dat = dest_dat; \
MIX_READ \
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask); \
#define MIX \
{ \
old_dest_dat = dest_dat; \
MIX_READ \
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask); \
}
#define ROPMIX_READ(D, P, S) \
@@ -7431,14 +7431,14 @@ polygon_setup(s3_t *s3)
}
#define WRITE(addr, dat) \
if (((s3->bpp == 0) && !s3->color_16bit) || (s3->bpp == 2)) { \
svga->vram[dword_remap(svga, addr) & s3->vram_mask] = dat; \
if (((s3->bpp == 0) && !s3->color_16bit) || (s3->bpp == 2)) { \
svga->vram[dword_remap(svga, addr) & s3->vram_mask] = dat; \
svga->changedvram[(dword_remap(svga, addr) & s3->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if ((s3->bpp == 1) || s3->color_16bit) { \
} else if ((s3->bpp == 1) || s3->color_16bit) { \
vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)] = dat; \
svga->changedvram[(dword_remap_w(svga, addr) & (s3->vram_mask >> 1)) >> 11] = svga->monitor->mon_changeframecount; \
} else { \
vram_l[dword_remap_l(svga, addr) & (s3->vram_mask >> 2)] = dat; \
vram_l[dword_remap_l(svga, addr) & (s3->vram_mask >> 2)] = dat; \
svga->changedvram[(dword_remap_l(svga, addr) & (s3->vram_mask >> 2)) >> 10] = svga->monitor->mon_changeframecount; \
}

586
src/video/vid_s3_virge.c
View File

@@ -2088,127 +2088,127 @@ s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv)
}
}
#define READ(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
#define READ(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
val = vram[addr & virge->vram_mask]; \
break; \
case 1: /*16 bpp*/ \
break; \
case 1: /*16 bpp*/ \
val = *(uint16_t *)&vram[addr & virge->vram_mask]; \
break; \
case 2: /*24 bpp*/ \
break; \
case 2: /*24 bpp*/ \
val = (*(uint32_t *)&vram[addr & virge->vram_mask]) & 0xffffff; \
break; \
} \
break; \
} \
} while (0)
#define Z_READ(addr) *(uint16_t *)&vram[addr & virge->vram_mask]
#define Z_WRITE(addr, val) \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
#define Z_WRITE(addr, val) \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
*(uint16_t *)&vram[addr & virge->vram_mask] = val
#define CLIP(x, y) \
do { \
if ((virge->s3d.cmd_set & CMD_SET_HC) && \
(x < virge->s3d.clip_l || x > virge->s3d.clip_r || \
y < virge->s3d.clip_t || y > virge->s3d.clip_b)) \
update = 0; \
#define CLIP(x, y) \
do { \
if ((virge->s3d.cmd_set & CMD_SET_HC) && \
(x < virge->s3d.clip_l || x > virge->s3d.clip_r || \
y < virge->s3d.clip_t || y > virge->s3d.clip_b)) \
update = 0; \
} while (0)
#define CLIP_3D(x, y) \
do { \
if ((s3d_tri->cmd_set & CMD_SET_HC) && (x < s3d_tri->clip_l || \
x > s3d_tri->clip_r || y < s3d_tri->clip_t || \
y > s3d_tri->clip_b)) \
update = 0; \
#define CLIP_3D(x, y) \
do { \
if ((s3d_tri->cmd_set & CMD_SET_HC) && (x < s3d_tri->clip_l || \
x > s3d_tri->clip_r || y < s3d_tri->clip_t || \
y > s3d_tri->clip_b)) \
update = 0; \
} while (0)
#define Z_CLIP(Zzb, Zs) \
do { \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
switch ((s3d_tri->cmd_set >> 20) & 7) { \
case 0: \
update = 0; \
break; \
case 1: \
if (Zs <= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 2: \
if (Zs != Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 3: \
if (Zs < Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 4: \
if (Zs >= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 5: \
if (Zs == Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 6: \
if (Zs > Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 7: \
update = 1; \
Zzb = Zs; \
break; \
} \
#define Z_CLIP(Zzb, Zs) \
do { \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
switch ((s3d_tri->cmd_set >> 20) & 7) { \
case 0: \
update = 0; \
break; \
case 1: \
if (Zs <= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 2: \
if (Zs != Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 3: \
if (Zs < Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 4: \
if (Zs >= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 5: \
if (Zs == Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 6: \
if (Zs > Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 7: \
update = 1; \
Zzb = Zs; \
break; \
} \
} while (0)
#define MIX() \
do { \
int c; \
for (c = 0; c < 24; c++) { \
int d = (dest & (1 << c)) ? 1 : 0; \
if (source & (1 << c)) \
d |= 2; \
if (pattern & (1 << c)) \
d |= 4; \
if (virge->s3d.rop & (1 << d)) \
out |= (1 << c); \
} \
#define MIX() \
do { \
int c; \
for (c = 0; c < 24; c++) { \
int d = (dest & (1 << c)) ? 1 : 0; \
if (source & (1 << c)) \
d |= 2; \
if (pattern & (1 << c)) \
d |= 4; \
if (virge->s3d.rop & (1 << d)) \
out |= (1 << c); \
} \
} while (0)
#define WRITE(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 1: /*16 bpp*/ \
*(uint16_t *)&vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 2: /*24 bpp*/ \
*(uint32_t *)&vram[addr & virge->vram_mask] = (val & 0xffffff) |\
(vram[(addr + 3) & virge->vram_mask] << 24); \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
} \
#define WRITE(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 1: /*16 bpp*/ \
*(uint16_t *)&vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 2: /*24 bpp*/ \
*(uint32_t *)&vram[addr & virge->vram_mask] = (val & 0xffffff) | \
(vram[(addr + 3) & virge->vram_mask] << 24); \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
} \
} while (0)
static void
@@ -2573,23 +2573,23 @@ skip_line:
g = ((val & 0x03e0) >> 2) | ((val & 0x03e0) >> 7); \
r = ((val & 0x7c00) >> 7) | ((val & 0x7c00) >> 12);
#define RGB24_TO_24(val, r, g, b) \
b = val & 0xff; \
g = (val & 0xff00) >> 8; \
#define RGB24_TO_24(val, r, g, b) \
b = val & 0xff; \
g = (val & 0xff00) >> 8; \
r = (val & 0xff0000) >> 16
#define RGB15(r, g, b, dest) \
if (virge->dithering_enabled) { \
int add = dither[_y & 3][_x & 3]; \
int _r = (r > 248) ? 248 : r + add; \
int _g = (g > 248) ? 248 : g + add; \
int _b = (b > 248) ? 248 : b + add; \
dest = ((_b >> 3) & 0x1f) | \
(((_g >> 3) & 0x1f) << 5) | \
(((_r >> 3) & 0x1f) << 10); \
} else \
dest = ((b >> 3) & 0x1f) | \
(((g >> 3) & 0x1f) << 5) | \
#define RGB15(r, g, b, dest) \
if (virge->dithering_enabled) { \
int add = dither[_y & 3][_x & 3]; \
int _r = (r > 248) ? 248 : r + add; \
int _g = (g > 248) ? 248 : g + add; \
int _b = (b > 248) ? 248 : b + add; \
dest = ((_b >> 3) & 0x1f) | \
(((_g >> 3) & 0x1f) << 5) | \
(((_r >> 3) & 0x1f) << 10); \
} else \
dest = ((b >> 3) & 0x1f) | \
(((g >> 3) & 0x1f) << 5) | \
(((r >> 3) & 0x1f) << 10)
#define RGB24(r, g, b) ((b) | ((g) << 8) | ((r) << 16))
@@ -3753,103 +3753,99 @@ s3_virge_hwcursor_draw(svga_t *svga, int displine)
svga->hwcursor_latch.addr += 16;
}
#define DECODE_YCbCr() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t Cr; \
int8_t Cb; \
int dR; \
int dG; \
int dB; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
#define DECODE_YCbCr() \
do { \
for (uint8_t c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t Cr; \
int8_t Cb; \
int dR; \
int dG; \
int dB; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
/*Both YUV formats are untested*/
#define DECODE_YUV211() \
do { \
uint8_t y1, y2, y3, y4; \
int8_t U, V; \
int dR; \
int dG; \
int dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
y2 = (298 * (src[2] - 16)) >> 8; \
V = src[3] - 0x80; \
y3 = (298 * (src[4] - 16)) >> 8; \
y4 = (298 * (src[5] - 16)) >> 8; \
src += 6; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
r[x_write + 2] = y3 + dR; \
CLAMP(r[x_write + 2]); \
g[x_write + 2] = y3 - dG; \
CLAMP(g[x_write + 2]); \
b[x_write + 2] = y3 + dB; \
CLAMP(b[x_write + 2]); \
\
r[x_write + 3] = y4 + dR; \
CLAMP(r[x_write + 3]); \
g[x_write + 3] = y4 - dG; \
CLAMP(g[x_write + 3]); \
b[x_write + 3] = y4 + dB; \
CLAMP(b[x_write + 3]); \
\
x_write = (x_write + 4) & 7; \
#define DECODE_YUV211() \
do { \
uint8_t y1, y2, y3, y4; \
int8_t U, V; \
int dR; \
int dG; \
int dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
y2 = (298 * (src[2] - 16)) >> 8; \
V = src[3] - 0x80; \
y3 = (298 * (src[4] - 16)) >> 8; \
y4 = (298 * (src[5] - 16)) >> 8; \
src += 6; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
r[x_write + 2] = y3 + dR; \
CLAMP(r[x_write + 2]); \
g[x_write + 2] = y3 - dG; \
CLAMP(g[x_write + 2]); \
b[x_write + 2] = y3 + dB; \
CLAMP(b[x_write + 2]); \
\
r[x_write + 3] = y4 + dR; \
CLAMP(r[x_write + 3]); \
g[x_write + 3] = y4 - dG; \
CLAMP(g[x_write + 3]); \
b[x_write + 3] = y4 + dB; \
CLAMP(b[x_write + 3]); \
\
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_YUV422() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
for (uint8_t c = 0; c < 2; c++) { \
uint8_t y1; \
uint8_t y2; \
int8_t U; \
@@ -3886,104 +3882,96 @@ s3_virge_hwcursor_draw(svga_t *svga, int displine)
} \
} while (0)
#define DECODE_RGB555() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x03e0) >> 2) | \
((dat & 0x03e0) >> 7); \
b[x_write + c] = \
((dat & 0x7c00) >> 7) | \
((dat & 0x7c00) >> 12); \
} \
x_write = (x_write + 4) & 7; \
#define DECODE_RGB555() \
do { \
for (uint8_t c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x03e0) >> 2) | \
((dat & 0x03e0) >> 7); \
b[x_write + c] = \
((dat & 0x7c00) >> 7) | \
((dat & 0x7c00) >> 12); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB565() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x07e0) >> 3) | \
((dat & 0x07e0) >> 9); \
b[x_write + c] = \
((dat & 0xf800) >> 8) | \
((dat & 0xf800) >> 13); \
} \
x_write = (x_write + 4) & 7; \
#define DECODE_RGB565() \
do { \
for (uint8_t c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x07e0) >> 3) | \
((dat & 0x07e0) >> 9); \
b[x_write + c] = \
((dat & 0xf800) >> 8) | \
((dat & 0xf800) >> 13); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 3; \
} \
x_write = (x_write + 4) & 7; \
#define DECODE_RGB888() \
do { \
for (uint8_t c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 3; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_XRGB8888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 4; \
} \
x_write = (x_write + 4) & 7; \
#define DECODE_XRGB8888() \
do { \
for (uint8_t c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 4; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define OVERLAY_SAMPLE() \
do { \
switch (virge->streams.sdif) { \
case 1: \
DECODE_YCbCr(); \
break; \
case 2: \
DECODE_YUV422(); \
break; \
case 3: \
DECODE_RGB555(); \
break; \
case 4: \
DECODE_YUV211(); \
break; \
case 5: \
DECODE_RGB565(); \
break; \
case 6: \
DECODE_RGB888(); \
break; \
case 7: \
default: \
DECODE_XRGB8888(); \
break; \
} \
#define OVERLAY_SAMPLE() \
do { \
switch (virge->streams.sdif) { \
case 1: \
DECODE_YCbCr(); \
break; \
case 2: \
DECODE_YUV422(); \
break; \
case 3: \
DECODE_RGB555(); \
break; \
case 4: \
DECODE_YUV211(); \
break; \
case 5: \
DECODE_RGB565(); \
break; \
case 6: \
DECODE_RGB888(); \
break; \
case 7: \
default: \
DECODE_XRGB8888(); \
break; \
} \
} while (0)
static void

29
src/video/vid_tgui9440.c
View File

@@ -112,8 +112,7 @@ typedef struct tgui_t {
uint8_t int_line;
uint8_t pci_regs[256];
struct
{
struct {
int16_t src_x, src_y;
int16_t src_x_clip, src_y_clip;
int16_t dst_x, dst_y;
@@ -350,7 +349,9 @@ tgui_out(uint16_t addr, uint8_t val, void *priv)
if (tgui->ramdac_state == 4) {
tgui->ramdac_state = 0;
tgui->ramdac_ctrl = val;
//pclog("TGUI ramdac ctrl=%02x.\n", (tgui->ramdac_ctrl >> 4) & 0x0f);
#if 0
pclog("TGUI ramdac ctrl=%02x.\n", (tgui->ramdac_ctrl >> 4) & 0x0f);
#endif
svga_recalctimings(svga);
return;
}
@@ -718,7 +719,9 @@ tgui_recalctimings(svga_t *svga)
if (((svga->crtc[0x29] & 0x30) && (svga->bpp >= 15)) || !svga->rowoffset)
svga->rowoffset |= 0x100;
//pclog("BPP=%d, DataWidth=%02x, CRTC29 bit 4-5=%02x, pixbusmode=%02x, rowoffset=%02x, doublerowoffset=%x.\n", svga->bpp, svga->crtc[0x2a] & 0x40, svga->crtc[0x29] & 0x30, svga->crtc[0x38], svga->rowoffset, svga->gdcreg[0x2f] & 4);
#if 0
pclog("BPP=%d, DataWidth=%02x, CRTC29 bit 4-5=%02x, pixbusmode=%02x, rowoffset=%02x, doublerowoffset=%x.\n", svga->bpp, svga->crtc[0x2a] & 0x40, svga->crtc[0x29] & 0x30, svga->crtc[0x38], svga->rowoffset, svga->gdcreg[0x2f] & 4);
#endif
if ((svga->crtc[0x1e] & 0xA0) == 0xA0)
svga->ma_latch |= 0x10000;
@@ -1468,15 +1471,15 @@ enum {
} \
} while (0)
#define WRITE(addr, dat) \
if (tgui->accel.bpp == 0) { \
svga->vram[(addr) &tgui->vram_mask] = dat; \
#define WRITE(addr, dat) \
if (tgui->accel.bpp == 0) { \
svga->vram[(addr) &tgui->vram_mask] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask)) >> 12] = svga->monitor->mon_changeframecount; \
} else if (tgui->accel.bpp == 1) { \
vram_w[(addr) & (tgui->vram_mask >> 1)] = dat; \
} else if (tgui->accel.bpp == 1) { \
vram_w[(addr) & (tgui->vram_mask >> 1)] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask >> 1)) >> 11] = svga->monitor->mon_changeframecount; \
} else { \
vram_l[(addr) & (tgui->vram_mask >> 2)] = dat; \
} else { \
vram_l[(addr) & (tgui->vram_mask >> 2)] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask >> 2)) >> 10] = svga->monitor->mon_changeframecount; \
}
@@ -2115,7 +2118,9 @@ tgui_accel_out(uint16_t addr, uint8_t val, void *priv)
case 0x2123:
tgui->accel.ger22 = (tgui->accel.ger22 & 0xff) | (val << 8);
//pclog("Pitch IO23: val = %02x, rowoffset = %x.\n", tgui->accel.ger22, svga->crtc[0x13]);
#if 0
pclog("Pitch IO23: val = %02x, rowoffset = %x.\n", tgui->accel.ger22, svga->crtc[0x13]);
#endif
switch (svga->bpp) {
case 8:
case 24:

40
src/video/vid_voodoo_banshee.c
View File

@@ -441,7 +441,9 @@ banshee_updatemapping(banshee_t *banshee)
svga_t *svga = &banshee->svga;
if (!(banshee->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
// banshee_log("Update mapping - PCI disabled\n");
#if 0
banshee_log("Update mapping - PCI disabled\n");
#endif
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&banshee->linear_mapping);
mem_mapping_disable(&banshee->reg_mapping_low);
@@ -1082,7 +1084,9 @@ banshee_ext_in(uint16_t addr, void *priv)
break;
}
// banshee_log("banshee_ext_in: addr=%04x val=%02x\n", addr, ret);
#if 0
banshee_log("banshee_ext_in: addr=%04x val=%02x\n", addr, ret);
#endif
return ret;
}
@@ -1273,7 +1277,9 @@ banshee_ext_inl(uint16_t addr, void *priv)
break;
default:
// fatal("bad banshee_ext_inl: addr=%04x\n", addr);
#if 0
fatal("bad banshee_ext_inl: addr=%04x\n", addr);
#endif
break;
}
@@ -1334,17 +1340,23 @@ banshee_cmd_read(banshee_t *banshee, uint32_t addr)
case cmdBaseAddr0:
ret = voodoo->cmdfifo_base >> 12;
// banshee_log("Read cmdfifo_base %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_base %08x\n", ret);
#endif
break;
case cmdRdPtrL0:
ret = voodoo->cmdfifo_rp;
// banshee_log("Read cmdfifo_rp %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_rp %08x\n", ret);
#endif
break;
case cmdFifoDepth0:
ret = voodoo->cmdfifo_depth_wr - voodoo->cmdfifo_depth_rd;
// banshee_log("Read cmdfifo_depth %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_depth %08x\n", ret);
#endif
break;
case cmdStatus0:
@@ -1357,17 +1369,23 @@ banshee_cmd_read(banshee_t *banshee, uint32_t addr)
case cmdBaseAddr1:
ret = voodoo->cmdfifo_base_2 >> 12;
// banshee_log("Read cmdfifo_base %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_base %08x\n", ret);
#endif
break;
case cmdRdPtrL1:
ret = voodoo->cmdfifo_rp_2;
// banshee_log("Read cmdfifo_rp %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_rp %08x\n", ret);
#endif
break;
case cmdFifoDepth1:
ret = voodoo->cmdfifo_depth_wr_2 - voodoo->cmdfifo_depth_rd_2;
// banshee_log("Read cmdfifo_depth %08x\n", ret);
#if 0
banshee_log("Read cmdfifo_depth %08x\n", ret);
#endif
break;
case cmdStatus1:
@@ -2833,7 +2851,9 @@ banshee_pci_read(int func, int addr, void *priv)
if (func)
return 0xff;
// banshee_log("Banshee PCI read %08X ", addr);
#if 0
banshee_log("Banshee PCI read %08X ", addr);
#endif
switch (addr) {
case 0x00:
ret = 0x1a;

16
src/video/vid_voodoo_render.c
View File

@@ -43,8 +43,7 @@
typedef struct voodoo_state_t {
int xstart, xend, xdir;
uint32_t base_r, base_g, base_b, base_a, base_z;
struct
{
struct {
int64_t base_s, base_t, base_w;
int lod;
} tmu[2];
@@ -1424,11 +1423,14 @@ voodoo_triangle(voodoo_t *voodoo, voodoo_params_t *params, int odd_even)
if ((params->vertexAy & 0xf) > 8)
dy += 16;
/* voodoo_render_log("voodoo_triangle %i %i %i : vA %f, %f vB %f, %f vC %f, %f f %i,%i %08x %08x %08x,%08x tex=%i,%i fogMode=%08x\n", odd_even, voodoo->params_read_idx[odd_even], voodoo->params_read_idx[odd_even] & PARAM_MASK, (float)params->vertexAx / 16.0, (float)params->vertexAy / 16.0,
(float)params->vertexBx / 16.0, (float)params->vertexBy / 16.0,
(float)params->vertexCx / 16.0, (float)params->vertexCy / 16.0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[0] : 0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[1] : 0, params->fbzColorPath, params->alphaMode, params->textureMode[0],params->textureMode[1], params->tex_entry[0],params->tex_entry[1], params->fogMode);*/
#if 0
voodoo_render_log("voodoo_triangle %i %i %i : vA %f, %f vB %f, %f vC %f, %f f %i,%i %08x %08x %08x,%08x tex=%i,%i fogMode=%08x\n",
odd_even, voodoo->params_read_idx[odd_even], voodoo->params_read_idx[odd_even] & PARAM_MASK, (float)params->vertexAx / 16.0, (float)params->vertexAy / 16.0,
(float)params->vertexBx / 16.0, (float)params->vertexBy / 16.0,
(float)params->vertexCx / 16.0, (float)params->vertexCy / 16.0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[0] : 0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[1] : 0, params->fbzColorPath, params->alphaMode, params->textureMode[0],params->textureMode[1], params->tex_entry[0],params->tex_entry[1], params->fogMode);
#endif
state.base_r = params->startR;
state.base_g = params->startG;

4
src/video/vid_voodoo_setup.c
View File

@@ -191,8 +191,8 @@ voodoo_triangle_setup(voodoo_t *voodoo)
voodoo->params.dWdX = (int64_t) (((verts[va].sWb - verts[vb].sWb) * dyBC - (verts[vb].sWb - verts[vc].sWb) * dyAB) * 4294967296.0f);
voodoo->params.dWdY = (int64_t) (((verts[vb].sWb - verts[vc].sWb) * dxAB - (verts[va].sWb - verts[vb].sWb) * dxBC) * 4294967296.0f);
voodoo->params.tmu[0].startW = voodoo->params.tmu[1].startW = voodoo->params.startW;
voodoo->params.tmu[0].dWdX = voodoo->params.tmu[1].dWdX = voodoo->params.dWdX;
voodoo->params.tmu[0].dWdY = voodoo->params.tmu[1].dWdY = voodoo->params.dWdY;
voodoo->params.tmu[0].dWdX = voodoo->params.tmu[1].dWdX = voodoo->params.dWdX;
voodoo->params.tmu[0].dWdY = voodoo->params.tmu[1].dWdY = voodoo->params.dWdY;
}
if (voodoo->sSetupMode & SETUPMODE_W0) {
voodoo->params.tmu[0].startW = (int64_t) (verts[va].sW0 * 4294967296.0f);

8
src/video/vid_voodoo_texture.c
View File

@@ -61,10 +61,10 @@ voodoo_texture_log(const char *fmt, ...)
void
voodoo_recalc_tex12(voodoo_t *voodoo, int tmu)
{
int aspect = (voodoo->params.tLOD[tmu] >> 21) & 3;
int width = 256;
int height = 256;
int shift = 8;
int aspect = (voodoo->params.tLOD[tmu] >> 21) & 3;
int width = 256;
int height = 256;
int shift = 8;
uint32_t base = voodoo->params.texBaseAddr[tmu];
uint32_t offset = 0;
int tex_lod = 0;

14
src/video/vid_xga.c
View File

@@ -856,18 +856,18 @@ xga_ext_inb(uint16_t addr, void *priv)
return ret;
}
#define READ(addr, dat) \
#define READ(addr, dat) \
dat = xga->vram[(addr) & (xga->vram_mask)];
#define WRITE(addr, dat) \
xga->vram[((addr)) & (xga->vram_mask)] = dat; \
#define WRITE(addr, dat) \
xga->vram[((addr)) & (xga->vram_mask)] = dat; \
xga->changedvram[(((addr)) & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
#define READW(addr, dat) \
#define READW(addr, dat) \
dat = *(uint16_t *) &xga->vram[(addr) & (xga->vram_mask)];
#define WRITEW(addr, dat) \
*(uint16_t *) &xga->vram[((addr)) & (xga->vram_mask)] = dat; \
#define WRITEW(addr, dat) \
*(uint16_t *) &xga->vram[((addr)) & (xga->vram_mask)] = dat; \
xga->changedvram[(((addr)) & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
#define ROP(mix, d, s) \
@@ -928,7 +928,7 @@ xga_ext_inb(uint16_t addr, void *priv)
d = MIN(s, d); \
break; \
case 0x12: \
d = MIN(~0, s + d); \
d = MIN(~0, s + d); \
break; \
case 0x13: \
d = MAX(0, d - s); \