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Clang-formatting in src/cpu

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This commit is contained in:
Jasmine Iwanek
2023-08-11 13:00:04 -04:00
parent be79ea78c7
commit 5cd18f3fbb
43 changed files with 1705 additions and 1622 deletions
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32
src/cpu/386.c
View File

@@ -26,7 +26,7 @@
#include <86box/machine.h>
#include <86box/gdbstub.h>
#ifndef OPS_286_386
#define OPS_286_386
# define OPS_286_386
#endif
#include "386_common.h"
#ifdef USE_NEW_DYNAREC
@@ -204,24 +204,24 @@ fetch_ea_16_long(uint32_t rmdat)
#define PREFETCH_FLUSH() prefetch_flush()
#ifndef FPU_CYCLES
#define FPU_CYCLES
# define FPU_CYCLES
#endif
#define OP_TABLE(name) ops_2386_##name
# define CLOCK_CYCLES(c) \
{ \
if (fpu_cycles > 0) { \
fpu_cycles -= (c); \
if (fpu_cycles < 0) { \
cycles += fpu_cycles; \
} \
} else { \
cycles -= (c); \
} \
}
#define OP_TABLE(name) ops_2386_##name
#define CLOCK_CYCLES(c) \
{ \
if (fpu_cycles > 0) { \
fpu_cycles -= (c); \
if (fpu_cycles < 0) { \
cycles += fpu_cycles; \
} \
} else { \
cycles -= (c); \
} \
}
# define CLOCK_CYCLES_FPU(c) cycles -= (c)
# define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#define CLOCK_CYCLES_FPU(c) cycles -= (c)
#define CONCURRENCY_CYCLES(c) fpu_cycles = (c)
#define CLOCK_CYCLES_ALWAYS(c) cycles -= (c)

46
src/cpu/386_common.c
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@@ -100,22 +100,22 @@ uint32_t backupregs[16];
x86seg _oldds;
int opcode_length[256] = { 3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 3, /* 0x0x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x1x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x2x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x3x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 0x4x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 0x5x */
1, 1, 3, 3, 1, 1, 1, 1, 3, 3, 2, 3, 1, 1, 1, 1, /* 0x6x */
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, /* 0x7x */
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, /* 0x8x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, /* 0x9x */
3, 3, 3, 3, 1, 1, 1, 1, 2, 3, 1, 1, 1, 1, 1, 1, /* 0xax */
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, /* 0xbx */
3, 3, 3, 1, 3, 3, 3, 3, 3, 1, 3, 1, 1, 2, 1, 1, /* 0xcx */
3, 3, 3, 3, 2, 2, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, /* 0xdx */
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 1, 1, 1, 1, /* 0xex */
1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, 1, 1, 3, 3 }; /* 0xfx */
int opcode_length[256] = { 3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 3, /* 0x0x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x1x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x2x */
3, 3, 3, 3, 3, 3, 1, 1, 3, 3, 3, 3, 3, 3, 1, 1, /* 0x3x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 0x4x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 0x5x */
1, 1, 3, 3, 1, 1, 1, 1, 3, 3, 2, 3, 1, 1, 1, 1, /* 0x6x */
2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, /* 0x7x */
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, /* 0x8x */
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, /* 0x9x */
3, 3, 3, 3, 1, 1, 1, 1, 2, 3, 1, 1, 1, 1, 1, 1, /* 0xax */
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, /* 0xbx */
3, 3, 3, 1, 3, 3, 3, 3, 3, 1, 3, 1, 1, 2, 1, 1, /* 0xcx */
3, 3, 3, 3, 2, 2, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, /* 0xdx */
2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 1, 1, 1, 1, /* 0xex */
1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, 1, 1, 3, 3 }; /* 0xfx */
uint32_t addr64;
uint32_t addr64_2;
@@ -382,7 +382,7 @@ x386_common_log(const char *fmt, ...)
Note that this is only used for 286 / 386 systems. It is disabled when the
internal cache on 486+ CPUs is enabled.
*/
static int prefetch_bytes = 0;
static int prefetch_bytes = 0;
void
prefetch_run(int instr_cycles, int bytes, int modrm, int reads, int reads_l, int writes, int writes_l, int ea32)
@@ -1164,13 +1164,13 @@ enter_smm(int in_hlt)
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
if (is_cxsmm) /* Cx6x86 */
if (is_cxsmm) /* Cx6x86 */
smram_save_state_cyrix(saved_state, in_hlt);
else if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
smram_save_state_p5(saved_state, in_hlt);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
else if (is_k5 || is_k6) /* AMD K5 and K6 */
smram_save_state_amd_k(saved_state, in_hlt);
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_save_state_p6(saved_state, in_hlt);
cr0 &= ~0x8000000d;
@@ -1335,13 +1335,13 @@ leave_smm(void)
}
x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
if (is_cxsmm) /* Cx6x86 */
if (is_cxsmm) /* Cx6x86 */
smram_restore_state_cyrix(saved_state);
else if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
smram_restore_state_p5(saved_state);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
else if (is_k5 || is_k6) /* AMD K5 and K6 */
smram_restore_state_amd_k(saved_state);
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_restore_state_p6(saved_state);
in_smm = 0;

399
src/cpu/386_common.h
View File

@@ -20,111 +20,111 @@
#define _386_COMMON_H_
#include <stddef.h>
#include <inttypes.h>
#include <inttypes.h>
#ifdef OPS_286_386
#define readmemb_n(s,a,b) readmembl_no_mmut_2386((s)+(a),b)
#define readmemw_n(s,a,b) readmemwl_no_mmut_2386((s)+(a),b)
#define readmeml_n(s,a,b) readmemll_no_mmut_2386((s)+(a),b)
#define readmemb(s,a) readmembl_2386((s)+(a))
#define readmemw(s,a) readmemwl_2386((s)+(a))
#define readmeml(s,a) readmemll_2386((s)+(a))
#define readmemq(s,a) readmemql_2386((s)+(a))
# define readmemb_n(s, a, b) readmembl_no_mmut_2386((s) + (a), b)
# define readmemw_n(s, a, b) readmemwl_no_mmut_2386((s) + (a), b)
# define readmeml_n(s, a, b) readmemll_no_mmut_2386((s) + (a), b)
# define readmemb(s, a) readmembl_2386((s) + (a))
# define readmemw(s, a) readmemwl_2386((s) + (a))
# define readmeml(s, a) readmemll_2386((s) + (a))
# define readmemq(s, a) readmemql_2386((s) + (a))
#define writememb_n(s,a,b,v) writemembl_no_mmut_2386((s)+(a),b,v)
#define writememw_n(s,a,b,v) writememwl_no_mmut_2386((s)+(a),b,v)
#define writememl_n(s,a,b,v) writememll_no_mmut_2386((s)+(a),b,v)
#define writememb(s,a,v) writemembl_2386((s)+(a),v)
#define writememw(s,a,v) writememwl_2386((s)+(a),v)
#define writememl(s,a,v) writememll_2386((s)+(a),v)
#define writememq(s,a,v) writememql_2386((s)+(a),v)
# define writememb_n(s, a, b, v) writemembl_no_mmut_2386((s) + (a), b, v)
# define writememw_n(s, a, b, v) writememwl_no_mmut_2386((s) + (a), b, v)
# define writememl_n(s, a, b, v) writememll_no_mmut_2386((s) + (a), b, v)
# define writememb(s, a, v) writemembl_2386((s) + (a), v)
# define writememw(s, a, v) writememwl_2386((s) + (a), v)
# define writememl(s, a, v) writememll_2386((s) + (a), v)
# define writememq(s, a, v) writememql_2386((s) + (a), v)
#define do_mmut_rb(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 0)
#define do_mmut_rw(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 0)
#define do_mmut_rl(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 0)
#define do_mmut_rb2(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 0)
#define do_mmut_rw2(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 0)
#define do_mmut_rl2(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 0)
# define do_mmut_rb(s, a, b) do_mmutranslate_2386((s) + (a), b, 1, 0)
# define do_mmut_rw(s, a, b) do_mmutranslate_2386((s) + (a), b, 2, 0)
# define do_mmut_rl(s, a, b) do_mmutranslate_2386((s) + (a), b, 4, 0)
# define do_mmut_rb2(s, a, b) do_mmutranslate_2386((s) + (a), b, 1, 0)
# define do_mmut_rw2(s, a, b) do_mmutranslate_2386((s) + (a), b, 2, 0)
# define do_mmut_rl2(s, a, b) do_mmutranslate_2386((s) + (a), b, 4, 0)
#define do_mmut_wb(s,a,b) do_mmutranslate_2386((s)+(a), b, 1, 1)
#define do_mmut_ww(s,a,b) do_mmutranslate_2386((s)+(a), b, 2, 1)
#define do_mmut_wl(s,a,b) do_mmutranslate_2386((s)+(a), b, 4, 1)
# define do_mmut_wb(s, a, b) do_mmutranslate_2386((s) + (a), b, 1, 1)
# define do_mmut_ww(s, a, b) do_mmutranslate_2386((s) + (a), b, 2, 1)
# define do_mmut_wl(s, a, b) do_mmutranslate_2386((s) + (a), b, 4, 1)
#else
#define readmemb_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl_no_mmut((s) + (a), b) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
#define readmemw_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl_no_mmut((s) + (a), b) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
#define readmeml_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll_no_mmut((s) + (a), b) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
#define readmemb(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl((s) + (a)) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
#define readmemw(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl((s) + (a)) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
#define readmeml(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll((s) + (a)) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
#define readmemq(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) ? readmemql((s) + (a)) : *(uint64_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
# define readmemb_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl_no_mmut((s) + (a), b) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
# define readmemw_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl_no_mmut((s) + (a), b) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
# define readmeml_n(s, a, b) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll_no_mmut((s) + (a), b) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
# define readmemb(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) ? readmembl((s) + (a)) : *(uint8_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
# define readmemw(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) ? readmemwl((s) + (a)) : *(uint16_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
# define readmeml(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) ? readmemll((s) + (a)) : *(uint32_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uint32_t) ((s) + (a))))
# define readmemq(s, a) ((readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) ? readmemql((s) + (a)) : *(uint64_t *) (readlookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))))
#define writememb_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
writemembl_no_mmut((s) + (a), b, v); \
else \
*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememw_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
writememwl_no_mmut((s) + (a), b, v); \
else \
*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememl_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
writememll_no_mmut((s) + (a), b, v); \
else \
*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememb(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
writemembl((s) + (a), v); \
else \
*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememw(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
writememwl((s) + (a), v); \
else \
*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememl(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
writememll((s) + (a), v); \
else \
*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define writememq(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) \
writememql((s) + (a), v); \
else \
*(uint64_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememb_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
writemembl_no_mmut((s) + (a), b, v); \
else \
*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememw_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
writememwl_no_mmut((s) + (a), b, v); \
else \
*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememl_n(s, a, b, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
writememll_no_mmut((s) + (a), b, v); \
else \
*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememb(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
writemembl((s) + (a), v); \
else \
*(uint8_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememw(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
writememwl((s) + (a), v); \
else \
*(uint16_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememl(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
writememll((s) + (a), v); \
else \
*(uint32_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
# define writememq(s, a, v) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 7)) \
writememql((s) + (a), v); \
else \
*(uint64_t *) (writelookup2[(uint32_t) ((s) + (a)) >> 12] + (uintptr_t) ((s) + (a))) = v
#define do_mmut_rb(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 0)
#define do_mmut_rw(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 0)
#define do_mmut_rl(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 0)
#define do_mmut_rb2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 0)
#define do_mmut_rw2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 0)
#define do_mmut_rl2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 0)
# define do_mmut_rb(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 0)
# define do_mmut_rw(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 0)
# define do_mmut_rl(s, a, b) \
if (readlookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 0)
# define do_mmut_rb2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 0)
# define do_mmut_rw2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 0)
# define do_mmut_rl2(s, a, b) \
old_rl2 = readlookup2[(uint32_t) ((s) + (a)) >> 12]; \
if (old_rl2 == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 0)
#define do_mmut_wb(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 1)
#define do_mmut_ww(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 1)
#define do_mmut_wl(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 1)
# define do_mmut_wb(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF) \
do_mmutranslate((s) + (a), b, 1, 1)
# define do_mmut_ww(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 1)) \
do_mmutranslate((s) + (a), b, 2, 1)
# define do_mmut_wl(s, a, b) \
if (writelookup2[(uint32_t) ((s) + (a)) >> 12] == (uintptr_t) LOOKUP_INV || (s) == 0xFFFFFFFF || (((s) + (a)) & 3)) \
do_mmutranslate((s) + (a), b, 4, 1)
#endif
int checkio(uint32_t port, int mask);
@@ -222,17 +222,20 @@ int checkio(uint32_t port, int mask);
#ifdef OPS_286_386
/* TODO: Introduce functions to read exec. */
static __inline uint8_t fastreadb(uint32_t a)
static __inline uint8_t
fastreadb(uint32_t a)
{
return readmembl(a);
}
static __inline uint16_t fastreadw(uint32_t a)
static __inline uint16_t
fastreadw(uint32_t a)
{
return readmemwl(a);
}
static __inline uint32_t fastreadl(uint32_t a)
static __inline uint32_t
fastreadl(uint32_t a)
{
return readmemll(a);
}
@@ -243,21 +246,21 @@ fastreadb(uint32_t a)
uint8_t *t;
if ((a >> 12) == pccache)
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint8_t *) &pccache2[a]);
#endif
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint8_t *) &pccache2[a]);
#endif
# endif
}
static __inline uint16_t
@@ -271,22 +274,22 @@ fastreadw(uint32_t a)
return val;
}
if ((a >> 12) == pccache)
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint16_t *) &pccache2[a]);
#endif
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint16_t *) &pccache2[a]);
#endif
# endif
}
static __inline uint32_t
@@ -302,11 +305,11 @@ fastreadl(uint32_t a)
pccache2 = t;
pccache = a >> 12;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint32_t *) &pccache2[a]);
#endif
# endif
}
val = fastreadw(a);
val |= (fastreadw(a + 2) << 16);
@@ -378,22 +381,22 @@ fastreadw_fetch(uint32_t a)
return val;
}
if ((a >> 12) == pccache)
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint16_t *) &pccache2[a]);
#endif
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint16_t *) &pccache2[a]);
#endif
# endif
}
static __inline uint32_t
@@ -409,11 +412,11 @@ fastreadl_fetch(uint32_t a)
pccache2 = t;
pccache = a >> 12;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
#else
# else
return *((uint32_t *) &pccache2[a]);
#endif
# endif
}
val = fastreadw_fetch(a);
if (opcode_length[val & 0xff] > 2)
@@ -451,65 +454,91 @@ getquad(void)
}
#ifdef OPS_286_386
static __inline uint8_t geteab(void)
static __inline uint8_t
geteab(void)
{
if (cpu_mod == 3)
return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm&3].b.l;
return (cpu_rm & 4) ? cpu_state.regs[cpu_rm & 3].b.h : cpu_state.regs[cpu_rm & 3].b.l;
return readmemb(easeg, cpu_state.eaaddr);
}
static __inline uint16_t geteaw(void)
static __inline uint16_t
geteaw(void)
{
if (cpu_mod == 3)
return cpu_state.regs[cpu_rm].w;
return readmemw(easeg, cpu_state.eaaddr);
}
static __inline uint32_t geteal(void)
static __inline uint32_t
geteal(void)
{
if (cpu_mod == 3)
return cpu_state.regs[cpu_rm].l;
return readmeml(easeg, cpu_state.eaaddr);
}
static __inline uint64_t geteaq(void)
static __inline uint64_t
geteaq(void)
{
return readmemq(easeg, cpu_state.eaaddr);
}
static __inline uint8_t geteab_mem(void)
static __inline uint8_t
geteab_mem(void)
{
return readmemb(easeg,cpu_state.eaaddr);
return readmemb(easeg, cpu_state.eaaddr);
}
static __inline uint16_t geteaw_mem(void)
static __inline uint16_t
geteaw_mem(void)
{
return readmemw(easeg,cpu_state.eaaddr);
return readmemw(easeg, cpu_state.eaaddr);
}
static __inline uint32_t geteal_mem(void)
static __inline uint32_t
geteal_mem(void)
{
return readmeml(easeg,cpu_state.eaaddr);
return readmeml(easeg, cpu_state.eaaddr);
}
static __inline int seteaq_cwc(void)
static __inline int
seteaq_cwc(void)
{
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr);
return 0;
}
static __inline void seteaq(uint64_t v)
static __inline void
seteaq(uint64_t v)
{
if (seteaq_cwc())
return;
writememql(easeg + cpu_state.eaaddr, v);
}
#define seteab(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); writemembl_2386(easeg+cpu_state.eaaddr,v); } else if (cpu_rm&4) cpu_state.regs[cpu_rm&3].b.h=v; else cpu_state.regs[cpu_rm].b.l=v
#define seteaw(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); writememwl_2386(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].w=v
#define seteal(v) if (cpu_mod!=3) { CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); writememll_2386(easeg+cpu_state.eaaddr,v); } else cpu_state.regs[cpu_rm].l=v
# define seteab(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); \
writemembl_2386(easeg + cpu_state.eaaddr, v); \
} else if (cpu_rm & 4) \
cpu_state.regs[cpu_rm & 3].b.h = v; \
else \
cpu_state.regs[cpu_rm].b.l = v
# define seteaw(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
writememwl_2386(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].w = v
# define seteal(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
writememll_2386(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].l = v
#define seteab_mem(v) writemembl_2386(easeg+cpu_state.eaaddr,v);
#define seteaw_mem(v) writememwl_2386(easeg+cpu_state.eaaddr,v);
#define seteal_mem(v) writememll_2386(easeg+cpu_state.eaaddr,v);
# define seteab_mem(v) writemembl_2386(easeg + cpu_state.eaaddr, v);
# define seteaw_mem(v) writememwl_2386(easeg + cpu_state.eaaddr, v);
# define seteal_mem(v) writememll_2386(easeg + cpu_state.eaaddr, v);
#else
static __inline uint8_t
geteab(void)
@@ -584,51 +613,51 @@ seteaq(uint64_t v)
writememql(easeg + cpu_state.eaaddr, v);
}
#define seteab(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); \
if (eal_w) \
*(uint8_t *) eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v); \
} else if (cpu_rm & 4) \
cpu_state.regs[cpu_rm & 3].b.h = v; \
else \
cpu_state.regs[cpu_rm].b.l = v
#define seteaw(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
if (eal_w) \
*(uint16_t *) eal_w = v; \
# define seteab(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr); \
if (eal_w) \
*(uint8_t *) eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v); \
} else if (cpu_rm & 4) \
cpu_state.regs[cpu_rm & 3].b.h = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].w = v
#define seteal(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].l = v
cpu_state.regs[cpu_rm].b.l = v
# define seteaw(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
if (eal_w) \
*(uint16_t *) eal_w = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].w = v
# define seteal(v) \
if (cpu_mod != 3) { \
CHECK_WRITE_COMMON(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v); \
} else \
cpu_state.regs[cpu_rm].l = v
#define seteab_mem(v) \
if (eal_w) \
*(uint8_t *) eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v);
#define seteaw_mem(v) \
if (eal_w) \
*(uint16_t *) eal_w = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v);
#define seteal_mem(v) \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v);
# define seteab_mem(v) \
if (eal_w) \
*(uint8_t *) eal_w = v; \
else \
writemembl(easeg + cpu_state.eaaddr, v);
# define seteaw_mem(v) \
if (eal_w) \
*(uint16_t *) eal_w = v; \
else \
writememwl(easeg + cpu_state.eaaddr, v);
# define seteal_mem(v) \
if (eal_w) \
*eal_w = v; \
else \
writememll(easeg + cpu_state.eaaddr, v);
#endif
#define getbytef() \

8
src/cpu/386_dynarec.c
View File

@@ -46,8 +46,8 @@
#define CPU_BLOCK_END() cpu_block_end = 1
int inrecomp = 0;
int cpu_block_end = 0;
int inrecomp = 0;
int cpu_block_end = 0;
int cpu_end_block_after_ins = 0;
#ifdef ENABLE_386_DYNAREC_LOG
@@ -335,9 +335,9 @@ exec386_dynarec_int(void)
static __inline void
exec386_dynarec_dyn(void)
{
uint32_t start_pc = 0;
uint32_t start_pc = 0;
uint32_t phys_addr = get_phys(cs + cpu_state.pc);
int hash = HASH(phys_addr);
int hash = HASH(phys_addr);
# ifdef USE_NEW_DYNAREC
codeblock_t *block = &codeblock[codeblock_hash[hash]];
# else

66
src/cpu/386_ops.h
View File

@@ -180,7 +180,7 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_bit.h"
#include "x86_ops_bitscan.h"
#ifndef OPS_286_386
#include "x86_ops_cyrix.h"
# include "x86_ops_cyrix.h"
#endif
#include "x86_ops_flag.h"
#include "x86_ops_fpu.h"
@@ -191,21 +191,21 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_misc.h"
#include "x87_ops.h"
#ifndef OPS_286_386
#include "x86_ops_i686.h"
#include "x86_ops_mmx.h"
#include "x86_ops_mmx_arith.h"
#include "x86_ops_mmx_cmp.h"
#include "x86_ops_mmx_logic.h"
#include "x86_ops_mmx_mov.h"
#include "x86_ops_mmx_pack.h"
#include "x86_ops_mmx_shift.h"
# include "x86_ops_i686.h"
# include "x86_ops_mmx.h"
# include "x86_ops_mmx_arith.h"
# include "x86_ops_mmx_cmp.h"
# include "x86_ops_mmx_logic.h"
# include "x86_ops_mmx_mov.h"
# include "x86_ops_mmx_pack.h"
# include "x86_ops_mmx_shift.h"
#endif
#include "x86_ops_mov.h"
#include "x86_ops_mov_ctrl.h"
#include "x86_ops_mov_seg.h"
#include "x86_ops_movx.h"
#ifndef OPS_286_386
#include "x86_ops_msr.h"
# include "x86_ops_msr.h"
#endif
#include "x86_ops_mul.h"
#include "x86_ops_pmode.h"
@@ -213,26 +213,26 @@ extern void x386_dynarec_log(const char *fmt, ...);
#ifdef IS_DYNAREC
# include "x86_ops_rep_dyn.h"
#else
#ifdef OPS_286_386
# include "x86_ops_rep_2386.h"
#else
# include "x86_ops_rep.h"
#endif
# ifdef OPS_286_386
# include "x86_ops_rep_2386.h"
# else
# include "x86_ops_rep.h"
# endif
#endif
#include "x86_ops_ret.h"
#include "x86_ops_set.h"
#include "x86_ops_stack.h"
#ifdef OPS_286_386
#include "x86_ops_string_2386.h"
# include "x86_ops_string_2386.h"
#else
#include "x86_ops_string.h"
# include "x86_ops_string.h"
#endif
#include "x86_ops_xchg.h"
#include "x86_ops_call.h"
#include "x86_ops_shift.h"
#ifndef OPS_286_386
#include "x86_ops_amd.h"
#include "x86_ops_3dnow.h"
# include "x86_ops_amd.h"
# include "x86_ops_3dnow.h"
#endif
#include <time.h>
@@ -351,40 +351,44 @@ opVPCEXT(uint32_t fetchdat)
#endif
#ifdef OPS_286_386
static int op0F_w_a16(uint32_t fetchdat)
static int
op0F_w_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
fopcode = opcode;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_2386_opcodes_0f[opcode](fetchdat >> 8);
}
static int op0F_l_a16(uint32_t fetchdat)
static int
op0F_l_a16(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
fopcode = opcode;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_2386_opcodes_0f[opcode | 0x100](fetchdat >> 8);
}
static int op0F_w_a32(uint32_t fetchdat)
static int
op0F_w_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
fopcode = opcode;
cpu_state.pc++;
PREFETCH_PREFIX();
return x86_2386_opcodes_0f[opcode | 0x200](fetchdat >> 8);
}
static int op0F_l_a32(uint32_t fetchdat)
static int
op0F_l_a32(uint32_t fetchdat)
{
int opcode = fetchdat & 0xff;
fopcode = opcode;
fopcode = opcode;
cpu_state.pc++;
PREFETCH_PREFIX();
@@ -1361,7 +1365,7 @@ const OpFn OP_TABLE(pentium_0f)[1024] = {
// clang-format on
};
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
# if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
const OpFn OP_TABLE(c6x86_0f)[1024] = {
// clang-format off
/*16-bit data, 16-bit addr*/
@@ -1453,7 +1457,7 @@ const OpFn OP_TABLE(c6x86_0f)[1024] = {
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(pentiummmx_0f)[1024] = {
// clang-format off
@@ -1731,7 +1735,7 @@ const OpFn OP_TABLE(k62_0f)[1024] = {
// clang-format on
};
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
# if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
const OpFn OP_TABLE(c6x86mx_0f)[1024] = {
// clang-format off
/*16-bit data, 16-bit addr*/
@@ -1823,7 +1827,7 @@ const OpFn OP_TABLE(c6x86mx_0f)[1024] = {
/*f0*/ ILLEGAL, opPSLLW_a32, opPSLLD_a32, opPSLLQ_a32, ILLEGAL, opPMADDWD_a32, ILLEGAL, ILLEGAL, opPSUBB_a32, opPSUBW_a32, opPSUBD_a32, ILLEGAL, opPADDB_a32, opPADDW_a32, opPADDD_a32, ILLEGAL,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(pentiumpro_0f)[1024] = {
// clang-format off

179
src/cpu/808x.c
View File

@@ -76,34 +76,34 @@ static int in_rep = 0;
static int repeating = 0;
static int rep_c_flag = 0;
static int oldc;
static int clear_lock = 0;
static int refresh = 0;
static int clear_lock = 0;
static int refresh = 0;
static int cycdiff;
static int access_code = 0;
static int hlda = 0;
static int not_ready = 0;
static int bus_request_type = 0;
static int pic_data = -1;
static int last_was_code = 0;
static uint16_t mem_data = 0;
static uint32_t mem_seg = 0;
static uint16_t mem_addr = 0;
static int schedule_fetch = 1;
static int pasv = 0;
static int access_code = 0;
static int hlda = 0;
static int not_ready = 0;
static int bus_request_type = 0;
static int pic_data = -1;
static int last_was_code = 0;
static uint16_t mem_data = 0;
static uint32_t mem_seg = 0;
static uint16_t mem_addr = 0;
static int schedule_fetch = 1;
static int pasv = 0;
#define BUS_OUT 1
#define BUS_HIGH 2
#define BUS_WIDE 4
#define BUS_CODE 8
#define BUS_IO 16
#define BUS_MEM 32
#define BUS_PIC 64
#define BUS_OUT 1
#define BUS_HIGH 2
#define BUS_WIDE 4
#define BUS_CODE 8
#define BUS_IO 16
#define BUS_MEM 32
#define BUS_PIC 64
#define BUS_ACCESS_TYPE (BUS_CODE | BUS_IO | BUS_MEM | BUS_PIC)
#define BUS_CYCLE (biu_cycles & 3)
#define BUS_CYCLE_T1 biu_cycles = 0
#define BUS_CYCLE_NEXT biu_cycles = (biu_cycles + 1) & 3
#define BUS_CYCLE (biu_cycles & 3)
#define BUS_CYCLE_T1 biu_cycles = 0
#define BUS_CYCLE_NEXT biu_cycles = (biu_cycles + 1) & 3
enum {
BUS_T1 = 0,
@@ -221,7 +221,7 @@ clock_end(void)
static void
process_timers(void)
{
{
clock_end();
clock_start();
}
@@ -258,7 +258,7 @@ bus_outw(uint16_t port, uint16_t val)
static uint8_t
bus_inb(uint16_t port)
{
int old_cycles = cycles;
int old_cycles = cycles;
uint8_t ret;
cycles--;
@@ -271,7 +271,7 @@ bus_inb(uint16_t port)
static uint16_t
bus_inw(uint16_t port)
{
int old_cycles = cycles;
int old_cycles = cycles;
uint16_t ret;
cycles--;
@@ -377,7 +377,7 @@ run_bus_cycle(int io_type)
not_ready = 0;
}
switch(BUS_CYCLE) {
switch (BUS_CYCLE) {
case BUS_T1:
access_code = !!(io_type & BUS_CODE);
break;
@@ -394,7 +394,7 @@ run_bus_cycle(int io_type)
bus_do_mem(io_type);
break;
case BUS_PIC:
pic_data = pic_irq_ack();
pic_data = pic_irq_ack();
last_was_code = 0;
break;
default:
@@ -455,17 +455,17 @@ cycles_biu(int bus, int init)
switch (BUS_CYCLE) {
case BUS_T1:
case BUS_T2:
BUS_CYCLE_T1; /* Simply abort the prefetch before actual scheduling, no penalty. */
BUS_CYCLE_T1; /* Simply abort the prefetch before actual scheduling, no penalty. */
break;
case BUS_T3:
case BUS_T4:
cycles_idle(5 - BUS_CYCLE); /* Leftover BIU cycles + 2 idle cycles. */
BUS_CYCLE_T1; /* Abort the prefetch. */
cycles_idle(5 - BUS_CYCLE); /* Leftover BIU cycles + 2 idle cycles. */
BUS_CYCLE_T1; /* Abort the prefetch. */
break;
}
schedule_fetch = 0;
access_code = 0;
access_code = 0;
}
}
@@ -570,7 +570,7 @@ cpu_io(int bits, int out, uint16_t port)
} else {
bus_request_type = BUS_IO | BUS_OUT;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_IO | BUS_OUT | BUS_HIGH;
wait(4, 1);
}
@@ -586,7 +586,7 @@ cpu_io(int bits, int out, uint16_t port)
} else {
bus_request_type = BUS_IO;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_IO | BUS_HIGH;
wait(4, 1);
}
@@ -609,11 +609,11 @@ readmemb(uint32_t s, uint16_t a)
bus_init();
#endif
mem_seg = s;
mem_addr = a;
mem_seg = s;
mem_addr = a;
bus_request_type = BUS_MEM;
wait(4, 1);
ret = mem_data & 0xff;
ret = mem_data & 0xff;
bus_request_type = 0;
return ret;
@@ -643,7 +643,7 @@ readmemw(uint32_t s, uint16_t a)
bus_init();
#endif
mem_seg = s;
mem_seg = s;
mem_addr = a;
if (is8086 && !(a & 1)) {
bus_request_type = BUS_MEM | BUS_WIDE;
@@ -651,11 +651,11 @@ readmemw(uint32_t s, uint16_t a)
} else {
bus_request_type = BUS_MEM | BUS_HIGH;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_MEM;
wait(4, 1);
}
ret = mem_data;
ret = mem_data;
bus_request_type = 0;
return ret;
@@ -716,9 +716,9 @@ writememb(uint32_t s, uint32_t a, uint8_t v)
bus_init();
#endif
mem_seg = s;
mem_addr = a;
mem_data = v;
mem_seg = s;
mem_addr = a;
mem_data = v;
bus_request_type = BUS_MEM | BUS_OUT;
wait(4, 1);
bus_request_type = 0;
@@ -737,7 +737,7 @@ writememw(uint32_t s, uint32_t a, uint16_t v)
bus_init();
#endif
mem_seg = s;
mem_seg = s;
mem_addr = a;
mem_data = v;
if (is8086 && !(a & 1)) {
@@ -746,7 +746,7 @@ writememw(uint32_t s, uint32_t a, uint16_t v)
} else {
bus_request_type = BUS_MEM | BUS_OUT | BUS_HIGH;
wait(4, 1);
schedule_fetch = 0;
schedule_fetch = 0;
bus_request_type = BUS_MEM | BUS_OUT;
wait(4, 1);
}
@@ -791,13 +791,13 @@ pfq_write(void)
free in the queue. */
tempw = readmemwf(pfq_ip);
*(uint16_t *) &(pfq[pfq_pos]) = tempw;
pfq_ip = (pfq_ip + 2) & 0xffff;
pfq_ip = (pfq_ip + 2) & 0xffff;
pfq_pos += 2;
} else if (!fetch_word && (pfq_pos < pfq_size)) {
/* The 8088 fetches 1 byte at a time, and only if there's at least 1 byte
free in the queue. */
pfq[pfq_pos] = readmembf(pfq_ip);
pfq_ip = (pfq_ip + 1) & 0xffff;
pfq_ip = (pfq_ip + 1) & 0xffff;
pfq_pos++;
}
@@ -890,8 +890,8 @@ pfq_add(void)
static void
pfq_clear(void)
{
pfq_pos = 0;
prefetching = 0;
pfq_pos = 0;
prefetching = 0;
schedule_fetch = 0;
BUS_CYCLE_T1;
@@ -900,8 +900,8 @@ pfq_clear(void)
static void
pfq_suspend(void)
{
pfq_clear();
cycles_idle(3);
pfq_clear();
cycles_idle(3);
}
static void
@@ -955,20 +955,20 @@ reset_808x(int hard)
schedule_fetch = 1;
pasv = 0;
cpu_alu_op = 0;
cpu_alu_op = 0;
use_custom_nmi_vector = 0x00;
custom_nmi_vector = 0x00000000;
access_code = 0;
hlda = 0;
not_ready = 0;
bus_request_type = 0;
pic_data = -1;
last_was_code = 0;
mem_data = 0;
mem_seg = 0;
mem_addr = 0;
access_code = 0;
hlda = 0;
not_ready = 0;
bus_request_type = 0;
pic_data = -1;
last_was_code = 0;
mem_data = 0;
mem_seg = 0;
mem_addr = 0;
}
static void
@@ -976,7 +976,7 @@ set_ip(uint16_t new_ip)
{
pfq_ip = cpu_state.pc = new_ip;
prefetching = 1;
schedule_fetch = prefetching && (pfq_pos < pfq_size);
schedule_fetch = prefetching && (pfq_pos < pfq_size);
}
/* Memory refresh read - called by reads and writes on DMA channel 0. */
@@ -1025,16 +1025,17 @@ do_mod_rm(void)
easeg = ovr_seg ? *ovr_seg : ds;
wait(2, 0);
return;
} else switch (cpu_rm) {
case 0:
case 3:
wait(2, 0);
break;
case 1:
case 2:
wait(3, 0);
break;
}
} else
switch (cpu_rm) {
case 0:
case 3:
wait(2, 0);
break;
case 1:
case 2:
wait(3, 0);
break;
}
cpu_state.eaaddr = (*mod1add[0][cpu_rm]) + (*mod1add[1][cpu_rm]);
easeg = ovr_seg ? *ovr_seg : *mod1seg[cpu_rm];
switch (rmdat & 0xc0) {
@@ -1220,11 +1221,11 @@ interrupt(uint16_t addr)
addr <<= 2;
cpu_state.eaaddr = addr;
old_cs = CS;
new_ip = readmemw(0, cpu_state.eaaddr);
new_ip = readmemw(0, cpu_state.eaaddr);
wait(1, 0);
cpu_state.eaaddr = (cpu_state.eaaddr + 2) & 0xffff;
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
new_cs = readmemw(0, cpu_state.eaaddr);
prefetching = 0;
pfq_clear();
ovr_seg = NULL;
wait(2, 0);
@@ -1296,7 +1297,7 @@ bus_pic_ack(void)
{
int old_in_lock = in_lock;
in_lock = 1;
in_lock = 1;
bus_request_type = BUS_PIC;
wait(4, 1);
in_lock = old_in_lock;
@@ -1376,7 +1377,7 @@ rep_interrupt(void)
return 0;
}
completed = 1;
CX = tmpc;
CX = tmpc;
pfq_clear();
if (is_nec && (ovr_seg != NULL))
set_ip(cpu_state.pc - 3);
@@ -2011,9 +2012,9 @@ execx86(int cycs)
#if 0
opcode = pfq_fetchb();
#endif
opcode = pfq_fetchb_common();
handled = 0;
oldc = cpu_state.flags & C_FLAG;
opcode = pfq_fetchb_common();
handled = 0;
oldc = cpu_state.flags & C_FLAG;
if (clear_lock) {
in_lock = 0;
clear_lock = 0;
@@ -2587,7 +2588,7 @@ execx86(int cycs)
break;
default:
opcode = orig_opcode;
opcode = orig_opcode;
cpu_state.pc = (cpu_state.pc - 1) & 0xffff;
break;
}
@@ -3165,7 +3166,7 @@ execx86(int cycs)
wait(2, 0);
cpu_state.eaaddr = DI;
cpu_data = readmem(es);
DI = string_increment(bits);
DI = string_increment(bits);
cpu_src = cpu_data;
cpu_dest = tmpa;
sub(bits);
@@ -3582,7 +3583,7 @@ execx86(int cycs)
case 0xE5:
bits = 8 << (opcode & 1);
wait(1, 0);
cpu_data = pfq_fetchb();
cpu_data = pfq_fetchb();
cpu_state.eaaddr = cpu_data;
wait(1, 0);
cpu_io(bits, 0, cpu_state.eaaddr);
@@ -3591,16 +3592,16 @@ execx86(int cycs)
case 0xE7:
bits = 8 << (opcode & 1);
wait(1, 0);
cpu_data = pfq_fetchb();
cpu_data = pfq_fetchb();
cpu_state.eaaddr = cpu_data;
cpu_data = (bits == 16) ? AX : AL;
cpu_data = (bits == 16) ? AX : AL;
wait(2, 0);
cpu_io(bits, 1, cpu_state.eaaddr);
break;
case 0xEC:
case 0xED:
bits = 8 << (opcode & 1);
cpu_data = DX;
bits = 8 << (opcode & 1);
cpu_data = DX;
cpu_state.eaaddr = cpu_data;
wait(1, 0);
cpu_io(bits, 0, cpu_state.eaaddr);
@@ -3609,9 +3610,9 @@ execx86(int cycs)
case 0xEF:
bits = 8 << (opcode & 1);
wait(2, 0);
cpu_data = DX;
cpu_data = DX;
cpu_state.eaaddr = cpu_data;
cpu_data = (bits == 16) ? AX : AL;
cpu_data = (bits == 16) ? AX : AL;
cpu_io(bits, 1, cpu_state.eaaddr);
wait(1, 0);
break;

4
src/cpu/codegen_timing_common.h
View File

@@ -5,9 +5,9 @@
/*Instruction has input dependency on register in R/M field*/
#define SRCDEP_RM (1ULL << 1)
/*Instruction modifies register in REG field*/
#define DSTDEP_REG (1ULL<< 2)
#define DSTDEP_REG (1ULL << 2)
/*Instruction modifies register in R/M field*/
#define DSTDEP_RM (1ULL << 3)
#define DSTDEP_RM (1ULL << 3)
#define SRCDEP_SHIFT 4
#define DSTDEP_SHIFT 12

36
src/cpu/cpu.c
View File

@@ -241,7 +241,7 @@ uint32_t cache_index = 0;
uint8_t _cache[2048];
uint64_t cpu_CR4_mask;
uint64_t tsc = 0;
uint64_t tsc = 0;
uint64_t pmc[2] = { 0, 0 };
double cpu_dmulti;
@@ -254,7 +254,7 @@ cyrix_t cyrix;
cpu_family_t *cpu_f;
CPU *cpu_s;
uint8_t do_translate = 0;
uint8_t do_translate = 0;
uint8_t do_translate2 = 0;
void (*cpu_exec)(int cycs);
@@ -474,7 +474,7 @@ SF_FPU_reset(void)
fpu_state.fcs = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
memset(fpu_state.st_space, 0, sizeof(floatx80)*8);
memset(fpu_state.st_space, 0, sizeof(floatx80) * 8);
}
}
@@ -561,11 +561,11 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_386_0f);
#endif
x86_setopcodes_2386(ops_2386_386, ops_2386_386_0f);
x86_opcodes_REPE = ops_REPE;
x86_opcodes_REPNE = ops_REPNE;
x86_2386_opcodes_REPE = ops_2386_REPE;
x86_opcodes_REPE = ops_REPE;
x86_opcodes_REPNE = ops_REPNE;
x86_2386_opcodes_REPE = ops_2386_REPE;
x86_2386_opcodes_REPNE = ops_2386_REPNE;
x86_opcodes_3DNOW = ops_3DNOW;
x86_opcodes_3DNOW = ops_3DNOW;
#ifdef USE_DYNAREC
x86_dynarec_opcodes_REPE = dynarec_ops_REPE;
x86_dynarec_opcodes_REPNE = dynarec_ops_REPNE;
@@ -1442,9 +1442,9 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_pentium_0f, dynarec_ops_386, dynarec_ops_pentium_0f);
else
x86_setopcodes(ops_386, ops_c6x86mx_0f, dynarec_ops_386, dynarec_ops_c6x86mx_0f);
#if 0
# if 0
x86_setopcodes(ops_386, ops_c6x86_0f, dynarec_ops_386, dynarec_ops_c6x86_0f);
#endif
# endif
# else
if (cpu_s->cpu_type == CPU_Cx6x86MX)
x86_setopcodes(ops_386, ops_c6x86mx_0f);
@@ -1452,9 +1452,9 @@ cpu_set(void)
x86_setopcodes(ops_386, ops_pentium_0f);
else
x86_setopcodes(ops_386, ops_c6x86mx_0f);
#if 0
# if 0
x86_setopcodes(ops_386, ops_c6x86_0f);
#endif
# endif
# endif
timing_rr = 1; /* register dest - register src */
@@ -1791,11 +1791,11 @@ cpu_set(void)
cpu_exec = exec386_dynarec;
else
#endif
/* Use exec386 for CPU_IBM486SLC because it can reach 100 MHz. */
if ((cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type > CPU_486DLC))
cpu_exec = exec386;
else
cpu_exec = exec386_2386;
/* Use exec386 for CPU_IBM486SLC because it can reach 100 MHz. */
if ((cpu_s->cpu_type == CPU_IBM486SLC) || (cpu_s->cpu_type > CPU_486DLC))
cpu_exec = exec386;
else
cpu_exec = exec386_2386;
} else if (cpu_s->cpu_type >= CPU_286)
cpu_exec = exec386_2386;
else
@@ -3567,7 +3567,7 @@ x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f,
#else
x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f)
{
x86_opcodes = opcodes;
x86_opcodes = opcodes;
x86_opcodes_0f = opcodes_0f;
}
#endif
@@ -3575,7 +3575,7 @@ x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f)
void
x86_setopcodes_2386(const OpFn *opcodes, const OpFn *opcodes_0f)
{
x86_2386_opcodes = opcodes;
x86_2386_opcodes = opcodes;
x86_2386_opcodes_0f = opcodes_0f;
}

32
src/cpu/cpu.h
View File

@@ -280,12 +280,12 @@ typedef struct {
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */
uint64_t ecx186; /* 0x00000186, 0x00000187 */
uint64_t ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx186; /* 0x00000186, 0x00000187 */
uint64_t ecx187; /* 0x00000186, 0x00000187 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t debug_ctl; /* 0x000001d9 - Debug Registers Control */
uint64_t ecx1e0; /* 0x000001e0 */
uint64_t ecx1e0; /* 0x000001e0 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
on the VIA Cyrix III */
@@ -450,7 +450,7 @@ typedef struct {
#define in_smm cpu_state._in_smm
#define smi_line cpu_state._smi_line
#define smbase cpu_state._smbase
#define smbase cpu_state._smbase
/*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
to be valid*/
@@ -460,9 +460,9 @@ typedef struct {
#define CPU_STATUS_V86 (1 << 3)
#define CPU_STATUS_SMM (1 << 4)
#ifdef USE_NEW_DYNAREC
#define CPU_STATUS_FLAGS 0xff
# define CPU_STATUS_FLAGS 0xff
#else
#define CPU_STATUS_FLAGS 0xffff
# define CPU_STATUS_FLAGS 0xffff
#endif
/*If the cpu_state.flags below are set in cpu_cur_status, they must be set in block->status.
@@ -621,8 +621,8 @@ extern uint64_t star;
#define FPU_CW_Reserved_Bits (0xe0c0)
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
#define cr0 cpu_state.CR0.l
#define msw cpu_state.CR0.w
extern uint32_t cr2;
extern uint32_t cr3;
extern uint32_t cr4;
@@ -726,8 +726,8 @@ extern void loadseg_dynarec(uint16_t seg, x86seg *s);
extern int loadseg(uint16_t seg, x86seg *s);
extern void loadcs(uint16_t seg);
#else
extern void loadseg(uint16_t seg, x86seg *s);
extern void loadcs(uint16_t seg);
extern void loadseg(uint16_t seg, x86seg *s);
extern void loadcs(uint16_t seg);
#endif
extern char *cpu_current_pc(char *bufp);
@@ -764,11 +764,11 @@ extern void pmodeint(int num, int soft);
extern void pmoderetf(int is32, uint16_t off);
extern void pmodeiret(int is32);
#else
extern void loadcscall(uint16_t seg);
extern void loadcsjmp(uint16_t seg, uint32_t old_pc);
extern void pmodeint(int num, int soft);
extern void pmoderetf(int is32, uint16_t off);
extern void pmodeiret(int is32);
extern void loadcscall(uint16_t seg);
extern void loadcsjmp(uint16_t seg, uint32_t old_pc);
extern void pmodeint(int num, int soft);
extern void pmoderetf(int is32, uint16_t off);
extern void pmodeiret(int is32);
#endif
extern void resetmcr(void);
extern void resetx86(void);
@@ -859,7 +859,7 @@ extern void cpu_fast_off_reset(void);
extern void smi_raise(void);
extern void nmi_raise(void);
extern MMX_REG *MMP[8];
extern MMX_REG *MMP[8];
extern uint16_t *MMEP[8];
extern void mmx_init(void);

6
src/cpu/x86.c
View File

@@ -59,11 +59,11 @@ uint32_t rmdat;
uint64_t xt_cpu_multi;
/* Variables for handling the non-maskable interrupts. */
int nmi = 0;
int nmi = 0;
int nmi_auto_clear = 0;
/* Was the CPU ever reset? */
int x86_was_reset = 0;
int x86_was_reset = 0;
int soft_reset_pci = 0;
/* Is the TRAP flag on? */
@@ -273,7 +273,7 @@ reset_common(int hard)
loadcs(0xF000);
cpu_state.pc = 0xFFF0;
if (hard) {
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
if (is6117)
rammask |= 0x03000000;
mem_a20_key = mem_a20_alt = mem_a20_state = 0;

3
src/cpu/x86_ops.h
View File

@@ -190,7 +190,6 @@ extern const OpFn dynarec_ops_3DNOWE[256];
extern void x86_setopcodes(const OpFn *opcodes, const OpFn *opcodes_0f);
#endif
extern const OpFn *x86_opcodes;
extern const OpFn *x86_opcodes_0f;
extern const OpFn *x86_opcodes_d8_a16;
@@ -330,7 +329,6 @@ extern const OpFn ops_REPNE[1024];
extern const OpFn ops_3DNOW[256];
extern const OpFn ops_3DNOWE[256];
extern void x86_setopcodes_2386(const OpFn *opcodes, const OpFn *opcodes_0f);
extern const OpFn *x86_2386_opcodes;
@@ -436,7 +434,6 @@ extern const OpFn ops_2386_REPE[1024];
extern const OpFn ops_2386_REPNE[1024];
extern const OpFn ops_2386_3DNOW[256];
#define C0 (1 << 8)
#define C1 (1 << 9)
#define C2 (1 << 10)

52
src/cpu/x86_ops_3dnow.h
View File

@@ -35,7 +35,7 @@ opFEMMS(uint32_t fetchdat)
static int
opPAVGUSB(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -56,7 +56,7 @@ opPAVGUSB(uint32_t fetchdat)
static int
opPF2ID(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -71,7 +71,7 @@ opPF2ID(uint32_t fetchdat)
static int
opPF2IW(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -86,9 +86,9 @@ opPF2IW(uint32_t fetchdat)
static int
opPFACC(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
float tempf;
float tempf;
MMX_GETSRC();
@@ -103,9 +103,9 @@ opPFACC(uint32_t fetchdat)
static int
opPFNACC(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
float tempf;
float tempf;
MMX_GETSRC();
@@ -120,9 +120,9 @@ opPFNACC(uint32_t fetchdat)
static int
opPFPNACC(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
float tempf;
float tempf;
MMX_GETSRC();
@@ -137,10 +137,10 @@ opPFPNACC(uint32_t fetchdat)
static int
opPSWAPD(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
float tempf;
float tempf2;
float tempf;
float tempf2;
MMX_GETSRC();
@@ -157,7 +157,7 @@ opPSWAPD(uint32_t fetchdat)
static int
opPFADD(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -172,7 +172,7 @@ opPFADD(uint32_t fetchdat)
static int
opPFCMPEQ(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -187,7 +187,7 @@ opPFCMPEQ(uint32_t fetchdat)
static int
opPFCMPGE(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -202,7 +202,7 @@ opPFCMPGE(uint32_t fetchdat)
static int
opPFCMPGT(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -217,7 +217,7 @@ opPFCMPGT(uint32_t fetchdat)
static int
opPFMAX(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -234,7 +234,7 @@ opPFMAX(uint32_t fetchdat)
static int
opPFMIN(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -251,7 +251,7 @@ opPFMIN(uint32_t fetchdat)
static int
opPFMUL(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -295,7 +295,7 @@ opPFRCP(uint32_t fetchdat)
static int
opPFRCPIT1(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -310,7 +310,7 @@ opPFRCPIT1(uint32_t fetchdat)
static int
opPFRCPIT2(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -364,7 +364,7 @@ opPFRSQIT1(uint32_t fetchdat)
static int
opPFSUB(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -379,7 +379,7 @@ opPFSUB(uint32_t fetchdat)
static int
opPFSUBR(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -394,7 +394,7 @@ opPFSUBR(uint32_t fetchdat)
static int
opPI2FD(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -409,7 +409,7 @@ opPI2FD(uint32_t fetchdat)
static int
opPI2FW(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
MMX_GETSRC();
@@ -424,7 +424,7 @@ opPI2FW(uint32_t fetchdat)
static int
opPMULHRW(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst = MMX_GETREGP(cpu_reg);
if (cpu_mod == 3) {

4
src/cpu/x86_ops_atomic.h
View File

@@ -133,7 +133,7 @@ opCMPXCHG8B_a16(uint32_t fetchdat)
{
uint32_t temp;
uint32_t temp_hi;
uint32_t temp2 = EAX;
uint32_t temp2 = EAX;
uint32_t temp2_hi = EDX;
fetch_ea_16(fetchdat);
@@ -164,7 +164,7 @@ opCMPXCHG8B_a32(uint32_t fetchdat)
{
uint32_t temp;
uint32_t temp_hi;
uint32_t temp2 = EAX;
uint32_t temp2 = EAX;
uint32_t temp2_hi = EDX;
fetch_ea_32(fetchdat);

194
src/cpu/x86_ops_i686.h
View File

@@ -46,10 +46,10 @@ opSYSEXIT(uint32_t fetchdat)
static int
sf_fx_save_stor_common(uint32_t fetchdat, int bits)
{
uint8_t fxinst = 0;
uint32_t tag_byte;
unsigned index;
floatx80 reg;
uint8_t fxinst = 0;
uint32_t tag_byte;
unsigned index;
floatx80 reg;
if (CPUID < 0x650)
return ILLEGAL(fetchdat);
@@ -129,33 +129,33 @@ sf_fx_save_stor_common(uint32_t fetchdat, int bits)
/* The lower 11 bits contain the FPU opcode, upper 5 bits are reserved */
writememw(easeg, cpu_state.eaaddr + 6, fpu_state.foo);
/*
* x87 FPU IP Offset (32/64 bits)
* The contents of this field differ depending on the current
* addressing mode (16/32/64 bit) when the FXSAVE instruction was executed:
* + 64-bit mode - 64-bit IP offset
* + 32-bit mode - 32-bit IP offset
* + 16-bit mode - low 16 bits are IP offset; high 16 bits are reserved.
* x87 CS FPU IP Selector
* + 16 bit, in 16/32 bit mode only
*/
/*
* x87 FPU IP Offset (32/64 bits)
* The contents of this field differ depending on the current
* addressing mode (16/32/64 bit) when the FXSAVE instruction was executed:
* + 64-bit mode - 64-bit IP offset
* + 32-bit mode - 32-bit IP offset
* + 16-bit mode - low 16 bits are IP offset; high 16 bits are reserved.
* x87 CS FPU IP Selector
* + 16 bit, in 16/32 bit mode only
*/
writememl(easeg, cpu_state.eaaddr + 8, fpu_state.fip);
writememl(easeg, cpu_state.eaaddr + 12, fpu_state.fcs);
/*
* x87 FPU Instruction Operand (Data) Pointer Offset (32/64 bits)
* The contents of this field differ depending on the current
* addressing mode (16/32 bit) when the FXSAVE instruction was executed:
* + 64-bit mode - 64-bit offset
* + 32-bit mode - 32-bit offset
* + 16-bit mode - low 16 bits are offset; high 16 bits are reserved.
* x87 DS FPU Instruction Operand (Data) Pointer Selector
* + 16 bit, in 16/32 bit mode only
*/
/*
* x87 FPU Instruction Operand (Data) Pointer Offset (32/64 bits)
* The contents of this field differ depending on the current
* addressing mode (16/32 bit) when the FXSAVE instruction was executed:
* + 64-bit mode - 64-bit offset
* + 32-bit mode - 32-bit offset
* + 16-bit mode - low 16 bits are offset; high 16 bits are reserved.
* x87 DS FPU Instruction Operand (Data) Pointer Selector
* + 16 bit, in 16/32 bit mode only
*/
writememl(easeg, cpu_state.eaaddr + 16, fpu_state.fdp);
writememl(easeg, cpu_state.eaaddr + 20, fpu_state.fds);
/* store i387 register file */
/* store i387 register file */
for (index = 0; index < 8; index++) {
const floatx80 fp = FPU_read_regi(index);
@@ -172,72 +172,72 @@ sf_fx_save_stor_common(uint32_t fetchdat, int bits)
static int
fx_save_stor_common(uint32_t fetchdat, int bits)
{
uint8_t fxinst = 0;
uint16_t twd = x87_gettag();
uint32_t old_eaaddr = 0;
uint8_t ftwb = 0;
uint16_t rec_ftw = 0;
uint16_t fpus = 0;
int i;
int mmx_tags = 0;
uint16_t exp = 0x0000;
uint64_t mant = 0x0000000000000000ULL;
uint64_t fraction;
uint8_t jm;
uint8_t valid;
/* Exp_all_1 Exp_all_0 Frac_all_0 J M FTW_Valid | Ent
----------------------------------------------+------ */
uint8_t ftw_table_idx;
uint8_t ftw_table[48] = { 0x03, /* 0 0 0 0 0 0 | 0x00 */
0x02, /* 0 0 0 0 0 1 | 0x01 */
0x03, /* 0 0 0 0 0 0 | 0x02 */
0x02, /* 0 0 0 0 1 1 | 0x03 */
0x03, /* 0 0 0 1 0 0 | 0x04 */
0x00, /* 0 0 0 1 0 1 | 0x05 */
0x03, /* 0 0 0 1 1 0 | 0x06 */
0x00, /* 0 0 0 1 1 1 | 0x07 */
0x03, /* 0 0 1 0 0 0 | 0x08 */
0x02, /* 0 0 1 0 0 1 | 0x09 */
0x03, /* 0 0 1 0 1 0 | 0x0a - Impossible */
0x03, /* 0 0 1 0 1 1 | 0x0b - Impossible */
0x03, /* 0 0 1 1 0 0 | 0x0c */
0x02, /* 0 0 1 1 0 1 | 0x0d */
0x03, /* 0 0 1 1 1 0 | 0x0e - Impossible */
0x03, /* 0 0 1 1 1 1 | 0x0f - Impossible */
0x03, /* 0 1 0 0 0 0 | 0x10 */
0x02, /* 0 1 0 0 0 1 | 0x11 */
0x03, /* 0 1 0 0 1 0 | 0x12 */
0x02, /* 0 1 0 0 1 1 | 0x13 */
0x03, /* 0 1 0 1 0 0 | 0x14 */
0x02, /* 0 1 0 1 0 1 | 0x15 */
0x03, /* 0 1 0 1 1 0 | 0x16 */
0x02, /* 0 1 0 1 1 1 | 0x17 */
0x03, /* 0 1 1 0 0 0 | 0x18 */
0x01, /* 0 1 1 0 0 1 | 0x19 */
0x03, /* 0 1 1 0 1 0 | 0x1a - Impossible */
0x03, /* 0 1 1 0 1 1 | 0x1b - Impossible */
0x03, /* 0 1 1 1 0 0 | 0x1c */
0x01, /* 0 1 1 1 0 1 | 0x1d */
0x03, /* 0 1 1 1 1 0 | 0x1e - Impossible */
0x03, /* 0 1 1 1 1 1 | 0x1f - Impossible */
0x03, /* 1 0 0 0 0 0 | 0x20 */
0x02, /* 1 0 0 0 0 1 | 0x21 */
0x03, /* 1 0 0 0 1 0 | 0x22 */
0x02, /* 1 0 0 0 1 1 | 0x23 */
0x03, /* 1 0 0 1 0 0 | 0x24 */
0x02, /* 1 0 0 1 0 1 | 0x25 */
0x03, /* 1 0 0 1 1 0 | 0x26 */
0x02, /* 1 0 0 1 1 1 | 0x27 */
0x03, /* 1 0 1 0 0 0 | 0x28 */
0x02, /* 1 0 1 0 0 1 | 0x29 */
0x03, /* 1 0 1 0 1 0 | 0x2a - Impossible */
0x03, /* 1 0 1 0 1 1 | 0x2b - Impossible */
0x03, /* 1 0 1 1 0 0 | 0x2c */
0x02, /* 1 0 1 1 0 1 | 0x2d */
0x03, /* 1 0 1 1 1 0 | 0x2e - Impossible */
0x03 }; /* 1 0 1 1 1 1 | 0x2f - Impossible */
/* M is the most significant bit of the franction, so it is impossible
for M to o be 1 when the fraction is all 0's. */
uint8_t fxinst = 0;
uint16_t twd = x87_gettag();
uint32_t old_eaaddr = 0;
uint8_t ftwb = 0;
uint16_t rec_ftw = 0;
uint16_t fpus = 0;
int i;
int mmx_tags = 0;
uint16_t exp = 0x0000;
uint64_t mant = 0x0000000000000000ULL;
uint64_t fraction;
uint8_t jm;
uint8_t valid;
/* Exp_all_1 Exp_all_0 Frac_all_0 J M FTW_Valid | Ent
----------------------------------------------+------ */
uint8_t ftw_table_idx;
uint8_t ftw_table[48] = { 0x03, /* 0 0 0 0 0 0 | 0x00 */
0x02, /* 0 0 0 0 0 1 | 0x01 */
0x03, /* 0 0 0 0 0 0 | 0x02 */
0x02, /* 0 0 0 0 1 1 | 0x03 */
0x03, /* 0 0 0 1 0 0 | 0x04 */
0x00, /* 0 0 0 1 0 1 | 0x05 */
0x03, /* 0 0 0 1 1 0 | 0x06 */
0x00, /* 0 0 0 1 1 1 | 0x07 */
0x03, /* 0 0 1 0 0 0 | 0x08 */
0x02, /* 0 0 1 0 0 1 | 0x09 */
0x03, /* 0 0 1 0 1 0 | 0x0a - Impossible */
0x03, /* 0 0 1 0 1 1 | 0x0b - Impossible */
0x03, /* 0 0 1 1 0 0 | 0x0c */
0x02, /* 0 0 1 1 0 1 | 0x0d */
0x03, /* 0 0 1 1 1 0 | 0x0e - Impossible */
0x03, /* 0 0 1 1 1 1 | 0x0f - Impossible */
0x03, /* 0 1 0 0 0 0 | 0x10 */
0x02, /* 0 1 0 0 0 1 | 0x11 */
0x03, /* 0 1 0 0 1 0 | 0x12 */
0x02, /* 0 1 0 0 1 1 | 0x13 */
0x03, /* 0 1 0 1 0 0 | 0x14 */
0x02, /* 0 1 0 1 0 1 | 0x15 */
0x03, /* 0 1 0 1 1 0 | 0x16 */
0x02, /* 0 1 0 1 1 1 | 0x17 */
0x03, /* 0 1 1 0 0 0 | 0x18 */
0x01, /* 0 1 1 0 0 1 | 0x19 */
0x03, /* 0 1 1 0 1 0 | 0x1a - Impossible */
0x03, /* 0 1 1 0 1 1 | 0x1b - Impossible */
0x03, /* 0 1 1 1 0 0 | 0x1c */
0x01, /* 0 1 1 1 0 1 | 0x1d */
0x03, /* 0 1 1 1 1 0 | 0x1e - Impossible */
0x03, /* 0 1 1 1 1 1 | 0x1f - Impossible */
0x03, /* 1 0 0 0 0 0 | 0x20 */
0x02, /* 1 0 0 0 0 1 | 0x21 */
0x03, /* 1 0 0 0 1 0 | 0x22 */
0x02, /* 1 0 0 0 1 1 | 0x23 */
0x03, /* 1 0 0 1 0 0 | 0x24 */
0x02, /* 1 0 0 1 0 1 | 0x25 */
0x03, /* 1 0 0 1 1 0 | 0x26 */
0x02, /* 1 0 0 1 1 1 | 0x27 */
0x03, /* 1 0 1 0 0 0 | 0x28 */
0x02, /* 1 0 1 0 0 1 | 0x29 */
0x03, /* 1 0 1 0 1 0 | 0x2a - Impossible */
0x03, /* 1 0 1 0 1 1 | 0x2b - Impossible */
0x03, /* 1 0 1 1 0 0 | 0x2c */
0x02, /* 1 0 1 1 0 1 | 0x2d */
0x03, /* 1 0 1 1 1 0 | 0x2e - Impossible */
0x03 }; /* 1 0 1 1 1 1 | 0x2f - Impossible */
/* M is the most significant bit of the franction, so it is impossible
for M to o be 1 when the fraction is all 0's. */
if (CPUID < 0x650)
return ILLEGAL(fetchdat);
@@ -287,11 +287,11 @@ fx_save_stor_common(uint32_t fetchdat, int bits)
for (i = 0; i <= 7; i++) {
cpu_state.eaaddr = old_eaaddr + 32 + (i << 4);
mant = readmemq(easeg, cpu_state.eaaddr);
fraction = mant & 0x7fffffffffffffffULL;
exp = readmemw(easeg, cpu_state.eaaddr + 8);
jm = (mant >> 62) & 0x03;
valid = !(ftwb & (1 << i));
mant = readmemq(easeg, cpu_state.eaaddr);
fraction = mant & 0x7fffffffffffffffULL;
exp = readmemw(easeg, cpu_state.eaaddr + 8);
jm = (mant >> 62) & 0x03;
valid = !(ftwb & (1 << i));
ftw_table_idx = (!!(exp == 0x1111)) << 5;
ftw_table_idx |= (!!(exp == 0x0000)) << 4;
@@ -381,7 +381,7 @@ fx_save_stor_common(uint32_t fetchdat, int bits)
static int
opFXSAVESTOR_a16(uint32_t fetchdat)
{
if (fpu_softfloat)
if (fpu_softfloat)
return sf_fx_save_stor_common(fetchdat, 16);
return fx_save_stor_common(fetchdat, 16);

2
src/cpu/x86_ops_jump.h
View File

@@ -86,7 +86,7 @@ opJ(L)
opJ(NL)
opJ(LE)
opJ(NLE)
// clang-format on
// clang-format on
static int
opLOOPNE_w(uint32_t fetchdat)

4
src/cpu/x86_ops_misc.h
View File

@@ -289,7 +289,7 @@ static int
opF7_w_a16(uint32_t fetchdat)
{
uint32_t templ;
uint32_t templ2 = 0;
uint32_t templ2 = 0;
int tempws;
int tempws2 = 0;
int16_t temps16;
@@ -402,7 +402,7 @@ static int
opF7_w_a32(uint32_t fetchdat)
{
uint32_t templ;
uint32_t templ2 = 0;
uint32_t templ2 = 0;
int tempws;
int tempws2 = 1;
int16_t temps16;

6
src/cpu/x86_ops_mmx.c
View File

@@ -27,7 +27,7 @@
#include "x86_flags.h"
#include "x86seg.h"
MMX_REG *MMP[8];
MMX_REG *MMP[8];
uint16_t *MMEP[8];
static uint16_t MME[8];
@@ -40,10 +40,10 @@ mmx_init(void)
for (uint8_t i = 0; i < 8; i++) {
if (fpu_softfloat) {
MMP[i] = (MMX_REG *) &fpu_state.st_space[i].fraction;
MMP[i] = (MMX_REG *) &fpu_state.st_space[i].fraction;
MMEP[i] = (uint16_t *) &fpu_state.st_space[i].exp;
} else {
MMP[i] = &(cpu_state.MM[i]);
MMP[i] = &(cpu_state.MM[i]);
MMEP[i] = &(MME[i]);
}
}

12
src/cpu/x86_ops_mmx.h
View File

@@ -1,12 +1,12 @@
#define SSATB(val) (((val) < -128) ? -128 : (((val) > 127) ? 127 : (val)))
#define SSATW(val) (((val) < -32768) ? -32768 : (((val) > 32767) ? 32767 : (val)))
#define USATB(val) (((val) < 0) ? 0 : (((val) > 255) ? 255 : (val)))
#define USATW(val) (((val) < 0) ? 0 : (((val) > 65535) ? 65535 : (val)))
#define SSATB(val) (((val) < -128) ? -128 : (((val) > 127) ? 127 : (val)))
#define SSATW(val) (((val) < -32768) ? -32768 : (((val) > 32767) ? 32767 : (val)))
#define USATB(val) (((val) < 0) ? 0 : (((val) > 255) ? 255 : (val)))
#define USATW(val) (((val) < 0) ? 0 : (((val) > 65535) ? 65535 : (val)))
#define MMX_GETREGP(r) MMP[r]
#define MMX_GETREG(r) *(MMP[r])
#define MMX_GETREG(r) *(MMP[r])
#define MMX_SETEXP(r) \
#define MMX_SETEXP(r) \
*(MMEP[r]) = 0xffff
#define MMX_GETSRC() \

68
src/cpu/x86_ops_mmx_arith.h
View File

@@ -1,7 +1,7 @@
static int
opPADDB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -27,7 +27,7 @@ opPADDB_a16(uint32_t fetchdat)
static int
opPADDB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -54,7 +54,7 @@ opPADDB_a32(uint32_t fetchdat)
static int
opPADDW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -76,7 +76,7 @@ opPADDW_a16(uint32_t fetchdat)
static int
opPADDW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -99,7 +99,7 @@ opPADDW_a32(uint32_t fetchdat)
static int
opPADDD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -119,7 +119,7 @@ opPADDD_a16(uint32_t fetchdat)
static int
opPADDD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -140,7 +140,7 @@ opPADDD_a32(uint32_t fetchdat)
static int
opPADDSB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -166,7 +166,7 @@ opPADDSB_a16(uint32_t fetchdat)
static int
opPADDSB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -193,7 +193,7 @@ opPADDSB_a32(uint32_t fetchdat)
static int
opPADDUSB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -219,7 +219,7 @@ opPADDUSB_a16(uint32_t fetchdat)
static int
opPADDUSB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -246,7 +246,7 @@ opPADDUSB_a32(uint32_t fetchdat)
static int
opPADDSW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -268,7 +268,7 @@ opPADDSW_a16(uint32_t fetchdat)
static int
opPADDSW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -291,7 +291,7 @@ opPADDSW_a32(uint32_t fetchdat)
static int
opPADDUSW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -313,7 +313,7 @@ opPADDUSW_a16(uint32_t fetchdat)
static int
opPADDUSW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -336,7 +336,7 @@ opPADDUSW_a32(uint32_t fetchdat)
static int
opPMADDWD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -363,7 +363,7 @@ opPMADDWD_a16(uint32_t fetchdat)
static int
opPMADDWD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -391,7 +391,7 @@ opPMADDWD_a32(uint32_t fetchdat)
static int
opPMULLW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -422,7 +422,7 @@ opPMULLW_a16(uint32_t fetchdat)
static int
opPMULLW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -454,7 +454,7 @@ opPMULLW_a32(uint32_t fetchdat)
static int
opPMULHW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -485,7 +485,7 @@ opPMULHW_a16(uint32_t fetchdat)
static int
opPMULHW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -517,7 +517,7 @@ opPMULHW_a32(uint32_t fetchdat)
static int
opPSUBB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -543,7 +543,7 @@ opPSUBB_a16(uint32_t fetchdat)
static int
opPSUBB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -570,7 +570,7 @@ opPSUBB_a32(uint32_t fetchdat)
static int
opPSUBW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -592,7 +592,7 @@ opPSUBW_a16(uint32_t fetchdat)
static int
opPSUBW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -615,7 +615,7 @@ opPSUBW_a32(uint32_t fetchdat)
static int
opPSUBD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -635,7 +635,7 @@ opPSUBD_a16(uint32_t fetchdat)
static int
opPSUBD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -656,7 +656,7 @@ opPSUBD_a32(uint32_t fetchdat)
static int
opPSUBSB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -682,7 +682,7 @@ opPSUBSB_a16(uint32_t fetchdat)
static int
opPSUBSB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -709,7 +709,7 @@ opPSUBSB_a32(uint32_t fetchdat)
static int
opPSUBUSB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -735,7 +735,7 @@ opPSUBUSB_a16(uint32_t fetchdat)
static int
opPSUBUSB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -762,7 +762,7 @@ opPSUBUSB_a32(uint32_t fetchdat)
static int
opPSUBSW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -784,7 +784,7 @@ opPSUBSW_a16(uint32_t fetchdat)
static int
opPSUBSW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -807,7 +807,7 @@ opPSUBSW_a32(uint32_t fetchdat)
static int
opPSUBUSW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -829,7 +829,7 @@ opPSUBUSW_a16(uint32_t fetchdat)
static int
opPSUBUSW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();

24
src/cpu/x86_ops_mmx_cmp.h
View File

@@ -1,7 +1,7 @@
static int
opPCMPEQB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -27,7 +27,7 @@ opPCMPEQB_a16(uint32_t fetchdat)
static int
opPCMPEQB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -54,7 +54,7 @@ opPCMPEQB_a32(uint32_t fetchdat)
static int
opPCMPGTB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -80,7 +80,7 @@ opPCMPGTB_a16(uint32_t fetchdat)
static int
opPCMPGTB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -107,7 +107,7 @@ opPCMPGTB_a32(uint32_t fetchdat)
static int
opPCMPEQW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -129,7 +129,7 @@ opPCMPEQW_a16(uint32_t fetchdat)
static int
opPCMPEQW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -152,7 +152,7 @@ opPCMPEQW_a32(uint32_t fetchdat)
static int
opPCMPGTW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -174,7 +174,7 @@ opPCMPGTW_a16(uint32_t fetchdat)
static int
opPCMPGTW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -197,7 +197,7 @@ opPCMPGTW_a32(uint32_t fetchdat)
static int
opPCMPEQD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -217,7 +217,7 @@ opPCMPEQD_a16(uint32_t fetchdat)
static int
opPCMPEQD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -238,7 +238,7 @@ opPCMPEQD_a32(uint32_t fetchdat)
static int
opPCMPGTD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -258,7 +258,7 @@ opPCMPGTD_a16(uint32_t fetchdat)
static int
opPCMPGTD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();

16
src/cpu/x86_ops_mmx_logic.h
View File

@@ -1,7 +1,7 @@
static int
opPAND_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -20,7 +20,7 @@ opPAND_a16(uint32_t fetchdat)
static int
opPAND_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -40,7 +40,7 @@ opPAND_a32(uint32_t fetchdat)
static int
opPANDN_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -59,7 +59,7 @@ opPANDN_a16(uint32_t fetchdat)
static int
opPANDN_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -79,7 +79,7 @@ opPANDN_a32(uint32_t fetchdat)
static int
opPOR_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -98,7 +98,7 @@ opPOR_a16(uint32_t fetchdat)
static int
opPOR_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -118,7 +118,7 @@ opPOR_a32(uint32_t fetchdat)
static int
opPXOR_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -137,7 +137,7 @@ opPXOR_a16(uint32_t fetchdat)
static int
opPXOR_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();

12
src/cpu/x86_ops_mmx_mov.h
View File

@@ -176,14 +176,14 @@ static int
opMOVQ_q_mm_a16(uint32_t fetchdat)
{
uint64_t dst;
MMX_REG src;
MMX_REG src;
MMX_REG *op;
MMX_ENTER();
fetch_ea_16(fetchdat);
src = MMX_GETREG(cpu_rm);
op = MMX_GETREGP(cpu_reg);
op = MMX_GETREGP(cpu_reg);
if (cpu_mod == 3) {
op->q = src.q;
@@ -206,14 +206,14 @@ static int
opMOVQ_q_mm_a32(uint32_t fetchdat)
{
uint64_t dst;
MMX_REG src;
MMX_REG src;
MMX_REG *op;
MMX_ENTER();
fetch_ea_32(fetchdat);
src = MMX_GETREG(cpu_rm);
op = MMX_GETREGP(cpu_reg);
op = MMX_GETREGP(cpu_reg);
if (cpu_mod == 3) {
op->q = src.q;
@@ -236,7 +236,7 @@ opMOVQ_q_mm_a32(uint32_t fetchdat)
static int
opMOVQ_mm_q_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -266,7 +266,7 @@ opMOVQ_mm_q_a16(uint32_t fetchdat)
static int
opMOVQ_mm_q_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();

44
src/cpu/x86_ops_mmx_pack.h
View File

@@ -2,7 +2,7 @@ static int
opPUNPCKLDQ_a16(uint32_t fetchdat)
{
uint32_t usrc;
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -32,7 +32,7 @@ static int
opPUNPCKLDQ_a32(uint32_t fetchdat)
{
uint32_t usrc;
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -62,7 +62,7 @@ opPUNPCKLDQ_a32(uint32_t fetchdat)
static int
opPUNPCKHDQ_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -82,7 +82,7 @@ opPUNPCKHDQ_a16(uint32_t fetchdat)
static int
opPUNPCKHDQ_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -103,7 +103,7 @@ opPUNPCKHDQ_a32(uint32_t fetchdat)
static int
opPUNPCKLBW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -129,7 +129,7 @@ opPUNPCKLBW_a16(uint32_t fetchdat)
static int
opPUNPCKLBW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -156,7 +156,7 @@ opPUNPCKLBW_a32(uint32_t fetchdat)
static int
opPUNPCKHBW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -182,7 +182,7 @@ opPUNPCKHBW_a16(uint32_t fetchdat)
static int
opPUNPCKHBW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -209,7 +209,7 @@ opPUNPCKHBW_a32(uint32_t fetchdat)
static int
opPUNPCKLWD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -231,7 +231,7 @@ opPUNPCKLWD_a16(uint32_t fetchdat)
static int
opPUNPCKLWD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -254,7 +254,7 @@ opPUNPCKLWD_a32(uint32_t fetchdat)
static int
opPUNPCKHWD_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -276,7 +276,7 @@ opPUNPCKHWD_a16(uint32_t fetchdat)
static int
opPUNPCKHWD_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -299,7 +299,7 @@ opPUNPCKHWD_a32(uint32_t fetchdat)
static int
opPACKSSWB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -325,7 +325,7 @@ opPACKSSWB_a16(uint32_t fetchdat)
static int
opPACKSSWB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -352,7 +352,7 @@ opPACKSSWB_a32(uint32_t fetchdat)
static int
opPACKUSWB_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -378,7 +378,7 @@ opPACKUSWB_a16(uint32_t fetchdat)
static int
opPACKUSWB_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_ENTER();
@@ -405,14 +405,14 @@ opPACKUSWB_a32(uint32_t fetchdat)
static int
opPACKSSDW_a16(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_REG dst2;
MMX_REG dst2;
MMX_ENTER();
fetch_ea_16(fetchdat);
dst = MMX_GETREGP(cpu_reg);
dst = MMX_GETREGP(cpu_reg);
dst2 = *dst;
MMX_GETSRC();
@@ -429,14 +429,14 @@ opPACKSSDW_a16(uint32_t fetchdat)
static int
opPACKSSDW_a32(uint32_t fetchdat)
{
MMX_REG src;
MMX_REG src;
MMX_REG *dst;
MMX_REG dst2;
MMX_REG dst2;
MMX_ENTER();
fetch_ea_32(fetchdat);
dst = MMX_GETREGP(cpu_reg);
dst = MMX_GETREGP(cpu_reg);
dst2 = *dst;
MMX_GETSRC();

50
src/cpu/x86_ops_mmx_shift.h
View File

@@ -13,9 +13,9 @@
static int
opPSxxW_imm(uint32_t fetchdat)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
MMX_REG *dst;
cpu_state.pc += 2;
@@ -67,7 +67,7 @@ static int
opPSLLW_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -94,7 +94,7 @@ static int
opPSLLW_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -122,7 +122,7 @@ static int
opPSRLW_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -149,7 +149,7 @@ static int
opPSRLW_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -177,7 +177,7 @@ static int
opPSRAW_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -203,7 +203,7 @@ static int
opPSRAW_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -229,9 +229,9 @@ opPSRAW_a32(uint32_t fetchdat)
static int
opPSxxD_imm(uint32_t fetchdat)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
MMX_REG *dst;
cpu_state.pc += 2;
@@ -278,7 +278,7 @@ static int
opPSLLD_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -303,7 +303,7 @@ static int
opPSLLD_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -329,7 +329,7 @@ static int
opPSRLD_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -354,7 +354,7 @@ static int
opPSRLD_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -380,7 +380,7 @@ static int
opPSRAD_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -404,7 +404,7 @@ static int
opPSRAD_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -428,9 +428,9 @@ opPSRAD_a32(uint32_t fetchdat)
static int
opPSxxQ_imm(uint32_t fetchdat)
{
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
int reg = fetchdat & 7;
int op = fetchdat & 0x38;
int shift = (fetchdat >> 8) & 0xff;
MMX_REG *dst;
cpu_state.pc += 2;
@@ -474,7 +474,7 @@ static int
opPSLLQ_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -497,7 +497,7 @@ static int
opPSLLQ_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -521,7 +521,7 @@ static int
opPSRLQ_a16(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();
@@ -544,7 +544,7 @@ static int
opPSRLQ_a32(uint32_t fetchdat)
{
MMX_REG *dst;
int shift;
int shift;
MMX_ENTER();

154
src/cpu/x86_ops_mov.h
View File

@@ -770,83 +770,83 @@ opMOV_r_l_a32(uint32_t fetchdat)
}
#ifndef OPS_286_386
#define opCMOV(condition) \
static int opCMOV##condition##_w_a16(uint32_t fetchdat) \
{ \
fetch_ea_16(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_w_a32(uint32_t fetchdat) \
{ \
fetch_ea_32(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_l_a16(uint32_t fetchdat) \
{ \
fetch_ea_16(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else { \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_l_a32(uint32_t fetchdat) \
{ \
fetch_ea_32(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else { \
uint32_t temp; \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
}
# define opCMOV(condition) \
static int opCMOV##condition##_w_a16(uint32_t fetchdat) \
{ \
fetch_ea_16(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_w_a32(uint32_t fetchdat) \
{ \
fetch_ea_32(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].w = cpu_state.regs[cpu_rm].w; \
else { \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 1); \
temp = geteaw(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].w = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_l_a16(uint32_t fetchdat) \
{ \
fetch_ea_16(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else { \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
} \
static int opCMOV##condition##_l_a32(uint32_t fetchdat) \
{ \
fetch_ea_32(fetchdat); \
if (cond_##condition) { \
if (cpu_mod == 3) \
cpu_state.regs[cpu_reg].l = cpu_state.regs[cpu_rm].l; \
else { \
uint32_t temp; \
CHECK_READ(cpu_state.ea_seg, cpu_state.eaaddr, cpu_state.eaaddr + 3); \
SEG_CHECK_READ(cpu_state.ea_seg); \
temp = geteal(); \
if (cpu_state.abrt) \
return 1; \
cpu_state.regs[cpu_reg].l = temp; \
} \
} \
CLOCK_CYCLES(1); \
return 0; \
}
// clang-format off
opCMOV(O)

2
src/cpu/x86_ops_mov_seg.h
View File

@@ -536,4 +536,4 @@ opLSS_l_a32(uint32_t fetchdat)
opLsel(ES, cpu_state.seg_es)
opLsel(FS, cpu_state.seg_fs)
opLsel(GS, cpu_state.seg_gs)
// clang-format on
// clang-format on

2
src/cpu/x86_ops_prefix.h
View File

@@ -88,7 +88,7 @@ op_seg(ES_REPNE, cpu_state.seg_es, x86_opcodes_REPNE, x86_opcodes)
op_seg(FS_REPNE, cpu_state.seg_fs, x86_opcodes_REPNE, x86_opcodes)
op_seg(GS_REPNE, cpu_state.seg_gs, x86_opcodes_REPNE, x86_opcodes)
op_seg(SS_REPNE, cpu_state.seg_ss, x86_opcodes_REPNE, x86_opcodes)
// clang-format on
// clang-format on
static int
op_66(uint32_t fetchdat) /*Data size select*/

2
src/cpu/x86_ops_set.h
View File

@@ -36,4 +36,4 @@ opSET(L)
opSET(NL)
opSET(LE)
opSET(NLE)
// clang-format on
// clang-format on

2
src/cpu/x86_ops_shift.h
View File

@@ -1071,4 +1071,4 @@ opSHxD(SHLD_w)
opSHxD(SHLD_l)
opSHxD(SHRD_w)
opSHxD(SHRD_l)
// clang-format on
// clang-format on

56
src/cpu/x86_ops_stack.h
View File

@@ -189,22 +189,50 @@ static int
opPOPA_l(uint32_t fetchdat)
{
if (stack32) {
EDI = readmeml(ss, ESP); if (cpu_state.abrt) return 1;
ESI = readmeml(ss, ESP + 4); if (cpu_state.abrt) return 1;
EBP = readmeml(ss, ESP + 8); if (cpu_state.abrt) return 1;
EBX = readmeml(ss, ESP + 16); if (cpu_state.abrt) return 1;
EDX = readmeml(ss, ESP + 20); if (cpu_state.abrt) return 1;
ECX = readmeml(ss, ESP + 24); if (cpu_state.abrt) return 1;
EAX = readmeml(ss, ESP + 28); if (cpu_state.abrt) return 1;
EDI = readmeml(ss, ESP);
if (cpu_state.abrt)
return 1;
ESI = readmeml(ss, ESP + 4);
if (cpu_state.abrt)
return 1;
EBP = readmeml(ss, ESP + 8);
if (cpu_state.abrt)
return 1;
EBX = readmeml(ss, ESP + 16);
if (cpu_state.abrt)
return 1;
EDX = readmeml(ss, ESP + 20);
if (cpu_state.abrt)
return 1;
ECX = readmeml(ss, ESP + 24);
if (cpu_state.abrt)
return 1;
EAX = readmeml(ss, ESP + 28);
if (cpu_state.abrt)
return 1;
ESP += 32;
} else {
EDI = readmeml(ss, ((SP) & 0xFFFF)); if (cpu_state.abrt) return 1;
ESI = readmeml(ss, ((SP + 4) & 0xFFFF)); if (cpu_state.abrt) return 1;
EBP = readmeml(ss, ((SP + 8) & 0xFFFF)); if (cpu_state.abrt) return 1;
EBX = readmeml(ss, ((SP + 16) & 0xFFFF)); if (cpu_state.abrt) return 1;
EDX = readmeml(ss, ((SP + 20) & 0xFFFF)); if (cpu_state.abrt) return 1;
ECX = readmeml(ss, ((SP + 24) & 0xFFFF)); if (cpu_state.abrt) return 1;
EAX = readmeml(ss, ((SP + 28) & 0xFFFF)); if (cpu_state.abrt) return 1;
EDI = readmeml(ss, ((SP) &0xFFFF));
if (cpu_state.abrt)
return 1;
ESI = readmeml(ss, ((SP + 4) & 0xFFFF));
if (cpu_state.abrt)
return 1;
EBP = readmeml(ss, ((SP + 8) & 0xFFFF));
if (cpu_state.abrt)
return 1;
EBX = readmeml(ss, ((SP + 16) & 0xFFFF));
if (cpu_state.abrt)
return 1;
EDX = readmeml(ss, ((SP + 20) & 0xFFFF));
if (cpu_state.abrt)
return 1;
ECX = readmeml(ss, ((SP + 24) & 0xFFFF));
if (cpu_state.abrt)
return 1;
EAX = readmeml(ss, ((SP + 28) & 0xFFFF));
if (cpu_state.abrt)
return 1;
SP += 32;
}
CLOCK_CYCLES((is486) ? 9 : 24);

2
src/cpu/x86_ops_xchg.h
View File

@@ -275,4 +275,4 @@ opBSWAP(ESI)
opBSWAP(EDI)
opBSWAP(EBP)
opBSWAP(ESP)
// clang-format on
// clang-format on

178
src/cpu/x87.c
View File

@@ -105,7 +105,6 @@ x87_settag(uint16_t new_tag)
}
#endif
static floatx80
FPU_handle_NaN32_Func(floatx80 a, int aIsNaN, float32 b32, int bIsNaN, struct float_status_t *status)
{
@@ -118,24 +117,27 @@ FPU_handle_NaN32_Func(floatx80 a, int aIsNaN, float32 b32, int bIsNaN, struct fl
// propagate QNaN to SNaN
a = propagateFloatx80NaNOne(a, status);
if (aIsNaN & !bIsNaN) return a;
if (aIsNaN & !bIsNaN)
return a;
// float32 is NaN so conversion will propagate SNaN to QNaN and raise
// appropriate exception flags
floatx80 b = float32_to_floatx80(b32, status);
if (aIsSignalingNaN) {
if (bIsSignalingNaN) goto returnLargerSignificand;
if (bIsSignalingNaN)
goto returnLargerSignificand;
return bIsNaN ? b : a;
}
else if (aIsNaN) {
if (bIsSignalingNaN) return a;
returnLargerSignificand:
if (a.fraction < b.fraction) return b;
if (b.fraction < a.fraction) return a;
} else if (aIsNaN) {
if (bIsSignalingNaN)
return a;
returnLargerSignificand:
if (a.fraction < b.fraction)
return b;
if (b.fraction < a.fraction)
return a;
return (a.exp < b.exp) ? a : b;
}
else {
} else {
return b;
}
}
@@ -172,24 +174,27 @@ FPU_handle_NaN64_Func(floatx80 a, int aIsNaN, float64 b64, int bIsNaN, struct fl
// propagate QNaN to SNaN
a = propagateFloatx80NaNOne(a, status);
if (aIsNaN & !bIsNaN) return a;
if (aIsNaN & !bIsNaN)
return a;
// float64 is NaN so conversion will propagate SNaN to QNaN and raise
// appropriate exception flags
floatx80 b = float64_to_floatx80(b64, status);
if (aIsSignalingNaN) {
if (bIsSignalingNaN) goto returnLargerSignificand;
if (bIsSignalingNaN)
goto returnLargerSignificand;
return bIsNaN ? b : a;
}
else if (aIsNaN) {
if (bIsSignalingNaN) return a;
returnLargerSignificand:
if (a.fraction < b.fraction) return b;
if (b.fraction < a.fraction) return a;
} else if (aIsNaN) {
if (bIsSignalingNaN)
return a;
returnLargerSignificand:
if (a.fraction < b.fraction)
return b;
if (b.fraction < a.fraction)
return a;
return (a.exp < b.exp) ? a : b;
}
else {
} else {
return b;
}
}
@@ -218,7 +223,7 @@ struct float_status_t
i387cw_to_softfloat_status_word(uint16_t control_word)
{
struct float_status_t status;
int precision = control_word & FPU_CW_PC;
int precision = control_word & FPU_CW_PC;
switch (precision) {
case FPU_PR_32_BITS:
@@ -231,24 +236,23 @@ i387cw_to_softfloat_status_word(uint16_t control_word)
status.float_rounding_precision = 80;
break;
default:
/* With the precision control bits set to 01 "(reserved)", a
real CPU behaves as if the precision control bits were
set to 11 "80 bits" */
/* With the precision control bits set to 01 "(reserved)", a
real CPU behaves as if the precision control bits were
set to 11 "80 bits" */
status.float_rounding_precision = 80;
break;
}
status.float_exception_flags = 0; // clear exceptions before execution
status.float_nan_handling_mode = float_first_operand_nan;
status.float_rounding_mode = (control_word & FPU_CW_RC) >> 10;
status.flush_underflow_to_zero = 0;
status.float_exception_flags = 0; // clear exceptions before execution
status.float_nan_handling_mode = float_first_operand_nan;
status.float_rounding_mode = (control_word & FPU_CW_RC) >> 10;
status.flush_underflow_to_zero = 0;
status.float_suppress_exception = 0;
status.float_exception_masks = control_word & FPU_CW_Exceptions_Mask;
status.denormals_are_zeros = 0;
status.float_exception_masks = control_word & FPU_CW_Exceptions_Mask;
status.denormals_are_zeros = 0;
return status;
}
int
FPU_status_word_flags_fpu_compare(int float_relation)
{
@@ -266,7 +270,7 @@ FPU_status_word_flags_fpu_compare(int float_relation)
return C3;
}
return (-1); // should never get here
return (-1); // should never get here
}
void
@@ -320,9 +324,9 @@ FPU_exception(uint32_t fetchdat, uint16_t exceptions, int store)
fpu_state.swd |= exceptions;
if (exceptions & FPU_SW_Stack_Fault) {
if (!(exceptions & C1)) {
/* This bit distinguishes over- from underflow for a stack fault,
and roundup from round-down for precision loss. */
fpu_state.swd &= ~C1;
/* This bit distinguishes over- from underflow for a stack fault,
and roundup from round-down for precision loss. */
fpu_state.swd &= ~C1;
}
}
return unmasked;
@@ -355,8 +359,8 @@ FPU_exception(uint32_t fetchdat, uint16_t exceptions, int store)
if (exceptions & FPU_EX_Precision) {
if (!(exceptions & C1)) {
/* This bit distinguishes over- from underflow for a stack fault,
and roundup from round-down for precision loss. */
/* This bit distinguishes over- from underflow for a stack fault,
and roundup from round-down for precision loss. */
fpu_state.swd &= ~C1;
}
}
@@ -445,14 +449,22 @@ pack_FPU_TW(uint16_t twd)
{
uint8_t tag_byte = 0;
if ((twd & 0x0003) != 0x0003) tag_byte |= 0x01;
if ((twd & 0x000c) != 0x000c) tag_byte |= 0x02;
if ((twd & 0x0030) != 0x0030) tag_byte |= 0x04;
if ((twd & 0x00c0) != 0x00c0) tag_byte |= 0x08;
if ((twd & 0x0300) != 0x0300) tag_byte |= 0x10;
if ((twd & 0x0c00) != 0x0c00) tag_byte |= 0x20;
if ((twd & 0x3000) != 0x3000) tag_byte |= 0x40;
if ((twd & 0xc000) != 0xc000) tag_byte |= 0x80;
if ((twd & 0x0003) != 0x0003)
tag_byte |= 0x01;
if ((twd & 0x000c) != 0x000c)
tag_byte |= 0x02;
if ((twd & 0x0030) != 0x0030)
tag_byte |= 0x04;
if ((twd & 0x00c0) != 0x00c0)
tag_byte |= 0x08;
if ((twd & 0x0300) != 0x0300)
tag_byte |= 0x10;
if ((twd & 0x0c00) != 0x0c00)
tag_byte |= 0x20;
if ((twd & 0x3000) != 0x3000)
tag_byte |= 0x40;
if ((twd & 0xc000) != 0xc000)
tag_byte |= 0x80;
return tag_byte;
}
@@ -462,45 +474,45 @@ unpack_FPU_TW(uint16_t tag_byte)
{
uint32_t twd = 0;
/* FTW
*
* Note that the original format for FTW can be recreated from the stored
* FTW valid bits and the stored 80-bit FP data (assuming the stored data
* was not the contents of MMX registers) using the following table:
/* FTW
*
* Note that the original format for FTW can be recreated from the stored
* FTW valid bits and the stored 80-bit FP data (assuming the stored data
* was not the contents of MMX registers) using the following table:
| Exponent | Exponent | Fraction | J,M bits | FTW valid | x87 FTW |
| all 1s | all 0s | all 0s | | | |
-------------------------------------------------------------------
| 0 | 0 | 0 | 0x | 1 | S 10 |
| 0 | 0 | 0 | 1x | 1 | V 00 |
-------------------------------------------------------------------
| 0 | 0 | 1 | 00 | 1 | S 10 |
| 0 | 0 | 1 | 10 | 1 | V 00 |
-------------------------------------------------------------------
| 0 | 1 | 0 | 0x | 1 | S 10 |
| 0 | 1 | 0 | 1x | 1 | S 10 |
-------------------------------------------------------------------
| 0 | 1 | 1 | 00 | 1 | Z 01 |
| 0 | 1 | 1 | 10 | 1 | S 10 |
-------------------------------------------------------------------
| 1 | 0 | 0 | 1x | 1 | S 10 |
| 1 | 0 | 0 | 1x | 1 | S 10 |
-------------------------------------------------------------------
| 1 | 0 | 1 | 00 | 1 | S 10 |
| 1 | 0 | 1 | 10 | 1 | S 10 |
-------------------------------------------------------------------
| all combinations above | 0 | E 11 |
| Exponent | Exponent | Fraction | J,M bits | FTW valid | x87 FTW |
| all 1s | all 0s | all 0s | | | |
-------------------------------------------------------------------
| 0 | 0 | 0 | 0x | 1 | S 10 |
| 0 | 0 | 0 | 1x | 1 | V 00 |
-------------------------------------------------------------------
| 0 | 0 | 1 | 00 | 1 | S 10 |
| 0 | 0 | 1 | 10 | 1 | V 00 |
-------------------------------------------------------------------
| 0 | 1 | 0 | 0x | 1 | S 10 |
| 0 | 1 | 0 | 1x | 1 | S 10 |
-------------------------------------------------------------------
| 0 | 1 | 1 | 00 | 1 | Z 01 |
| 0 | 1 | 1 | 10 | 1 | S 10 |
-------------------------------------------------------------------
| 1 | 0 | 0 | 1x | 1 | S 10 |
| 1 | 0 | 0 | 1x | 1 | S 10 |
-------------------------------------------------------------------
| 1 | 0 | 1 | 00 | 1 | S 10 |
| 1 | 0 | 1 | 10 | 1 | S 10 |
-------------------------------------------------------------------
| all combinations above | 0 | E 11 |
*
* The J-bit is defined to be the 1-bit binary integer to the left of
* the decimal place in the significand.
*
* The M-bit is defined to be the most significant bit of the fractional
* portion of the significand (i.e., the bit immediately to the right of
* the decimal place). When the M-bit is the most significant bit of the
* fractional portion of the significand, it must be 0 if the fraction
* is all 0's.
*/
*
* The J-bit is defined to be the 1-bit binary integer to the left of
* the decimal place in the significand.
*
* The M-bit is defined to be the most significant bit of the fractional
* portion of the significand (i.e., the bit immediately to the right of
* the decimal place). When the M-bit is the most significant bit of the
* fractional portion of the significand, it must be 0 if the fraction
* is all 0's.
*/
for (int index = 7; index >= 0; index--, twd <<= 2, tag_byte <<= 1) {
if (tag_byte & 0x80) {

167
src/cpu/x87.h
View File

@@ -16,9 +16,9 @@ x87_set_mmx(void)
fpu_state.tag = 0;
fpu_state.tos = 0; /* reset FPU Top-Of-Stack */
} else {
cpu_state.TOP = 0;
p = (uint64_t *) cpu_state.tag;
*p = 0x0101010101010101ULL;
cpu_state.TOP = 0;
p = (uint64_t *) cpu_state.tag;
*p = 0x0101010101010101ULL;
}
cpu_state.ismmx = 1;
}
@@ -31,8 +31,8 @@ x87_emms(void)
fpu_state.tag = 0xffff;
fpu_state.tos = 0; /* reset FPU Top-Of-Stack */
} else {
p = (uint64_t *) cpu_state.tag;
*p = 0;
p = (uint64_t *) cpu_state.tag;
*p = 0;
}
cpu_state.ismmx = 0;
}
@@ -60,81 +60,87 @@ void x87_settag(uint16_t new_tag);
void codegen_set_rounding_mode(int mode);
/* Status Word */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define FPU_SW_Backward (0x8000) /* backward compatibility */
#define FPU_SW_C3 (0x4000) /* condition bit 3 */
#define FPU_SW_Top (0x3800) /* top of stack */
#define FPU_SW_C2 (0x0400) /* condition bit 2 */
#define FPU_SW_C1 (0x0200) /* condition bit 1 */
#define FPU_SW_C0 (0x0100) /* condition bit 0 */
#define FPU_SW_Summary (0x0080) /* exception summary */
#define FPU_SW_Stack_Fault (0x0040) /* stack fault */
#define FPU_SW_Precision (0x0020) /* loss of precision */
#define FPU_SW_Underflow (0x0010) /* underflow */
#define FPU_SW_Overflow (0x0008) /* overflow */
#define FPU_SW_Zero_Div (0x0004) /* divide by zero */
#define FPU_SW_Denormal_Op (0x0002) /* denormalized operand */
#define FPU_SW_Invalid (0x0001) /* invalid operation */
#define C0 (1 << 8)
#define C1 (1 << 9)
#define C2 (1 << 10)
#define C3 (1 << 14)
#define C0 (1 << 8)
#define C1 (1 << 9)
#define C2 (1 << 10)
#define C3 (1 << 14)
#define FPU_SW_CC (C0 | C1 | C2 | C3)
#define FPU_SW_CC (C0 | C1 | C2 | C3)
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
#define FPU_SW_Exceptions_Mask (0x027f) /* status word exceptions bit mask */
/* Exception flags: */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
#define FPU_EX_Precision (0x0020) /* loss of precision */
#define FPU_EX_Underflow (0x0010) /* underflow */
#define FPU_EX_Overflow (0x0008) /* overflow */
#define FPU_EX_Zero_Div (0x0004) /* divide by zero */
#define FPU_EX_Denormal (0x0002) /* denormalized operand */
#define FPU_EX_Invalid (0x0001) /* invalid operation */
/* Special exceptions: */
#define FPU_EX_Stack_Overflow (0x0041| C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
#define FPU_EX_Stack_Overflow (0x0041 | C1) /* stack overflow */
#define FPU_EX_Stack_Underflow (0x0041) /* stack underflow */
/* precision control */
#define FPU_EX_Precision_Lost_Up (EX_Precision | C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define FPU_EX_Precision_Lost_Up (EX_Precision | C1)
#define FPU_EX_Precision_Lost_Dn (EX_Precision)
#define setcc(cc) \
fpu_state.swd = (fpu_state.swd & ~(FPU_SW_CC)) | ((cc) & FPU_SW_CC)
#define setcc(cc) \
fpu_state.swd = (fpu_state.swd & ~(FPU_SW_CC)) | ((cc) &FPU_SW_CC)
#define clear_C1() { fpu_state.swd &= ~C1; }
#define clear_C2() { fpu_state.swd &= ~C2; }
#define clear_C1() \
{ \
fpu_state.swd &= ~C1; \
}
#define clear_C2() \
{ \
fpu_state.swd &= ~C2; \
}
/* ************ */
/* Control Word */
/* ************ */
#define FPU_CW_Inf (0x1000) /* infinity control, legacy */
#define FPU_CW_Inf (0x1000) /* infinity control, legacy */
#define FPU_CW_RC (0x0C00) /* rounding control */
#define FPU_CW_PC (0x0300) /* precision control */
#define FPU_CW_RC (0x0C00) /* rounding control */
#define FPU_CW_PC (0x0300) /* precision control */
#define FPU_RC_RND (0x0000) /* rounding control */
#define FPU_RC_DOWN (0x0400)
#define FPU_RC_UP (0x0800)
#define FPU_RC_CHOP (0x0C00)
#define FPU_RC_RND (0x0000) /* rounding control */
#define FPU_RC_DOWN (0x0400)
#define FPU_RC_UP (0x0800)
#define FPU_RC_CHOP (0x0C00)
#define FPU_CW_Precision (0x0020) /* loss of precision mask */
#define FPU_CW_Underflow (0x0010) /* underflow mask */
#define FPU_CW_Overflow (0x0008) /* overflow mask */
#define FPU_CW_Zero_Div (0x0004) /* divide by zero mask */
#define FPU_CW_Denormal (0x0002) /* denormalized operand mask */
#define FPU_CW_Invalid (0x0001) /* invalid operation mask */
#define FPU_CW_Precision (0x0020) /* loss of precision mask */
#define FPU_CW_Underflow (0x0010) /* underflow mask */
#define FPU_CW_Overflow (0x0008) /* overflow mask */
#define FPU_CW_Zero_Div (0x0004) /* divide by zero mask */
#define FPU_CW_Denormal (0x0002) /* denormalized operand mask */
#define FPU_CW_Invalid (0x0001) /* invalid operation mask */
#define FPU_CW_Exceptions_Mask (0x003f) /* all masks */
#define FPU_CW_Exceptions_Mask (0x003f) /* all masks */
/* Precision control bits affect only the following:
ADD, SUB(R), MUL, DIV(R), and SQRT */
#define FPU_PR_32_BITS (0x000)
#define FPU_PR_RESERVED_BITS (0x100)
#define FPU_PR_64_BITS (0x200)
#define FPU_PR_80_BITS (0x300)
#define FPU_PR_32_BITS (0x000)
#define FPU_PR_RESERVED_BITS (0x100)
#define FPU_PR_64_BITS (0x200)
#define FPU_PR_80_BITS (0x300)
#include "softfloat/softfloatx80.h"
@@ -145,16 +151,16 @@ is_IA_masked(void)
}
struct float_status_t i387cw_to_softfloat_status_word(uint16_t control_word);
uint16_t FPU_exception(uint32_t fetchdat, uint16_t exceptions, int store);
int FPU_status_word_flags_fpu_compare(int float_relation);
void FPU_write_eflags_fpu_compare(int float_relation);
void FPU_stack_overflow(uint32_t fetchdat);
void FPU_stack_underflow(uint32_t fetchdat, int stnr, int pop_stack);
int FPU_handle_NaN32(floatx80 a, float32 b, floatx80 *r, struct float_status_t *status);
int FPU_handle_NaN64(floatx80 a, float64 b, floatx80 *r, struct float_status_t *status);
int FPU_tagof(const floatx80 reg);
uint8_t pack_FPU_TW(uint16_t twd);
uint16_t unpack_FPU_TW(uint16_t tag_byte);
uint16_t FPU_exception(uint32_t fetchdat, uint16_t exceptions, int store);
int FPU_status_word_flags_fpu_compare(int float_relation);
void FPU_write_eflags_fpu_compare(int float_relation);
void FPU_stack_overflow(uint32_t fetchdat);
void FPU_stack_underflow(uint32_t fetchdat, int stnr, int pop_stack);
int FPU_handle_NaN32(floatx80 a, float32 b, floatx80 *r, struct float_status_t *status);
int FPU_handle_NaN64(floatx80 a, float64 b, floatx80 *r, struct float_status_t *status);
int FPU_tagof(const floatx80 reg);
uint8_t pack_FPU_TW(uint16_t twd);
uint16_t unpack_FPU_TW(uint16_t tag_byte);
static __inline uint16_t
i387_get_control_word(void)
@@ -181,7 +187,7 @@ static __inline void
FPU_settagi_valid(int stnr)
{
int regnr = (stnr + fpu_state.tos) & 7;
fpu_state.tag &= ~(3 << (regnr * 2)); // FPU_Tag_Valid == '00
fpu_state.tag &= ~(3 << (regnr * 2)); // FPU_Tag_Valid == '00
}
static __inline void
@@ -228,16 +234,15 @@ FPU_save_regi_tag(floatx80 reg, int tag, int stnr)
FPU_settagi(tag, stnr);
}
#define FPU_check_pending_exceptions() \
do { \
if (fpu_state.swd & FPU_SW_Summary) { \
if (cr0 & 0x20) { \
x86_int(16); \
return 1; \
} else { \
picint(1 << 13); \
return 1; \
} \
} \
} while (0)
#define FPU_check_pending_exceptions() \
do { \
if (fpu_state.swd & FPU_SW_Summary) { \
if (cr0 & 0x20) { \
x86_int(16); \
return 1; \
} else { \
picint(1 << 13); \
return 1; \
} \
} \
} while (0)

42
src/cpu/x87_ops.h
View File

@@ -45,21 +45,20 @@ static int rounding_modes[4] = { FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARD
#define C2 (1 << 10)
#define C3 (1 << 14)
#define X87_TAG_VALID 0
#define X87_TAG_ZERO 1
#define X87_TAG_INVALID 2
#define X87_TAG_EMPTY 3
#define X87_TAG_VALID 0
#define X87_TAG_ZERO 1
#define X87_TAG_INVALID 2
#define X87_TAG_EMPTY 3
#define STATUS_ZERODIVIDE 4
typedef union
{
typedef union {
double d;
struct {
uint64_t mantissa:52;
uint64_t exponent:11;
uint64_t negative:1;
uint64_t mantissa : 52;
uint64_t exponent : 11;
uint64_t negative : 1;
};
} double_decompose_t;
@@ -1074,7 +1073,6 @@ const OpFn OP_TABLE(fpu_8087_df)[256] = {
#else
# define ILLEGAL_a32 FPU_ILLEGAL_a32
const OpFn OP_TABLE(sf_fpu_d8_a16)[32] = {
// clang-format off
sf_FADDs_a16, sf_FMULs_a16, sf_FCOMs_a16, sf_FCOMPs_a16, sf_FSUBs_a16, sf_FSUBRs_a16, sf_FDIVs_a16, sf_FDIVRs_a16,
@@ -1413,7 +1411,7 @@ const OpFn OP_TABLE(sf_fpu_da_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(sf_fpu_686_da_a16)[256] = {
// clang-format off
sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16, sf_FADDil_a16,
@@ -1493,7 +1491,7 @@ const OpFn OP_TABLE(sf_fpu_686_da_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(sf_fpu_287_db_a16)[256] = {
// clang-format off
@@ -1655,7 +1653,7 @@ const OpFn OP_TABLE(sf_fpu_db_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(sf_fpu_686_db_a16)[256] = {
// clang-format off
sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16, sf_FILDil_a16,
@@ -1734,7 +1732,7 @@ const OpFn OP_TABLE(sf_fpu_686_db_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(sf_fpu_287_dc_a16)[32] = {
// clang-format off
@@ -2252,7 +2250,7 @@ const OpFn OP_TABLE(sf_fpu_df_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(sf_fpu_686_df_a16)[256] = {
// clang-format off
sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16, sf_FILDiw_a16,
@@ -2332,7 +2330,7 @@ const OpFn OP_TABLE(sf_fpu_686_df_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(fpu_d8_a16)[32] = {
// clang-format off
@@ -2672,7 +2670,7 @@ const OpFn OP_TABLE(fpu_da_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(fpu_686_da_a16)[256] = {
// clang-format off
opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16, opFADDil_a16,
@@ -2752,7 +2750,7 @@ const OpFn OP_TABLE(fpu_686_da_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(fpu_287_db_a16)[256] = {
// clang-format off
@@ -2914,7 +2912,7 @@ const OpFn OP_TABLE(fpu_db_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(fpu_686_db_a16)[256] = {
// clang-format off
opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16, opFILDil_a16,
@@ -2993,7 +2991,7 @@ const OpFn OP_TABLE(fpu_686_db_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(fpu_287_dc_a16)[32] = {
// clang-format off
@@ -3511,7 +3509,7 @@ const OpFn OP_TABLE(fpu_df_a32)[256] = {
// clang-format on
};
#ifndef OPS_286_386
# ifndef OPS_286_386
const OpFn OP_TABLE(fpu_686_df_a16)[256] = {
// clang-format off
opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16, opFILDiw_a16,
@@ -3591,7 +3589,7 @@ const OpFn OP_TABLE(fpu_686_df_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32,
// clang-format on
};
#endif
# endif
const OpFn OP_TABLE(nofpu_a16)[256] = {
// clang-format off

12
src/cpu/x87_ops_arith.h
View File

@@ -143,9 +143,9 @@ opFPU(il, uint32_t, 16, t, geteal, (double) (int32_t) t, _i32)
#ifndef FPU_8087
opFPU(il, uint32_t, 32, t, geteal, (double) (int32_t) t, _i32)
#endif
// clang-format on
// clang-format on
static int opFADD(uint32_t fetchdat)
static int opFADD(uint32_t fetchdat)
{
FP_ENTER();
cpu_state.pc++;
@@ -242,7 +242,7 @@ opFUCOMPP(uint32_t fetchdat)
return 0;
}
#ifndef OPS_286_386
# ifndef OPS_286_386
static int
opFCOMI(uint32_t fetchdat)
{
@@ -274,7 +274,7 @@ opFCOMIP(uint32_t fetchdat)
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
#endif
# endif
#endif
static int
@@ -478,7 +478,7 @@ opFUCOMP(uint32_t fetchdat)
return 0;
}
#ifndef OPS_286_386
# ifndef OPS_286_386
static int
opFUCOMI(uint32_t fetchdat)
{
@@ -510,5 +510,5 @@ opFUCOMIP(uint32_t fetchdat)
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
#endif
# endif
#endif

34
src/cpu/x87_ops_misc.h
View File

@@ -1046,23 +1046,23 @@ opFSTCW_a32(uint32_t fetchdat)
#endif
#ifndef FPU_8087
#ifndef OPS_286_386
# define opFCMOV(condition) \
static int opFCMOV##condition(uint32_t fetchdat) \
{ \
FP_ENTER(); \
cpu_state.pc++; \
if (cond_##condition) { \
cpu_state.tag[cpu_state.TOP & 7] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7]; \
cpu_state.MM[cpu_state.TOP & 7].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q; \
ST(0) = ST(fetchdat & 7); \
} \
CLOCK_CYCLES_FPU(4); \
return 0; \
}
# ifndef OPS_286_386
# define opFCMOV(condition) \
static int opFCMOV##condition(uint32_t fetchdat) \
{ \
FP_ENTER(); \
cpu_state.pc++; \
if (cond_##condition) { \
cpu_state.tag[cpu_state.TOP & 7] = cpu_state.tag[(cpu_state.TOP + fetchdat) & 7]; \
cpu_state.MM[cpu_state.TOP & 7].q = cpu_state.MM[(cpu_state.TOP + fetchdat) & 7].q; \
ST(0) = ST(fetchdat & 7); \
} \
CLOCK_CYCLES_FPU(4); \
return 0; \
}
# define cond_U (PF_SET())
# define cond_NU (!PF_SET())
# define cond_U (PF_SET())
# define cond_NU (!PF_SET())
// clang-format off
opFCMOV(B)
@@ -1074,5 +1074,5 @@ opFCMOV(NE)
opFCMOV(NBE)
opFCMOV(NU)
// clang-format on
#endif
# endif
#endif

434
src/cpu/x87_ops_sf.h
View File

@@ -1,7 +1,7 @@
static uint32_t
fpu_save_environment(void)
{
int tag;
int tag;
unsigned offset = 0;
/* read all registers in stack order and update x87 tag word */
@@ -16,94 +16,98 @@ fpu_save_environment(void)
fpu_state.swd = (fpu_state.swd & ~(7 << 11)) | ((fpu_state.tos & 7) << 11);
switch ((cr0 & 1) | (cpu_state.op32 & 0x100)) {
case 0x000: { /*16-bit real mode*/
uint16_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
case 0x000:
{ /*16-bit real mode*/
uint16_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
fp_ip = ((uint32_t)(fpu_state.fcs << 4)) | fpu_state.fip;
fp_dp = ((uint32_t)(fpu_state.fds << 4)) | fpu_state.fdp;
fp_ip = ((uint32_t) (fpu_state.fcs << 4)) | fpu_state.fip;
fp_dp = ((uint32_t) (fpu_state.fds << 4)) | fpu_state.fdp;
tmp = i387_get_control_word();
writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = i387_get_status_word();
writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
tmp = fpu_state.tag;
writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = fp_ip & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
tmp = (uint16_t)((fp_ip & 0xf0000) >> 4) | fpu_state.foo;
writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = fp_dp & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
tmp = (uint16_t)((fp_dp & 0xf0000) >> 4);
writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
offset = 0x0e;
}
break;
case 0x001: {/*16-bit protected mode*/
uint16_t tmp;
tmp = i387_get_control_word();
writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = i387_get_status_word();
writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
tmp = fpu_state.tag;
writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = (uint16_t)(fpu_state.fip) & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
tmp = fpu_state.fcs;
writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = (uint16_t)(fpu_state.fdp) & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
tmp = fpu_state.fds;
writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
offset = 0x0e;
}
break;
case 0x100: { /*32-bit real mode*/
uint32_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
tmp = i387_get_control_word();
writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = i387_get_status_word();
writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
tmp = fpu_state.tag;
writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = fp_ip & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
tmp = (uint16_t) ((fp_ip & 0xf0000) >> 4) | fpu_state.foo;
writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = fp_dp & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
tmp = (uint16_t) ((fp_dp & 0xf0000) >> 4);
writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
offset = 0x0e;
}
break;
case 0x001:
{ /*16-bit protected mode*/
uint16_t tmp;
tmp = i387_get_control_word();
writememw(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = i387_get_status_word();
writememw(easeg, cpu_state.eaaddr + 0x02, tmp);
tmp = fpu_state.tag;
writememw(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = (uint16_t) (fpu_state.fip) & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x06, tmp);
tmp = fpu_state.fcs;
writememw(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = (uint16_t) (fpu_state.fdp) & 0xffff;
writememw(easeg, cpu_state.eaaddr + 0x0a, tmp);
tmp = fpu_state.fds;
writememw(easeg, cpu_state.eaaddr + 0x0c, tmp);
offset = 0x0e;
}
break;
case 0x100:
{ /*32-bit real mode*/
uint32_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
fp_ip = ((uint32_t)(fpu_state.fcs << 4)) | fpu_state.fip;
fp_dp = ((uint32_t)(fpu_state.fds << 4)) | fpu_state.fdp;
fp_ip = ((uint32_t) (fpu_state.fcs << 4)) | fpu_state.fip;
fp_dp = ((uint32_t) (fpu_state.fds << 4)) | fpu_state.fdp;
tmp = 0xffff0000 | i387_get_control_word();
writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = 0xffff0000 | i387_get_status_word();
writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = 0xffff0000 | fpu_state.tag;
writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = 0xffff0000 | (fp_ip & 0xffff);
writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
tmp = ((fp_ip & 0xffff0000) >> 4) | fpu_state.foo;
writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
tmp = 0xffff0000 | (fp_dp & 0xffff);
writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
tmp = (fp_dp & 0xffff0000) >> 4;
writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
offset = 0x1c;
}
break;
case 0x101: { /*32-bit protected mode*/
uint32_t tmp;
tmp = 0xffff0000 | i387_get_control_word();
writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = 0xffff0000 | i387_get_status_word();
writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = 0xffff0000 | fpu_state.tag;
writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = (uint32_t)(fpu_state.fip);
writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
tmp = fpu_state.fcs | (((uint32_t)(fpu_state.foo)) << 16);
writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
tmp = (uint32_t)(fpu_state.fdp);
writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
tmp = 0xffff0000 | fpu_state.fds;
writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
offset = 0x1c;
}
break;
tmp = 0xffff0000 | i387_get_control_word();
writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = 0xffff0000 | i387_get_status_word();
writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = 0xffff0000 | fpu_state.tag;
writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = 0xffff0000 | (fp_ip & 0xffff);
writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
tmp = ((fp_ip & 0xffff0000) >> 4) | fpu_state.foo;
writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
tmp = 0xffff0000 | (fp_dp & 0xffff);
writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
tmp = (fp_dp & 0xffff0000) >> 4;
writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
offset = 0x1c;
}
break;
case 0x101:
{ /*32-bit protected mode*/
uint32_t tmp;
tmp = 0xffff0000 | i387_get_control_word();
writememl(easeg, cpu_state.eaaddr + 0x00, tmp);
tmp = 0xffff0000 | i387_get_status_word();
writememl(easeg, cpu_state.eaaddr + 0x04, tmp);
tmp = 0xffff0000 | fpu_state.tag;
writememl(easeg, cpu_state.eaaddr + 0x08, tmp);
tmp = (uint32_t) (fpu_state.fip);
writememl(easeg, cpu_state.eaaddr + 0x0c, tmp);
tmp = fpu_state.fcs | (((uint32_t) (fpu_state.foo)) << 16);
writememl(easeg, cpu_state.eaaddr + 0x10, tmp);
tmp = (uint32_t) (fpu_state.fdp);
writememl(easeg, cpu_state.eaaddr + 0x14, tmp);
tmp = 0xffff0000 | fpu_state.fds;
writememl(easeg, cpu_state.eaaddr + 0x18, tmp);
offset = 0x1c;
}
break;
}
return (cpu_state.eaaddr + offset);
@@ -115,100 +119,104 @@ fpu_load_environment(void)
unsigned offset = 0;
switch ((cr0 & 1) | (cpu_state.op32 & 0x100)) {
case 0x000: { /*16-bit real mode*/
uint16_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
case 0x000:
{ /*16-bit real mode*/
uint16_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
fp_dp = (tmp & 0xf000) << 4;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
fpu_state.fdp = fp_dp | tmp;
fpu_state.fds = 0;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
fp_ip = (tmp & 0xf000) << 4;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
fpu_state.fip = fp_ip | tmp;
fpu_state.fcs = 0;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
fpu_state.tag = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
fpu_state.swd = tmp;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp;
offset = 0x0e;
}
break;
case 0x001: {/*16-bit protected mode*/
uint16_t tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
fpu_state.fds = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
fpu_state.fdp = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
fpu_state.fcs = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
fpu_state.fip = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
fpu_state.tag = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
fpu_state.swd = tmp;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp;
offset = 0x0e;
}
break;
case 0x100: { /*32-bit real mode*/
uint32_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
fp_dp = (tmp & 0xf000) << 4;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
fpu_state.fdp = fp_dp | tmp;
fpu_state.fds = 0;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
fp_ip = (tmp & 0xf000) << 4;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
fpu_state.fip = fp_ip | tmp;
fpu_state.fcs = 0;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
fpu_state.tag = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
fpu_state.swd = tmp;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp;
offset = 0x0e;
}
break;
case 0x001:
{ /*16-bit protected mode*/
uint16_t tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0c);
fpu_state.fds = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x0a);
fpu_state.fdp = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x08);
fpu_state.fcs = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x06);
fpu_state.fip = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x04);
fpu_state.tag = tmp;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x02);
fpu_state.swd = tmp;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmemw(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp;
offset = 0x0e;
}
break;
case 0x100:
{ /*32-bit real mode*/
uint32_t tmp;
uint32_t fp_ip;
uint32_t fp_dp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
fp_dp = (tmp & 0x0ffff000) << 4;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
fp_dp |= (tmp & 0xffff);
fpu_state.fdp = fp_dp;
fpu_state.fds = 0;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
fpu_state.foo = tmp & 0x07ff;
fp_ip = (tmp & 0x0ffff000) << 4;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
fp_ip |= (tmp & 0xffff);
fpu_state.fip = fp_ip;
fpu_state.fcs = 0;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
fpu_state.tag = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
fpu_state.swd = tmp & 0xffff;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp & 0xffff;
offset = 0x1c;
}
break;
case 0x101: { /*32-bit protected mode*/
uint32_t tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
fpu_state.fds = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
fpu_state.fdp = tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
fpu_state.fcs = tmp & 0xffff;
fpu_state.foo = (tmp >> 16) & 0x07ff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
fpu_state.fip = tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
fpu_state.tag = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
fpu_state.swd = tmp & 0xffff;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp & 0xffff;
offset = 0x1c;
}
break;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
fp_dp = (tmp & 0x0ffff000) << 4;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
fp_dp |= (tmp & 0xffff);
fpu_state.fdp = fp_dp;
fpu_state.fds = 0;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
fpu_state.foo = tmp & 0x07ff;
fp_ip = (tmp & 0x0ffff000) << 4;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
fp_ip |= (tmp & 0xffff);
fpu_state.fip = fp_ip;
fpu_state.fcs = 0;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
fpu_state.tag = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
fpu_state.swd = tmp & 0xffff;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp & 0xffff;
offset = 0x1c;
}
break;
case 0x101:
{ /*32-bit protected mode*/
uint32_t tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x18);
fpu_state.fds = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x14);
fpu_state.fdp = tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x10);
fpu_state.fcs = tmp & 0xffff;
fpu_state.foo = (tmp >> 16) & 0x07ff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x0c);
fpu_state.fip = tmp;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x08);
fpu_state.tag = tmp & 0xffff;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x04);
fpu_state.swd = tmp & 0xffff;
fpu_state.tos = (tmp >> 11) & 7;
tmp = readmeml(easeg, cpu_state.eaaddr + 0x00);
fpu_state.cwd = tmp & 0xffff;
offset = 0x1c;
}
break;
}
/* always set bit 6 as '1 */
@@ -364,7 +372,7 @@ static int
sf_FRSTOR_a16(uint32_t fetchdat)
{
floatx80 tmp;
int offset;
int offset;
FP_ENTER();
fetch_ea_16(fetchdat);
@@ -372,7 +380,7 @@ sf_FRSTOR_a16(uint32_t fetchdat)
offset = fpu_load_environment();
for (int n = 0; n < 8; n++) {
tmp.fraction = readmemq(easeg, offset + (n * 10));
tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
FPU_save_regi_tag(tmp, IS_TAG_EMPTY(n) ? X87_TAG_EMPTY : FPU_tagof(tmp), n);
}
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
@@ -384,7 +392,7 @@ static int
sf_FRSTOR_a32(uint32_t fetchdat)
{
floatx80 tmp;
int offset;
int offset;
FP_ENTER();
fetch_ea_32(fetchdat);
@@ -392,7 +400,7 @@ sf_FRSTOR_a32(uint32_t fetchdat)
offset = fpu_load_environment();
for (int n = 0; n < 8; n++) {
tmp.fraction = readmemq(easeg, offset + (n * 10));
tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
tmp.exp = readmemw(easeg, offset + (n * 10) + 8);
FPU_save_regi_tag(tmp, IS_TAG_EMPTY(n) ? X87_TAG_EMPTY : FPU_tagof(tmp), n);
}
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.frstor) : (x87_timings.frstor * cpu_multi));
@@ -405,7 +413,7 @@ static int
sf_FNSAVE_a16(uint32_t fetchdat)
{
floatx80 stn;
int offset;
int offset;
FP_ENTER();
fetch_ea_16(fetchdat);
@@ -423,15 +431,15 @@ sf_FNSAVE_a16(uint32_t fetchdat)
#else
fpu_state.cwd = 0x37F;
#endif
fpu_state.swd = 0;
fpu_state.tos = 0;
fpu_state.tag = 0xffff;
fpu_state.swd = 0;
fpu_state.tos = 0;
fpu_state.tag = 0xffff;
cpu_state.ismmx = 0;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsave) : (x87_concurrency.fsave * cpu_multi));
return cpu_state.abrt;
@@ -441,7 +449,7 @@ static int
sf_FNSAVE_a32(uint32_t fetchdat)
{
floatx80 stn;
int offset;
int offset;
FP_ENTER();
fetch_ea_32(fetchdat);
@@ -454,20 +462,20 @@ sf_FNSAVE_a32(uint32_t fetchdat)
writememw(easeg, offset + (m * 10) + 8, stn.exp);
}
#ifdef FPU_8087
# ifdef FPU_8087
fpu_state.swd = 0x3FF;
#else
# else
fpu_state.cwd = 0x37F;
#endif
fpu_state.swd = 0;
fpu_state.tos = 0;
fpu_state.tag = 0xffff;
# endif
fpu_state.swd = 0;
fpu_state.tos = 0;
fpu_state.tag = 0xffff;
cpu_state.ismmx = 0;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fsave) : (x87_timings.fsave * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fsave) : (x87_concurrency.fsave * cpu_multi));
return cpu_state.abrt;
@@ -479,9 +487,7 @@ sf_FNCLEX(uint32_t fetchdat)
{
FP_ENTER();
cpu_state.pc++;
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary | FPU_SW_Stack_Fault | FPU_SW_Precision |
FPU_SW_Underflow | FPU_SW_Overflow | FPU_SW_Zero_Div | FPU_SW_Denormal_Op |
FPU_SW_Invalid);
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary | FPU_SW_Stack_Fault | FPU_SW_Precision | FPU_SW_Underflow | FPU_SW_Overflow | FPU_SW_Zero_Div | FPU_SW_Denormal_Op | FPU_SW_Invalid);
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fnop) : (x87_timings.fnop * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fnop) : (x87_concurrency.fnop * cpu_multi));
return 0;
@@ -497,14 +503,14 @@ sf_FNINIT(uint32_t fetchdat)
#else
fpu_state.cwd = 0x37F;
#endif
fpu_state.swd = 0;
fpu_state.swd = 0;
fpu_state.tos = 0;
fpu_state.tag = 0xffff;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
fpu_state.tag = 0xffff;
fpu_state.foo = 0;
fpu_state.fds = 0;
fpu_state.fdp = 0;
fpu_state.fcs = 0;
fpu_state.fip = 0;
cpu_state.ismmx = 0;
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.finit) : (x87_timings.finit * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.finit) : (x87_concurrency.finit * cpu_multi));
@@ -567,7 +573,7 @@ sf_FNSTENV_a16(uint32_t fetchdat)
/* mask all floating point exceptions */
fpu_state.cwd |= FPU_CW_Exceptions_Mask;
/* clear the B and ES bits in the status word */
fpu_state.swd &= ~(FPU_SW_Backward|FPU_SW_Summary);
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary);
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
return cpu_state.abrt;
@@ -583,7 +589,7 @@ sf_FNSTENV_a32(uint32_t fetchdat)
/* mask all floating point exceptions */
fpu_state.cwd |= FPU_CW_Exceptions_Mask;
/* clear the B and ES bits in the status word */
fpu_state.swd &= ~(FPU_SW_Backward|FPU_SW_Summary);
fpu_state.swd &= ~(FPU_SW_Backward | FPU_SW_Summary);
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fstenv) : (x87_timings.fstenv * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fstenv) : (x87_concurrency.fstenv * cpu_multi));
return cpu_state.abrt;

347
src/cpu/x87_ops_sf_arith.h
View File

@@ -1,180 +1,180 @@
#define sf_FPU(name, optype, a_size, load_var, rw, use_var, is_nan, cycle_postfix) \
static int sf_FADD##name##_a##a_size(uint32_t fetchdat) \
#define sf_FPU(name, optype, a_size, load_var, rw, use_var, is_nan, cycle_postfix) \
static int sf_FADD##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_add(a, use_var, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_add(a, use_var, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd##cycle_postfix) : ((x87_timings.fadd##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd##cycle_postfix) : ((x87_concurrency.fadd##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FDIV##name##_a##a_size(uint32_t fetchdat) \
static int sf_FDIV##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_div(a, use_var, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_div(a, use_var, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv##cycle_postfix) : ((x87_timings.fdiv##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd##cycle_postfix) : ((x87_concurrency.fadd##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FDIVR##name##_a##a_size(uint32_t fetchdat) \
static int sf_FDIVR##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_div(use_var, a, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_div(use_var, a, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fdiv##cycle_postfix) : ((x87_timings.fdiv##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fdiv##cycle_postfix) : ((x87_concurrency.fdiv##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FMUL##name##_a##a_size(uint32_t fetchdat) \
static int sf_FMUL##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_mul(a, use_var, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) { \
result = floatx80_mul(a, use_var, &status); \
} \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fmul##cycle_postfix) : ((x87_timings.fmul##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fmul##cycle_postfix) : ((x87_concurrency.fmul##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FSUB##name##_a##a_size(uint32_t fetchdat) \
static int sf_FSUB##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_sub(a, use_var, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_sub(a, use_var, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd##cycle_postfix) : ((x87_timings.fadd##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd##cycle_postfix) : ((x87_concurrency.fadd##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FSUBR##name##_a##a_size(uint32_t fetchdat) \
static int sf_FSUBR##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
floatx80 a, result; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
FPU_check_pending_exceptions(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_sub(use_var, a, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_stack_underflow(fetchdat, 0, 0); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (!is_nan) \
result = floatx80_sub(use_var, a, &status); \
\
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_save_regi(result, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fadd##cycle_postfix) : ((x87_timings.fadd##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fadd##cycle_postfix) : ((x87_concurrency.fadd##cycle_postfix) * cpu_multi)); \
return 0; \
@@ -198,10 +198,9 @@ sf_FPU(il, uint32_t, 16, temp, geteal(), int32_to_floatx80((int32_t)temp), 0, _i
#ifndef FPU_8087
sf_FPU(il, uint32_t, 32, temp, geteal(), int32_to_floatx80((int32_t)temp), 0, _i32)
#endif
// clang-format on
// clang-format on
static int
sf_FADD_st0_stj(uint32_t fetchdat)
static int sf_FADD_st0_stj(uint32_t fetchdat)
{
floatx80 a;
floatx80 b;
@@ -217,8 +216,8 @@ sf_FADD_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_add(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -246,8 +245,8 @@ sf_FADD_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_add(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -276,8 +275,8 @@ sf_FADDP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_add(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -307,8 +306,8 @@ sf_FDIV_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -336,8 +335,8 @@ sf_FDIV_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -364,8 +363,8 @@ sf_FDIVP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -395,8 +394,8 @@ sf_FDIVR_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -423,8 +422,8 @@ sf_FDIVR_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
@@ -451,8 +450,8 @@ sf_FDIVRP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_div(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -482,8 +481,8 @@ sf_FMUL_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_mul(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -511,8 +510,8 @@ sf_FMUL_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_mul(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -540,8 +539,8 @@ sf_FMULP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_mul(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -571,8 +570,8 @@ sf_FSUB_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -600,8 +599,8 @@ sf_FSUB_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -629,8 +628,8 @@ sf_FSUBP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -660,8 +659,8 @@ sf_FSUBR_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
a = FPU_read_regi(fetchdat & 7);
b = FPU_read_regi(0);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -689,8 +688,8 @@ sf_FSUBR_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -718,8 +717,8 @@ sf_FSUBRP_sti_st0(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
result = floatx80_sub(a, b, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
@@ -736,7 +735,7 @@ next_ins:
static int
sf_FSQRT(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();
@@ -762,7 +761,7 @@ next_ins:
static int
sf_FRNDINT(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();

237
src/cpu/x87_ops_sf_compare.h
View File

@@ -1,76 +1,76 @@
#define cmp_FPU(name, optype, a_size, load_var, rw, use_var, is_nan, cycle_postfix) \
static int sf_FCOM##name##_a##a_size(uint32_t fetchdat) \
#define cmp_FPU(name, optype, a_size, load_var, rw, use_var, is_nan, cycle_postfix) \
static int sf_FCOM##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a; \
int rc; \
struct float_status_t status; \
optype temp; \
floatx80 a; \
int rc; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_exception(fetchdat, FPU_EX_Stack_Underflow, 0); \
setcc(C0 | C2 | C3); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (is_nan) { \
rc = float_relation_unordered; \
float_raise(&status, float_flag_invalid); \
} else { \
rc = floatx80_compare_two(a, use_var, &status); \
} \
setcc(FPU_status_word_flags_fpu_compare(rc)); \
FPU_exception(fetchdat, status.float_exception_flags, 0); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_exception(fetchdat, FPU_EX_Stack_Underflow, 0); \
setcc(C0 | C2 | C3); \
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (is_nan) { \
rc = float_relation_unordered; \
float_raise(&status, float_flag_invalid); \
} else { \
rc = floatx80_compare_two(a, use_var, &status); \
} \
setcc(FPU_status_word_flags_fpu_compare(rc)); \
FPU_exception(fetchdat, status.float_exception_flags, 0); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom##cycle_postfix) : ((x87_timings.fcom##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom##cycle_postfix) : ((x87_concurrency.fcom##cycle_postfix) * cpu_multi)); \
return 0; \
} \
static int sf_FCOMP##name##_a##a_size(uint32_t fetchdat) \
static int sf_FCOMP##name##_a##a_size(uint32_t fetchdat) \
{ \
floatx80 a; \
int rc; \
struct float_status_t status; \
optype temp; \
floatx80 a; \
int rc; \
struct float_status_t status; \
optype temp; \
FP_ENTER(); \
fetch_ea_##a_size(fetchdat); \
SEG_CHECK_READ(cpu_state.ea_seg); \
load_var = rw; \
if (cpu_state.abrt) \
return 1;\
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_exception(fetchdat, FPU_EX_Stack_Underflow, 0); \
setcc(C0 | C2 | C3); \
if (is_IA_masked()) \
FPU_pop(); \
\
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (is_nan) { \
rc = float_relation_unordered; \
float_raise(&status, float_flag_invalid); \
} else { \
rc = floatx80_compare_two(a, use_var, &status); \
} \
setcc(FPU_status_word_flags_fpu_compare(rc)); \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_pop(); \
\
next_ins: \
load_var = rw; \
if (cpu_state.abrt) \
return 1; \
clear_C1(); \
if (IS_TAG_EMPTY(0)) { \
FPU_exception(fetchdat, FPU_EX_Stack_Underflow, 0); \
setcc(C0 | C2 | C3); \
if (is_IA_masked()) \
FPU_pop(); \
\
goto next_ins; \
} \
status = i387cw_to_softfloat_status_word(i387_get_control_word()); \
a = FPU_read_regi(0); \
if (is_nan) { \
rc = float_relation_unordered; \
float_raise(&status, float_flag_invalid); \
} else { \
rc = floatx80_compare_two(a, use_var, &status); \
} \
setcc(FPU_status_word_flags_fpu_compare(rc)); \
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) \
FPU_pop(); \
\
next_ins: \
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fcom##cycle_postfix) : ((x87_timings.fcom##cycle_postfix) * cpu_multi)); \
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom##cycle_postfix) : ((x87_concurrency.fcom##cycle_postfix) * cpu_multi)); \
return 0; \
} \
}
// clang-format off
cmp_FPU(s, float32, 16, temp, geteal(), float32_to_floatx80(temp, &status), floatx80_is_nan(a) || floatx80_is_unsupported(a) || float32_is_nan(temp), _32)
@@ -90,15 +90,14 @@ cmp_FPU(il, int32_t, 16, temp, (int32_t)geteal(), int32_to_floatx80(temp), 0, _i
#ifndef FPU_8087
cmp_FPU(il, int32_t, 32, temp, (int32_t)geteal(), int32_to_floatx80(temp), 0, _i32)
#endif
// clang-format on
// clang-format on
static int
sf_FCOM_sti(uint32_t fetchdat)
static int sf_FCOM_sti(uint32_t fetchdat)
{
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -109,9 +108,9 @@ sf_FCOM_sti(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
FPU_exception(fetchdat, status.float_exception_flags, 0);
@@ -127,7 +126,7 @@ sf_FCOMP_sti(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -141,9 +140,9 @@ sf_FCOMP_sti(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
@@ -161,7 +160,7 @@ sf_FCOMPP(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -176,9 +175,9 @@ sf_FCOMPP(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(1);
rc = floatx80_compare_two(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(1);
rc = floatx80_compare_two(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
@@ -198,7 +197,7 @@ sf_FUCOMPP(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -213,9 +212,9 @@ sf_FUCOMPP(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(1);
rc = floatx80_compare_quiet(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(1);
rc = floatx80_compare_quiet(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
@@ -228,14 +227,14 @@ next_ins:
return 0;
}
#ifndef OPS_286_386
# ifndef OPS_286_386
static int
sf_FCOMI_st0_stj(uint32_t fetchdat)
{
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -247,9 +246,9 @@ sf_FCOMI_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
FPU_write_eflags_fpu_compare(rc);
FPU_exception(fetchdat, status.float_exception_flags, 0);
@@ -264,7 +263,7 @@ sf_FCOMIP_st0_stj(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -279,9 +278,9 @@ sf_FCOMIP_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_two(a, b, &status);
FPU_write_eflags_fpu_compare(rc);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
@@ -292,7 +291,7 @@ next_ins:
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fcom) : (x87_concurrency.fcom * cpu_multi));
return 0;
}
#endif
# endif
static int
sf_FUCOM_sti(uint32_t fetchdat)
@@ -300,7 +299,7 @@ sf_FUCOM_sti(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -311,9 +310,9 @@ sf_FUCOM_sti(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
FPU_exception(fetchdat, status.float_exception_flags, 0);
@@ -329,7 +328,7 @@ sf_FUCOMP_sti(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -343,9 +342,9 @@ sf_FUCOMP_sti(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_pop();
@@ -356,14 +355,14 @@ next_ins:
return 0;
}
#ifndef OPS_286_386
# ifndef OPS_286_386
static int
sf_FUCOMI_st0_stj(uint32_t fetchdat)
{
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -375,9 +374,9 @@ sf_FUCOMI_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
FPU_write_eflags_fpu_compare(rc);
FPU_exception(fetchdat, status.float_exception_flags, 0);
@@ -392,7 +391,7 @@ sf_FUCOMIP_st0_stj(uint32_t fetchdat)
floatx80 a;
floatx80 b;
struct float_status_t status;
int rc;
int rc;
FP_ENTER();
cpu_state.pc++;
@@ -407,9 +406,9 @@ sf_FUCOMIP_st0_stj(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
a = FPU_read_regi(0);
b = FPU_read_regi(fetchdat & 7);
rc = floatx80_compare_quiet(a, b, &status);
FPU_write_eflags_fpu_compare(rc);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_pop();
@@ -419,13 +418,13 @@ next_ins:
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fucom) : (x87_concurrency.fucom * cpu_multi));
return 0;
}
#endif
# endif
#endif
static int
sf_FTST(uint32_t fetchdat)
{
int rc;
int rc;
struct float_status_t status;
FP_ENTER();
@@ -436,7 +435,7 @@ sf_FTST(uint32_t fetchdat)
setcc(C0 | C2 | C3);
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
rc = floatx80_compare_two(FPU_read_regi(0), Const_Z, &status);
rc = floatx80_compare_two(FPU_read_regi(0), Const_Z, &status);
setcc(FPU_status_word_flags_fpu_compare(rc));
FPU_exception(fetchdat, status.float_exception_flags, 0);
}
@@ -448,19 +447,19 @@ sf_FTST(uint32_t fetchdat)
static int
sf_FXAM(uint32_t fetchdat)
{
floatx80 reg;
int sign;
floatx80 reg;
int sign;
float_class_t aClass;
FP_ENTER();
cpu_state.pc++;
reg = FPU_read_regi(0);
reg = FPU_read_regi(0);
sign = floatx80_sign(reg);
/*
* Examine the contents of the ST(0) register and sets the condition
* code flags C0, C2 and C3 in the FPU status word to indicate the
* class of value or number in the register.
*/
/*
* Examine the contents of the ST(0) register and sets the condition
* code flags C0, C2 and C3 in the FPU status word to indicate the
* class of value or number in the register.
*/
if (IS_TAG_EMPTY(0)) {
setcc(C3 | C1 | C0);
} else {
@@ -490,10 +489,10 @@ sf_FXAM(uint32_t fetchdat)
break;
}
}
/*
* The C1 flag is set to the sign of the value in ST(0), regardless
* of whether the register is empty or full.
*/
/*
* The C1 flag is set to the sign of the value in ST(0), regardless
* of whether the register is empty or full.
*/
if (!sign)
clear_C1();

8
src/cpu/x87_ops_sf_const.h
View File

@@ -1,14 +1,14 @@
/* A fast way to find out whether x is one of RC_DOWN or RC_CHOP
(and not one of RC_RND or RC_UP).
*/
#define DOWN_OR_CHOP() (fpu_state.cwd & FPU_CW_RC & FPU_RC_DOWN)
#define DOWN_OR_CHOP() (fpu_state.cwd & FPU_CW_RC & FPU_RC_DOWN)
static __inline floatx80
FPU_round_const(const floatx80 a, int adj)
{
floatx80 result = a;
result.fraction += adj;
return result;
floatx80 result = a;
result.fraction += adj;
return result;
}
static int

267
src/cpu/x87_ops_sf_load_store.h
View File

@@ -17,13 +17,18 @@
* Copyright 2016-2019 Miran Grca.
*/
#define swap_values16u(a, b) { uint16_t tmp = a; a = b; b = tmp; }
#define swap_values16u(a, b) \
{ \
uint16_t tmp = a; \
a = b; \
b = tmp; \
}
static int
sf_FILDiw_a16(uint32_t fetchdat)
{
floatx80 result;
int16_t temp;
int16_t temp;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -49,7 +54,7 @@ static int
sf_FILDiw_a32(uint32_t fetchdat)
{
floatx80 result;
int16_t temp;
int16_t temp;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -76,7 +81,7 @@ static int
sf_FILDil_a16(uint32_t fetchdat)
{
floatx80 result;
int32_t templ;
int32_t templ;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -102,7 +107,7 @@ static int
sf_FILDil_a32(uint32_t fetchdat)
{
floatx80 result;
int32_t templ;
int32_t templ;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -129,7 +134,7 @@ static int
sf_FILDiq_a16(uint32_t fetchdat)
{
floatx80 result;
int64_t temp64;
int64_t temp64;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -155,7 +160,7 @@ static int
sf_FILDiq_a32(uint32_t fetchdat)
{
floatx80 result;
int64_t temp64;
int64_t temp64;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -182,9 +187,9 @@ static int
sf_FLDs_a16(uint32_t fetchdat)
{
struct float_status_t status;
floatx80 result;
float32 load_reg;
unsigned unmasked;
floatx80 result;
float32 load_reg;
unsigned unmasked;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -198,8 +203,8 @@ sf_FLDs_a16(uint32_t fetchdat)
FPU_stack_overflow(fetchdat);
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float32_to_floatx80(load_reg, &status);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float32_to_floatx80(load_reg, &status);
unmasked = FPU_exception(fetchdat, status.float_exception_flags, 0);
if (!(unmasked & FPU_CW_Invalid)) {
FPU_push();
@@ -216,9 +221,9 @@ static int
sf_FLDs_a32(uint32_t fetchdat)
{
struct float_status_t status;
floatx80 result;
float32 load_reg;
unsigned unmasked;
floatx80 result;
float32 load_reg;
unsigned unmasked;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -232,8 +237,8 @@ sf_FLDs_a32(uint32_t fetchdat)
FPU_stack_overflow(fetchdat);
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float32_to_floatx80(load_reg, &status);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float32_to_floatx80(load_reg, &status);
unmasked = FPU_exception(fetchdat, status.float_exception_flags, 0);
if (!(unmasked & FPU_CW_Invalid)) {
FPU_push();
@@ -251,9 +256,9 @@ static int
sf_FLDd_a16(uint32_t fetchdat)
{
struct float_status_t status;
floatx80 result;
float64 load_reg;
unsigned unmasked;
floatx80 result;
float64 load_reg;
unsigned unmasked;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -267,8 +272,8 @@ sf_FLDd_a16(uint32_t fetchdat)
FPU_stack_overflow(fetchdat);
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float64_to_floatx80(load_reg, &status);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float64_to_floatx80(load_reg, &status);
unmasked = FPU_exception(fetchdat, status.float_exception_flags, 0);
if (!(unmasked & FPU_CW_Invalid)) {
FPU_push();
@@ -285,9 +290,9 @@ static int
sf_FLDd_a32(uint32_t fetchdat)
{
struct float_status_t status;
floatx80 result;
float64 load_reg;
unsigned unmasked;
floatx80 result;
float64 load_reg;
unsigned unmasked;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -301,8 +306,8 @@ sf_FLDd_a32(uint32_t fetchdat)
FPU_stack_overflow(fetchdat);
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float64_to_floatx80(load_reg, &status);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = float64_to_floatx80(load_reg, &status);
unmasked = FPU_exception(fetchdat, status.float_exception_flags, 0);
if (!(unmasked & FPU_CW_Invalid)) {
FPU_push();
@@ -326,7 +331,7 @@ sf_FLDe_a16(uint32_t fetchdat)
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
result.fraction = readmemq(easeg, cpu_state.eaaddr);
result.exp = readmemw(easeg, cpu_state.eaaddr + 8);
result.exp = readmemw(easeg, cpu_state.eaaddr + 8);
if (cpu_state.abrt)
return 1;
clear_C1();
@@ -351,7 +356,7 @@ sf_FLDe_a32(uint32_t fetchdat)
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
result.fraction = readmemq(easeg, cpu_state.eaaddr);
result.exp = readmemw(easeg, cpu_state.eaaddr + 8);
result.exp = readmemw(easeg, cpu_state.eaaddr + 8);
if (cpu_state.abrt)
return 1;
clear_C1();
@@ -371,7 +376,7 @@ static int
sf_FLD_sti(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 sti_reg;
floatx80 sti_reg;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -403,8 +408,8 @@ static int
sf_FISTiw_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -417,7 +422,7 @@ sf_FISTiw_a16(uint32_t fetchdat)
goto next_ins;
}
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int16(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -438,8 +443,8 @@ static int
sf_FISTiw_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -451,7 +456,7 @@ sf_FISTiw_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int16(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -472,8 +477,8 @@ static int
sf_FISTPiw_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -485,7 +490,7 @@ sf_FISTPiw_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int16(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -509,8 +514,8 @@ static int
sf_FISTPiw_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
uint16_t sw = fpu_state.swd;
int16_t save_reg = int16_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -522,7 +527,7 @@ sf_FISTPiw_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int16(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -546,8 +551,8 @@ static int
sf_FISTil_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -559,7 +564,7 @@ sf_FISTil_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -580,8 +585,8 @@ static int
sf_FISTil_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -593,7 +598,7 @@ sf_FISTil_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -614,8 +619,8 @@ static int
sf_FISTPil_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -627,7 +632,7 @@ sf_FISTPil_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -651,8 +656,8 @@ static int
sf_FISTPil_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
uint16_t sw = fpu_state.swd;
int32_t save_reg = int32_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -664,7 +669,7 @@ sf_FISTPil_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -688,8 +693,8 @@ static int
sf_FISTPiq_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int64_t save_reg = int64_indefinite;
uint16_t sw = fpu_state.swd;
int64_t save_reg = int64_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -701,9 +706,9 @@ sf_FISTPiq_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
}
}
@@ -725,8 +730,8 @@ static int
sf_FISTPiq_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
int64_t save_reg = int64_indefinite;
uint16_t sw = fpu_state.swd;
int64_t save_reg = int64_indefinite;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -738,7 +743,7 @@ sf_FISTPiq_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_int64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -762,12 +767,12 @@ static int
sf_FBSTP_PACKED_BCD_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
uint16_t save_reg_hi = 0xffff;
uint64_t save_reg_lo = BX_CONST64(0xC000000000000000);
floatx80 reg;
int64_t save_val;
int sign;
uint16_t sw = fpu_state.swd;
uint16_t save_reg_hi = 0xffff;
uint64_t save_reg_lo = BX_CONST64(0xC000000000000000);
floatx80 reg;
int64_t save_val;
int sign;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -779,10 +784,10 @@ sf_FBSTP_PACKED_BCD_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
reg = FPU_read_regi(0);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
reg = FPU_read_regi(0);
save_val = floatx80_to_int64(reg, &status);
sign = (reg.exp & 0x8000) != 0;
sign = (reg.exp & 0x8000) != 0;
if (sign)
save_val = -save_val;
@@ -793,12 +798,12 @@ sf_FBSTP_PACKED_BCD_a16(uint32_t fetchdat)
save_reg_hi = sign ? 0x8000 : 0;
save_reg_lo = 0;
for (int i = 0; i < 16; i++) {
save_reg_lo += ((uint64_t)(save_val % 10)) << (4 * i);
save_reg_lo += ((uint64_t) (save_val % 10)) << (4 * i);
save_val /= 10;
}
save_reg_hi += (uint16_t)(save_val % 10);
save_reg_hi += (uint16_t) (save_val % 10);
save_val /= 10;
save_reg_hi += (uint16_t)(save_val % 10) << 4;
save_reg_hi += (uint16_t) (save_val % 10) << 4;
}
/* check for fpu arithmetic exceptions */
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
@@ -826,12 +831,12 @@ static int
sf_FBSTP_PACKED_BCD_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
uint16_t save_reg_hi = 0xffff;
uint64_t save_reg_lo = BX_CONST64(0xC000000000000000);
floatx80 reg;
int64_t save_val;
int sign;
uint16_t sw = fpu_state.swd;
uint16_t save_reg_hi = 0xffff;
uint64_t save_reg_lo = BX_CONST64(0xC000000000000000);
floatx80 reg;
int64_t save_val;
int sign;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -843,10 +848,10 @@ sf_FBSTP_PACKED_BCD_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
reg = FPU_read_regi(0);
status = i387cw_to_softfloat_status_word(i387_get_control_word());
reg = FPU_read_regi(0);
save_val = floatx80_to_int64(reg, &status);
sign = (reg.exp & 0x8000) != 0;
sign = (reg.exp & 0x8000) != 0;
if (sign)
save_val = -save_val;
@@ -857,12 +862,12 @@ sf_FBSTP_PACKED_BCD_a32(uint32_t fetchdat)
save_reg_hi = sign ? 0x8000 : 0;
save_reg_lo = 0;
for (int i = 0; i < 16; i++) {
save_reg_lo += ((uint64_t)(save_val % 10)) << (4 * i);
save_reg_lo += ((uint64_t) (save_val % 10)) << (4 * i);
save_val /= 10;
}
save_reg_hi += (uint16_t)(save_val % 10);
save_reg_hi += (uint16_t) (save_val % 10);
save_val /= 10;
save_reg_hi += (uint16_t)(save_val % 10) << 4;
save_reg_hi += (uint16_t) (save_val % 10) << 4;
}
/* check for fpu arithmetic exceptions */
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
@@ -891,8 +896,8 @@ static int
sf_FSTs_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -904,7 +909,7 @@ sf_FSTs_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -925,8 +930,8 @@ static int
sf_FSTs_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -938,7 +943,7 @@ sf_FSTs_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -959,8 +964,8 @@ static int
sf_FSTPs_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -972,7 +977,7 @@ sf_FSTPs_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -997,8 +1002,8 @@ static int
sf_FSTPs_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
uint16_t sw = fpu_state.swd;
float32 save_reg = float32_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1010,7 +1015,7 @@ sf_FSTPs_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float32(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -1034,8 +1039,8 @@ static int
sf_FSTd_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1047,7 +1052,7 @@ sf_FSTd_a16(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -1068,8 +1073,8 @@ static int
sf_FSTd_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1081,7 +1086,7 @@ sf_FSTd_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -1102,8 +1107,8 @@ static int
sf_FSTPd_a16(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1116,7 +1121,7 @@ sf_FSTPd_a16(uint32_t fetchdat)
goto next_ins;
}
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1)) {
goto next_ins;
@@ -1140,8 +1145,8 @@ static int
sf_FSTPd_a32(uint32_t fetchdat)
{
struct float_status_t status;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
uint16_t sw = fpu_state.swd;
float64 save_reg = float64_default_nan;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1153,7 +1158,7 @@ sf_FSTPd_a32(uint32_t fetchdat)
if (!is_IA_masked())
goto next_ins;
} else {
status = i387cw_to_softfloat_status_word(i387_get_control_word());
status = i387cw_to_softfloat_status_word(i387_get_control_word());
save_reg = floatx80_to_float64(FPU_read_regi(0), &status);
if (FPU_exception(fetchdat, status.float_exception_flags, 1))
goto next_ins;
@@ -1177,7 +1182,7 @@ static int
sf_FSTPe_a16(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 save_reg;
floatx80 save_reg;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1209,7 +1214,7 @@ static int
sf_FSTPe_a32(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 save_reg;
floatx80 save_reg;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -1279,26 +1284,26 @@ sf_FSTP_sti(uint32_t fetchdat)
}
#ifndef FPU_8087
#ifndef OPS_286_386
# define sf_FCMOV(condition) \
static int sf_FCMOV##condition(uint32_t fetchdat) \
{ \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
cpu_state.pc++; \
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(fetchdat & 7)) \
FPU_stack_underflow(fetchdat, 0, 0); \
else { \
if (cond_##condition) { \
FPU_save_regi(FPU_read_regi(fetchdat & 7), 0); \
} \
} \
CLOCK_CYCLES_FPU(4); \
return 0; \
}
# ifndef OPS_286_386
# define sf_FCMOV(condition) \
static int sf_FCMOV##condition(uint32_t fetchdat) \
{ \
FP_ENTER(); \
FPU_check_pending_exceptions(); \
cpu_state.pc++; \
if (IS_TAG_EMPTY(0) || IS_TAG_EMPTY(fetchdat & 7)) \
FPU_stack_underflow(fetchdat, 0, 0); \
else { \
if (cond_##condition) { \
FPU_save_regi(FPU_read_regi(fetchdat & 7), 0); \
} \
} \
CLOCK_CYCLES_FPU(4); \
return 0; \
}
# define cond_U (PF_SET())
# define cond_NU (!PF_SET())
# define cond_U (PF_SET())
# define cond_NU (!PF_SET())
// clang-format off
sf_FCMOV(B)
@@ -1310,5 +1315,5 @@ sf_FCMOV(NE)
sf_FCMOV(NBE)
sf_FCMOV(NU)
// clang-format on
#endif
# endif
#endif

12
src/cpu/x87_ops_sf_misc.h
View File

@@ -2,10 +2,10 @@ static int
sf_FXCH_sti(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 st0_reg;
floatx80 sti_reg;
int st0_tag;
int sti_tag;
floatx80 st0_reg;
floatx80 sti_reg;
int st0_tag;
int sti_tag;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -50,7 +50,7 @@ sf_FCHS(uint32_t fetchdat)
else {
clear_C1();
st0_reg = FPU_read_regi(0);
result = floatx80_chs(st0_reg);
result = floatx80_chs(st0_reg);
FPU_save_regi(result, 0);
}
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fchs) : (x87_timings.fchs * cpu_multi));
@@ -72,7 +72,7 @@ sf_FABS(uint32_t fetchdat)
else {
clear_C1();
st0_reg = FPU_read_regi(0);
result = floatx80_abs(st0_reg);
result = floatx80_abs(st0_reg);
FPU_save_regi(result, 0);
}
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fabs) : (x87_timings.fabs * cpu_multi));

70
src/cpu/x87_ops_sf_trans.h
View File

@@ -1,7 +1,7 @@
static int
sf_F2XM1(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();
@@ -13,7 +13,7 @@ sf_F2XM1(uint32_t fetchdat)
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
result = f2xm1(FPU_read_regi(0), &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0))
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_save_regi(result, 0);
next_ins:
@@ -25,7 +25,7 @@ next_ins:
static int
sf_FYL2X(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();
@@ -37,7 +37,7 @@ sf_FYL2X(uint32_t fetchdat)
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
result = fyl2x(FPU_read_regi(0), FPU_read_regi(1), &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
FPU_save_regi(result, 0);
}
@@ -51,8 +51,8 @@ next_ins:
static int
sf_FPTAN(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 y;
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
floatx80 y;
struct float_status_t status;
FP_ENTER();
@@ -74,14 +74,14 @@ sf_FPTAN(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
y = FPU_read_regi(0);
y = FPU_read_regi(0);
if (ftan(&y, &status) == -1) {
fpu_state.swd |= C2;
goto next_ins;
}
if (floatx80_is_nan(y)) {
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_save_regi(y, 0);
FPU_push();
FPU_save_regi(y, 0);
@@ -89,7 +89,7 @@ sf_FPTAN(uint32_t fetchdat)
goto next_ins;
}
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_save_regi(y, 0);
FPU_push();
FPU_save_regi(Const_1, 0);
@@ -115,11 +115,11 @@ sf_FPATAN(uint32_t fetchdat)
FPU_stack_underflow(fetchdat, 1, 1);
goto next_ins;
}
a = FPU_read_regi(0);
b = FPU_read_regi(1);
a = FPU_read_regi(0);
b = FPU_read_regi(1);
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
result = fpatan(a, b, &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_pop();
FPU_save_regi(result, 0);
}
@@ -141,7 +141,7 @@ sf_FXTRACT(uint32_t fetchdat)
cpu_state.pc++;
clear_C1();
#if 0 //TODO
#if 0 // TODO
if ((IS_TAG_EMPTY(0) || IS_TAG_EMPTY(-1))) {
if (IS_TAG_EMPTY(0))
FPU_exception(fetchdat, FPU_EX_Stack_Underflow, 0);
@@ -159,15 +159,15 @@ sf_FXTRACT(uint32_t fetchdat)
#endif
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = floatx80_extract(&a, &status);
a = FPU_read_regi(0);
b = floatx80_extract(&a, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_save_regi(b, 0); // exponent
FPU_push();
FPU_save_regi(a, 0); // fraction
}
#if 0 //TODO.
#if 0 // TODO.
next_ins:
#endif
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fxtract) : (x87_timings.fxtract * cpu_multi));
@@ -195,10 +195,10 @@ sf_FPREM1(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(1);
flags = floatx80_ieee754_remainder(a, b, &result, &quotient, &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
a = FPU_read_regi(0);
b = FPU_read_regi(1);
flags = floatx80_ieee754_remainder(a, b, &result, &quotient, &status);
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (flags >= 0) {
cc = 0;
if (flags)
@@ -242,11 +242,11 @@ sf_FPREM(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
a = FPU_read_regi(0);
b = FPU_read_regi(1);
a = FPU_read_regi(0);
b = FPU_read_regi(1);
// handle unsupported extended double-precision floating encodings
flags = floatx80_remainder(a, b, &result, &quotient, &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (flags >= 0) {
cc = 0;
if (flags)
@@ -273,7 +273,7 @@ next_ins:
static int
sf_FYL2XP1(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();
@@ -285,7 +285,7 @@ sf_FYL2XP1(uint32_t fetchdat)
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
result = fyl2xp1(FPU_read_regi(0), FPU_read_regi(1), &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_save_regi(result, 1);
FPU_pop();
}
@@ -325,12 +325,12 @@ sf_FSINCOS(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
y = FPU_read_regi(0);
y = FPU_read_regi(0);
if (fsincos(y, &sin_y, &cos_y, &status) == -1) {
fpu_state.swd |= C2;
goto next_ins;
}
if (! FPU_exception(fetchdat, status.float_exception_flags, 0)) {
if (!FPU_exception(fetchdat, status.float_exception_flags, 0)) {
FPU_save_regi(sin_y, 0);
FPU_push();
FPU_save_regi(cos_y, 0);
@@ -346,7 +346,7 @@ next_ins:
static int
sf_FSCALE(uint32_t fetchdat)
{
floatx80 result;
floatx80 result;
struct float_status_t status;
FP_ENTER();
@@ -358,7 +358,7 @@ sf_FSCALE(uint32_t fetchdat)
}
status = i387cw_to_softfloat_status_word(i387_get_control_word());
result = floatx80_scale(FPU_read_regi(0), FPU_read_regi(1), &status);
if (! FPU_exception(fetchdat, status.float_exception_flags, 0))
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_save_regi(result, 0);
next_ins:
@@ -371,7 +371,7 @@ next_ins:
static int
sf_FSIN(uint32_t fetchdat)
{
floatx80 y;
floatx80 y;
struct float_status_t status;
FP_ENTER();
@@ -383,12 +383,12 @@ sf_FSIN(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
y = FPU_read_regi(0);
y = FPU_read_regi(0);
if (fsin(&y, &status) == -1) {
fpu_state.swd |= C2;
goto next_ins;
}
if (! FPU_exception(fetchdat, status.float_exception_flags, 0))
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_save_regi(y, 0);
next_ins:
@@ -400,7 +400,7 @@ next_ins:
static int
sf_FCOS(uint32_t fetchdat)
{
floatx80 y;
floatx80 y;
struct float_status_t status;
FP_ENTER();
@@ -412,12 +412,12 @@ sf_FCOS(uint32_t fetchdat)
goto next_ins;
}
status = i387cw_to_softfloat_status_word(i387_get_control_word() | FPU_PR_80_BITS);
y = FPU_read_regi(0);
y = FPU_read_regi(0);
if (fcos(&y, &status) == -1) {
fpu_state.swd |= C2;
goto next_ins;
}
if (! FPU_exception(fetchdat, status.float_exception_flags, 0))
if (!FPU_exception(fetchdat, status.float_exception_flags, 0))
FPU_save_regi(y, 0);
next_ins: