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Merged various SMC FDC67C6xx Super I/O chips into one file, re-added the UMC88xx 486 chipsets (and four machines for it) based on work by tiseno100 and my own work, various other fixes, and added quite a few machines (including the AOpen AP5VM which now works), also added the remaining ALi M6117 machine (Protech SBC with Award BIOS), and made the Intel Advanced/ATX's on-board S3 Trio64V+ work, as well as the on-board S3 Trio64/V2 of the two Compaq Presarios.

Browse Source
This commit is contained in:
OBattler
2021-08-21 18:19:10 +02:00
parent b0ea9185d0
commit 67367798a7
32 changed files with 1030 additions and 1141 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/chipset/CMakeLists.txt
View File

@@ -18,8 +18,8 @@ add_library(chipset OBJECT acc2168.c cs8230.c ali1429.c ali1489.c ali1531.c ali1
intel_4x0.c intel_sio.c intel_piix.c ../ioapic.c neat.c opti283.c opti291.c opti391.c
opti495.c opti822.c opti895.c opti5x7.c scamp.c scat.c sis_85c310.c sis_85c4xx.c
sis_85c496.c sis_85c50x.c sis_5511.c sis_5571.c via_vt82c49x.c via_vt82c505.c sis_85c310.c
sis_85c4xx.c sis_85c496.c sis_85c50x.c gc100.c stpc.c via_apollo.c via_pipc.c vl82c480.c
wd76c10.c)
sis_85c4xx.c sis_85c496.c sis_85c50x.c gc100.c stpc.c umc_8886.c umc_hb4.c via_apollo.c
via_pipc.c vl82c480.c wd76c10.c)
if(I450KX)
target_sources(chipset PRIVATE intel_i450kx.c)

22
src/chipset/intel_piix.c
View File

@@ -1234,6 +1234,17 @@ piix_reset(void *p)
piix_write(3, 0x91, 0x00, p);
piix_write(3, 0xd2, 0x00, p);
}
sff_set_irq_mode(dev->bm[0], 0, 0);
sff_set_irq_mode(dev->bm[1], 0, 0);
if (dev->type >= 4) {
sff_set_irq_mode(dev->bm[0], 1, 0);
sff_set_irq_mode(dev->bm[1], 1, 0);
} else {
sff_set_irq_mode(dev->bm[0], 1, 2);
sff_set_irq_mode(dev->bm[1], 1, 2);
}
}
@@ -1286,6 +1297,17 @@ static void
ide_board_set_force_ata3(1, 1);
}
sff_set_irq_mode(dev->bm[0], 0, 0);
sff_set_irq_mode(dev->bm[1], 0, 0);
if (dev->type >= 4) {
sff_set_irq_mode(dev->bm[0], 1, 0);
sff_set_irq_mode(dev->bm[1], 1, 0);
} else {
sff_set_irq_mode(dev->bm[0], 1, 2);
sff_set_irq_mode(dev->bm[1], 1, 2);
}
if (dev->type >= 3)
dev->usb = device_add(&usb_device);

3
src/chipset/sis_85c50x.c
View File

@@ -107,8 +107,7 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev)
switch ((dev->pci_conf[0x65] & 0xe0) >> 5) {
case 0x00:
if (!(dev->pci_conf[0x54] & 0xc0))
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
break;
case 0x01:
smram_enable(dev->smram, 0xb0000, ram_base, 0x10000, (dev->pci_conf[0x65] & 0x10), 1);

219
src/chipset/umc_8886.c
View File

@@ -16,10 +16,11 @@
* Copyright 2021 Tiseno100.
*/
/* UMC 8886 Configuration Registers
/*
UMC 8886xx Configuration Registers
TODO:
- More Appropriate Bitmasking(If it's even possible)
Note: PMU functionality is quite basic. There may be Enable/Disable bits, IRQ/SMI picks and it also
required for 386_common.c to get patched in order to function properly.
Warning: Register documentation may be inaccurate!
@@ -35,10 +36,8 @@
Bits 3-0 PCI IRQ for INTC
Function 0 Register 46:
Bit 7: Replace SMI request for non-SMM CPU's (1: IRQ15/0: IRQ10)
Function 0 Register 51:
Bit 2: VGA Power Down (0: Standard/1: VESA DPMS)
Bit 7: PMU Trigger(1: By IRQ/0: By SMI)
Bit 6: IRQ SMI Request (1: IRQ 10) (Supposedly 0 according to Phoenix is IRQ 15 but doesn't seem to make sense)
Function 0 Register 56:
Bit 1-0 ISA Bus Speed
@@ -46,10 +45,14 @@
0 1 PCICLK/4
1 0 PCICLK/2
Function 0 Register A3:
Bit 7: Unlock SMM
Bit 6: Software SMI trigger
Function 0 Register A4:
Bit 0: Host to PCI Clock (1: 1 by 1/0: 1 by half)
Function 1 Register 4:
Function 1 Register 4: (UMC 8886AF/8886BF Only!)
Bit 0: Enable Internal IDE
*/
@@ -69,6 +72,7 @@
#include <86box/hdd.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/pic.h>
#include <86box/pci.h>
#include <86box/chipset.h>
@@ -76,16 +80,17 @@
#ifdef ENABLE_UMC_8886_LOG
int umc_8886_do_log = ENABLE_UMC_8886_LOG;
static void
umc_8886_log(const char *fmt, ...)
{
va_list ap;
if (umc_8886_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
if (umc_8886_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
@@ -94,23 +99,24 @@ umc_8886_log(const char *fmt, ...)
/* PCI IRQ Flags */
#define INTA (PCI_INTA + (2 * !(addr & 1)))
#define INTB (PCI_INTB + (2 * !(addr & 1)))
#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED)
#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED)
#define INTA (PCI_INTA + (2 * !(addr & 1)))
#define INTB (PCI_INTB + (2 * !(addr & 1)))
#define IRQRECALCA (((val & 0xf0) != 0) ? ((val & 0xf0) >> 4) : PCI_IRQ_DISABLED)
#define IRQRECALCB (((val & 0x0f) != 0) ? (val & 0x0f) : PCI_IRQ_DISABLED)
/* Disable Internal IDE Flag needed for the BF Southbridge variant */
#define HAS_IDE dev->has_ide
/* Disable Internal IDE Flag needed for the AF or BF Southbridge variant */
#define HAS_IDE dev->has_ide
/* Southbridge Revision */
#define SB_ID dev->sb_id
#define SB_ID dev->sb_id
typedef struct umc_8886_t
{
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
uint8_t pci_conf_sb[2][256]; /* PCI Registers */
uint16_t sb_id; /* Southbridge Revision */
int has_ide; /* Check if Southbridge Revision is AF or F */
} umc_8886_t;
@@ -121,39 +127,69 @@ umc_8886_ide_handler(int status)
ide_sec_disable();
if (status) {
ide_pri_enable();
ide_sec_enable();
ide_pri_enable();
ide_sec_enable();
}
}
static void
um8886_write(int func, int addr, uint8_t val, void *priv)
umc_8886_write(int func, int addr, uint8_t val, void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
umc_8886_log("UM8886: dev->regs[%02x] = %02x (%02x)\n", addr, val, func);
/* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
if (addr > 3) switch (func) {
case 0: /* Southbridge */
switch (func) {
case 0: /* PCI to ISA Bridge */
umc_8886_log("UM8886: dev->regs[%02x] = %02x POST %02x\n", addr, val, inb(0x80));
switch (addr) {
case 0x43:
case 0x44:
case 0x04: case 0x05:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x07:
dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
break;
case 0x0c: case 0x0d:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x40: case 0x41:
case 0x42:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x43: case 0x44:
dev->pci_conf_sb[func][addr] = val;
pci_set_irq_routing(INTA, IRQRECALCA);
pci_set_irq_routing(INTB, IRQRECALCB);
break;
case 0x45:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x46:
dev->pci_conf_sb[func][addr] = val & 0xaf;
dev->pci_conf_sb[func][addr] = val;
if (val & 0x40)
picint(1 << ((val & 0x80) ? 15 : 10));
break;
case 0x47:
dev->pci_conf_sb[func][addr] = val & 0x4f;
dev->pci_conf_sb[func][addr] = val;
break;
case 0x50: case 0x51: case 0x52: case 0x53:
case 0x54: case 0x55:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x56:
dev->pci_conf_sb[func][addr] = val;
switch (val & 2) {
case 0:
cpu_set_isa_pci_div(3);
@@ -165,51 +201,65 @@ um8886_write(int func, int addr, uint8_t val, void *priv)
cpu_set_isa_pci_div(2);
break;
}
break;
case 0x57:
dev->pci_conf_sb[func][addr] = val & 0x38;
case 0x70 ... 0x76:
case 0x80: case 0x81:
case 0x90 ... 0x92:
case 0xa0 ... 0xa2:
dev->pci_conf_sb[func][addr] = val;
break;
case 0x71:
dev->pci_conf_sb[func][addr] = val & 1;
break;
case 0xa3:
dev->pci_conf_sb[func][addr] = val;
case 0x90:
dev->pci_conf_sb[func][addr] = val & 2;
break;
/* SMI Provocation (Bit 7 Enable SMM + Bit 6 Software SMI */
if (((dev->pci_conf_sb[0][0xa3] >> 6) == 3) && !in_smm)
smi_line = 1;
case 0x92:
dev->pci_conf_sb[func][addr] = val & 0x1f;
break;
case 0xa0:
dev->pci_conf_sb[func][addr] = val & 0xfc;
break;
case 0xa4:
dev->pci_conf_sb[func][addr] = val & 0x89;
dev->pci_conf_sb[func][addr] = val;
cpu_set_pci_speed(cpu_busspeed / ((val & 1) ? 1 : 2));
break;
default:
case 0xa5 ... 0xa8:
dev->pci_conf_sb[func][addr] = val;
break;
}
break;
case 1: /* IDE Controller */
dev->pci_conf_sb[func][addr] = val;
if ((addr == 4) && HAS_IDE)
umc_8886_ide_handler(val & 1);
case 1: /* IDE Controller */
umc_8886_log("UM8886-IDE: dev->regs[%02x] = %02x POST: %02x\n", addr, val, inb(0x80));
switch (addr) {
case 0x04:
dev->pci_conf_sb[func][addr] = val;
umc_8886_ide_handler(val & 1);
break;
case 0x07:
dev->pci_conf_sb[func][addr] &= ~(val & 0xf9);
break;
case 0x3c:
case 0x40: case 0x41:
dev->pci_conf_sb[func][addr] = val;
break;
}
break;
}
}
static uint8_t
um8886_read(int func, int addr, void *priv)
umc_8886_read(int func, int addr, void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
return dev->pci_conf_sb[func][addr];
}
@@ -219,26 +269,51 @@ umc_8886_reset(void *priv)
{
umc_8886_t *dev = (umc_8886_t *)priv;
/* Defaults */
dev->pci_conf_sb[0][0] = 0x60; /* UMC */
dev->pci_conf_sb[0][0] = 0x60; /* UMC */
dev->pci_conf_sb[0][1] = 0x10;
dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */
dev->pci_conf_sb[0][2] = (SB_ID & 0xff); /* 8886xx */
dev->pci_conf_sb[0][3] = ((SB_ID >> 8) & 0xff);
dev->pci_conf_sb[0][8] = 1;
dev->pci_conf_sb[0][4] = 0x0f;
dev->pci_conf_sb[0][7] = 2;
dev->pci_conf_sb[0][8] = 0x0e;
dev->pci_conf_sb[0][0x09] = 0x00;
dev->pci_conf_sb[0][0x0a] = 0x01;
dev->pci_conf_sb[0][0x0b] = 0x06;
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
dev->pci_conf_sb[0][0x40] = 1;
dev->pci_conf_sb[0][0x41] = 6;
dev->pci_conf_sb[0][0x42] = 8;
dev->pci_conf_sb[0][0x43] = 0x9a;
dev->pci_conf_sb[0][0x44] = 0xbc;
dev->pci_conf_sb[0][0x45] = 4;
dev->pci_conf_sb[0][0x47] = 0x40;
dev->pci_conf_sb[0][0x50] = 1;
dev->pci_conf_sb[0][0x51] = 3;
dev->pci_conf_sb[0][0xa8] = 0x20;
if (HAS_IDE) {
dev->pci_conf_sb[1][0] = 0x60; /* UMC */
dev->pci_conf_sb[1][1] = 0x10;
dev->pci_conf_sb[1][2] = 0x3a; /* 8886BF IDE */
dev->pci_conf_sb[1][3] = 0x67;
dev->pci_conf_sb[1][4] = 1; /* Start with Internal IDE Enabled */
dev->pci_conf_sb[1][8] = 0x10;
dev->pci_conf_sb[1][0x09] = 0x0f;
dev->pci_conf_sb[1][0x0a] = dev->pci_conf_sb[1][0x0b] = 1;
umc_8886_ide_handler(1);
}
for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
pci_set_irq_routing(i, PCI_IRQ_DISABLED);
}
@@ -257,12 +332,12 @@ umc_8886_init(const device_t *info)
umc_8886_t *dev = (umc_8886_t *)malloc(sizeof(umc_8886_t));
memset(dev, 0, sizeof(umc_8886_t));
dev->has_ide = (info->local == 0x886a);
pci_add_card(PCI_ADD_SOUTHBRIDGE, um8886_read, um8886_write, dev); /* Device 12: UMC 8886xx */
dev->has_ide = !!(info->local == 0x886a);
pci_add_card(PCI_ADD_SOUTHBRIDGE, umc_8886_read, umc_8886_write, dev); /* Device 12: UMC 8886xx */
/* Add IDE if UM8886AF variant */
if (HAS_IDE)
device_add(&ide_pci_2ch_device);
device_add(&ide_pci_2ch_device);
/* Get the Southbridge Revision */
SB_ID = info->local;
@@ -277,24 +352,16 @@ const device_t umc_8886f_device = {
"UMC 8886F",
DEVICE_PCI,
0x8886,
umc_8886_init,
umc_8886_close,
umc_8886_reset,
{ NULL },
NULL,
NULL,
umc_8886_init, umc_8886_close, umc_8886_reset,
{ NULL }, NULL, NULL,
NULL
};
const device_t umc_8886af_device = {
"UMC 8886AF",
"UMC 8886AF/8886BF",
DEVICE_PCI,
0x886a,
umc_8886_init,
umc_8886_close,
umc_8886_reset,
{ NULL },
NULL,
NULL,
umc_8886_init, umc_8886_close, umc_8886_reset,
{ NULL }, NULL, NULL,
NULL
};

180
src/chipset/umc_8890.c
View File

@@ -1,180 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the UMC 8890 Chipset.
*
* Note: This chipset has no datasheet, everything were done via
* reverse engineering the BIOS of various machines using it.
*
*
* Authors: Tiseno100,
*
* Copyright 2021 Tiseno100.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
#include <86box/smram.h>
#include <86box/chipset.h>
#ifdef ENABLE_UMC_8890_LOG
int umc_8890_do_log = ENABLE_UMC_8890_LOG;
static void
umc_8890_log(const char *fmt, ...)
{
va_list ap;
if (umc_8890_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define umc_8890_log(fmt, ...)
#endif
/* Shadow RAM Flags */
#define ENABLE_SHADOW (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL)
#define DISABLE_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
typedef struct umc_8890_t
{
apm_t *apm;
smram_t *smram;
uint8_t pci_conf[256];
} umc_8890_t;
uint16_t umc_8890_shadow_flag(uint8_t flag)
{
return (flag & 1) ? (MEM_READ_INTERNAL | ((flag & 2) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
void umc_8890_shadow(umc_8890_t *dev)
{
mem_set_mem_state_both(0xe0000, 0x10000, umc_8890_shadow_flag((dev->pci_conf[0x5f] & 0x0c) >> 2));
mem_set_mem_state_both(0xf0000, 0x10000, umc_8890_shadow_flag((dev->pci_conf[0x5f] & 0xc0) >> 6));
for(int i = 0; i < 8; i++)
mem_set_mem_state_both(0xc0000 + (i << 14), 0x4000, umc_8890_shadow_flag(!!(dev->pci_conf[0x5d] & (1 << i))));
flushmmucache_nopc();
}
static void
um8890_write(int func, int addr, uint8_t val, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
dev->pci_conf[addr] = val;
switch (addr)
{
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f:
umc_8890_shadow(dev);
break;
case 0x65: /* We don't know the default SMRAM values */
smram_disable_all();
smram_enable(dev->smram, 0xe0000, 0xe0000, 0x10000, dev->pci_conf[0x65] & 0x10, 1);
flushmmucache_nopc();
break;
}
umc_8890_log("UM8890: dev->regs[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
}
static uint8_t
um8890_read(int func, int addr, void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
return dev->pci_conf[addr];
}
static void
umc_8890_reset(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
/* Defaults */
dev->pci_conf[0] = 0x60; /* UMC */
dev->pci_conf[1] = 0x10;
dev->pci_conf[2] = 0x91; /* 8891F */
dev->pci_conf[3] = 0x88;
dev->pci_conf[8] = 1;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
}
static void
umc_8890_close(void *priv)
{
umc_8890_t *dev = (umc_8890_t *)priv;
smram_del(dev->smram);
free(dev);
}
static void *
umc_8890_init(const device_t *info)
{
umc_8890_t *dev = (umc_8890_t *)malloc(sizeof(umc_8890_t));
memset(dev, 0, sizeof(umc_8890_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, um8890_read, um8890_write, dev); /* Device 0: UMC 8890 */
/* APM */
dev->apm = device_add(&apm_pci_device);
/* SMRAM(Needs excessive documentation before we begin SMM implementation) */
dev->smram = smram_add();
/* Port 92 */
device_add(&port_92_pci_device);
umc_8890_reset(dev);
return dev;
}
const device_t umc_8890_device = {
"UMC 8890(8891BF/8892BF)",
DEVICE_PCI,
0x886a,
umc_8890_init,
umc_8890_close,
umc_8890_reset,
{NULL},
NULL,
NULL,
NULL};

272
src/chipset/umc_hb4.c
View File

@@ -20,66 +20,72 @@
*/
/*
UMC HB4 Configuration Registers
UMC HB4 Configuration Registers
Sources & Notes:
Cache registers were found at Vogons: https://www.vogons.org/viewtopic.php?f=46&t=68829&start=20
Basic Reverse engineering effort was done personally by me
Sources & Notes:
Cache registers were found at Vogons: https://www.vogons.org/viewtopic.php?f=46&t=68829&start=20
Basic Reverse engineering effort was done personally by me
TODO:
- APM, SMM, SMRAM registers(Did some early work. Still quite incomplete)
- More Appropriate Bitmasking(If it's even possible)
Warning: Register documentation may be inaccurate!
Warning: Register documentation may be inaccurate!
UMC 8881x:
UMC 8881x:
Register 50:
Bit 7: Enable L2 Cache
Bit 6: Cache Policy (0: Write Thru / 1: Write Back)
Register 50:
Bit 7: Enable L2 Cache
Bit 6: Cache Policy (0: Write Thru / 1: Write Back)
Bit 5-4 Cache Speed
0 0 Read 3-2-2-2 Write 3T
0 1 Read 3-1-1-1 Write 3T
1 0 Read 2-2-2-2 Write 2T
1 1 Read 2-1-1-1 Write 2T
Bit 5-4 Cache Speed
0 0 Read 3-2-2-2 Write 3T
0 1 Read 3-1-1-1 Write 3T
1 0 Read 2-2-2-2 Write 2T
1 1 Read 2-1-1-1 Write 2T
Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
Bit 3 Cache Banks (0: 1 Bank / 1: 2 Banks)
Bit 2-1-0 Cache Size
0 0 0 0KB
0 0 1 64KB
x-x-x Multiplications of 2(64*2 for 0 1 0) till 2MB
Bit 2-1-0 Cache Size
0 0 0 0KB
0 0 1 64KB
x-x-x Multiplications of 2(64*2 for 0 1 0) till 2MB
Register 51:
Bit 7-6 DRAM Read Speed
5-4 DRAM Write Speed
0 0 1 Waits
0 1 1 Waits
1 0 1 Wait
1 1 0 Waits
Register 51:
Bit 7-6 DRAM Read Speed
5-4 DRAM Write Speed
0 0 1 Waits
0 1 1 Waits
1 0 1 Wait
1 1 0 Waits
Bit 3 Resource Lock Enable
Bit 2 Graphics Adapter (0: VL Bus / 1: PCI Bus)
Bit 1 L1 WB Policy (0: WT / 1: WB)
Bit 0 L2 Cache Tag Lenght (0: 7 Bits / 1: 8 Bits)
Bit 3 Resource Lock Enable
Bit 2 Graphics Adapter (0: VL Bus / 1: PCI Bus)
Bit 1 L1 WB Policy (0: WT / 1: WB)
Bit 0 L2 Cache Tag Lenght (0: 7 Bits / 1: 8 Bits)
Register 52:
Bit 7: Host-to-PCI Post Write (0: 1 Wait State / 1: 0 Wait States)
Register 52:
Bit 7: Host-to-PCI Post Write (0: 1 Wait State / 1: 0 Wait States)
Register 54:
Bit 7: DC000-DFFFF Read Enable
Bit 6: D8000-DBFFF Read Enable
Bit 5: D4000-D7FFF Read Enable
Bit 4: D0000-D3FFF Read Enable
Bit 3: CC000-CFFFF Read Enable
Bit 2: C8000-CBFFF Read Enable
Bit 1: C0000-C7FFF Read Enable
Bit 0: Enable C0000-DFFFF Shadow Segment Bits
Register 54:
Bit 7: DC000-DFFFF
Bit 6: D8000-DBFFF
Bit 5: D4000-D7FFF
Bit 4: D0000-D3FFF
Bit 3: CC000-CFFFF
Bit 2: C8000-CBFFF
Bit 1: C0000-C7FFF
Bit 0: Reserved
Register 55:
Bit 7: E0000-FFFF Read Enable
Bit 6: Shadow Write Status (1: Write Protect/0: Write)
Register 55:
Bit 7: Enable Shadow Reads For System & Selected Segments
Bit 6: Write Protect Enable
Register 56h & 57h: DRAM Bank 0 Configuration
Register 58h & 59h: DRAM Bank 1 Configuration
Register 60:
Bit 5-4: SMRAM Position(Lot's of uncertainty to those bits)
0 0 A0000 to E0000
1 0 A0000 to ????? (Phoenix uses it to no avail)
Bit 0: SMRAM Local Access Enable
*/
#include <stdarg.h>
@@ -95,7 +101,6 @@ Bit 6: Write Protect Enable
#include <86box/io.h>
#include <86box/device.h>
#include <86box/apm.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/port_92.h>
@@ -103,149 +108,192 @@ Bit 6: Write Protect Enable
#include <86box/chipset.h>
#ifdef ENABLE_HB4_LOG
int hb4_do_log = ENABLE_HB4_LOG;
static void
hb4_log(const char *fmt, ...)
{
va_list ap;
if (hb4_do_log)
{
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
if (hb4_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define hb4_log(fmt, ...)
#endif
/* Shadow RAM Flags */
#define CAN_READ ((dev->pci_conf[0x55] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY)
#define CAN_WRITE ((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL)
#define DISABLE (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
typedef struct hb4_t
{
apm_t *apm;
smram_t *smram;
uint8_t pci_conf[256]; /* PCI Registers */
uint8_t pci_conf[128]; /* PCI Registers */
smram_t *smram; /* SMRAM Handler */
} hb4_t;
void hb4_shadow(int cur_addr, hb4_t *dev)
{
mem_set_mem_state_both(0xc0000, 0x8000, (dev->pci_conf[0x54] & 2) ? (CAN_READ | CAN_WRITE) : DISABLE);
for (int i = 2; i < 8; i++)
mem_set_mem_state_both(0xc8000 + ((i - 2) << 14), 0x4000, (dev->pci_conf[0x54] & (1 << i)) ? (CAN_READ | CAN_WRITE) : DISABLE);
mem_set_mem_state_both(0xe0000, 0x20000, CAN_READ | CAN_WRITE);
flushmmucache_nopc();
void
hb4_shadow(hb4_t *dev)
{
mem_set_mem_state_both(0xe0000, 0x20000, ((dev->pci_conf[0x55] & 0x80) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) |
((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY : MEM_WRITE_INTERNAL));
if (dev->pci_conf[0x54] & 1) {
if (dev->pci_conf[0x54] & 2)
mem_set_mem_state_both(0xc0000, 0x8000, MEM_READ_INTERNAL | ((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY :MEM_WRITE_INTERNAL));
else
mem_set_mem_state_both(0xc0000, 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
for (int i = 0; i < 5; i++) {
if ((dev->pci_conf[0x54] >> i) & 4)
mem_set_mem_state_both(0xc8000 + (i << 14), 0x8000, MEM_READ_INTERNAL | ((dev->pci_conf[0x55] & 0x40) ? MEM_WRITE_EXTANY :MEM_WRITE_INTERNAL));
else
mem_set_mem_state_both(0xc8000 + (i << 14), 0x8000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
}
}
flushmmucache_nopc();
}
static void
um8881_write(int func, int addr, uint8_t val, void *priv)
hb4_smram(hb4_t *dev)
{
smram_disable_all();
smram_enable(dev->smram, 0x000a0000, 0x000a0000, 0x20000, dev->pci_conf[0x60] & 0x01, 1);
}
static void
hb4_write(int func, int addr, uint8_t val, void *priv)
{
hb4_t *dev = (hb4_t *)priv;
hb4_log("UM8881: dev->regs[%02x] = %02x\n", addr, val);
hb4_log("UM8881: dev->regs[%02x] = %02x POST: %02x \n", addr, val, inb(0x80));
if (addr > 3) /* We don't know the RW status of registers but Phoenix writes on some RO registers too*/
switch (addr) {
case 0x04: case 0x05:
dev->pci_conf[addr] = val;
break;
switch (addr)
{
case 0x50:
dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/
cpu_update_waitstates();
break;
case 0x07:
dev->pci_conf[addr] &= ~(val & 0xf9);
break;
case 0x54:
case 0x55:
dev->pci_conf[addr] = val & (!(addr & 1) ? 0xfe : 0xff);
hb4_shadow(addr, dev);
break;
case 0x0c: case 0x0d:
dev->pci_conf[addr] = val;
break;
case 0x60:
dev->pci_conf[addr] = val & 0x3f;
break;
case 0x50:
dev->pci_conf[addr] = ((val & 0xf8) | 4); /* Hardcode Cache Size to 512KB */
cpu_cache_ext_enabled = !!(val & 0x80); /* Fixes freezing issues on the HOT-433A*/
cpu_update_waitstates();
break;
case 0x61:
dev->pci_conf[addr] = val & 0x0f;
break;
case 0x51: case 0x52:
case 0x53:
dev->pci_conf[addr] = val;
break;
default:
dev->pci_conf[addr] = val;
break;
}
case 0x54: case 0x55:
dev->pci_conf[addr] = val;
hb4_shadow(dev);
break;
case 0x56 ... 0x5f:
dev->pci_conf[addr] = val;
break;
case 0x60:
dev->pci_conf[addr] = val;
hb4_smram(dev);
break;
case 0x61:
dev->pci_conf[addr] = val;
break;
}
}
static uint8_t
um8881_read(int func, int addr, void *priv)
hb4_read(int func, int addr, void *priv)
{
hb4_t *dev = (hb4_t *)priv;
return dev->pci_conf[addr];
}
static void
hb4_reset(void *priv)
{
hb4_t *dev = (hb4_t *)priv;
/* Defaults */
dev->pci_conf[0] = 0x60; /* UMC */
dev->pci_conf[1] = 0x10;
dev->pci_conf[2] = 0x81; /* 8881x */
dev->pci_conf[3] = 0x88;
dev->pci_conf[8] = 1;
dev->pci_conf[7] = 2;
dev->pci_conf[8] = 4;
dev->pci_conf[0x09] = 0x00;
dev->pci_conf[0x0a] = 0x00;
dev->pci_conf[0x0b] = 0x06;
dev->pci_conf[0x51] = 1;
dev->pci_conf[0x52] = 1;
dev->pci_conf[0x5a] = 4;
dev->pci_conf[0x5c] = 0xc0;
dev->pci_conf[0x5d] = 0x20;
dev->pci_conf[0x5f] = 0xff;
hb4_shadow(dev);
hb4_write(0, 0x60, 0x20, dev);
}
static void
hb4_close(void *priv)
{
hb4_t *dev = (hb4_t *)priv;
//smram_del(dev->smram);
free(dev);
}
static void *
hb4_init(const device_t *info)
{
hb4_t *dev = (hb4_t *)malloc(sizeof(hb4_t));
memset(dev, 0, sizeof(hb4_t));
pci_add_card(PCI_ADD_NORTHBRIDGE, um8881_read, um8881_write, dev); /* Device 10: UMC 8881x */
/* APM */
dev->apm = device_add(&apm_pci_device);
/* SMRAM(Needs excessive documentation before we begin SMM implementation) */
//dev->smram = smram_add();
pci_add_card(PCI_ADD_NORTHBRIDGE, hb4_read, hb4_write, dev); /* Device 10: UMC 8881x */
/* Port 92 */
device_add(&port_92_pci_device);
/* SMRAM */
dev->smram = smram_add();
hb4_reset(dev);
return dev;
}
const device_t umc_hb4_device = {
"UMC HB4(8881F)",
DEVICE_PCI,
0x886a,
hb4_init,
hb4_close,
hb4_reset,
{NULL},
NULL,
NULL,
NULL};
hb4_init, hb4_close, hb4_reset,
{ NULL }, NULL, NULL,
NULL
};

9
src/device/keyboard_at.c
View File

@@ -1184,7 +1184,7 @@ write_output(atkbd_t *dev, uint8_t val)
kbd_log("ATkbc: write output port: %02X (old: %02X)\n", val, dev->p2);
if (!(dev->flags & KBC_FLAG_PS2))
val |= ((dev->mem[0x20] << 4) & 0x30);
val |= ((dev->mem[0x20] << 4) & 0x10);
dev->kbd_inhibit = (val & 0x40);
dev->mouse_inhibit = (val & 0x08);
@@ -1211,6 +1211,7 @@ write_output(atkbd_t *dev, uint8_t val)
if ((dev->p2 ^ val) & 0x01) { /*Reset*/
if (! (val & 0x01)) {
/* Pin 0 selected. */
pclog("write_output(): Pulse reset!\n");
softresetx86(); /*Pulse reset!*/
cpu_set_edx();
smbase = is_am486dxl ? 0x00060000 : 0x00030000;
@@ -1503,10 +1504,8 @@ kbc_command(atkbd_t *dev)
case 0xd0: /* read output port */
kbd_log("ATkbc: read output port\n");
mask = 0xff;
if (dev->mem[0x20] & 0x10)
if (!(dev->flags & KBC_FLAG_PS2) && (dev->mem[0x20] & 0x10))
mask &= 0xbf;
if ((dev->flags & KBC_FLAG_PS2) && (dev->mem[0x20] & 0x20))
mask &= 0xf7;
kbc_transmit(dev, dev->p2 & mask);
break;
@@ -2885,7 +2884,7 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
dev->status &= ~STAT_IFULL;
kbc_send_to_ob(dev, 'H', 0, 0x00);
} */
kbc_process(dev);
// kbc_process(dev);
#endif
break;
}

5
src/include/86box/chipset.h
View File

@@ -124,6 +124,11 @@ extern const device_t stpc_atlas_device;
extern const device_t stpc_serial_device;
extern const device_t stpc_lpt_device;
/* UMC */
extern const device_t umc_8886f_device;
extern const device_t umc_8886af_device;
extern const device_t umc_hb4_device;
/* VIA */
extern const device_t via_vt82c49x_device;
extern const device_t via_vt82c49x_pci_device;

17
src/include/86box/machine.h
View File

@@ -284,6 +284,7 @@ extern int machine_at_sbc_350a_init(const machine_t *);
extern int machine_at_flytech386_init(const machine_t *);
extern int machine_at_mr1217_init(const machine_t *);
extern int machine_at_pja511m_init(const machine_t *);
extern int machine_at_prox1332_init(const machine_t *);
extern int machine_at_awardsx_init(const machine_t *);
@@ -369,12 +370,18 @@ extern int machine_at_arb1479_init(const machine_t *);
extern int machine_at_pcm9340_init(const machine_t *);
extern int machine_at_pcm5330_init(const machine_t *);
extern int machine_at_ecs486_init(const machine_t *);
extern int machine_at_hot433_init(const machine_t *);
extern int machine_at_atc1415_init(const machine_t *);
extern int machine_at_actionpc2600_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_acera1g_get_device(void);
extern const device_t *at_vect486vl_get_device(void);
extern const device_t *at_d824_get_device(void);
extern const device_t *at_pcs46c_get_device(void);
extern const device_t *at_valuepoint433_get_device(void);
extern const device_t *at_sbc_490_get_device(void);
#endif
/* m_at_commodore.c */
@@ -394,6 +401,7 @@ extern void machine_at_award_common_init(const machine_t *);
extern void machine_at_sp4_common_init(const machine_t *model);
extern int machine_at_excalibur_pci_init(const machine_t *);
extern int machine_at_p5mp3_init(const machine_t *);
extern int machine_at_dellxp60_init(const machine_t *);
extern int machine_at_opti560l_init(const machine_t *);
@@ -407,6 +415,7 @@ extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_p5vl_init(const machine_t *);
extern int machine_at_excalibur_pci_2_init(const machine_t *);
extern int machine_at_p5sp4_init(const machine_t *);
#ifdef EMU_DEVICE_H
@@ -462,6 +471,7 @@ extern int machine_at_ap5s_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_endeavor_get_device(void);
extern const device_t *at_thor_get_device(void);
#define at_mrthor_get_device at_thor_get_device
extern const device_t *at_pb640_get_device(void);
#endif
@@ -474,6 +484,7 @@ extern int machine_at_equium5200_init(const machine_t *);
extern int machine_at_pcv240_init(const machine_t *);
extern int machine_at_p65up5_cp55t2d_init(const machine_t *);
extern int machine_at_ap5vm_init(const machine_t *);
extern int machine_at_p55tvp4_init(const machine_t *);
extern int machine_at_5ivg_init(const machine_t *);
extern int machine_at_8500tvxa_init(const machine_t *);
@@ -504,6 +515,11 @@ extern int machine_at_ms5146_init(const machine_t *);
extern int machine_at_m560_init(const machine_t *);
extern int machine_at_ms5164_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t *at_presario2240_get_device(void);
#define at_presario4500_get_device at_presario2240_get_device
#endif
/* m_at_sockets7.c */
extern int machine_at_p5a_init(const machine_t *);
extern int machine_at_m579_init(const machine_t *);
@@ -513,6 +529,7 @@ extern int machine_at_ga_5ax_init(const machine_t *);
extern int machine_at_ax59pro_init(const machine_t *);
extern int machine_at_mvp3_init(const machine_t *);
extern int machine_at_ficva503a_init(const machine_t *);
extern int machine_at_sy_5ema_pro_init(const machine_t *);
/* m_at_socket8.c */
#if defined(DEV_BRANCH) && defined(USE_I450KX)

2
src/include/86box/pci.h
View File

@@ -52,6 +52,8 @@
#define PCI_IRQ_DISABLED -1
#define PCI_ADD_STRICT 0x80
enum {
PCI_CARD_NORTHBRIDGE = 0,
PCI_CARD_AGPBRIDGE,

3
src/include/86box/video.h
View File

@@ -167,6 +167,7 @@ extern void updatewindowsize(int x, int y);
extern void video_init(void);
extern void video_close(void);
extern void video_reset_close(void);
extern void video_pre_reset(int card);
extern void video_reset(int card);
extern uint8_t video_force_resize_get(void);
extern void video_force_resize_set(uint8_t res);
@@ -357,6 +358,7 @@ extern const device_t s3_elsa_winner2000_pro_x_964_vlb_device;
extern const device_t s3_elsa_winner2000_pro_x_pci_device;
extern const device_t s3_elsa_winner2000_pro_x_vlb_device;
extern const device_t s3_trio64v2_dx_pci_device;
extern const device_t s3_trio64v2_dx_onboard_pci_device;
/* S3 ViRGE */
extern const device_t s3_virge_325_vlb_device;
@@ -380,6 +382,7 @@ extern const device_t sigma_device;
extern const device_t tgui9400cxi_device;
extern const device_t tgui9440_vlb_device;
extern const device_t tgui9440_pci_device;
extern const device_t tgui9440_onboard_pci_device;
extern const device_t tgui9660_pci_device;
extern const device_t tgui9680_pci_device;

6
src/io.c
View File

@@ -315,6 +315,10 @@ inb(uint16_t port)
if (!found)
cycles -= io_delay;
/* TriGem 486-BIOS MHz output. */
if (port == 0x1ed)
ret = 0xfe;
io_log("[%04X:%08X] (%i, %i, %04i) in b(%04X) = %02X\n", CS, cpu_state.pc, in_smm, found, qfound, port, ret);
return(ret);
@@ -338,7 +342,7 @@ outb(uint16_t port, uint8_t val)
}
p = q;
}
if (!found) {
cycles -= io_delay;
#ifdef USE_DYNAREC

54
src/machine/m_at_286_386sx.c
View File

@@ -120,11 +120,11 @@ machine_at_ama932j_init(const machine_t *model)
machine_at_common_ide_init(model);
machine_at_headland_common_init(1);
if (gfxcard == VID_INTERNAL)
device_add(&oti067_ama932j_device);
machine_at_headland_common_init(1);
return ret;
}
@@ -439,14 +439,14 @@ machine_at_spc4620p_init(const machine_t *model)
if (bios_only || !ret)
return ret;
if (gfxcard == VID_INTERNAL)
device_add(&ati28800k_spc4620p_device);
machine_at_scat_init(model, 1);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
if (gfxcard == VID_INTERNAL)
device_add(&ati28800k_spc4620p_device);
return ret;
}
@@ -550,13 +550,13 @@ machine_at_wd76c10_init(const machine_t *model)
machine_at_common_init(model);
if (gfxcard == VID_INTERNAL)
device_add(&paradise_wd90c11_megapc_device);
device_add(&keyboard_ps2_quadtel_device);
device_add(&wd76c10_device);
if (gfxcard == VID_INTERNAL)
device_add(&paradise_wd90c11_megapc_device);
return ret;
}
@@ -621,11 +621,11 @@ machine_at_cmdsl386sx25_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_scamp_common_init(model);
if (gfxcard == VID_INTERNAL)
device_add(&gd5402_onboard_device);
machine_at_scamp_common_init(model);
return ret;
}
@@ -648,11 +648,11 @@ machine_at_spc6033p_init(const machine_t *model)
if (bios_only || !ret)
return ret;
machine_at_scamp_common_init(model);
if (gfxcard == VID_INTERNAL)
device_add(&ati28800k_spc6033p_device);
machine_at_scamp_common_init(model);
return ret;
}
@@ -736,11 +736,12 @@ machine_at_flytech386_init(const machine_t *model)
device_add(&ali1217_device);
device_add(&w83787f_ide_en_device);
device_add(&keyboard_ps2_device);
if (gfxcard == VID_INTERNAL)
device_add(&tvga8900d_device);
device_add(&keyboard_ps2_device);
return ret;
}
@@ -788,7 +789,29 @@ machine_at_pja511m_init(const machine_t *model)
machine_at_common_init(model);
device_add_inst(&fdc37c669_device, 1);
//device_add_inst(&fdc37c669_device, 2); /* enable when dual FDC37C669 is implemented */
device_add_inst(&fdc37c669_device, 2);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ali6117d_device);
device_add(&sst_flash_29ee010_device);
return ret;
}
int
machine_at_prox1332_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/prox1332/D30B3AC1.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&fdc37c669_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ali6117d_device);
device_add(&sst_flash_29ee010_device);
@@ -845,13 +868,14 @@ machine_at_3302_init(const machine_t *model)
machine_at_common_ide_init(model);
device_add(&neat_device);
device_add(&keyboard_at_ncr_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
if (gfxcard == VID_INTERNAL)
device_add(&paradise_pvga1a_ncr3302_device);
device_add(&keyboard_at_ncr_device);
return ret;
}

164
src/machine/m_at_386dx_486.c
View File

@@ -175,23 +175,25 @@ machine_at_valuepoint433_init(const machine_t *model) // hangs without the PS/2
machine_at_common_ide_init(model);
device_add(&sis_85c461_device);
device_add(&keyboard_ps2_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
if (gfxcard == VID_INTERNAL)
device_add(&et4000w32_onboard_device);
device_add(&keyboard_ps2_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
const device_t *
at_valuepoint433_get_device(void)
{
return &et4000w32_onboard_device;
}
int
machine_at_ecs386_init(const machine_t *model)
{
@@ -346,15 +348,16 @@ machine_at_vect486vl_init(const machine_t *model) // has HDC problems
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
machine_at_common_ide_init(model);
device_add(&vl82c480_device);
device_add(&keyboard_ps2_ami_device);
device_add(&fdc37c651_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&keyboard_ps2_ami_device);
device_add(&fdc37c651_ide_device);
return ret;
}
@@ -379,12 +382,13 @@ machine_at_d824_init(const machine_t *model)
machine_at_common_init(model);
device_add(&vl82c480_device);
device_add(&keyboard_ps2_device);
device_add(&fdc37c651_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&keyboard_ps2_device);
device_add(&fdc37c651_device);
return ret;
}
@@ -408,11 +412,11 @@ machine_at_acera1g_init(const machine_t *model)
return ret;
machine_at_common_init(model);
device_add(&ali1429_device);
if (gfxcard == VID_INTERNAL)
device_add(&gd5428_onboard_device);
device_add(&ali1429_device);
device_add(&keyboard_ps2_acer_pci_device);
device_add(&ide_isa_2ch_device);
@@ -1364,14 +1368,18 @@ machine_at_sbc_490_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_VIDEO, 4, 1, 2, 3);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x01, PCI_CARD_VIDEO, 4, 1, 2, 3);
device_add(&ali1489_device);
device_add(&fdc37c665_device);
if (gfxcard == VID_INTERNAL)
device_add(&tgui9440_onboard_pci_device);
device_add(&keyboard_ps2_ami_device);
device_add(&sst_flash_29ee010_device);
@@ -1379,6 +1387,13 @@ machine_at_sbc_490_init(const machine_t *model)
}
const device_t *
at_sbc_490_get_device(void)
{
return &tgui9440_onboard_pci_device;
}
int
machine_at_tf_486_init(const machine_t *model)
{
@@ -1519,3 +1534,128 @@ machine_at_pcm5330_init(const machine_t *model)
return ret;
}
int
machine_at_ecs486_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ecs486/8810AIO.32J",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0f, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886f_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&fdc37c665_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_hot433_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/hot433/433AUS33.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0f, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_at_ami_device);
return ret;
}
int
machine_at_atc1415_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/atc1415/1415V330.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x14, PCI_CARD_NORMAL, 3, 4, 1, 2);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_actionpc2600_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/actionpc2600/action2600.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x10, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x12, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x0c, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0d, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0e, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0f, PCI_CARD_NORMAL, 2, 3, 4, 1);
device_add(&umc_hb4_device);
device_add(&umc_8886af_device);
device_add(&um8669f_device);
device_add(&intel_flash_bxt_device);
device_add(&keyboard_at_ami_device);
return ret;
}

4
src/machine/m_at_compaq.c
View File

@@ -810,8 +810,6 @@ at_cpqiii_get_device(void)
static void
machine_at_compaq_init(const machine_t *model, int type)
{
machine_at_init(model);
if (type != COMPAQ_DESKPRO386)
mem_remap_top(384);
@@ -846,6 +844,8 @@ machine_at_compaq_init(const machine_t *model, int type)
device_add(&ide_isa_device);
break;
}
machine_at_init(model);
}

7
src/machine/m_at_slot1.c
View File

@@ -645,13 +645,14 @@ machine_at_ms6168_common_init(const machine_t *model)
device_add(&i440zx_device);
device_add(&piix4e_device);
device_add(&w83977ef_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
if (gfxcard == VID_INTERNAL)
device_add(&voodoo_3_2000_agp_onboard_8m_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&intel_flash_bxt_device);
spd_register(SPD_TYPE_SDRAM, 0x3, 256);
if (sound_card_current == SOUND_INTERNAL) {
device_add(&es1371_onboard_device);
device_add(&cs4297_device);

65
src/machine/m_at_socket4.c
View File

@@ -111,6 +111,38 @@ machine_at_sp4_common_init(const machine_t *model)
}
int
machine_at_excalibur_pci_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excalibur_pci/S701P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_2);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x03, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x02, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&i430lx_device);
device_add(&sio_zb_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p5mp3_init(const machine_t *model)
{
@@ -331,6 +363,7 @@ machine_at_pb520r_init(const machine_t *model)
return ret;
}
const device_t *
at_pb520r_get_device(void)
{
@@ -389,6 +422,38 @@ machine_at_p5vl_init(const machine_t *model)
}
int
machine_at_excalibur_pci_2_init(const machine_t *model)
{
int ret;
ret = bios_load_linear_inverted("roms/machines/excalibur_pci-2/S722P.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x01, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x08, PCI_CARD_IDE, 0, 0, 0, 0);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&fdc37c665_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&ide_cmd640_pci_legacy_only_device);
device_add(&sis_85c50x_device);
device_add(&intel_flash_bxt_ami_device);
return ret;
}
int
machine_at_p5sp4_init(const machine_t *model)
{

64
src/machine/m_at_socket7.c
View File

@@ -44,6 +44,7 @@
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/nvr.h>
#include <86box/scsi_ncr53c8xx.h>
int
@@ -78,6 +79,41 @@ machine_at_acerv35n_init(const machine_t *model)
}
int
machine_at_ap5vm_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/ap5vm/AP5V270.ROM",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
/* It seems there were plans for an on-board NCR 53C810 according to some clues
left in the manual, but were latter scrapped. The BIOS still support that
PCI device, though, so why not. */
pci_register_slot(0x06, PCI_CARD_SCSI, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
device_add(&fdc37c665_device);
device_add(&ncr53c810_onboard_pci_device);
device_add(&intel_flash_bxt_device);
return ret;
}
int
machine_at_p55t2p4_init(const machine_t *model)
{
@@ -366,9 +402,12 @@ machine_at_presario2240_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_SOUND, 3, 0, 0, 0);
pci_register_slot(0x14, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
if (gfxcard == VID_INTERNAL)
device_add(&s3_trio64v2_dx_onboard_pci_device);
device_add(&i430vx_device);
device_add(&piix3_device);
device_add(&keyboard_ps2_ami_pci_device);
@@ -379,6 +418,13 @@ machine_at_presario2240_init(const machine_t *model)
}
const device_t *
at_presario2240_get_device(void)
{
return &s3_trio64v2_dx_onboard_pci_device;
}
int
machine_at_presario4500_init(const machine_t *model)
{
@@ -395,8 +441,11 @@ machine_at_presario4500_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x14, PCI_CARD_VIDEO, 3, 0, 0, 0);
pci_register_slot(0x13, PCI_CARD_NORMAL, 1, 2, 3, 4);
if (gfxcard == VID_INTERNAL)
device_add(&s3_trio64v2_dx_onboard_pci_device);
device_add(&i430vx_device);
device_add(&piix3_device);
@@ -646,12 +695,21 @@ machine_at_an430tx_init(const machine_t *model)
{
int ret;
#if 1
ret = bios_load_linear_combined2("roms/machines/an430tx/P10-0095.BIO",
"roms/machines/an430tx/P10-0095.BI1",
"roms/machines/an430tx/P10-0095.BI2",
"roms/machines/an430tx/P10-0095.BI3",
"roms/machines/an430tx/P10-0095.RCV",
0x3a000, 160);
#else
ret = bios_load_linear_combined2("roms/machines/an430tx/P06-0062.BIO",
"roms/machines/an430tx/P06-0062.BI1",
"roms/machines/an430tx/P06-0062.BI2",
"roms/machines/an430tx/P06-0062.BI3",
"roms/machines/an430tx/P10-0095.RCV",
0x3a000, 160);
#endif
if (bios_only || !ret)
return ret;
@@ -661,7 +719,7 @@ machine_at_an430tx_init(const machine_t *model)
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 1, 2, 3, 4); /* PIIX4 */
pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
// pci_register_slot(0x08, PCI_CARD_VIDEO, 4, 0, 0, 0);
pci_register_slot(0x0D, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x0E, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);

10
src/machine/m_at_socket7_3v.c
View File

@@ -60,6 +60,9 @@ machine_at_thor_common_init(const machine_t *model, int mr)
pci_register_slot(0x10, PCI_CARD_NORMAL, 4, 3, 2, 1);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 0, 0);
if (gfxcard == VID_INTERNAL)
device_add(&s3_phoenix_trio64vplus_onboard_pci_device);
// device_add(&keyboard_ps2_ami_pci_device);
device_add(&keyboard_ps2_intel_ami_pci_device);
device_add(&i430fx_device);
@@ -165,6 +168,13 @@ machine_at_thor_init(const machine_t *model)
}
const device_t *
at_thor_get_device(void)
{
return &s3_phoenix_trio64vplus_onboard_pci_device;
}
int
machine_at_mrthor_init(const machine_t *model)
{

41
src/machine/m_at_sockets7.c
View File

@@ -284,3 +284,44 @@ machine_at_ficva503a_init(const machine_t *model)
return ret;
}
int
machine_at_sy_5ema_pro_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/sy-5ema_pro/5emo1aa2.bin",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
pci_register_slot(0x00, PCI_CARD_NORTHBRIDGE, 0, 0, 0, 0);
pci_register_slot(0x07, PCI_CARD_SOUTHBRIDGE, 0, 0, 3, 4);
pci_register_slot(0x08, PCI_CARD_NORMAL, 1, 2, 3, 4);
pci_register_slot(0x09, PCI_CARD_NORMAL, 2, 3, 4, 1);
pci_register_slot(0x0A, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x0B, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x0C, PCI_CARD_NORMAL, 4, 1, 2, 3);
pci_register_slot(0x01, PCI_CARD_AGPBRIDGE, 1, 2, 3, 4);
device_add(&via_mvp3_device);
device_add(&via_vt82c686a_device);
device_add(&keyboard_ps2_ami_pci_device);
// device_add(&via_vt82c686_sio_device);
device_add(&fdc37c669_device);
device_add(&sst_flash_39sf010_device);
spd_register(SPD_TYPE_SDRAM, 0x7, 256);
device_add(&via_vt82c686_hwm_device); /* fans: CPU1, Chassis; temperatures: CPU, System, unused */
hwm_values.temperatures[0] += 2; /* CPU offset */
hwm_values.temperatures[1] += 2; /* System offset */
hwm_values.temperatures[2] = 0; /* unused */
device_add(&wm9701a_device); /* on daughtercard */
return ret;
}

4
src/machine/machine.c
View File

@@ -97,6 +97,10 @@ machine_init_ex(int m)
device_add(&cassette_device);
cart_reset();
/* Prepare some video-related things if we're using internal
or no video. */
video_pre_reset(gfxcard);
}
/* All good, boot the machine! */

37
src/machine/machine_table.c
View File

@@ -252,6 +252,8 @@ const machine_t machines[] = {
{ "[ALi M1217] MR 386SX clone", "mr1217", MACHINE_TYPE_386SX, CPU_PKG_386SX, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE | MACHINE_VIDEO, 1024, 16384, 1024, 127, machine_at_mr1217_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ALi M6117] Acrosser PJ-A511M", "pja511m", MACHINE_TYPE_386SX, CPU_PKG_M6117, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 32768,1024, 127, machine_at_pja511m_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
{ "[ALi M6117C] Protech ProX-1332", "prox1332", MACHINE_TYPE_386SX, CPU_PKG_M6117, 0, 0, 0, 0, 0, 0, 0, MACHINE_AT | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 32768,1024, 127, machine_at_prox1332_init, NULL },
/* Has an AMI KBC firmware, the only photo of this is too low resolution
for me to read what's on the KBC chip, so I'm going to assume AMI 'F'
based on the other known HT18 AMI BIOS strings. */
@@ -398,7 +400,7 @@ const machine_t machines[] = {
/* 486 machines which utilize the PCI bus */
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[ALi M1489] AAEON SBC-490", "sbc-490", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_sbc_490_init, NULL },
{ "[ALi M1489] AAEON SBC-490", "sbc-490", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 1024, 65536, 1024, 255, machine_at_sbc_490_init, at_sbc_490_get_device },
/* Has the ALi M1487/9's on-chip keyboard controller which clones a standard AT
KBC. */
{ "[ALi M1489] ABIT AB-PB4", "abpb4", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_abpb4_init, NULL },
@@ -443,6 +445,14 @@ const machine_t machines[] = {
/* According to MrKsoft, his real 4DPS has an AMIKey-2, which is an updated version
of type 'H'. */
{ "[SiS 496] Zida Tomato 4DP", "4dps", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_4dps_init, NULL },
/* This has the UMC 88xx on-chip KBC. */
{ "[UMC 8881] A-Trend ATC-1415", "atc1415", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_atc1415_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[UMC 8881] ECS Elite UM8810PAIO", "ecs486", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ecs486_init, NULL },
/* Has AMIKey Z(!) KBC firmware. */
{ "[UMC 8881] Epson Action PC 2600", "actionpc2600", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 262144, 1024, 255, machine_at_actionpc2600_init, NULL },
/* This has a Holtek KBC. */
{ "[UMC 8881] Shuttle HOT-433A", "hot433", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 262144, 1024, 255, machine_at_hot433_init, NULL },
/* Has a VIA VT82C406 KBC+RTC that likely has identical commands to the VT82C42N. */
{ "[VIA VT82C496G] DFI G486VPA", "g486vpa", MACHINE_TYPE_486_S3, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_g486vpa_init, NULL },
/* Has a VIA VT82C42N KBC. */
@@ -465,6 +475,12 @@ const machine_t machines[] = {
/* Socket 4 machines */
/* 430LX */
/* Has AMIKey H KBC firmware (AMIKey-2), per POST screen with BIOS string
shown in the manual. Has PS/2 mouse support with serial-style (DB9)
connector.
The boot block for BIOS recovery requires an unknown bit on port 805h
to be clear. */
{ "[i430LX] AMI Excalibur PCI Pentium", "excalibur_pci", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_excalibur_pci_init, NULL },
/* Has AMIKey F KBC firmware (AMIKey). */
{ "[i430LX] ASUS P/I-P5MP3", "p5mp3", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 2048, 196608, 2048, 127, machine_at_p5mp3_init, NULL },
/* Has IBM PS/2 Type 1 KBC firmware. */
@@ -494,9 +510,11 @@ const machine_t machines[] = {
/* This has AMIKey 'F' KBC firmware. */
{ "[OPTi 597] Supermicro P5VL-PCI", "p5vl", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_p5vl_init, NULL },
/* SiS 85C50x */
/* SiS 50x */
/* This has an unknown AMI KBC firmware, most likely AMIKey / type 'F'. */
{ "[SiS 50x] AMI Excalibur PCI-II Pentium ISA","excalibur_pci-2", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_excalibur_pci_2_init, NULL },
/* This has an AMIKey-2, which is an updated version of type 'H'. */
{ "[SiS 85C50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
{ "[SiS 50x] ASUS PCI/I-P5SP4", "p5sp4", MACHINE_TYPE_SOCKET4, CPU_PKG_SOCKET4, 0, 60000000, 66666667, 5000, 5000, MACHINE_MULTIPLIER_FIXED, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p5sp4_init, NULL },
/* Socket 5 machines */
/* 430NX */
@@ -557,11 +575,11 @@ const machine_t machines[] = {
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/ATX", "thor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_thor_init, NULL },
{ "[i430FX] Intel Advanced/ATX", "thor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_thor_init, at_thor_get_device },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_mrthor_init, NULL },
{ "[i430FX] Intel Advanced/ATX (MR BIOS)", "mrthor", MACHINE_TYPE_SOCKET7_3V, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_mrthor_init, at_mrthor_get_device },
/* According to tests from real hardware: This has AMI MegaKey KBC firmware on the
PC87306 Super I/O chip, command 0xA1 returns '5'.
Command 0xA0 copyright string: (C)1994 AMI . */
@@ -624,6 +642,8 @@ const machine_t machines[] = {
{ "[i430HX] ASUS P/I-P65UP5 (C-P55T2D)", "p65up5_cp55t2d", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 524288, 8192, 127, machine_at_p65up5_cp55t2d_init, NULL },
/* 430VX */
/* This has the VIA VT82C42N KBC. */
{ "[i430VX] AOpen AP5VM", "ap5vm", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_SCSI, 8192, 131072, 8192, 127, machine_at_ap5vm_init, NULL },
/* Has AMIKey H KBC firmware (AMIKey-2). */
{ "[i430VX] ASUS P/I-P55TVP4", "p55tvp4", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55tvp4_init, NULL },
/* The BIOS does not send a single non-standard KBC command, so it must have a standard IBM
@@ -633,9 +653,9 @@ const machine_t machines[] = {
{ "[i430VX] Biostar MB-8500TVX-A", "8500tvxa", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2600, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_8500tvxa_init, NULL },
/* The BIOS does not send a single non-standard KBC command, but the board has a SMC Super I/O
chip with on-chip KBC and AMI MegaKey KBC firmware. */
{ "[i430VX] Compaq Presario 2240", "presario2240", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario2240_init, NULL },
{ "[i430VX] Compaq Presario 2240", "presario2240", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario2240_init, at_presario2240_get_device },
/* This most likely has AMI MegaKey as above. */
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, NULL },
{ "[i430VX] Compaq Presario 4500", "presario4500", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2800, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL | MACHINE_VIDEO, 8192, 131072, 8192, 127, machine_at_presario4500_init, at_presario4500_get_device },
/* The BIOS sends KBC command CB which is an AMI KBC command, so it has an AMI KBC firmware. */
{ "[i430VX] Epox P55-VA", "p55va", MACHINE_TYPE_SOCKET7, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 2500, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_p55va_init, NULL },
/* The BIOS does not send a single non-standard KBC command. */
@@ -711,6 +731,9 @@ const machine_t machines[] = {
/* Has the VIA VT82C686A southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA MVP3] FIC VA-503A", "ficva503a", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 1800, 3100, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_ficva503a_init, NULL },
/* Has the VIA VT82C686A southbridge with on-chip KBC identical to the VIA
VT82C42N. */
{ "[VIA MVP3] Soyo SY-5EMA Pro", "sy-5ema_pro", MACHINE_TYPE_SOCKETS7, CPU_PKG_SOCKET5_7, 0, 66666667, 124242424, 1800, 3100, 1.5, 5.5, MACHINE_AGP | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 786432, 8192, 255, machine_at_sy_5ema_pro_init, NULL },
/* Socket 8 machines */
/* 450KX */

15
src/pci.c
View File

@@ -888,10 +888,17 @@ pci_find_slot(uint8_t add_type, uint8_t ignore_slot)
dev = &pci_cards[i];
if (!dev->read && !dev->write && ((ignore_slot == 0xff) || (i != ignore_slot))) {
if (((dev->type == PCI_CARD_NORMAL) && (add_type >= PCI_ADD_NORMAL)) ||
(dev->type == add_type)) {
ret = i;
break;
if (add_type & PCI_ADD_STRICT) {
if (dev->type == (add_type & 0x7f)) {
ret = i;
break;
}
} else {
if (((dev->type == PCI_CARD_NORMAL) && ((add_type & 0x7f) >= PCI_ADD_NORMAL)) ||
(dev->type == (add_type & 0x7f))) {
ret = i;
break;
}
}
}
}

17
src/port_92.c
View File

@@ -64,7 +64,13 @@ port_92_readb(uint16_t port, void *priv)
static uint16_t
port_92_readw(uint16_t port, void *priv)
{
return port_92_readb(port, priv);
uint16_t ret = 0xffff;
port_92_t *dev = (port_92_t *) priv;
if (!(dev->flags & PORT_92_PCI))
ret = port_92_readb(port, priv);
return ret;
}
@@ -106,7 +112,10 @@ port_92_writeb(uint16_t port, uint8_t val, void *priv)
static void
port_92_writew(uint16_t port, uint16_t val, void *priv)
{
port_92_writeb(port, val & 0xff, priv);
port_92_t *dev = (port_92_t *) priv;
if (!(dev->flags & PORT_92_PCI))
port_92_writeb(port, val & 0xff, priv);
}
@@ -146,7 +155,7 @@ port_92_add(void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (dev->flags & PORT_92_WORD)
if (dev->flags & (PORT_92_WORD | PORT_92_PCI))
io_sethandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
else
@@ -160,7 +169,7 @@ port_92_remove(void *priv)
{
port_92_t *dev = (port_92_t *) priv;
if (dev->flags & PORT_92_WORD)
if (dev->flags & (PORT_92_WORD | PORT_92_PCI))
io_removehandler(0x0092, 2,
port_92_readb, port_92_readw, NULL, port_92_writeb, port_92_writew, NULL, dev);
else

4
src/sio/CMakeLists.txt
View File

@@ -13,8 +13,8 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(sio OBJECT sio_acc3221.c sio_f82c710.c sio_82091aa.c sio_fdc37c651.c sio_fdc37c661.c
sio_fdc37c66x.c sio_fdc37c67x.c sio_fdc37c669.c sio_fdc37c93x.c sio_fdc37m60x.c
add_library(sio OBJECT sio_acc3221.c sio_f82c710.c sio_82091aa.c sio_fdc37c6xx.c
sio_fdc37c67x.c sio_fdc37c669.c sio_fdc37c93x.c sio_fdc37m60x.c
sio_it8661f.c
sio_pc87306.c sio_pc87307.c sio_pc87309.c sio_pc87310.c sio_pc87311.c sio_pc87332.c
sio_prime3b.c sio_prime3c.c

314
src/sio/sio_fdc37c651.c
View File

@@ -1,314 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C651 Super I/O Chip.
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2021 Miran Grca.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
#ifdef ENABLE_FDC37C651_LOG
int fdc37c651_do_log = ENABLE_FDC37C651_LOG;
static void
fdc37c651_log(const char *fmt, ...)
{
va_list ap;
if (fdc37c651_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define fdc37c651_log(fmt, ...)
#endif
typedef struct {
uint8_t tries, has_ide,
regs[16];
int cur_reg,
com3_addr, com4_addr;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c651_t;
static void
set_com34_addr(fdc37c651_t *dev)
{
switch (dev->regs[1] & 0x60) {
case 0x00:
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
break;
case 0x20:
dev->com3_addr = 0x3e8;
dev->com4_addr = 0x2e8;
break;
case 0x40:
dev->com3_addr = 0x3e8;
dev->com4_addr = 0x2e0;
break;
case 0x60:
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
}
}
static void
set_serial_addr(fdc37c651_t *dev, int port)
{
uint8_t shift = (port << 2);
serial_remove(dev->uart[port]);
if (dev->regs[2] & (4 << shift)) {
switch ((dev->regs[2] >> shift) & 3) {
case 0:
serial_setup(dev->uart[port], SERIAL1_ADDR, SERIAL1_IRQ);
break;
case 1:
serial_setup(dev->uart[port], SERIAL2_ADDR, SERIAL2_IRQ);
break;
case 2:
serial_setup(dev->uart[port], dev->com3_addr, 4);
break;
case 3:
serial_setup(dev->uart[port], dev->com4_addr, 3);
break;
}
}
}
static void
lpt1_handler(fdc37c651_t *dev)
{
lpt1_remove();
switch (dev->regs[1] & 3) {
case 1:
lpt1_init(0x3bc);
lpt1_irq(7);
break;
case 2:
lpt1_init(0x378);
lpt1_irq(7 /*5*/);
break;
case 3:
lpt1_init(0x278);
lpt1_irq(7 /*5*/);
break;
}
}
static void
fdc_handler(fdc37c651_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0] & 0x10)
fdc_set_base(dev->fdc, 0x03f0);
}
static void
ide_handler(fdc37c651_t *dev)
{
/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
if (dev->has_ide == 2) {
ide_sec_disable();
ide_set_base(1, 0x1f0);
ide_set_side(1, 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_sec_enable();
} else if (dev->has_ide == 1) {
ide_pri_disable();
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_pri_enable();
}
}
static void
fdc37c651_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c651_t *dev = (fdc37c651_t *) priv;
uint8_t valxor = 0;
if (dev->tries == 2) {
if (port == 0x3f0) {
if (val == 0xaa)
dev->tries = 0;
else
dev->cur_reg = val;
} else {
if (dev->cur_reg > 15)
return;
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
switch(dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
if (valxor & 0x10)
fdc_handler(dev);
break;
case 1:
if (valxor & 3)
lpt1_handler(dev);
if (valxor & 0x60) {
set_com34_addr(dev);
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
}
break;
case 2:
if (valxor & 7)
set_serial_addr(dev, 0);
if (valxor & 0x70)
set_serial_addr(dev, 1);
break;
}
}
} else if ((port == 0x3f0) && (val == 0x55))
dev->tries++;
}
static uint8_t
fdc37c651_read(uint16_t port, void *priv)
{
fdc37c651_t *dev = (fdc37c651_t *) priv;
uint8_t ret = 0x00;
if (dev->tries == 2) {
if (port == 0x3f1)
ret = dev->regs[dev->cur_reg];
}
return ret;
}
static void
fdc37c651_reset(fdc37c651_t *dev)
{
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
lpt1_remove();
lpt1_init(0x378);
fdc_reset(dev->fdc);
fdc_remove(dev->fdc);
dev->tries = 0;
memset(dev->regs, 0, 16);
dev->regs[0x0] = 0x3f;
dev->regs[0x1] = 0x9f;
dev->regs[0x2] = 0xdc;
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
lpt1_handler(dev);
fdc_handler(dev);
if (dev->has_ide)
ide_handler(dev);
}
static void
fdc37c651_close(void *priv)
{
fdc37c651_t *dev = (fdc37c651_t *) priv;
free(dev);
}
static void *
fdc37c651_init(const device_t *info)
{
fdc37c651_t *dev = (fdc37c651_t *) malloc(sizeof(fdc37c651_t));
memset(dev, 0, sizeof(fdc37c651_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
dev->has_ide = (info->local >> 8) & 0xff;
io_sethandler(0x03f0, 0x0002,
fdc37c651_read, NULL, NULL, fdc37c651_write, NULL, NULL, dev);
fdc37c651_reset(dev);
return dev;
}
/* The three appear to differ only in the chip ID, if I
understood their datasheets correctly. */
const device_t fdc37c651_device = {
"SMC FDC37C651 Super I/O",
0,
0,
fdc37c651_init, fdc37c651_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c651_ide_device = {
"SMC FDC37C651 Super I/O (With IDE)",
0,
0x100,
fdc37c651_init, fdc37c651_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

299
src/sio/sio_fdc37c661.c
View File

@@ -1,299 +0,0 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the SMC FDC37C661 Super I/O Chip.
*
*
*
* Authors: Sarah Walker, <http://pcem-emulator.co.uk/>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2020 Sarah Walker.
* Copyright 2016-2020 Miran Grca.
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pci.h>
#include <86box/lpt.h>
#include <86box/serial.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/sio.h>
typedef struct {
uint8_t chip_id, tries,
has_ide, regs[16];
int cur_reg,
com3_addr, com4_addr;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c661_t;
static void
set_com34_addr(fdc37c661_t *dev)
{
switch (dev->regs[1] & 0x60) {
case 0x00:
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
break;
case 0x20:
dev->com3_addr = 0x3e8;
dev->com4_addr = 0x2e8;
break;
case 0x40:
dev->com3_addr = 0x3e8;
dev->com4_addr = 0x2e0;
break;
case 0x60:
dev->com3_addr = 0x220;
dev->com4_addr = 0x228;
break;
}
}
static void
set_serial_addr(fdc37c661_t *dev, int port)
{
uint8_t shift = (port << 2);
serial_remove(dev->uart[port]);
if (dev->regs[2] & (4 << shift)) {
switch ((dev->regs[2] >> shift) & 3) {
case 0:
serial_setup(dev->uart[port], SERIAL1_ADDR, SERIAL1_IRQ);
break;
case 1:
serial_setup(dev->uart[port], SERIAL2_ADDR, SERIAL2_IRQ);
break;
case 2:
serial_setup(dev->uart[port], dev->com3_addr, 4);
break;
case 3:
serial_setup(dev->uart[port], dev->com4_addr, 3);
break;
}
}
}
static void
lpt1_handler(fdc37c661_t *dev)
{
lpt1_remove();
switch (dev->regs[1] & 3) {
case 1:
lpt1_init(0x3bc);
lpt1_irq(7);
break;
case 2:
lpt1_init(0x378);
lpt1_irq(7 /*5*/);
break;
case 3:
lpt1_init(0x278);
lpt1_irq(7 /*5*/);
break;
}
}
static void
fdc_handler(fdc37c661_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0] & 0x10)
fdc_set_base(dev->fdc, 0x03f0);
}
static void
ide_handler(fdc37c661_t *dev)
{
/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
if (dev->has_ide == 2) {
ide_sec_disable();
ide_set_base(1, 0x1f0);
ide_set_side(1, 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_sec_enable();
} else if (dev->has_ide == 1) {
ide_pri_disable();
ide_set_base(0, 0x1f0);
ide_set_side(0, 0x3f6);
if (dev->regs[0x00] & 0x01)
ide_pri_enable();
}
}
static void
fdc37c661_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c661_t *dev = (fdc37c661_t *) priv;
uint8_t valxor = 0;
if (dev->tries == 2) {
if (port == 0x3f0) {
if (val == 0xaa)
dev->tries = 0;
else
dev->cur_reg = val;
} else {
if (dev->cur_reg > 15)
return;
valxor = val ^ dev->regs[dev->cur_reg];
dev->regs[dev->cur_reg] = val;
switch(dev->cur_reg) {
case 0:
if (dev->has_ide && (valxor & 0x01))
ide_handler(dev);
if (valxor & 0x10)
fdc_handler(dev);
break;
case 1:
if (valxor & 3)
lpt1_handler(dev);
if (valxor & 0x60) {
set_com34_addr(dev);
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
}
break;
case 2:
if (valxor & 7)
set_serial_addr(dev, 0);
if (valxor & 0x70)
set_serial_addr(dev, 1);
break;
}
}
} else if ((port == 0x3f0) && (val == 0x55))
dev->tries++;
}
static uint8_t
fdc37c661_read(uint16_t port, void *priv)
{
fdc37c661_t *dev = (fdc37c661_t *) priv;
uint8_t ret = 0x00;
if (dev->tries == 2) {
if (port == 0x3f1)
ret = dev->regs[dev->cur_reg];
}
return ret;
}
static void
fdc37c661_reset(fdc37c661_t *dev)
{
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
serial_remove(dev->uart[0]);
serial_setup(dev->uart[0], SERIAL1_ADDR, SERIAL1_IRQ);
serial_remove(dev->uart[1]);
serial_setup(dev->uart[1], SERIAL2_ADDR, SERIAL2_IRQ);
lpt1_remove();
lpt1_init(0x378);
fdc_reset(dev->fdc);
fdc_remove(dev->fdc);
dev->tries = 0;
memset(dev->regs, 0, 16);
dev->regs[0x0] = 0x3f;
dev->regs[0x1] = 0x9f;
dev->regs[0x2] = 0xdc;
dev->regs[0x3] = 0x78;
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
lpt1_handler(dev);
fdc_handler(dev);
if (dev->has_ide)
ide_handler(dev);
}
static void
fdc37c661_close(void *priv)
{
fdc37c661_t *dev = (fdc37c661_t *) priv;
free(dev);
}
static void *
fdc37c661_init(const device_t *info)
{
fdc37c661_t *dev = (fdc37c661_t *) malloc(sizeof(fdc37c661_t));
memset(dev, 0, sizeof(fdc37c661_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
dev->chip_id = info->local & 0xff;
dev->has_ide = (info->local >> 8) & 0xff;
io_sethandler(0x03f0, 0x0002,
fdc37c661_read, NULL, NULL, fdc37c661_write, NULL, NULL, dev);
fdc37c661_reset(dev);
return dev;
}
/* The three appear to differ only in the chip ID, if I
understood their datasheets correctly. */
const device_t fdc37c661_device = {
"SMC FDC37C661 Super I/O",
0,
0x00,
fdc37c661_init, fdc37c661_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c661_ide_device = {
"SMC FDC37C661 Super I/O (With IDE)",
0,
0x100,
fdc37c661_init, fdc37c661_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

130
src/sio/sio_fdc37c66x.c → src/sio/sio_fdc37c6xx.c
View File

@@ -37,17 +37,18 @@
typedef struct {
uint8_t chip_id, tries,
has_ide, regs[16];
uint8_t max_reg, chip_id,
tries, has_ide,
regs[16];
int cur_reg,
com3_addr, com4_addr;
fdc_t *fdc;
serial_t *uart[2];
} fdc37c66x_t;
} fdc37c6xx_t;
static void
set_com34_addr(fdc37c66x_t *dev)
set_com34_addr(fdc37c6xx_t *dev)
{
switch (dev->regs[1] & 0x60) {
case 0x00:
@@ -71,7 +72,7 @@ set_com34_addr(fdc37c66x_t *dev)
static void
set_serial_addr(fdc37c66x_t *dev, int port)
set_serial_addr(fdc37c6xx_t *dev, int port)
{
uint8_t shift = (port << 2);
double clock_src = 24000000.0 / 13.0;
@@ -102,7 +103,7 @@ set_serial_addr(fdc37c66x_t *dev, int port)
static void
lpt1_handler(fdc37c66x_t *dev)
lpt1_handler(fdc37c6xx_t *dev)
{
lpt1_remove();
switch (dev->regs[1] & 3) {
@@ -123,7 +124,7 @@ lpt1_handler(fdc37c66x_t *dev)
static void
fdc_handler(fdc37c66x_t *dev)
fdc_handler(fdc37c6xx_t *dev)
{
fdc_remove(dev->fdc);
if (dev->regs[0] & 0x10)
@@ -133,7 +134,7 @@ fdc_handler(fdc37c66x_t *dev)
static void
ide_handler(fdc37c66x_t *dev)
ide_handler(fdc37c6xx_t *dev)
{
/* TODO: Make an ide_disable(channel) and ide_enable(channel) so we can simplify this. */
if (dev->has_ide == 2) {
@@ -153,9 +154,9 @@ ide_handler(fdc37c66x_t *dev)
static void
fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
fdc37c6xx_write(uint16_t port, uint8_t val, void *priv)
{
fdc37c66x_t *dev = (fdc37c66x_t *) priv;
fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
uint8_t valxor = 0;
if (dev->tries == 2) {
@@ -165,7 +166,7 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
else
dev->cur_reg = val;
} else {
if (dev->cur_reg > 15)
if (dev->cur_reg > dev->max_reg)
return;
valxor = val ^ dev->regs[dev->cur_reg];
@@ -221,9 +222,9 @@ fdc37c66x_write(uint16_t port, uint8_t val, void *priv)
static uint8_t
fdc37c66x_read(uint16_t port, void *priv)
fdc37c6xx_read(uint16_t port, void *priv)
{
fdc37c66x_t *dev = (fdc37c66x_t *) priv;
fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
uint8_t ret = 0x00;
if (dev->tries == 2) {
@@ -236,7 +237,7 @@ fdc37c66x_read(uint16_t port, void *priv)
static void
fdc37c66x_reset(fdc37c66x_t *dev)
fdc37c6xx_reset(fdc37c6xx_t *dev)
{
dev->com3_addr = 0x338;
dev->com4_addr = 0x238;
@@ -256,13 +257,33 @@ fdc37c66x_reset(fdc37c66x_t *dev)
dev->tries = 0;
memset(dev->regs, 0, 16);
dev->regs[0x0] = 0x3a;
switch (dev->chip_id) {
case 0x63: case 0x65:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x3b;
break;
case 0x64: case 0x66:
dev->max_reg = 0x0f;
dev->regs[0x0] = 0x2b;
break;
default:
dev->max_reg = (dev->chip_id >= 0x61) ? 0x03 : 0x02;
dev->regs[0x0] = 0x3f;
break;
}
dev->regs[0x1] = 0x9f;
dev->regs[0x2] = 0xdc;
dev->regs[0x3] = 0x78;
dev->regs[0x6] = 0xff;
dev->regs[0xd] = dev->chip_id;
dev->regs[0xe] = 0x01;
if (dev->chip_id >= 0x63) {
dev->regs[0x6] = 0xff;
dev->regs[0xd] = dev->chip_id;
if (dev->chip_id >= 0x65)
dev->regs[0xe] = 0x02;
else
dev->regs[0xe] = 0x01;
}
set_serial_addr(dev, 0);
set_serial_addr(dev, 1);
@@ -277,32 +298,37 @@ fdc37c66x_reset(fdc37c66x_t *dev)
static void
fdc37c66x_close(void *priv)
fdc37c6xx_close(void *priv)
{
fdc37c66x_t *dev = (fdc37c66x_t *) priv;
fdc37c6xx_t *dev = (fdc37c6xx_t *) priv;
free(dev);
}
static void *
fdc37c66x_init(const device_t *info)
fdc37c6xx_init(const device_t *info)
{
fdc37c66x_t *dev = (fdc37c66x_t *) malloc(sizeof(fdc37c66x_t));
memset(dev, 0, sizeof(fdc37c66x_t));
fdc37c6xx_t *dev = (fdc37c6xx_t *) malloc(sizeof(fdc37c6xx_t));
memset(dev, 0, sizeof(fdc37c6xx_t));
dev->fdc = device_add(&fdc_at_smc_device);
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
dev->chip_id = info->local & 0xff;
dev->has_ide = (info->local >> 8) & 0xff;
io_sethandler(0x03f0, 0x0002,
fdc37c66x_read, NULL, NULL, fdc37c66x_write, NULL, NULL, dev);
if (dev->chip_id >= 0x63) {
dev->uart[0] = device_add_inst(&ns16550_device, 1);
dev->uart[1] = device_add_inst(&ns16550_device, 2);
} else {
dev->uart[0] = device_add_inst(&ns16450_device, 1);
dev->uart[1] = device_add_inst(&ns16450_device, 2);
}
fdc37c66x_reset(dev);
io_sethandler(0x03f0, 0x0002,
fdc37c6xx_read, NULL, NULL, fdc37c6xx_write, NULL, NULL, dev);
fdc37c6xx_reset(dev);
return dev;
}
@@ -310,11 +336,47 @@ fdc37c66x_init(const device_t *info)
/* The three appear to differ only in the chip ID, if I
understood their datasheets correctly. */
const device_t fdc37c651_device = {
"SMC FDC37C651 Super I/O",
0,
0x51,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c651_ide_device = {
"SMC FDC37C651 Super I/O (With IDE)",
0,
0x151,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c661_device = {
"SMC FDC37C661 Super I/O",
0,
0x61,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c661_ide_device = {
"SMC FDC37C661 Super I/O (With IDE)",
0,
0x161,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t fdc37c663_device = {
"SMC FDC37C663 Super I/O",
0,
0x63,
fdc37c66x_init, fdc37c66x_close, NULL,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -323,7 +385,7 @@ const device_t fdc37c663_ide_device = {
"SMC FDC37C663 Super I/O (With IDE)",
0,
0x163,
fdc37c66x_init, fdc37c66x_close, NULL,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -332,7 +394,7 @@ const device_t fdc37c665_device = {
"SMC FDC37C665 Super I/O",
0,
0x65,
fdc37c66x_init, fdc37c66x_close, NULL,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -341,7 +403,7 @@ const device_t fdc37c665_ide_device = {
"SMC FDC37C665 Super I/O (With IDE)",
0,
0x265,
fdc37c66x_init, fdc37c66x_close, NULL,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
@@ -350,7 +412,7 @@ const device_t fdc37c666_device = {
"SMC FDC37C666 Super I/O",
0,
0x66,
fdc37c66x_init, fdc37c66x_close, NULL,
fdc37c6xx_init, fdc37c6xx_close, NULL,
{ NULL }, NULL, NULL,
NULL
};

31
src/video/vid_s3.c
View File

@@ -73,6 +73,7 @@ enum
S3_METHEUS_86C928,
S3_AMI_86C924,
S3_TRIO64V2_DX,
S3_TRIO64V2_DX_ONBOARD,
S3_PHOENIX_TRIO64VPLUS,
S3_PHOENIX_TRIO64VPLUS_ONBOARD,
S3_DIAMOND_STEALTH_SE,
@@ -2460,8 +2461,14 @@ s3_in(uint16_t addr, void *p)
break;
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20)
return svga->seqregs[svga->seqaddr];
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) {
temp = svga->seqregs[svga->seqaddr];
/* This is needed for the Intel Advanced/ATX's built-in S3 Trio64V+ BIOS to not
get stuck in an infinite loop. */
if ((s3->card_type == S3_PHOENIX_TRIO64VPLUS_ONBOARD) && (svga->seqaddr == 0x17))
svga->seqregs[svga->seqaddr] ^= 0x01;
return temp;
}
break;
case 0x3c6: case 0x3c7: case 0x3c8: case 0x3c9:
@@ -5884,6 +5891,11 @@ static void *s3_init(const device_t *info)
chip = S3_TRIO64V2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
break;
case S3_TRIO64V2_DX_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO64V2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
break;
default:
free(s3);
return NULL;
@@ -6205,6 +6217,7 @@ static void *s3_init(const device_t *info)
break;
case S3_TRIO64V2_DX:
case S3_TRIO64V2_DX_ONBOARD:
svga->decode_mask = (4 << 20) - 1;
s3->id = 0xe1; /*Trio64V2/DX*/
s3->id_ext = s3->id_ext_pci = 0x01;
@@ -6981,3 +6994,17 @@ const device_t s3_trio64v2_dx_pci_device =
s3_standard_config
};
const device_t s3_trio64v2_dx_onboard_pci_device =
{
"S3 Trio64V2/DX On-Board PCI",
DEVICE_PCI,
S3_TRIO64V2_DX_ONBOARD,
s3_init,
s3_close,
NULL,
{ NULL },
s3_speed_changed,
s3_force_redraw,
s3_standard_config
};

44
src/video/vid_table.c
View File

@@ -235,18 +235,9 @@ video_reset_close(void)
}
void
video_reset(int card)
static void
video_prepare(void)
{
/* This is needed to avoid duplicate resets. */
if ((video_get_type() != VIDEO_FLAG_TYPE_NONE) && was_reset)
return;
vid_table_log("VIDEO: reset (gfxcard=%d, internal=%d)\n",
card, (machines[machine].flags & MACHINE_VIDEO)?1:0);
loadfont("roms/video/mda/mda.rom", 0);
/* Reset (deallocate) the video font arrays. */
if (fontdatksc5601) {
free(fontdatksc5601);
@@ -260,14 +251,39 @@ video_reset(int card)
/* Reset the blend. */
herc_blend = 0;
/* Do an inform on the default values, so that that there's some sane values initialized
even if the device init function does not do an inform of its own. */
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_default);
}
void
video_pre_reset(int card)
{
if ((card == VID_NONE) || \
(card == VID_INTERNAL) || (machines[machine].flags & MACHINE_VIDEO_ONLY))
video_prepare();
}
void
video_reset(int card)
{
/* This is needed to avoid duplicate resets. */
if ((video_get_type() != VIDEO_FLAG_TYPE_NONE) && was_reset)
return;
vid_table_log("VIDEO: reset (gfxcard=%d, internal=%d)\n",
card, (machines[machine].flags & MACHINE_VIDEO)?1:0);
loadfont("roms/video/mda/mda.rom", 0);
/* Do not initialize internal cards here. */
if (!(card == VID_NONE) && \
!(card == VID_INTERNAL) && !(machines[machine].flags & MACHINE_VIDEO_ONLY)) {
vid_table_log("VIDEO: initializing '%s'\n", video_cards[card].name);
/* Do an inform on the default values, so that that there's some sane values initialized
even if the device init function does not do an inform of its own. */
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_default);
video_prepare();
/* Initialize the video card. */
device_add(video_cards[card].device);

118
src/video/vid_tgui9440.c
View File

@@ -88,10 +88,12 @@ enum
{
TGUI_9400CXI = 0,
TGUI_9440,
TGUI_9660,
TGUI_9680
TGUI_9660,
TGUI_9680
};
#define ONBOARD 0x0100
typedef struct tgui_t
{
mem_mapping_t linear_mapping;
@@ -160,6 +162,8 @@ typedef struct tgui_t
volatile int write_blitter;
void *i2c, *ddc;
int has_bios;
} tgui_t;
video_timings_t timing_tgui_vlb = {VIDEO_BUS, 4, 8, 16, 4, 8, 16};
@@ -908,13 +912,13 @@ uint8_t tgui_pci_read(int func, int addr, void *p)
case 0x16: return tgui->mmio_base >> 16;
case 0x17: return tgui->mmio_base >> 24;
case 0x30: return (tgui->pci_regs[0x30] & 0x01); /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return tgui->pci_regs[0x32];
case 0x33: return tgui->pci_regs[0x33];
case 0x3c: return tgui->int_line;
case 0x3d: return PCI_INTA;
case 0x30: return tgui->has_bios ? (tgui->pci_regs[0x30] & 0x01) : 0x00; /*BIOS ROM address*/
case 0x31: return 0x00;
case 0x32: return tgui->has_bios ? tgui->pci_regs[0x32] : 0x00;
case 0x33: return tgui->has_bios ? tgui->pci_regs[0x33] : 0x00;
case 0x3c: return tgui->int_line;
case 0x3d: return PCI_INTA;
}
return 0;
}
@@ -970,23 +974,25 @@ void tgui_pci_write(int func, int addr, uint8_t val, void *p)
tgui->mmio_base = (tgui->mmio_base & 0x00e00000) | (val << 24);
tgui_recalcmapping(tgui);
break;
case 0x30: case 0x32: case 0x33:
tgui->pci_regs[addr] = val;
if (tgui->pci_regs[0x30] & 0x01)
{
uint32_t biosaddr = (tgui->pci_regs[0x32] << 16) | (tgui->pci_regs[0x33] << 24);
mem_mapping_set_addr(&tgui->bios_rom.mapping, biosaddr, 0x8000);
}
else
{
mem_mapping_disable(&tgui->bios_rom.mapping);
}
return;
case 0x3c:
tgui->int_line = val;
return;
case 0x30: case 0x32: case 0x33:
if (tgui->has_bios) {
tgui->pci_regs[addr] = val;
if (tgui->pci_regs[0x30] & 0x01)
{
uint32_t biosaddr = (tgui->pci_regs[0x32] << 16) | (tgui->pci_regs[0x33] << 24);
mem_mapping_set_addr(&tgui->bios_rom.mapping, biosaddr, 0x8000);
}
else
{
mem_mapping_disable(&tgui->bios_rom.mapping);
}
}
return;
case 0x3c:
tgui->int_line = val;
return;
}
}
@@ -2801,16 +2807,15 @@ tgui_mmio_read_l(uint32_t addr, void *p)
static void *tgui_init(const device_t *info)
{
const char *bios_fn;
int type = info->local;
tgui_t *tgui = malloc(sizeof(tgui_t));
svga_t *svga = &tgui->svga;
svga_t *svga = &tgui->svga;
memset(tgui, 0, sizeof(tgui_t));
tgui->vram_size = device_get_config_int("memory") << 20;
tgui->vram_mask = tgui->vram_size - 1;
tgui->type = type;
tgui->type = info->local & 0xff;
tgui->pci = !!(info->flags & DEVICE_PCI);
@@ -2819,7 +2824,7 @@ static void *tgui_init(const device_t *info)
bios_fn = ROM_TGUI_9400CXI;
break;
case TGUI_9440:
bios_fn = ROM_TGUI_9440;
bios_fn = (info->local & ONBOARD) ? NULL : ROM_TGUI_9440;
break;
case TGUI_9660:
case TGUI_9680:
@@ -2830,7 +2835,10 @@ static void *tgui_init(const device_t *info)
return NULL;
}
rom_init(&tgui->bios_rom, (char *) bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
tgui->has_bios = (bios_fn != NULL);
if (tgui->has_bios)
rom_init(&tgui->bios_rom, (char *) bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (tgui->pci)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tgui_pci);
@@ -2844,33 +2852,39 @@ static void *tgui_init(const device_t *info)
NULL);
if (tgui->type == TGUI_9400CXI)
svga->ramdac = device_add(&tkd8001_ramdac_device);
svga->ramdac = device_add(&tkd8001_ramdac_device);
mem_mapping_add(&tgui->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, tgui_accel_write_fb_b, tgui_accel_write_fb_w, tgui_accel_write_fb_l, NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&tgui->accel_mapping, 0, 0, tgui_accel_read, tgui_accel_read_w, tgui_accel_read_l, tgui_accel_write, tgui_accel_write_w, tgui_accel_write_l, NULL, MEM_MAPPING_EXTERNAL, tgui);
if (tgui->type >= TGUI_9440)
mem_mapping_add(&tgui->mmio_mapping, 0, 0, tgui_mmio_read, tgui_mmio_read_w, tgui_mmio_read_l, tgui_mmio_write, tgui_mmio_write_w, tgui_mmio_write_l, NULL, MEM_MAPPING_EXTERNAL, tgui);
if (tgui->type >= TGUI_9440)
mem_mapping_add(&tgui->mmio_mapping, 0, 0, tgui_mmio_read, tgui_mmio_read_w, tgui_mmio_read_l, tgui_mmio_write, tgui_mmio_write_w, tgui_mmio_write_l, NULL, MEM_MAPPING_EXTERNAL, tgui);
mem_mapping_disable(&tgui->accel_mapping);
mem_mapping_disable(&tgui->mmio_mapping);
mem_mapping_disable(&tgui->mmio_mapping);
tgui_set_io(tgui);
tgui_set_io(tgui);
if (tgui->pci && (tgui->type >= TGUI_9440))
if (tgui->pci && (tgui->type >= TGUI_9440)) {
if (tgui->has_bios)
tgui->card = pci_add_card(PCI_ADD_VIDEO, tgui_pci_read, tgui_pci_write, tgui);
else
tgui->card = pci_add_card(PCI_ADD_VIDEO | PCI_ADD_STRICT, tgui_pci_read, tgui_pci_write, tgui);
}
tgui->pci_regs[PCI_REG_COMMAND] = 3;
tgui->pci_regs[PCI_REG_COMMAND] = 3;
if (tgui->has_bios) {
tgui->pci_regs[0x30] = 0x00;
tgui->pci_regs[0x32] = 0x0c;
tgui->pci_regs[0x33] = 0x00;
}
if (tgui->type >= TGUI_9440)
svga->packed_chain4 = 1;
if (tgui->type >= TGUI_9660) {
tgui->i2c = i2c_gpio_init("ddc_tgui");
tgui->ddc = ddc_init(i2c_gpio_get_bus(tgui->i2c));
}
if (tgui->type >= TGUI_9440)
svga->packed_chain4 = 1;
if (tgui->type >= TGUI_9660) {
tgui->i2c = i2c_gpio_init("ddc_tgui");
tgui->ddc = ddc_init(i2c_gpio_get_bus(tgui->i2c));
}
return tgui;
}
@@ -3019,6 +3033,20 @@ const device_t tgui9440_pci_device =
tgui9440_config
};
const device_t tgui9440_onboard_pci_device =
{
"Trident TGUI 9440AGi On-Board PCI",
DEVICE_PCI,
TGUI_9440 | ONBOARD,
tgui_init,
tgui_close,
NULL,
{ NULL },
tgui_speed_changed,
tgui_force_redraw,
tgui9440_config
};
const device_t tgui9660_pci_device =
{
"Trident TGUI 9660XGi PCI",

7
src/win/Makefile.mingw
View File

@@ -328,7 +328,7 @@ else
endif
endif
ifeq ($(DEBUG), y)
DFLAGS += -ggdb -DDEBUG
DFLAGS += -ggdb -DDEBUG -DUSE_ACYCS
AOPTIM :=
ifndef COPTIM
COPTIM := -Og
@@ -599,6 +599,7 @@ CHIPSETOBJ := acc2168.o \
scamp.o scat.o \
stpc.o \
wd76c10.o vl82c480.o \
umc_8886.o umc_hb4.o \
via_vt82c49x.o via_vt82c505.o via_apollo.o via_pipc.o \
sis_85c310.o sis_85c4xx.o sis_85c496.o sis_85c50x.o sis_5511.o sis_5571.o
@@ -645,8 +646,8 @@ DEVOBJ := bugger.o cartridge.o cassette.o hasp.o hwm.o hwm_lm75.o hwm_lm78.o hw
endif
SIOOBJ := sio_acc3221.o \
sio_f82c710.o sio_82091aa.o sio_fdc37c651.o \
sio_fdc37c661.o sio_fdc37c66x.o sio_fdc37c67x.o sio_fdc37c669.o sio_fdc37c93x.o sio_fdc37m60x.o \
sio_f82c710.o sio_82091aa.o sio_fdc37c6xx.o \
sio_fdc37c67x.o sio_fdc37c669.o sio_fdc37c93x.o sio_fdc37m60x.o \
sio_it8661f.o \
sio_pc87306.o sio_pc87307.o sio_pc87309.o sio_pc87310.o sio_pc87311.o sio_pc87332.o \
sio_prime3b.o sio_prime3c.o \