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PRMVIO and interrupt fixes.

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This commit is contained in:
starfrost013
2024-12-31 16:36:24 +00:00
parent 54bafba20c
commit 713ef4585b
3 changed files with 12 additions and 3 deletions
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6
src/video/nv/nv3/nv3_core.c
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@@ -120,6 +120,8 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv)
// Write 8-bit MMIO
void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv)
{
addr &= 0xFFFFFF;
// This is weitek vga stuff
if (addr >= NV3_PRMVIO_START
&& addr <= NV3_PRMVIO_END)
@@ -144,6 +146,8 @@ void nv3_mmio_write8(uint32_t addr, uint8_t val, void* priv)
// Write 16-bit MMIO
void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
{
addr &= 0xFFFFFF;
// This is weitek vga stuff
if (addr >= NV3_PRMVIO_START
&& addr <= NV3_PRMVIO_END)
@@ -169,6 +173,8 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
// Write 32-bit MMIO
void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
{
addr &= 0xFFFFFF;
// This is weitek vga stuff
if (addr >= NV3_PRMVIO_START
&& addr <= NV3_PRMVIO_END)

2
src/video/nv/nv3/subsystems/nv3_pgraph.c
View File

@@ -231,7 +231,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
// Fire a VALID Pgraph interrupt: num is the bit# of the interrupt in the GPU subsystem INTR_EN register.
void nv3_pgraph_interrupt_valid(uint32_t num)
{
nv3->pgraph.interrupt_enable_0 |= (1 << num);
nv3->pgraph.interrupt_status_0 |= (1 << num);
nv3_pmc_handle_interrupts(true);
}

7
src/video/nv/nv3/subsystems/nv3_pmc.c
View File

@@ -89,9 +89,12 @@ uint32_t nv3_pmc_handle_interrupts(bool send_now)
new_intr_value |= (NV3_PMC_INTERRUPT_PFIFO_PENDING << NV3_PMC_INTERRUPT_PFIFO);
// PFB interrupt is VBLANK PGRAPH interrupt...what nvidia...clean this up once we verify it
if (nv3->pgraph.interrupt_status_0 & (1 << 8))
if (nv3->pgraph.interrupt_status_0 & (1 << 8)
&& nv3->pgraph.interrupt_enable_0 & (1 << 8))
new_intr_value |= (NV3_PMC_INTERRUPT_PFB_PENDING << NV3_PMC_INTERRUPT_PFB);
else if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt
if (nv3->pgraph.interrupt_status_0 & ~(1 << 8)
&& nv3->pgraph.interrupt_enable_0 & ~(1 << 8)) // otherwise PGRAPH-0 interurpt
new_intr_value |= (NV3_PMC_INTERRUPT_PGRAPH0_PENDING << NV3_PMC_INTERRUPT_PGRAPH0);
// Check second pgraph interrupt register