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Merge branch '86Box:master' into master

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This commit is contained in:
Toni Riikonen
2025-09-18 17:13:24 +03:00
committed by GitHub
parent 55495c2b57 84e4a29528
commit 71c61db10c
49 changed files with 1019 additions and 664 deletions
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2
CMakeLists.txt
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@@ -36,7 +36,7 @@ if(MUNT_EXTERNAL)
endif()
project(86Box
VERSION 6.0
VERSION 5.2
DESCRIPTION "Emulator of x86-based systems"
HOMEPAGE_URL "https://86box.net"
LANGUAGES C CXX)

4
debian/changelog vendored
View File

@@ -1,5 +1,5 @@
86box (6.0) UNRELEASED; urgency=medium
86box (5.2) UNRELEASED; urgency=medium
* Bump release.
-- Jasmine Iwanek <jriwanek@gmail.com> Sun, 14 Sep 2025 01:57:44 +0200
-- Jasmine Iwanek <jriwanek@gmail.com> Thu, 18 Sep 2025 04:25:57 +0200

3
src/86box.c
View File

@@ -1806,9 +1806,6 @@ pc_close(UNUSED(thread_t *ptr))
gdbstub_close();
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
mem_free();
#endif
}
#ifdef __APPLE__

6
src/acpi.c
View File

@@ -41,6 +41,7 @@
#include <86box/i2c.h>
#include <86box/video.h>
#include <86box/smbus.h>
#include <86box/hdc.h>
#include <86box/hdc_ide.h>
#include <86box/hdc_ide_sff8038i.h>
#include <86box/sis_55xx.h>
@@ -1219,8 +1220,11 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *priv)
case 0x36:
case 0x37:
/* GPOREG - General Purpose Output Register (IO) */
if (size == 1)
if (size == 1) {
dev->regs.gporeg[addr & 3] = val;
if ((addr == 0x34) && !strcmp(machine_get_internal_name(), "cubx"))
hdc_onboard_enabled = (val & 0x01);
}
break;
default:
acpi_reg_write_common_regs(size, addr, val, priv);

4
src/arch_detect.c
View File

@@ -15,9 +15,7 @@
* Copyright 2020-2021 David Hrdlička.
*/
#if defined(__arm__) || defined(__TARGET_ARCH_ARM)
# error ARCH arm
#elif defined(__aarch64__) || defined(_M_ARM64)
#if defined(__aarch64__) || defined(_M_ARM64)
# error ARCH arm64
#elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) || defined(_M_X64)
# error ARCH x86_64

5
src/chipset/compaq_386.c
View File

@@ -714,11 +714,6 @@ compaq_386_init(UNUSED(const device_t *info))
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
/* Should never be the case, but you never know what a user may set. */
if (mem_size > 1048576)
mem_mapping_disable(&ram_2gb_mapping);
#endif
/* Initialize in reverse order for memory mapping precedence
reasons. */

4
src/config.c
View File

@@ -1035,7 +1035,7 @@ load_storage_controllers(void)
if (!hdc_current[j]) {
if (!legacy_cards[i]) {
if (!p) {
hdc_current[j] = hdc_get_from_internal_name("internal");
hdc_current[j] = hdc_get_from_internal_name((j == 0) ? "internal" : "none");
} else if (!strcmp(p, "xtide_plus")) {
hdc_current[j] = hdc_get_from_internal_name("xtide");
sprintf(temp, "PC/XT XTIDE #%i", j + 1);
@@ -3069,7 +3069,7 @@ save_storage_controllers(void)
else
def_hdc = "none";
if (!strcmp(hdc_get_internal_name(hdc_current[c]), def_hdc))
if (!strcmp(hdc_get_internal_name(hdc_current[c]), def_hdc) || ((c > 0) && (hdc_current[c] == 1)))
ini_section_delete_var(cat, temp);
else
ini_section_set_string(cat, temp,

44
src/cpu/386_common.h
View File

@@ -357,22 +357,17 @@ fastreadb(uint32_t a)
mem_debug_check_addr(a, read_type);
read_type = 4;
# endif
if ((a >> 12) == pccache)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint8_t *) &pccache2[a]);
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint8_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint8_t *) &pccache2[a]);
# endif
}
static __inline uint16_t
@@ -392,22 +387,16 @@ fastreadw(uint32_t a)
return val;
}
if ((a >> 12) == pccache)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint16_t *) &pccache2[a]);
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint16_t *) &pccache2[a]);
# endif
}
static __inline uint32_t
@@ -431,11 +420,8 @@ fastreadl(uint32_t a)
pccache2 = t;
pccache = a >> 12;
}
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint32_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint32_t *) &pccache2[a]);
# endif
}
val = fastreadw(a);
val |= (fastreadw(a + 2) << 16);
@@ -447,18 +433,10 @@ static __inline void *
get_ram_ptr(uint32_t a)
{
if ((a >> 12) == pccache)
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return (void *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL));
#else
return &pccache2[a];
#endif
else {
uint8_t *t = getpccache(a);
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return (void *) (((uintptr_t) &t[a] & 0x00000000ffffffffULL) | ((uintptr_t) &t[0] & 0xffffffff00000000ULL));
#else
return &t[a];
#endif
}
}
@@ -528,22 +506,16 @@ fastreadw_fetch(uint32_t a)
return val;
}
if ((a >> 12) == pccache)
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint16_t *) &pccache2[a]);
# endif
t = getpccache(a);
if (cpu_state.abrt)
return 0;
pccache = a >> 12;
pccache2 = t;
# if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
return *((uint16_t *) (((uintptr_t) &pccache2[a] & 0x00000000ffffffffULL) | ((uintptr_t) &pccache2[0] & 0xffffffff00000000ULL)));
# else
return *((uint16_t *) &pccache2[a]);
# endif
}
static __inline uint32_t

4
src/cpu/cpu.h
View File

@@ -388,10 +388,6 @@ typedef struct {
uint32_t old_fp_control;
uint32_t new_fp_control;
# endif
# if defined _M_IX86
uint16_t old_fp_control2;
uint16_t new_fp_control2;
# endif
# if defined __amd64__ || defined _M_X64
uint32_t trunc_fp_control;
# endif

10
src/cpu/x87_ops.h
View File

@@ -22,16 +22,12 @@
*/
#include <math.h>
#include <fenv.h>
#if defined(_MSC_VER) && !defined(__clang__)
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
#if defined _M_X64 || defined __amd64__
# define X87_INLINE_ASM
# endif
#else
# if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined _M_X64 || defined __amd64__
# define X87_INLINE_ASM
# endif
#endif
#ifdef X87_INLINE_ASM
#include <immintrin.h>
#endif

4
src/disk/hdc.c
View File

@@ -32,6 +32,8 @@
int hdc_current[HDC_MAX] = { 0, 0 };
int hdc_onboard_enabled = 1;
#ifdef ENABLE_HDC_LOG
int hdc_do_log = ENABLE_HDC_LOG;
@@ -114,6 +116,8 @@ hdc_init(void)
void
hdc_reset(void)
{
hdc_onboard_enabled = 1;
for (int i = 0; i < HDC_MAX; i++) {
hdc_log("HDC %i: reset(current=%d, internal=%d)\n", i,
hdc_current[i], hdc_current[i] == HDC_INTERNAL);

24
src/disk/hdc_ide_cmd646.c
View File

@@ -145,6 +145,7 @@ cmd646_ide_handlers(cmd646_t *dev)
int first = 0;
int reg09 = dev->regs[0x09];
int reg50 = dev->regs[0x50];
int dev_enabled = (hdc_onboard_enabled || !(dev->local & CMD64X_ONBOARD));
if ((dev->local & CMD_TYPE_648) && (dev->local & CMD648_RAID)) {
reg09 = 0xff;
@@ -180,7 +181,7 @@ cmd646_ide_handlers(cmd646_t *dev)
if (dev->local & CMD_TYPE_648)
pri_enabled = pri_enabled && (dev->regs[0x51] & 0x04);
if (pri_enabled)
if (dev_enabled && pri_enabled)
ide_handlers(first, 1);
if (dev->single_channel)
@@ -205,7 +206,7 @@ cmd646_ide_handlers(cmd646_t *dev)
sff_set_irq_mode(dev->bm[1], irq_mode[1]);
cmd646_log("IDE %i: %04X, %04X, %i\n", first + 1, main, side, irq_mode[1]);
if ((dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
if (dev_enabled && (dev->regs[0x04] & 0x01) && (dev->regs[0x51] & 0x08))
ide_handlers(first + 1, 1);
}
@@ -213,9 +214,10 @@ static void
cmd646_ide_bm_handlers(cmd646_t *dev)
{
uint16_t base = (dev->regs[0x20] & 0xf0) | (dev->regs[0x21] << 8);
int dev_enabled = (hdc_onboard_enabled || !(dev->local & CMD64X_ONBOARD));
sff_bus_master_handler(dev->bm[0], (dev->regs[0x04] & 1), base);
sff_bus_master_handler(dev->bm[1], (dev->regs[0x04] & 1), base + 8);
sff_bus_master_handler(dev->bm[0], dev_enabled && (dev->regs[0x04] & 1), base);
sff_bus_master_handler(dev->bm[1], dev_enabled && (dev->regs[0x04] & 1), base + 8);
}
uint8_t
@@ -296,15 +298,16 @@ cmd646_bios_handler(cmd646_t *dev)
static void
cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
int reg50 = dev->regs[0x50];
cmd646_t *dev = (cmd646_t *) priv;
int reg50 = dev->regs[0x50];
int dev_enabled = (hdc_onboard_enabled || !(dev->local & CMD64X_ONBOARD));
if ((dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04) && (dev->regs[0x0b] == 0x01))
reg50 |= 0x40;
cmd646_log("[%04X:%08X] (%08X) cmd646_pci_write(%i, %02X, %02X)\n", CS, cpu_state.pc, ESI, func, addr, val);
if (func == 0x00)
if (dev_enabled && (func == 0x00))
switch (addr) {
case 0x04:
if (dev->has_bios)
@@ -480,10 +483,11 @@ cmd646_pci_write(int func, int addr, uint8_t val, void *priv)
static uint8_t
cmd646_pci_read(int func, int addr, void *priv)
{
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = 0xff;
cmd646_t *dev = (cmd646_t *) priv;
uint8_t ret = 0xff;
int dev_enabled = (hdc_onboard_enabled || !(dev->local & CMD64X_ONBOARD));
if (func == 0x00) {
if (dev_enabled && (func == 0x00)) {
ret = dev->regs[addr];
if ((addr == 0x09) && (dev->local & CMD_TYPE_648) && (dev->regs[0x0a] == 0x04))

2
src/floppy/lzf/lzf_d.c
View File

@@ -44,7 +44,7 @@
#endif
#if USE_REP_MOVSB /* small win on amd, big loss on intel */
#if (__i386 || __amd64) && __GNUC__ >= 3
#if (__amd64) && __GNUC__ >= 3
# define lzf_movsb(dst, src, len) \
asm ("rep movsb" \
: "=D" (dst), "=S" (src), "=c" (len) \

2
src/include/86box/bswap.h
View File

@@ -163,7 +163,7 @@ CPU_CONVERT(le, 64, uint64_t)
/* unaligned versions (optimized for frequent unaligned accesses)*/
#if defined(__i386__) || defined(__powerpc__)
#if defined(__powerpc__)
# define cpu_to_le16wu(p, v) cpu_to_le16w(p, v)
# define cpu_to_le32wu(p, v) cpu_to_le32w(p, v)
# define le16_to_cpupu(p) le16_to_cpup(p)

1
src/include/86box/hdc.h
View File

@@ -30,6 +30,7 @@
#define HDC_MAX 4
extern int hdc_current[HDC_MAX];
extern int hdc_onboard_enabled;
extern const device_t st506_xt_xebec_device; /* st506_xt_xebec */
extern const device_t st506_xt_wdxt_gen_device; /* st506_xt_wdxt_gen */

9
src/include/86box/machine.h
View File

@@ -174,11 +174,7 @@
#define CPU_BLOCK_NONE 0
/* Make sure it's always an invalid value to avoid misdetections. */
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
# define MACHINE_AVAILABLE 0xffffffffffffffffULL
#else
# define MACHINE_AVAILABLE 0xffffffff
#endif
#define MACHINE_AVAILABLE 0xffffffffffffffffULL
enum {
MACHINE_TYPE_NONE = 0,
@@ -996,6 +992,9 @@ extern int machine_at_cu430hx_init(const machine_t *);
extern const device_t tc430hx_device;
#endif
extern int machine_at_tc430hx_init(const machine_t *);
#ifdef EMU_DEVICE_H
extern const device_t m7shi_device;
#endif
extern int machine_at_m7shi_init(const machine_t *);
extern int machine_at_epc2102_init(const machine_t *);
extern int machine_at_pcv90_init(const machine_t *);

17
src/include/86box/mem.h
View File

@@ -265,24 +265,17 @@ extern uint32_t biosmask;
extern uint32_t biosaddr;
extern int readlookup[256];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
extern uintptr_t *readlookup2;
#endif
extern uintptr_t old_rl2;
extern uint8_t uncached;
extern int readlnext;
extern int writelookup[256];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
extern uintptr_t *writelookup2;
#endif
extern int writelnext;
extern uint32_t ram_mapped_addr[64];
extern uint8_t page_ff[4096];
extern mem_mapping_t ram_low_mapping;
#if 1
extern mem_mapping_t ram_mid_mapping;
#endif
extern mem_mapping_t ram_remapped_mapping;
extern mem_mapping_t ram_high_mapping;
extern mem_mapping_t ram_2gb_mapping;
@@ -292,16 +285,11 @@ extern mem_mapping_t bios_high_mapping;
extern uint32_t mem_logical_addr;
extern page_t *pages;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
extern page_t **page_lookup;
#endif
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
/* The lookup tables. */
extern page_t *page_lookup[1048576];
extern uintptr_t readlookup2[1048576];
extern uintptr_t writelookup2[1048576];
#endif
extern uint32_t get_phys_virt;
extern uint32_t get_phys_phys;
@@ -470,9 +458,6 @@ extern void mem_a20_init(void);
extern void mem_a20_recalc(void);
extern void mem_init(void);
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
extern void mem_free(void);
#endif
extern void mem_close(void);
extern void mem_zero(void);
extern void mem_reset(void);

2
src/include/86box/snd_ad1848.h
View File

@@ -78,6 +78,8 @@ typedef struct ad1848_t {
pc_timer_t timer_count;
uint64_t timer_latch;
pc_timer_t cs4231a_irq_timer;
int16_t buffer[SOUNDBUFLEN * 2];
int pos;

3
src/include/86box/sound.h
View File

@@ -242,6 +242,9 @@ extern const device_t tndy_device;
extern const device_t wss_device;
extern const device_t ncr_business_audio_device;
/* Yamaha YMF-7xx */
extern const device_t ymf701_device;
#ifdef USE_LIBSERIALPORT
/* External Audio device OPL2Board (Host Connected hardware)*/
extern const device_t opl2board_device;

38
src/include/86box/vid_clockgen_icd2061.h Normal file
View File

@@ -0,0 +1,38 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ICD2061 clock generator emulation.
* Also emulates the ICS9161 which is the same as the ICD2016,
* but without the need for tuning (which is irrelevant in
* emulation anyway).
*
* Used by ET4000w32/p (Diamond Stealth 32) and the S3
* Vision964 family.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.
*/
#ifndef VIDEO_CLOCKGEN_ICD2061_H
#define VIDEO_CLOCKGEN_ICD2061_H
typedef struct icd2061_t {
float freq[3];
float ref_clock;
int count;
int bit_count;
int unlocked;
int state;
uint32_t data;
uint32_t ctrl;
} icd2061_t;
#endif // VIDEO_CLOCKGEN_ICD2061_H

5
src/include/86box/vid_svga.h
View File

@@ -142,6 +142,9 @@ typedef struct svga_t {
int start_retrace_latch;
int vga_mode;
int half_pixel;
int clock_multiplier;
int true_color_bypass;
int multiplexing_rate;
/*The three variables below allow us to implement memory maps like that seen on a 1MB Trio64 :
0MB-1MB - VRAM
@@ -450,7 +453,7 @@ extern void ibm_rgb528_ramdac_set_ref_clock(void *priv, svga_t *svga, float r
extern void icd2061_write(void *priv, int val);
extern float icd2061_getclock(int clock, void *priv);
extern void icd2061_set_ref_clock(void *priv, svga_t *svga, float ref_clock);
extern void icd2061_set_ref_clock(void *priv, float ref_clock);
/* The code is the same, the #define's are so that the correct name can be used. */
# define ics9161_write icd2061_write

59
src/machine/m_at_socket7.c
View File

@@ -320,6 +320,9 @@ machine_at_tc430hx_gpio_init(void)
else if (cpu_busspeed > 60000000)
gpio |= 0xffff00ff;
if (sound_card_current[0] == SOUND_INTERNAL)
gpio |= 0xffff04ff;
machine_set_gpio_default(gpio);
}
@@ -354,6 +357,9 @@ machine_at_tc430hx_init(const machine_t *model)
if (gfxcard[0] == VID_INTERNAL)
device_add(machine_get_vid_device(machine));
if (sound_card_current[0] == SOUND_INTERNAL)
machine_snd = device_add(machine_get_snd_device(machine));
device_add(&i430hx_device);
device_add(&piix3_device);
device_add_params(&pc87306_device, (void *) PCX730X_AMI);
@@ -362,17 +368,57 @@ machine_at_tc430hx_init(const machine_t *model)
return ret;
}
static const device_config_t m7shi_config[] = {
// clang-format off
{
.name = "bios",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "m7shi",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.bios = {
{ .name = "PhoenixBIOS 4.0 Release 6.0 - Revision 05/20/97", .internal_name = "m7shi", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/m7shi/m7shi2n.rom", "" } },
{ .name = "PhoenixBIOS 4.0 Release 6.0 - Revision 01/21/98", .internal_name = "m7shi_4", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 262144, .files = { "roms/machines/m7shi/M7ns04.rom", "" } },
{ .files_no = 0 }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t m7shi_device = {
.name = "Micronics M7S-Hi",
.internal_name = "m7shi_device",
.flags = 0,
.local = 0,
.init = NULL,
.close = NULL,
.reset = NULL,
.available = NULL,
.speed_changed = NULL,
.force_redraw = NULL,
.config = m7shi_config
};
int
machine_at_m7shi_init(const machine_t *model)
{
int ret;
int ret = 0;
const char* fn;
ret = bios_load_linear("roms/machines/m7shi/m7shi2n.rom",
0x000c0000, 262144, 0);
if (bios_only || !ret)
/* No ROMs available */
if (!device_available(model->device))
return ret;
device_context(model->device);
fn = device_get_bios_file(machine_get_device(machine), device_get_config_bios("bios"), 0);
ret = bios_load_linear(fn, 0x000c0000, 262144, 0);
device_context_restore();
machine_at_common_init_ex(model, 2);
pci_init(PCI_CONFIG_TYPE_1);
@@ -456,6 +502,9 @@ machine_at_pcv90_init(const machine_t *model)
device_add_params(&pc87306_device, (void *) PCX730X_AMI);
device_add(&intel_flash_bxt_ami_device);
if (sound_card_current[0] == SOUND_INTERNAL)
machine_snd = device_add(machine_get_snd_device(machine));
return ret;
}

14
src/machine/machine_table.c
View File

@@ -14075,7 +14075,7 @@ const machine_t machines[] = {
.max_multi = 3.5
},
.bus_flags = MACHINE_PS2_PCI | MACHINE_BUS_USB,
.flags = MACHINE_VIDEO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_GAMEPORT | MACHINE_USB, /* Has internal sound: Yamaha YMF701-S */
.flags = MACHINE_VIDEO | MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_SOUND | MACHINE_GAMEPORT | MACHINE_USB, /* Has internal sound: Yamaha YMF701-S */
.ram = {
.min = 8192,
.max = 524288,
@@ -14094,7 +14094,7 @@ const machine_t machines[] = {
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = &s3_virge_375_pci_device,
.snd_device = NULL,
.snd_device = &ymf701_device,
.net_device = NULL
},
/* Has a SM(S)C FDC37C935 Super I/O chip with on-chip KBC with Phoenix
@@ -14134,7 +14134,7 @@ const machine_t machines[] = {
.kbc_p1 = 0x00000cf0,
.gpio = 0xffffffff,
.gpio_acpi = 0xffffffff,
.device = NULL,
.device = &m7shi_device,
.kbd_device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
@@ -14212,7 +14212,7 @@ const machine_t machines[] = {
.max_multi = 3.0
},
.bus_flags = MACHINE_PS2_PCI,
.flags = MACHINE_IDE_DUAL | MACHINE_APM, /* Machine has internal video: ATI Mach64GT-B 3D Rage II */
.flags = MACHINE_IDE_DUAL | MACHINE_APM | MACHINE_SOUND | MACHINE_GAMEPORT, /* Machine has internal video: ATI Mach64GT-B 3D Rage II */
.ram = {
.min = 8192,
.max = 524288,
@@ -14231,7 +14231,7 @@ const machine_t machines[] = {
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.snd_device = &ymf701_device,
.net_device = NULL
},
/* [TEST] The board doesn't seem to have a KBC at all, which probably means it's an on-chip one on the PC87306 SIO.
@@ -19589,11 +19589,7 @@ machine_get_min_ram(int m)
int
machine_get_max_ram(int m)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
return MIN(((int) machines[m].ram.max), 2097152);
#else
return MIN(((int) machines[m].ram.max), 3145728);
#endif
}
int

177
src/mem/mem.c
View File

@@ -67,9 +67,6 @@ mem_mapping_t bios_mapping;
mem_mapping_t bios_high_mapping;
page_t *pages; /* RAM page table */
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
page_t **page_lookup; /* pagetable lookup */
#endif
uint32_t pages_sz; /* #pages in table */
uint8_t *ram; /* the virtual RAM */
@@ -87,23 +84,16 @@ uint8_t *pccache2;
int readlnext;
int readlookup[256];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uintptr_t *readlookup2;
#endif
uintptr_t old_rl2;
uint8_t uncached = 0;
int writelnext;
int writelookup[256];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uintptr_t *writelookup2;
#endif
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
/* The lookup tables. */
page_t *page_lookup[1048576] = { 0 };
uintptr_t readlookup2[1048576] = { 0 };
uintptr_t writelookup2[1048576] = { 0 };
#endif
uint32_t mem_logical_addr;
@@ -147,12 +137,7 @@ static uint8_t ff_pccache[4] = { 0xff, 0xff, 0xff, 0xff };
static mem_state_t _mem_state[MEM_MAPPINGS_NO];
static uint32_t remap_start_addr;
static uint32_t remap_start_addr2;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
static size_t ram_size = 0;
static size_t ram2_size = 0;
#else
static size_t ram_size = 0;
#endif
#ifdef ENABLE_MEM_LOG
int mem_do_log = ENABLE_MEM_LOG;
@@ -274,24 +259,10 @@ void
mem_flush_write_page(uint32_t addr, uint32_t virt)
{
const page_t *page_target = &pages[addr >> 12];
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
for (uint16_t c = 0; c < 256; c++) {
if (writelookup[c] != (int) 0xffffffff) {
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
uintptr_t target = (uintptr_t) &ram[(uintptr_t) (addr & ~0xfff) - (virt & ~0xfff)];
#else
a = (uintptr_t) (addr & ~0xfff) - (virt & ~0xfff);
uintptr_t target;
if ((addr & ~0xfff) >= (1 << 30))
target = (uintptr_t) &ram2[a - (1 << 30)];
else
target = (uintptr_t) &ram[a];
#endif
if (writelookup2[writelookup[c]] == target || page_lookup[writelookup[c]] == page_target) {
writelookup2[writelookup[c]] = LOOKUP_INV;
page_lookup[writelookup[c]] = NULL;
@@ -599,10 +570,6 @@ mem_addr_translate(uint32_t addr, uint32_t chunk_start, uint32_t len)
void
addreadlookup(uint32_t virt, uint32_t phys)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
if (virt == 0xffffffff)
return;
@@ -615,16 +582,7 @@ addreadlookup(uint32_t virt, uint32_t phys)
readlookup2[readlookup[readlnext]] = LOOKUP_INV;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
readlookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)];
#else
a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff));
if ((phys & ~0xfff) >= (1 << 30))
readlookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)];
else
readlookup2[virt >> 12] = (uintptr_t) &ram[a];
#endif
readlookup[readlnext++] = virt >> 12;
readlnext &= (cachesize - 1);
@@ -635,10 +593,6 @@ addreadlookup(uint32_t virt, uint32_t phys)
void
addwritelookup(uint32_t virt, uint32_t phys)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
uint32_t a;
#endif
if (virt == 0xffffffff)
return;
@@ -665,16 +619,8 @@ addwritelookup(uint32_t virt, uint32_t phys)
#endif
page_lookup[virt >> 12] = &pages[phys >> 12];
} else {
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
writelookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)];
#else
a = ((uint32_t) (phys & ~0xfff) - (uint32_t) (virt & ~0xfff));
if ((phys & ~0xfff) >= (1 << 30))
writelookup2[virt >> 12] = (uintptr_t) &ram2[a - (1 << 30)];
else
writelookup2[virt >> 12] = (uintptr_t) &ram[a];
#endif
writelookup2[virt >> 12] = (uintptr_t) &ram[(uintptr_t) (phys & ~0xFFF) - (uintptr_t) (virt & ~0xfff)];
}
writelookup[writelnext++] = virt >> 12;
@@ -687,9 +633,7 @@ uint8_t *
getpccache(uint32_t a)
{
uint64_t a64 = (uint64_t) a;
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
uint8_t *p;
#endif
uint32_t a2;
a2 = a;
@@ -710,12 +654,8 @@ getpccache(uint32_t a)
cpu_prefetch_cycles = cpu_mem_prefetch_cycles;
}
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
p = &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t) (a64 & MEM_GRANULARITY_PAGE) - (uintptr_t) (a2 & ~0xfff)];
return (uint8_t *) (((uintptr_t) p & 0x00000000ffffffffULL) | ((uintptr_t) &_mem_exec[a64 >> MEM_GRANULARITY_BITS][0] & 0xffffffff00000000ULL));
#else
return &_mem_exec[a64 >> MEM_GRANULARITY_BITS][(uintptr_t) (a64 & MEM_GRANULARITY_PAGE) - (uintptr_t) (a2 & ~0xfff)];
#endif
}
mem_log("Bad getpccache %08X%08X\n", (uint32_t) (a64 >> 32), (uint32_t) (a64 & 0xffffffffULL));
@@ -2771,11 +2711,6 @@ mem_init_ram_mapping(mem_mapping_t *mapping, uint32_t base, uint32_t size)
void
mem_zero(void)
{
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576)
memset(ram2, 0x00, ram2_size + 16);
#endif
memset(ram, 0x00, ram_size + 16);
}
@@ -2810,55 +2745,17 @@ mem_reset(void)
ram = NULL;
ram_size = 0;
}
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (ram2 != NULL) {
plat_munmap(ram2, ram2_size);
ram2 = NULL;
ram2_size = 0;
}
if (mem_size > 2097152)
mem_size = 2097152;
#endif
m = 1024UL * (size_t) mem_size;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
ram_size = 1 << 30;
ram = (uint8_t *) plat_mmap(ram_size, 0); /* allocate and clear the RAM block of the first 1 GB */
if (ram == NULL) {
fatal("Failed to allocate primary RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram, 0x00, ram_size);
ram2_size = m - (1 << 30);
/* Allocate 16 extra bytes of RAM to mitigate some dynarec recompiler memory access quirks. */
ram2 = (uint8_t *) plat_mmap(ram2_size + 16, 0); /* allocate and clear the RAM block above 1 GB */
if (ram2 == NULL) {
if (config_changed == 2)
fatal(EMU_NAME " must be restarted for the memory amount change to be applied.\n");
else
fatal("Failed to allocate secondary RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram2, 0x00, ram2_size + 16);
} else
#endif
{
ram_size = m;
/* Allocate 16 extra bytes of RAM to mitigate some dynarec recompiler memory access quirks. */
ram = (uint8_t *) plat_mmap(ram_size + 16, 0); /* allocate and clear the RAM block */
if (ram == NULL) {
fatal("Failed to allocate RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram, 0x00, ram_size + 16);
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576)
ram2 = &(ram[1 << 30]);
#endif
ram_size = m;
/* Allocate 16 extra bytes of RAM to mitigate some dynarec recompiler memory access quirks. */
ram = (uint8_t *) plat_mmap(ram_size + 16, 0); /* allocate and clear the RAM block */
if (ram == NULL) {
fatal("Failed to allocate RAM block. Make sure you have enough RAM available.\n");
return;
}
memset(ram, 0x00, ram_size + 16);
/*
* Allocate the page table based on how much RAM we have.
@@ -2905,17 +2802,8 @@ mem_reset(void)
if ((c << 12) >= (mem_size << 10))
pages[c].mem = page_ff;
else {
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
if ((c << 12) < (1 << 30))
pages[c].mem = &ram[c << 12];
else
pages[c].mem = &ram2[(c << 12) - (1 << 30)];
} else
pages[c].mem = &ram[c << 12];
#else
pages[c].mem = &ram[c << 12];
#endif
}
if (c < m) {
pages[c].write_b = mem_write_ramb_page;
@@ -2951,22 +2839,7 @@ mem_reset(void)
else if (cpu_16bitbus && is6117 && mem_size > 65408)
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (65408 - 1024) * 1024);
else {
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (1048576 - 1024) * 1024);
mem_set_mem_state_both((1 << 30), (mem_size - 1048576) * 1024,
MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
mem_mapping_add(&ram_2gb_mapping, (1 << 30),
((mem_size - 1048576) * 1024),
mem_read_ram_2gb, mem_read_ram_2gbw, mem_read_ram_2gbl,
mem_write_ram, mem_write_ramw, mem_write_raml,
ram2, MEM_MAPPING_INTERNAL, NULL);
} else
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024);
#else
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024);
#endif
mem_init_ram_mapping(&ram_high_mapping, 0x100000, (mem_size - 1024) * 1024);
}
}
@@ -3005,26 +2878,8 @@ mem_init(void)
ram = rom = NULL;
ram2 = NULL;
pages = NULL;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
/* Allocate the lookup tables. */
page_lookup = (page_t **) malloc((1 << 20) * sizeof(page_t *));
readlookup2 = malloc((1 << 20) * sizeof(uintptr_t));
writelookup2 = malloc((1 << 20) * sizeof(uintptr_t));
#endif
}
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
void
mem_free(void)
{
free(page_lookup);
free(readlookup2);
free(writelookup2);
}
#endif
static void
umc_page_recalc(uint32_t c, uint32_t phys, int set)
{
@@ -3125,17 +2980,7 @@ mem_remap_top_ex_common(int kb, uint32_t start, int mid)
if (sis_mode || ((c << 12) >= (mem_size << 10)))
pages[c].mem = page_ff;
else {
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576) {
if ((c << 12) < (1 << 30))
pages[c].mem = &ram[c << 12];
else
pages[c].mem = &ram2[(c << 12) - (1 << 30)];
} else
pages[c].mem = &ram[c << 12];
#else
pages[c].mem = &ram[c << 12];
#endif
}
if (!sis_mode && (c < addr_space_size)) {
pages[c].write_b = mem_write_ramb_page;

22
src/mem/row.c
View File

@@ -155,18 +155,9 @@ row_allocate(uint8_t row_id, uint8_t set)
mem_mapping_set_exec(&rows[row_id].mapping, rows[row_id].buf + rows[row_id].ram_base);
mem_mapping_set_mask(&rows[row_id].mapping, rows[row_id].ram_mask);
if ((rows[row_id].host_base == rows[row_id].ram_base) && (rows[row_id].host_size == rows[row_id].ram_size)) {
#if (defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64)
mem_mapping_set_handler(&rows[row_id].mapping, mem_read_ram,mem_read_ramw,mem_read_raml,
mem_write_ram,mem_write_ramw,mem_write_raml);
#else
if (rows[row_id].buf == ram2) {
mem_mapping_set_handler(&rows[row_id].mapping, mem_read_ram_2gb,mem_read_ram_2gbw,mem_read_ram_2gbl,
mem_write_ram,mem_write_ramw,mem_write_raml);
} else {
mem_mapping_set_handler(&rows[row_id].mapping, mem_read_ram,mem_read_ramw,mem_read_raml,
mem_write_ram,mem_write_ramw,mem_write_raml);
}
#endif
} else {
mem_mapping_set_handler(&rows[row_id].mapping, row_read, row_readw, row_readl,
row_write, row_writew, row_writel);
@@ -268,10 +259,6 @@ row_init(const device_t *info)
mem_mapping_disable(&ram_low_mapping);
mem_mapping_disable(&ram_mid_mapping);
mem_mapping_disable(&ram_high_mapping);
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (mem_size > 1048576)
mem_mapping_disable(&ram_2gb_mapping);
#endif
for (uint32_t c = 0; c < pages_sz; c++) {
pages[c].mem = page_ff;
@@ -303,12 +290,7 @@ row_init(const device_t *info)
rows[i].ram_size -= rows[i].ram_base;
rows[i].buf = ram;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (rows[i].ram_base >= (1 << 30)) {
rows[i].ram_base -= (1 << 30);
rows[i].buf = ram2;
}
#endif
rows[i].ram_mask = rows[i].ram_size - 1;

15
src/mem/smram.c
View File

@@ -59,11 +59,6 @@ smram_read(uint32_t addr, void *priv)
const smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (new_addr >= (1 << 30))
return mem_read_ram_2gb(new_addr, priv);
else
#endif
if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_ram(new_addr, priv);
else
@@ -76,11 +71,6 @@ smram_readw(uint32_t addr, void *priv)
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (new_addr >= (1 << 30))
return mem_read_ram_2gbw(new_addr, priv);
else
#endif
if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_ramw(new_addr, priv);
else
@@ -93,11 +83,6 @@ smram_readl(uint32_t addr, void *priv)
smram_t *dev = (smram_t *) priv;
uint32_t new_addr = addr - dev->host_base + dev->ram_base;
#if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
if (new_addr >= (1 << 30))
return mem_read_ram_2gbl(new_addr, priv);
else
#endif
if (!use_separate_smram || (new_addr >= 0xa0000))
return mem_read_raml(new_addr, priv);
else

9
src/printer/prt_ps.c
View File

@@ -48,13 +48,8 @@
#define gs_error_Quit -101
#ifdef _WIN32
# if (!(defined __amd64__ || defined _M_X64 || defined __aarch64__ || defined _M_ARM64))
# define PATH_GHOSTSCRIPT_DLL "gsdll32.dll"
# define PATH_GHOSTPCL_DLL "gpcl6dll32.dll"
# else
# define PATH_GHOSTSCRIPT_DLL "gsdll64.dll"
# define PATH_GHOSTPCL_DLL "gpcl6dll64.dll"
# endif
# define PATH_GHOSTSCRIPT_DLL "gsdll64.dll"
# define PATH_GHOSTPCL_DLL "gpcl6dll64.dll"
#elif defined __APPLE__
# define PATH_GHOSTSCRIPT_DLL "libgs.dylib"
# define PATH_GHOSTPCL_DLL "libgpcl6.9.54.dylib"

6
src/qt/qt_main.cpp
View File

@@ -515,6 +515,8 @@ main_thread_fn()
static std::thread *main_thread;
QTimer discordupdate;
#ifdef Q_OS_WINDOWS
WindowsDarkModeFilter* vmm_dark_mode_filter = nullptr;
#endif
@@ -865,7 +867,6 @@ main(int argc, char *argv[])
onesec.start(1000);
#ifdef DISCORD
QTimer discordupdate;
if (discord_loaded) {
QTimer::singleShot(1000, &app, [] {
if (enable_discord) {
@@ -877,7 +878,8 @@ main(int argc, char *argv[])
QObject::connect(&discordupdate, &QTimer::timeout, &app, [] {
discord_run_callbacks();
});
discordupdate.start(1000);
if (enable_discord)
discordupdate.start(1000);
}
#endif

5
src/qt/qt_mainwindow.cpp
View File

@@ -2344,8 +2344,11 @@ MainWindow::on_actionEnable_Discord_integration_triggered(bool checked)
if (enable_discord) {
discord_init();
discord_update_activity(dopause);
} else
discordupdate.start(1000);
} else {
discord_close();
discordupdate.stop();
}
#endif
}

2
src/qt/qt_mainwindow.hpp
View File

@@ -15,6 +15,8 @@
#include "qt_vmmanager_protocol.hpp"
extern QTimer discordupdate;
class MediaMenu;
class RendererStack;

8
src/qt/qt_openglrenderer.cpp
View File

@@ -1708,15 +1708,15 @@ OpenGLRenderer::render()
plat_tempfile(fn, NULL, (char*)".png");
strcat(path, fn);
unsigned char *rgba = (unsigned char *) calloc(1, (size_t) width * height * 4);
unsigned char *rgb = (unsigned char *) calloc(1, (size_t) width * height * 3);
glw.glFinish();
glw.glReadPixels(window_rect.x, window_rect.y, width, height, GL_RGBA, GL_UNSIGNED_BYTE, rgba);
glw.glReadPixels(window_rect.x, window_rect.y, width, height, GL_RGB, GL_UNSIGNED_BYTE, rgb);
QImage image(rgba, width, height, QImage::Format_RGBA8888);
QImage image(rgb, width, height, QImage::Format_RGB888);
image.mirrored(false, true).save(path, "png");
monitors[r_monitor_index].mon_screenshots--;
free(rgba);
free(rgb);
}
glw.glDisable(GL_FRAMEBUFFER_SRGB);

9
src/qt/qt_platform.cpp
View File

@@ -614,13 +614,8 @@ c16stombs(char dst[], const uint16_t src[], int len)
#endif
#ifdef _WIN32
# if defined(__amd64__) || defined(_M_X64) || defined(__aarch64__) || defined(_M_ARM64)
# define LIB_NAME_GS "gsdll64.dll"
# define LIB_NAME_GPCL "gpcl6dll64.dll"
# else
# define LIB_NAME_GS "gsdll32.dll"
# define LIB_NAME_GPCL "gpcl6dll32.dll"
# endif
# define LIB_NAME_GS "gsdll64.dll"
# define LIB_NAME_GPCL "gpcl6dll64.dll"
# define LIB_NAME_PCAP "Npcap"
#else
# define LIB_NAME_GS "libgs"

5
src/qt/qt_softwarerenderer.cpp
View File

@@ -59,13 +59,12 @@ SoftwareRenderer::onBlit(int buf_idx, int x, int y, int w, int h)
{
/* TODO: should look into deleteLater() */
auto tval = this;
void *nuldata = 0;
if (memcmp(&tval, &nuldata, sizeof(void *)) == 0)
if ((void *) tval == nullptr)
return;
auto origSource = source;
cur_image = buf_idx;
buf_usage[(buf_idx + 1) % 2].clear();
buf_usage[buf_idx ^ 1].clear();
source.setRect(x, y, w, h);

1
src/sound/CMakeLists.txt
View File

@@ -51,6 +51,7 @@ add_library(snd OBJECT
snd_ym7128.c
snd_optimc.c
snd_opl_esfm.c
snd_ymf701.c
)
# TODO: Should platform-specific audio driver be here?

29
src/sound/snd_ad1848.c
View File

@@ -285,6 +285,7 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
ad1848_t *ad1848 = (ad1848_t *) priv;
uint8_t temp = 0;
uint8_t updatefreq = 0;
double i8_timebase = 0;
switch (addr & 3) {
case 0: /* Index */
@@ -344,6 +345,21 @@ ad1848_write(uint16_t addr, uint8_t val, void *priv)
ad1848->count = ad1848->regs[15] | (val << 8);
break;
case 16:
if ((ad1848->type >= AD1848_TYPE_CS4231) && (ad1848->type < AD1848_TYPE_CS4235)) {
if (val & 0x40) {
ad1848_log("Timer Enable\n");
ad1848_log("Timer value: %04X\n", ((ad1848->regs[21] << 8) + (ad1848->regs[20])));
i8_timebase = (ad1848->regs[8] & 1) ? 9.92 : 9.969;
timer_set_delay_u64(&ad1848->cs4231a_irq_timer, (((ad1848->regs[21] << 8) + (ad1848->regs[20])) * i8_timebase * TIMER_USEC));
}
else {
ad1848_log("Timer Disable\n");
timer_disable(&ad1848->cs4231a_irq_timer);
}
}
break;
case 18 ... 19:
if (ad1848->type >= AD1848_TYPE_CS4236B) {
if (ad1848->type >= AD1848_TYPE_CS4235) {
@@ -746,6 +762,16 @@ ad1848_poll(void *priv)
}
}
void
cs4231a_irq_poll(void *priv)
{
ad1848_t *ad1848 = (ad1848_t *) priv;
ad1848_log("Firing timer IRQ\n");
picint(1 << ad1848->irq);
ad1848_log("Setting timer interrupt bit in I24\n");
ad1848->regs[24] |= 0x40;
}
void
ad1848_set_cd_audio_channel(void *priv, int channel)
{
@@ -910,4 +936,7 @@ ad1848_init(ad1848_t *ad1848, uint8_t type)
if ((ad1848->type != AD1848_TYPE_DEFAULT) && (ad1848->type != AD1848_TYPE_CS4248))
sound_set_cd_audio_filter(ad1848_filter_cd_audio, ad1848);
if ((ad1848->type >= AD1848_TYPE_CS4231) && (ad1848->type < AD1848_TYPE_CS4235))
timer_add(&ad1848->cs4231a_irq_timer, cs4231a_irq_poll, ad1848, 0);
}

519
src/sound/snd_ymf701.c Normal file
View File

@@ -0,0 +1,519 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Yamaha YMF-701 (OPL3-SA) audio controller emulation.
*
*
*
* Authors: Cacodemon345
* Eluan Costa Miranda <eluancm@gmail.com>
* win2kgamer
*
* Copyright 2022 Cacodemon345.
* Copyright 2020 Eluan Costa Miranda.
* Copyright 2025 win2kgamer
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/midi.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/sound.h>
#include <86box/gameport.h>
#include <86box/snd_ad1848.h>
#include <86box/snd_sb.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/plat_unused.h>
#include <86box/log.h>
#ifdef ENABLE_YMF701_LOG
int ymf701_do_log = ENABLE_YMF701_LOG;
static void
ymf701_log(void *priv, const char *fmt, ...)
{
if (ymf701_do_log) {
va_list ap;
va_start(ap, fmt);
log_out(priv, fmt, ap);
va_end(ap);
}
}
#else
# define ymf701_log(fmt, ...)
#endif
static int ymf701_wss_dma[4] = { 0, 0, 1, 3 };
static int ymf701_wss_irq[8] = { 0, 7, 9, 10, 11, 0, 0, 0 };
typedef struct ymf701_t {
uint8_t type;
uint8_t wss_config;
uint8_t reg_enabled;
uint16_t cur_sb_addr;
uint16_t cur_wss_addr;
uint16_t cur_mpu401_addr;
int cur_sb_irq;
int cur_sb_dma;
int cur_wss_enabled;
int cur_wss_irq;
int cur_wss_dma;
int cur_mpu401_irq;
int cur_mpu401_enabled;
void *gameport;
uint8_t cur_mode;
ad1848_t ad1848;
mpu_t *mpu;
sb_t *sb;
uint8_t index;
uint8_t regs[6];
uint8_t passwd_phase;
void * log; /* New logging system */
} ymf701_t;
static void
ymf701_filter_opl(void *priv, double *out_l, double *out_r)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
if (ymf701->cur_wss_enabled) {
ad1848_filter_channel((void *) &ymf701->ad1848, AD1848_AUX2, out_l, out_r);
}
}
static uint8_t
ymf701_wss_read(uint16_t addr, void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
uint8_t ret = 0x00;
uint8_t port = addr - ymf701->cur_wss_addr;
switch (port) {
case 0:
ret = ymf701->wss_config;
break;
case 3:
ret = 0x04 | (ymf701->wss_config & 0x40);
break;
default:
ret = ymf701->wss_config;
break;
}
ymf701_log(ymf701->log, "WSS Read: addr = %02X, val = %02X\n", addr, ret);
return ret;
}
static void
ymf701_wss_write(uint16_t addr, uint8_t val, void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
uint8_t port = addr - ymf701->cur_wss_addr;
ymf701_log(ymf701->log, "WSS Write: addr = %02X, val = %02X\n", addr, val);
switch (port) {
case 0:
ymf701->wss_config = val;
ymf701->cur_wss_dma = ymf701_wss_dma[val & 3];
ymf701->cur_wss_irq = ymf701_wss_irq[(val >> 3) & 7];
ad1848_setdma(&ymf701->ad1848, ymf701_wss_dma[val & 3]);
ad1848_setirq(&ymf701->ad1848, ymf701_wss_irq[(val >> 3) & 7]);
ymf701_log(ymf701->log, "Set IRQ to %02X\n", ymf701->cur_wss_irq);
ymf701_log(ymf701->log, "Set DMA to %02X\n", ymf701->cur_wss_dma);
break;
default:
break;
}
}
static void
ymf701_get_buffer(int32_t *buffer, int len, void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
/* wss part */
ad1848_update(&ymf701->ad1848);
for (int c = 0; c < len * 2; c++)
buffer[c] += (ymf701->ad1848.buffer[c] / 2);
ymf701->ad1848.pos = 0;
/* sbprov2 part */
sb_get_buffer_sbpro(buffer, len, ymf701->sb);
}
static void
ymf701_remove_opl(ymf701_t *ymf701)
{
io_removehandler(ymf701->cur_sb_addr + 0, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_removehandler(ymf701->cur_sb_addr + 8, 0x0002, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_removehandler(0x0388, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
}
static void
ymf701_add_opl(ymf701_t *ymf701)
{
/* DSP I/O handler is activated in sb_dsp_setaddr */
io_sethandler(ymf701->cur_sb_addr + 0, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_sethandler(ymf701->cur_sb_addr + 8, 0x0002, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_sethandler(0x0388, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
}
static void
ymf701_reg_write(uint16_t addr, uint8_t val, void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
if (ymf701->reg_enabled) {
ymf701_log(ymf701->log, "Write with reg access enabled:\n");
ymf701_log(ymf701->log, "addr = %02X, val = %02X\n", addr, val);
switch (addr) {
case 0xF86:
ymf701->index = val;
ymf701->passwd_phase = 0x01;
ymf701_log(ymf701->log, "Passwd phase 1\n");
break;
case 0xF87:
switch (ymf701->index) {
case 0x01: /* WSS Config */
ymf701->regs[0x01] = val;
ymf701->cur_mode = ymf701->cur_wss_enabled = !!(val & 0x20);
sound_set_cd_audio_filter(NULL, NULL);
if (ymf701->cur_wss_enabled) /* WSS */
sound_set_cd_audio_filter(ad1848_filter_cd_audio, &ymf701->ad1848);
else /* SBPro */
sound_set_cd_audio_filter(sbpro_filter_cd_audio, ymf701->sb);
io_removehandler(ymf701->cur_wss_addr, 0x0004, ymf701_wss_read, NULL, NULL, ymf701_wss_write, NULL, NULL, ymf701);
io_removehandler(ymf701->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &ymf701->ad1848);
switch ((val >> 3) & 0x3) {
case 0: /* WSBase = 0x530 */
ymf701_log(ymf701->log, "WSS base is now 530h\n");
ymf701->cur_wss_addr = 0x530;
break;
case 1: /* WSBase = 0xE80 */
ymf701_log(ymf701->log, "WSS base is now E80h\n");
ymf701->cur_wss_addr = 0xE80;
break;
case 2: /* WSBase = 0xF40 */
ymf701_log(ymf701->log, "WSS base is now F40h\n");
ymf701->cur_wss_addr = 0xF40;
break;
case 3: /* WSBase = 0x604 */
ymf701_log(ymf701->log, "WSS base is now 604h\n");
ymf701->cur_wss_addr = 0x604;
break;
default:
break;
}
io_sethandler(ymf701->cur_wss_addr, 0x0004, ymf701_wss_read, NULL, NULL, ymf701_wss_write, NULL, NULL, ymf701);
io_sethandler(ymf701->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &ymf701->ad1848);
break;
case 0x02: /* SB Config */
ymf701->regs[0x02] = val;
io_removehandler(ymf701->cur_sb_addr + 4, 0x0002, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, ymf701->sb);
ymf701_remove_opl(ymf701);
ymf701->cur_sb_addr = (val & 0x20) ? 0x240 : 0x220;
switch (val & 0x3) {
case 0:
ymf701->cur_sb_dma = -1;
break;
case 1:
ymf701->cur_sb_dma = 0;
break;
case 2:
ymf701->cur_sb_dma = 1;
break;
case 3:
ymf701->cur_sb_dma = 3;
break;
}
switch ((val >> 2) & 0x7) {
case 0:
ymf701->cur_sb_irq = -1;
break;
case 1:
ymf701->cur_sb_irq = 5;
break;
case 2:
ymf701->cur_sb_irq = 7;
break;
case 3:
ymf701->cur_sb_irq = 9;
break;
case 4:
ymf701->cur_sb_irq = 10;
break;
case 5:
ymf701->cur_sb_irq = 11;
break;
default:
break;
}
sb_dsp_setaddr(&ymf701->sb->dsp, ymf701->cur_sb_addr);
sb_dsp_setirq(&ymf701->sb->dsp, ymf701->cur_sb_irq);
sb_dsp_setdma8(&ymf701->sb->dsp, ymf701->cur_sb_dma);
ymf701_add_opl(ymf701);
if (ymf701->cur_sb_addr != 0x00)
io_sethandler(ymf701->cur_sb_addr + 4, 0x0002, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, ymf701->sb);
break;
case 0x03: /* MPU/OPL/Gameport Config */
ymf701->regs[0x03] = val;
switch ((val >> 2) & 0x7) {
case 0:
ymf701->cur_mpu401_irq = -1;
break;
case 1:
ymf701->cur_mpu401_irq = 5;
break;
case 2:
ymf701->cur_mpu401_irq = 7;
break;
case 3:
ymf701->cur_mpu401_irq = 9;
break;
case 4:
ymf701->cur_mpu401_irq = 10;
break;
default:
break;
}
switch ((val >> 5) & 0x3) {
case 0:
ymf701->cur_mpu401_addr = 0x330;
break;
case 1:
ymf701->cur_mpu401_addr = 0x332;
break;
case 2:
ymf701->cur_mpu401_addr = 0x334;
break;
case 3:
ymf701->cur_mpu401_addr = 0x300;
break;
default:
break;
}
mpu401_change_addr(ymf701->mpu, ymf701->cur_mpu401_addr);
mpu401_setirq(ymf701->mpu, ymf701->cur_mpu401_irq);
gameport_remap(ymf701->gameport, (ymf701->regs[3] & 0x1) ? 0x200 : 0x00);
break;
case 0x04: /* LSI Version Register, on a real Intel Ruby board this is always 0 */
break;
default:
break;
}
ymf701->passwd_phase = 0x02;
ymf701_log(ymf701->log, "Passwd phase 2\n");
default:
break;
}
}
ymf701_log(ymf701->log, "Write: addr = %02X, val = %02X\n", addr, val);
if ((ymf701->reg_enabled) && (ymf701->passwd_phase == 0x02)) {
ymf701->reg_enabled = 0;
ymf701->passwd_phase = 0x00;
ymf701_log(ymf701->log, "Disabling reg access\n");
}
if ((addr == 0xF86) && (val == 0x1D) && (!ymf701->reg_enabled)) {
ymf701->reg_enabled = 1;
ymf701_log(ymf701->log, "Enabling reg access\n");
}
}
static uint8_t
ymf701_reg_read(uint16_t addr, void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
uint8_t temp = 0xFF;
if (ymf701->reg_enabled) {
switch (addr) {
case 0xF86:
temp = ymf701->index;
break;
case 0xF87:
temp = ymf701->regs[ymf701->index];
/* Only goes into phase 2 on data reads? */
ymf701->passwd_phase = 0x02;
ymf701_log(ymf701->log, "Passwd phase 2\n");
break;
default:
break;
}
ymf701_log(ymf701->log, "Read with reg access enabled:\n");
ymf701_log(ymf701->log, "addr = %02X, ret = %02X\n", addr, temp);
}
if ((ymf701->reg_enabled) && (ymf701->passwd_phase == 0x02)) {
ymf701->reg_enabled = 0;
ymf701->passwd_phase = 0x00;
ymf701_log(ymf701->log, "Disabling reg access\n");
}
ymf701_log(ymf701->log, "Read: addr = %02X, ret = %02X\n", addr, temp);
return temp;
}
static void *
ymf701_init(const device_t *info)
{
ymf701_t *ymf701 = calloc(1, sizeof(ymf701_t));
ymf701->type = info->local & 0xFF;
ymf701->cur_wss_addr = 0x530;
ymf701->cur_mode = 1;
ymf701->cur_sb_addr = 0x220;
ymf701->cur_sb_irq = 5;
ymf701->cur_wss_enabled = 1;
ymf701->cur_sb_dma = 1;
ymf701->cur_mpu401_irq = 9;
ymf701->cur_mpu401_addr = 0x330;
ymf701->cur_mpu401_enabled = 1;
ymf701->cur_wss_dma = 0;
ymf701->cur_wss_irq = 11;
/* Power-on default values are unknown, using BIOS-initialized values from an Intel Ruby board */
ymf701->regs[0] = 0xFF; /* Index 0 is unused, return 0xFF */
ymf701->regs[1] = 0x24;
ymf701->regs[2] = 0x46;
ymf701->regs[3] = 0x87;
ymf701->regs[4] = 0x00; /* LSI version register, always returns 0 */
ymf701->log = log_open("YMF701");
ymf701->gameport = gameport_add(&gameport_pnp_device);
gameport_remap(ymf701->gameport, (ymf701->regs[3] & 0x1) ? 0x200 : 0x00);
ad1848_init(&ymf701->ad1848, AD1848_TYPE_CS4231);
ad1848_setirq(&ymf701->ad1848, ymf701->cur_wss_irq);
ad1848_setdma(&ymf701->ad1848, ymf701->cur_wss_dma);
io_sethandler(0xF86, 2, ymf701_reg_read, NULL, NULL, ymf701_reg_write, NULL, NULL, ymf701);
io_sethandler(ymf701->cur_wss_addr, 0x0004, ymf701_wss_read, NULL, NULL, ymf701_wss_write, NULL, NULL, ymf701);
io_sethandler(ymf701->cur_wss_addr + 0x0004, 0x0004, ad1848_read, NULL, NULL, ad1848_write, NULL, NULL, &ymf701->ad1848);
ymf701->sb = calloc(1, sizeof(sb_t));
ymf701->sb->opl_enabled = 1;
sb_dsp_set_real_opl(&ymf701->sb->dsp, 1);
sb_dsp_init(&ymf701->sb->dsp, SBPRO2_DSP_302, SB_SUBTYPE_DEFAULT, ymf701);
sb_dsp_setaddr(&ymf701->sb->dsp, ymf701->cur_sb_addr);
sb_dsp_setirq(&ymf701->sb->dsp, ymf701->cur_sb_irq);
sb_dsp_setdma8(&ymf701->sb->dsp, ymf701->cur_sb_dma);
sb_ct1345_mixer_reset(ymf701->sb);
ymf701->sb->opl_mixer = ymf701;
ymf701->sb->opl_mix = ymf701_filter_opl;
fm_driver_get(FM_YMF262, &ymf701->sb->opl);
io_sethandler(ymf701->cur_sb_addr + 0, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_sethandler(ymf701->cur_sb_addr + 8, 0x0002, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_sethandler(0x0388, 0x0004, ymf701->sb->opl.read, NULL, NULL, ymf701->sb->opl.write, NULL, NULL, ymf701->sb->opl.priv);
io_sethandler(ymf701->cur_sb_addr + 4, 0x0002, sb_ct1345_mixer_read, NULL, NULL, sb_ct1345_mixer_write, NULL, NULL, ymf701->sb);
sound_add_handler(ymf701_get_buffer, ymf701);
music_add_handler(sb_get_music_buffer_sbpro, ymf701->sb);
ad1848_set_cd_audio_channel(&ymf701->ad1848, AD1848_AUX1);
sound_set_cd_audio_filter(ad1848_filter_cd_audio, &ymf701->ad1848);
ymf701->mpu = (mpu_t *) calloc(1, sizeof(mpu_t));
mpu401_init(ymf701->mpu, ymf701->cur_mpu401_addr, ymf701->cur_mpu401_irq, M_UART, device_get_config_int("receive_input401"));
if (device_get_config_int("receive_input"))
midi_in_handler(1, sb_dsp_input_msg, sb_dsp_input_sysex, &ymf701->sb->dsp);
return ymf701;
}
static void
ymf701_close(void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
if (ymf701->log != NULL) {
log_close(ymf701->log);
ymf701->log = NULL;
}
sb_close(ymf701->sb);
free(ymf701->mpu);
free(priv);
}
static void
ymf701_speed_changed(void *priv)
{
ymf701_t *ymf701 = (ymf701_t *) priv;
ad1848_speed_changed(&ymf701->ad1848);
sb_speed_changed(ymf701->sb);
}
static const device_config_t ymf701_config[] = {
// clang-format off
{
.name = "receive_input",
.description = "Receive MIDI input",
.type = CONFIG_BINARY,
.default_string = NULL,
.default_int = 1,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = { { 0 } }
},
{
.name = "receive_input401",
.description = "Receive MIDI input (MPU-401)",
.type = CONFIG_BINARY,
.default_string = NULL,
.default_int = 0,
.file_filter = NULL,
.spinner = { 0 },
.selection = { { 0 } },
.bios = { { 0 } }
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t ymf701_device = {
.name = "Yamaha YMF-701 (OPL3-SA)",
.internal_name = "ymf701",
.flags = DEVICE_ISA16,
.local = 0x00,
.init = ymf701_init,
.close = ymf701_close,
.reset = NULL,
.available = NULL,
.speed_changed = ymf701_speed_changed,
.force_redraw = NULL,
.config = ymf701_config
};

1
src/sound/sound.c
View File

@@ -167,6 +167,7 @@ static const SOUND_CARD sound_cards[] = {
{ &sb_vibra16s_device },
{ &sb_vibra16xv_device },
{ &wss_device },
{ &ymf701_device },
/* MCA */
{ &adlib_mca_device },
{ &ess_chipchat_16_mca_device },

16
src/sound/ymfm/ymfm_opl.cpp
View File

@@ -1716,15 +1716,15 @@ uint8_t ymf278b::read_status()
uint8_t ymf278b::read_data_pcm()
{
// read from PCM
if (bitfield(m_address, 9) != 0)
{
uint8_t result = m_pcm.read(m_address & 0xff);
if ((m_address & 0xff) == 0x02)
result |= 0x20;
return result;
if (bitfield(m_address, 9) != 0) {
auto ret = m_pcm.read(m_address & 0xff);
if (m_address == 0x202) {
ret &= ~0xe0;
ret |= 0x20;
}
return ret;
}
return 0;
return 0;
}

1
src/sound/ymfm/ymfm_pcm.cpp
View File

@@ -46,6 +46,7 @@ namespace ymfm
void pcm_registers::reset()
{
std::fill_n(&m_regdata[0], REGISTERS, 0);
m_regdata[0x02] = 0x20;
m_regdata[0xf8] = 0x1b;
}

4
src/unix/assets/86Box.spec
View File

@@ -15,7 +15,7 @@
%global romver 4.1
Name: 86Box
Version: 6.0
Version: 5.2
Release: 1%{?dist}
Summary: Classic PC emulator
License: GPLv2+
@@ -121,5 +121,5 @@ popd
%{_datadir}/%{name}/roms
%changelog
* Sat Aug 31 Jasmine Iwanek <jriwanek[AT]gmail.com> 6.0-1
* Sat Aug 31 Jasmine Iwanek <jriwanek[AT]gmail.com> 5.2-1
- Bump release

2
src/unix/assets/net.86box.86Box.metainfo.xml
View File

@@ -11,7 +11,7 @@
</categories>
<launchable type="desktop-id">net.86box.86Box.desktop</launchable>
<releases>
<release version="6.0" date="2025-09-14"/>
<release version="5.2" date="2025-09-18"/>
</releases>
<content_rating type="oars-1.1" />
<description>

2
src/utils/random.c
View File

@@ -50,7 +50,7 @@ rotr32c(uint32_t x, uint32_t n)
static __inline unsigned long long
rdtsc(void)
{
#if defined(__i386__) || defined(__x86_64__)
#if defined(__x86_64__)
unsigned int hi;
unsigned int lo;
# ifdef _MSC_VER

19
src/video/clockgen/vid_clockgen_icd2061.c
View File

@@ -33,20 +33,9 @@
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_clockgen_icd2061.h>
#include <86box/plat_unused.h>
typedef struct icd2061_t {
float freq[3];
float ref_clock;
int count;
int bit_count;
int unlocked;
int state;
uint32_t data;
uint32_t ctrl;
} icd2061_t;
#ifdef ENABLE_ICD2061_LOG
int icd2061_do_log = ENABLE_ICD2061_LOG;
@@ -155,14 +144,12 @@ icd2061_getclock(int clock, void *priv)
}
void
icd2061_set_ref_clock(void *priv, svga_t *svga, float ref_clock)
icd2061_set_ref_clock(void *priv, float ref_clock)
{
icd2061_t *icd2061 = (icd2061_t *) priv;
if (icd2061)
if (icd2061 != NULL)
icd2061->ref_clock = ref_clock;
svga_recalctimings(svga);
}
static void *

21
src/video/ramdac/vid_ramdac_bt48x.c
View File

@@ -101,7 +101,7 @@ bt48x_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
case 0x03:
case 0x03: /* Palette Read Index Register (RS value = 0011) */
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
svga->dac_pos = 0;
svga->dac_status = addr & 0x03;
@@ -362,14 +362,21 @@ bt48x_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga)
void
bt48x_recalctimings(void *priv, svga_t *svga)
{
const bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
svga->interlace = ramdac->cmd_r2 & 0x08;
if (ramdac->cmd_r3 & 0x08) {
svga->hdisp <<= 1; /* x2 clock multiplier */
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
svga->interlace = !!(ramdac->cmd_r2 & 0x08);
svga->clock_multiplier = 0;
svga->multiplexing_rate = 0;
svga->true_color_bypass = 0;
if (ramdac->cmd_r3 & 0x08) { /* x2 clock multiplier */
//pclog("2x multiplier.\n");
svga->clock_multiplier = 1;
}
svga->multiplexing_rate = (ramdac->cmd_r1 & 0x60) >> 5;
if (svga->bpp >= 15)
svga->true_color_bypass = !!(ramdac->cmd_r1 & 0x10);
//pclog("CR0=%02x, CR1=%02x, CR2=%02x.\n", ramdac->cmd_r0, ramdac->cmd_r1, ramdac->cmd_r2);
}
void

4
src/video/ramdac/vid_ramdac_sc1502x.c
View File

@@ -44,6 +44,7 @@ static void
sc1502x_ramdac_bpp(sc1502x_ramdac_t *ramdac, svga_t *svga)
{
int oldbpp = svga->bpp;
//pclog("BPP Val=%02x, truecolortype=%02x.\n", ramdac->ctrl, ramdac->regs[0x10] & 0x01);
if (ramdac->ctrl & 0x80) {
if (ramdac->ctrl & 0x40) {
svga->bpp = 16;
@@ -60,6 +61,7 @@ sc1502x_ramdac_bpp(sc1502x_ramdac_t *ramdac, svga_t *svga)
} else
svga->bpp = 8;
}
//pclog("SVGA BPP=%d.\n", svga->bpp);
if (oldbpp != svga->bpp)
svga_recalctimings(svga);
}
@@ -135,9 +137,11 @@ sc1502x_rs2_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
//pclog("RS=%02x, Write=%02x.\n", rs, val);
switch (rs) {
case 0x00:
if (ramdac->ctrl & 0x10) {
//pclog("RAMDAC IDX=%02x, Write=%02x.\n", ramdac->idx, val);
switch (ramdac->idx) {
case 8:
ramdac->regs[8] = val;

19
src/video/vid_et4000w32.c
View File

@@ -2654,9 +2654,9 @@ et4000w32p_pci_read(UNUSED(int func), int addr, void *priv)
case 0x31:
return 0x00;
case 0x32:
return 0x00;
return et4000->pci_regs[0x32];
case 0x33:
return et4000->pci_regs[0x33] & 0xf0;
return et4000->pci_regs[0x33];
default:
break;
@@ -2695,20 +2695,13 @@ et4000w32p_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
break;
case 0x30:
case 0x31:
case 0x32:
case 0x33:
et4000->pci_regs[addr] = val;
et4000->pci_regs[0x30] = 1;
et4000->pci_regs[0x31] = 0;
et4000->pci_regs[0x32] = 0;
et4000->pci_regs[0x33] &= 0xf0;
if (et4000->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (et4000->pci_regs[0x33] << 24);
if (!biosaddr)
biosaddr = 0xc0000;
et4000w32_log("ET4000 bios_rom enabled at %08x\n", biosaddr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, biosaddr, 0x8000);
uint32_t addr = (et4000->pci_regs[0x32] << 16) | (et4000->pci_regs[0x33] << 24);
et4000w32_log("ET4000 bios_rom enabled at %08x\n", addr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, addr, 0x8000);
} else {
et4000w32_log("ET4000 bios_rom disabled\n");
mem_mapping_disable(&et4000->bios_rom.mapping);
@@ -2845,6 +2838,8 @@ et4000w32p_init(const device_t *info)
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&icd2061_device);
et4000->svga.getclock = icd2061_getclock;
icd2061_set_ref_clock(et4000->svga.ramdac, 14318184.0f);
svga_recalctimings(&et4000->svga);
break;
default:

6
src/video/vid_pcjr.c
View File

@@ -467,8 +467,10 @@ vid_render(pcjr_t *pcjr, int line, int ho_s, int ho_d)
dat = (pcjr->vram[((pcjr->memaddr << 1) & mask) + offset] << 8) |
pcjr->vram[((pcjr->memaddr << 1) & mask) + offset + 1];
pcjr->memaddr++;
for (uint8_t c = 0; c < 8; c++)
buffer32->line[line][ef_x + (c << 1)] = buffer32->line[line][ef_x + (c << 1) + 1] = dat <<= 2;
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[line][ef_x + (c << 1)] = buffer32->line[line][ef_x + (c << 1) + 1] = cols[dat >> 14];
dat <<= 2;
}
}
break;
case 0x102: /*640x200x2*/

513
src/video/vid_s3.c
View File

@@ -16,6 +16,7 @@
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
@@ -3000,6 +3001,8 @@ s3_out(uint16_t addr, uint8_t val, void *priv)
if (svga->getclock == icd2061_getclock) {
if (((val >> 2) & 3) != 3)
icd2061_write(svga->clock_gen, (val >> 2) & 3);
else
icd2061_write(svga->clock_gen, svga->crtc[0x42] & 0x0f);
}
break;
@@ -3026,7 +3029,9 @@ s3_out(uint16_t addr, uint8_t val, void *priv)
}
if (svga->seqaddr == 4) /*Chain-4 - update banking*/
{
if (val & 0x08)
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
if (svga->chain4)
svga->write_bank = svga->read_bank = s3->bank << 16;
else
svga->write_bank = svga->read_bank = s3->bank << 14;
@@ -3212,7 +3217,7 @@ s3_out(uint16_t addr, uint8_t val, void *priv)
svga->hwcursor.addr = ((((svga->crtc[0x4c] << 8) | svga->crtc[0x4d]) & 0xfff) * 1024) + (svga->hwcursor.yoff * 16);
if ((s3->chip >= S3_TRIO32) && (svga->bpp == 32))
svga->hwcursor.x <<= 1;
else if ((s3->chip >= S3_86C928 && s3->chip <= S3_86C805) && ((svga->bpp == 15) || (svga->bpp == 16))) {
else if ((s3->chip >= S3_86C928) && (s3->chip <= S3_86C805) && ((svga->bpp == 15) || (svga->bpp == 16))) {
if ((s3->card_type == S3_MIROCRYSTAL10SD_805) && !(svga->crtc[0x45] & 0x04) && (svga->bpp == 16))
svga->hwcursor.x >>= 2;
else
@@ -3787,7 +3792,6 @@ s3_recalctimings(svga_t *svga)
case 0xc0:
s3->width = 1280;
break;
default:
break;
}
@@ -3823,112 +3827,51 @@ s3_recalctimings(svga_t *svga)
if ((svga->crtc[0x3a] & 0x10) && !svga->lowres) {
s3_log("BPP=%d, pitch=%d, width=%02x, double?=%x, 16bit?=%d, highres?=%d, "
"attr=%02x, hdisp=%d.\n", svga->bpp, s3->width, svga->crtc[0x50],
svga->crtc[0x31] & 0x02, s3->color_16bit, s3->accel.advfunc_cntl & 4,
svga->attrregs[0x10] & 0x40, svga->hdisp);
"attr=%02x, hdisp=%d, dotsperclock=%x, clksel=%x, clockmultiplier=%d, multiplexingrate=%d.\n", svga->bpp, s3->width, svga->crtc[0x50],
svga->crtc[0x31] & 0x02, s3->color_16bit, s3->accel.advfunc_cntl & 0x04,
svga->attrregs[0x10] & 0x40, svga->hdisp, svga->dots_per_clock, clk_sel, svga->clock_multiplier, svga->multiplexing_rate);
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
switch (s3->chip) {
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
s3_log("928 8bpp: ClockSel=%02x, width=%d, hdisp=%d, dotsperclock=%d.\n", clk_sel, s3->width, svga->hdisp, svga->dots_per_clock);
switch (s3->width) {
case 1280: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case BT48X: /*BT485 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if ((svga->clock_multiplier == 1) || (s3->width >= 1024)) {
if (svga->multiplexing_rate == 2) {
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
} else {
if (!svga->clock_multiplier) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
}
break;
case 2048: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
svga->clock *= 2.0;
} else {
if (svga->multiplexing_rate == 0) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
break;
default:
break;
}
break;
case S3_ELSAWIN1K_86C928:
case S3_ELSAWIN2K_86C928:
switch (s3->width) {
case 1024:
switch (svga->hdisp) {
case 256:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 512:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
} else if (svga->getclock == ics2494_getclock) { /*ICS2494 clock chip*/
if (svga->clock_multiplier == 1) {
if (svga->multiplexing_rate == 2) {
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
}
break;
case 1280: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
svga->clock *= 2.0;
} else {
if (svga->multiplexing_rate == 2) {
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
svga->clock *= 4.0;
}
break;
case 2048: /*Account for the 1280x1024 resolution and the ELSA EEPROM resolutions*/
switch (svga->hdisp) {
case 320:
case 384:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 576:
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
if (s3->ramdac_type == BT48X) {
if (!svga->interlace) {
if (svga->dispend >= 1024) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
} else {
if (svga->dispend >= 512) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
}
}
break;
}
break;
default:
break;
}
}
break;
default:
@@ -3936,72 +3879,8 @@ s3_recalctimings(svga_t *svga)
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_ELSAWIN1KPCI_86C928:
switch (s3->width) {
case 1024:
switch (svga->hdisp) {
case 256:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 512:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
case 1280: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
case 2048: /*Account for the 1280x1024 resolution and the ELSA EEPROM resolutions*/
switch (svga->hdisp) {
case 320:
case 384:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 576:
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
default:
break;
}
if (!svga->chain4)
svga->chain4 |= 0x08;
break;
case S3_VISION964:
switch (s3->card_type) {
@@ -4126,69 +4005,82 @@ s3_recalctimings(svga_t *svga)
}
break;
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
if (!s3->color_16bit) {
s3_log("928 15bpp: ClockSel=%02x, width=%d, hdisp=%d, dotsperclock=%d.\n", clk_sel, s3->width, svga->hdisp, svga->dots_per_clock);
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
switch (svga->hdisp) { /*This might be a driver issue*/
case 800:
s3->width = 1024;
break;
case 1280:
s3->width = 2048;
break;
default:
break;
}
break;
case S3_ELSAWIN1K_86C928:
case S3_ELSAWIN2K_86C928:
switch (s3->width) {
case 2048:
if (s3->ramdac_type == SC1502X) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
} else {
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case BT48X: /*BT485 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if ((svga->clock_multiplier == 1) || (s3->width >= 1024)) {
if (svga->multiplexing_rate == 1) {
if (svga->true_color_bypass) {
if (svga->crtc[0x31] & 0x02) {
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
} else {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
svga->clock *= 2.0;
} else {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
if (!svga->clock_multiplier)
svga->clock *= 2.0;
}
}
} else {
if (svga->multiplexing_rate == 1) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
break;
default:
if (s3->ramdac_type == BT48X)
svga->clock /= 2.0;
else if (s3->ramdac_type == SC1502X) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
break;
}
} else if (svga->getclock == ics2494_getclock) { /*ICS2494 clock chip*/
if (svga->multiplexing_rate == 1) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
}
break;
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_ELSAWIN1KPCI_86C928:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
} else if (svga->getclock == av9194_getclock) { /*AV9194 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
if (s3->width == 640)
svga->hdisp >>= 1;
}
}
break;
default:
break;
}
@@ -4350,67 +4242,82 @@ s3_recalctimings(svga_t *svga)
}
break;
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
s3_log("928 16bpp: ClockSel=%02x, width=%d, hdisp=%d, dotsperclock=%d.\n", clk_sel, s3->width, svga->hdisp, svga->dots_per_clock);
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
switch (svga->hdisp) { /*This might be a driver issue*/
case 800:
s3->width = 1024;
break;
case 1280:
s3->width = 2048;
break;
default:
break;
}
break;
case S3_ELSAWIN1K_86C928:
case S3_ELSAWIN2K_86C928:
switch (s3->width) {
case 2048:
if (s3->ramdac_type == SC1502X) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
} else {
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case BT48X: /*BT485 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if ((svga->clock_multiplier == 1) || (s3->width >= 1024)) {
if (svga->multiplexing_rate == 1) {
if (svga->true_color_bypass) {
if (svga->crtc[0x31] & 0x02) {
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
} else {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
svga->clock *= 2.0;
} else {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
if (!svga->clock_multiplier)
svga->clock *= 2.0;
}
}
} else {
if (svga->multiplexing_rate == 1) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
break;
default:
if (s3->ramdac_type == BT48X)
svga->clock /= 2.0;
else if (s3->ramdac_type == SC1502X) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
break;
}
} else if (svga->getclock == ics2494_getclock) { /*ICS2494 clock chip*/
if (svga->multiplexing_rate == 1) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
}
break;
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_ELSAWIN1KPCI_86C928:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
} else if (svga->getclock == av9194_getclock) { /*AV9194 clock chip*/
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->clock *= 2.0;
} else {
if (s3->width == 640)
svga->hdisp >>= 1;
}
}
break;
default:
break;
}
@@ -4561,8 +4468,22 @@ s3_recalctimings(svga_t *svga)
break;
}
break;
case S3_86C928PCI:
case S3_86C928: /*Technically the 928 cards don't support 24bpp.*/
if (!svga->chain4)
svga->chain4 |= 0x08;
break;
case S3_86C928PCI: /*Technically the 928 cards don't support 24bpp.*/
switch (s3->card_type) {
case S3_ELSAWIN1KPCI_86C928:
if (svga->dots_per_clock == 16) {
svga->dots_per_clock >>= 1;
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
svga->clock /= (2.0 / 3.0);
if (svga->hdisp == 640)
s3->width = 640;
}
break;
case S3_SPEA_MERCURY_LITE_PCI:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
@@ -4602,22 +4523,54 @@ s3_recalctimings(svga_t *svga)
svga->render = svga_render_32bpp_highres;
switch (s3->chip) {
case S3_86C928:
switch (s3->card_type) {
case S3_ELSAWIN1K_86C928:
svga->hdisp >>= 2;
svga->dots_per_clock >>= 2;
svga->clock *= 2.0;
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case BT48X: /*BT485 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if ((svga->clock_multiplier == 1) || (s3->width >= 1024)) {
if (svga->true_color_bypass) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
svga->clock *= 2.0;
}
}
if (svga->hdisp == 800)
s3->width = 1024;
}
break;
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (svga->crtc[0x31] & 0x02) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
if (svga->hdisp == 640)
s3->width = 1024;
} else {
svga->hdisp >>= 2;
svga->dots_per_clock >>= 2;
if (svga->hdisp == 800)
s3->width = 1024;
}
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_ELSAWIN1KPCI_86C928:
svga->hdisp >>= 2;
svga->dots_per_clock >>= 2;
svga->clock *= 2.0;
if (!svga->chain4)
svga->chain4 |= 0x08;
switch (s3->ramdac_type) {
case SC1502X: /*SC15025 RAMDAC*/
if (svga->getclock == icd2061_getclock) { /*ICD2061 clock chip*/
if (!(svga->crtc[0x31] & 0x02)) {
svga->hdisp >>= 2;
svga->dots_per_clock >>= 2;
if (s3->width >= 800)
svga->clock *= 2.0;
}
}
break;
default:
break;
@@ -10792,7 +10745,8 @@ s3_init(const device_t *info)
/* DCS2824-0 = Diamond ICD2061A-compatible. */
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
icd2061_set_ref_clock(svga->ramdac, svga, 14318184.0f);
icd2061_set_ref_clock(svga->ramdac, 14318184.0f);
svga_recalctimings(svga);
}
break;
@@ -10890,7 +10844,8 @@ s3_init(const device_t *info)
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
s3->elsa_eeprom = 1;
icd2061_set_ref_clock(svga->ramdac, svga, 28322000.0f);
icd2061_set_ref_clock(svga->ramdac, 28322000.0f);
svga_recalctimings(svga);
break;
case S3_ELSAWIN2K_86C928:
@@ -10906,7 +10861,8 @@ s3_init(const device_t *info)
svga->clock_gen = device_add(&ics9161_device);
svga->getclock = ics9161_getclock;
s3->elsa_eeprom = 1;
icd2061_set_ref_clock(svga->ramdac, svga, 28322000.0f);
icd2061_set_ref_clock(svga->ramdac, 28322000.0f);
svga_recalctimings(svga);
break;
case S3_METHEUS_86C928:
@@ -10936,7 +10892,8 @@ s3_init(const device_t *info)
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
s3->elsa_eeprom = 1;
icd2061_set_ref_clock(svga->ramdac, svga, 28322000.0f);
icd2061_set_ref_clock(svga->ramdac, 28322000.0f);
svga_recalctimings(svga);
break;
case S3_SPEA_MERCURY_LITE_PCI:
@@ -10996,7 +10953,8 @@ s3_init(const device_t *info)
s3->ramdac_type = BT48X;
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
icd2061_set_ref_clock(svga->ramdac, svga, 14318184.0f);
icd2061_set_ref_clock(svga->ramdac, 14318184.0f);
svga_recalctimings(svga);
break;
}
break;
@@ -11075,7 +11033,8 @@ s3_init(const device_t *info)
s3->ramdac_type = ATT498;
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
icd2061_set_ref_clock(svga->ramdac, svga, 14318184.0f);
icd2061_set_ref_clock(svga->ramdac, 14318184.0f);
svga_recalctimings(svga);
} else {
svga->ramdac = device_add(&sdac_ramdac_device);
s3->ramdac_type = S3_SDAC;

2
vcpkg.json
View File

@@ -1,6 +1,6 @@
{
"name": "86box",
"version-string": "6.0",
"version-string": "5.2",
"homepage": "https://86box.net/",
"documentation": "https://86box.readthedocs.io/",
"license": "GPL-2.0-or-later",