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Merge remote-tracking branch 'upstream/master' into feature/ich2

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This commit is contained in:
Jasmine Iwanek
2023-05-02 10:11:15 -04:00
parent af0d1b29ea 18f96d2823
commit 7cc0b7bf3b
18 changed files with 112 additions and 34 deletions
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4
src/cpu/808x.c
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@@ -440,10 +440,10 @@ pfq_write(void)
static uint8_t
pfq_read(void)
{
uint8_t temp, i;
uint8_t temp;
temp = pfq[0];
for (i = 0; i < (pfq_size - 1); i++)
for (int i = 0; i < (pfq_size - 1); i++)
pfq[i] = pfq[i + 1];
pfq_pos--;
cpu_state.pc = (cpu_state.pc + 1) & 0xffff;

8
src/cpu/x87_ops.h
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@@ -851,8 +851,8 @@ const OpFn OP_TABLE(fpu_8087_d9)[256] = {
ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, ILLEGAL_a16, /*Invalid*/
opFCHS, opFABS, ILLEGAL_a16, ILLEGAL_a16, opFTST, opFXAM, ILLEGAL_a16, ILLEGAL_a16,
opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a16,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, ILLEGAL_a16, opFRNDINT, opFSCALE, ILLEGAL_a16, ILLEGAL_a16
opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, ILLEGAL_a16, opFRNDINT, opFSCALE, ILLEGAL_a16, ILLEGAL_a16
// clang-format on
};
@@ -2414,7 +2414,7 @@ const OpFn OP_TABLE(fpu_287_d9_a32)[256] = {
ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, ILLEGAL_a32, /*Invalid*/
opFCHS, opFABS, ILLEGAL_a32, ILLEGAL_a32, opFTST, opFXAM, ILLEGAL_a32, ILLEGAL_a32,
opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a32,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a32, opFPREM1, opFDECSTP, opFINCSTP,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS
// clang-format on
};
@@ -2494,7 +2494,7 @@ const OpFn OP_TABLE(fpu_d9_a32)[256] = {
opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, opFSTP, /*Invalid*/
opFCHS, opFABS, ILLEGAL_a32, ILLEGAL_a32, opFTST, opFXAM, ILLEGAL_a32, ILLEGAL_a32,
opFLD1, opFLDL2T, opFLDL2E, opFLDPI, opFLDEG2, opFLDLN2, opFLDZ, ILLEGAL_a32,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, ILLEGAL_a32, opFPREM1, opFDECSTP, opFINCSTP,
opF2XM1, opFYL2X, opFPTAN, opFPATAN, opFXTRACT, opFPREM1, opFDECSTP, opFINCSTP,
opFPREM, opFYL2XP1, opFSQRT, opFSINCOS, opFRNDINT, opFSCALE, opFSIN, opFCOS
// clang-format on
};

4
src/cpu/x87_ops_sf.h
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@@ -2,7 +2,7 @@ static uint32_t
fpu_save_environment(void)
{
int tag;
unsigned offset;
unsigned offset = 0;
/* read all registers in stack order and update x87 tag word */
for (int n = 0; n < 8; n++) {
@@ -109,7 +109,7 @@ fpu_save_environment(void)
static uint32_t
fpu_load_environment(void)
{
unsigned offset;
unsigned offset = 0;
switch ((cr0 & 1) | (cpu_state.op32 & 0x100)) {
case 0x000: { /*16-bit real mode*/

2
src/cpu/x87_ops_sf_const.h
View File

@@ -21,7 +21,7 @@ sf_FLDL2T(uint32_t fetchdat)
FPU_stack_overflow(fetchdat);
else {
FPU_push();
FPU_save_regi(FPU_round_const(Const_L2T, (fpu_state.cwd & FPU_CW_RC) == X87_ROUNDING_UP), 0);
FPU_save_regi(FPU_round_const(Const_L2T, (fpu_state.cwd & FPU_CW_RC) == FPU_RC_UP), 0);
}
CLOCK_CYCLES_FPU((fpu_type >= FPU_487SX) ? (x87_timings.fld_const) : (x87_timings.fld_const * cpu_multi));
CONCURRENCY_CYCLES((fpu_type >= FPU_487SX) ? (x87_concurrency.fld_const) : (x87_concurrency.fld_const * cpu_multi));

2
src/cpu/x87_ops_sf_load_store.h
View File

@@ -768,7 +768,6 @@ sf_FBSTP_PACKED_BCD_a16(uint32_t fetchdat)
floatx80 reg;
int64_t save_val;
int sign;
int c;
FP_ENTER();
FPU_check_pending_exceptions();
@@ -833,7 +832,6 @@ sf_FBSTP_PACKED_BCD_a32(uint32_t fetchdat)
floatx80 reg;
int64_t save_val;
int sign;
int c;
FP_ENTER();
FPU_check_pending_exceptions();

1
src/cpu/x87_ops_sf_trans.h
View File

@@ -131,7 +131,6 @@ next_ins:
static int
sf_FXTRACT(uint32_t fetchdat)
{
const floatx80 floatx80_default_nan = packFloatx80(0, floatx80_default_nan_exp, floatx80_default_nan_fraction);
struct float_status_t status;
floatx80 a, b;

12
src/floppy/fdd_86f.c
View File

@@ -2550,7 +2550,7 @@ uint16_t
d86f_prepare_pretrack(int drive, int side, int iso)
{
d86f_t *dev = d86f[drive];
uint16_t i, pos;
uint16_t pos;
int mfm;
int real_gap0_len;
int sync_len;
@@ -2575,22 +2575,22 @@ d86f_prepare_pretrack(int drive, int side, int iso)
d86f_destroy_linked_lists(drive, side);
for (i = 0; i < raw_size; i++)
for (uint32_t i = 0; i < raw_size; i++)
d86f_write_direct_common(drive, side, gap_fill, 0, i);
pos = 0;
if (!iso) {
for (i = 0; i < real_gap0_len; i++) {
for (int i = 0; i < real_gap0_len; i++) {
d86f_write_direct_common(drive, side, gap_fill, 0, pos);
pos = (pos + 1) % raw_size;
}
for (i = 0; i < sync_len; i++) {
for (int i = 0; i < sync_len; i++) {
d86f_write_direct_common(drive, side, 0, 0, pos);
pos = (pos + 1) % raw_size;
}
if (mfm) {
for (i = 0; i < 3; i++) {
for (uint8_t i = 0; i < 3; i++) {
d86f_write_direct_common(drive, side, 0x2452, 1, pos);
pos = (pos + 1) % raw_size;
}
@@ -2600,7 +2600,7 @@ d86f_prepare_pretrack(int drive, int side, int iso)
pos = (pos + 1) % raw_size;
}
for (i = 0; i < real_gap1_len; i++) {
for (int i = 0; i < real_gap1_len; i++) {
d86f_write_direct_common(drive, side, gap_fill, 0, pos);
pos = (pos + 1) % raw_size;
}

1
src/include/86box/machine.h
View File

@@ -776,6 +776,7 @@ extern int machine_ps2_model_65sx_init(const machine_t *);
extern int machine_ps2_model_70_type3_init(const machine_t *);
extern int machine_ps2_model_80_init(const machine_t *);
extern int machine_ps2_model_80_axx_init(const machine_t *);
extern int machine_ps2_model_70_type4_init(const machine_t *);
/* m_tandy.c */
extern int tandy1k_eeprom_read(void);

2
src/include/86box/usb.h
View File

@@ -39,6 +39,8 @@ typedef struct usb_t
int uhci_enable, ohci_enable;
uint32_t ohci_mem_base;
mem_mapping_t ohci_mmio_mapping;
pc_timer_t ohci_frame_timer;
pc_timer_t ohci_port_reset_timer[2];
usb_params_t* usb_params;
} usb_t;

21
src/machine/m_ps2_mca.c
View File

@@ -1492,3 +1492,24 @@ machine_ps2_model_80_axx_init(const machine_t *model)
return ret;
}
int
machine_ps2_model_70_type4_init(const machine_t *model)
{
int ret;
ret = bios_load_interleaved("roms/machines/ibmps2_m70_type4/64F3126.BIN",
"roms/machines/ibmps2_m70_type4/64F3125.BIN",
0x000e0000, 131072, 0);
if (bios_only || !ret)
return ret;
machine_ps2_common_init(model);
ps2.planar_id = 0xf9ff;
ps2_mca_board_model_70_type34_init(1, 4);
return ret;
}

40
src/machine/machine_table.c
View File

@@ -5471,7 +5471,45 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
/* Has IBM PS/2 Type 1 KBC firmware. */
{
.name = "[MCA] IBM PS/2 model 70 (type 4)",
.internal_name = "ibmps2_m70_type4",
.type = MACHINE_TYPE_486,
.chipset = MACHINE_CHIPSET_PROPRIETARY,
.init = machine_ps2_model_70_type4_init,
.pad = 0,
.pad0 = 0,
.pad1 = MACHINE_AVAILABLE,
.pad2 = 0,
.cpu = {
.package = CPU_PKG_SOCKET1,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PS2_MCA,
.flags = MACHINE_VIDEO,
.ram = {
.min = 2048,
.max = 65536,
.step = 2048
},
.nvrmask = 63,
.kbc_device = NULL,
.kbc_p1 = 0,
.gpio = 0,
.device = NULL,
.fdc_device = NULL,
.sio_device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
/* 486 machines - Socket 2 */
/* 486 machines with just the ISA slot */
/* Uses some variant of Phoenix MultiKey/42 as the BIOS sends keyboard controller

3
src/sound/snd_adlibgold.c
View File

@@ -842,7 +842,6 @@ static void
adgold_input_msg(void *p, uint8_t *msg, uint32_t len)
{
adgold_t *adgold = (adgold_t *) p;
uint8_t i;
if (adgold->sysex)
return;
@@ -850,7 +849,7 @@ adgold_input_msg(void *p, uint8_t *msg, uint32_t len)
if (adgold->uart_in) {
adgold->adgold_mma_status |= 0x04;
for (i = 0; i < len; i++) {
for (uint32_t i = 0; i < len; i++) {
adgold->midi_queue[adgold->midi_w++] = msg[i];
adgold->midi_w &= 0x0f;
}

3
src/sound/snd_audiopci.c
View File

@@ -1969,9 +1969,8 @@ static void
es1371_input_msg(void *p, uint8_t *msg, uint32_t len)
{
es1371_t *dev = (es1371_t *) p;
uint8_t i;
for (i = 0; i < len; i++)
for (uint32_t i = 0; i < len; i++)
es1371_write_fifo(dev, msg[i]);
}

3
src/sound/snd_gus.c
View File

@@ -1085,7 +1085,6 @@ static void
gus_input_msg(void *p, uint8_t *msg, uint32_t len)
{
gus_t *gus = (gus_t *) p;
uint8_t i;
if (gus->sysex)
return;
@@ -1093,7 +1092,7 @@ gus_input_msg(void *p, uint8_t *msg, uint32_t len)
if (gus->uart_in) {
gus->midi_status |= MIDI_INT_RECEIVE;
for (i = 0; i < len; i++) {
for (uint32_t i = 0; i < len; i++) {
gus->midi_queue[gus->midi_w++] = msg[i];
gus->midi_w &= 63;
}

5
src/sound/snd_sb_dsp.c
View File

@@ -1055,7 +1055,6 @@ void
sb_dsp_input_msg(void *p, uint8_t *msg, uint32_t len)
{
sb_dsp_t *dsp = (sb_dsp_t *) p;
uint8_t i = 0;
sb_dsp_log("MIDI in sysex = %d, uart irq = %d, msg = %d\n", dsp->midi_in_sysex, dsp->uart_irq, len);
@@ -1068,11 +1067,11 @@ sb_dsp_input_msg(void *p, uint8_t *msg, uint32_t len)
return;
if (dsp->uart_irq) {
for (i = 0; i < len; i++)
for (uint32_t i = 0; i < len; i++)
sb_add_data(dsp, msg[i]);
sb_irq(dsp, 1);
} else if (dsp->midi_in_poll) {
for (i = 0; i < len; i++)
for (uint32_t i = 0; i < len; i++)
sb_add_data(dsp, msg[i]);
}
}

31
src/usb.c
View File

@@ -26,8 +26,8 @@
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/usb.h>
#include "cpu.h"
#ifdef ENABLE_USB_LOG
int usb_do_log = ENABLE_USB_LOG;
@@ -189,6 +189,28 @@ ohci_mmio_read(uint32_t addr, void *p)
return ret;
}
void
ohci_update_frame_counter(void* priv)
{
usb_t *dev = (usb_t *) priv;
}
void
ohci_port_reset_callback(void* priv)
{
usb_t *dev = (usb_t *) priv;
dev->ohci_mmio[OHCI_HcRhPortStatus1] &= ~0x10;
}
void
ohci_port_reset_callback_2(void* priv)
{
usb_t *dev = (usb_t *) priv;
dev->ohci_mmio[OHCI_HcRhPortStatus2] &= ~0x10;
}
static void
ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
{
@@ -331,8 +353,7 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
if (val & 0x10) {
if (old & 0x01) {
dev->ohci_mmio[addr] |= 0x10;
/* TODO: The clear should be on a 10 ms timer. */
dev->ohci_mmio[addr] &= ~0x10;
timer_on_auto(&dev->ohci_port_reset_timer[(addr - OHCI_HcRhPortStatus1) / 4], 10000.);
dev->ohci_mmio[addr + 2] |= 0x10;
} else
dev->ohci_mmio[addr + 2] |= 0x01;
@@ -388,7 +409,6 @@ ohci_mmio_write(uint32_t addr, uint8_t val, void *p)
dev->ohci_mmio[addr] = val;
}
void
ohci_update_mem_mapping(usb_t *dev, uint8_t base1, uint8_t base2, uint8_t base3, int enable)
{
@@ -447,6 +467,9 @@ usb_init_ext(const device_t *info, void* params)
ohci_mmio_read, NULL, NULL,
ohci_mmio_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
timer_add(&dev->ohci_frame_timer, ohci_update_frame_counter, dev, 0); /* Unused for now, to be used for frame counting. */
timer_add(&dev->ohci_port_reset_timer[0], ohci_port_reset_callback, dev, 0);
timer_add(&dev->ohci_port_reset_timer[1], ohci_port_reset_callback_2, dev, 0);
usb_reset(dev);
return dev;

2
src/video/vid_ht216.c
View File

@@ -1347,7 +1347,7 @@ ht216_read_common(ht216_t *ht216, uint32_t addr)
temp = 0xff;
for (pixel = 0; pixel < 8; pixel++) {
for (plane = 0; plane < (1 << count); plane++) {
for (plane = 0; plane < (uint8_t)(1 << count); plane++) {
if (svga->colournocare & (1 << plane)) {
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
if (((svga->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))

2
src/video/vid_s3.c
View File

@@ -8928,7 +8928,7 @@ const device_t s3_9fx_771_pci_device = {
{ .available = s3_9fx_771_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
.config = s3_968_config
};
const device_t s3_phoenix_vision968_pci_device = {