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A lot of cleanaps, got rid of all warnings with -Wall;

Browse Source 
The makefile now uses -Wall.
This commit is contained in:
OBattler
2017-06-16 06:44:11 +02:00
parent 464b1a624f
commit 8061db66fe
60 changed files with 1614 additions and 1693 deletions
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9
src/CPU/codegen.h
View File

@@ -311,7 +311,8 @@ static __inline void addbyte(uint8_t val)
static __inline void addword(uint16_t val)
{
*(uint16_t *)&codeblock[block_current].data[block_pos] = val;
uint16_t *p = (uint16_t *)&codeblock[block_current].data[block_pos];
*p = val;
block_pos += 2;
if (block_pos >= BLOCK_MAX)
{
@@ -321,7 +322,8 @@ static __inline void addword(uint16_t val)
static __inline void addlong(uint32_t val)
{
*(uint32_t *)&codeblock[block_current].data[block_pos] = val;
uint32_t *p = (uint32_t *)&codeblock[block_current].data[block_pos];
*p = val;
block_pos += 4;
if (block_pos >= BLOCK_MAX)
{
@@ -331,7 +333,8 @@ static __inline void addlong(uint32_t val)
static __inline void addquad(uint64_t val)
{
*(uint64_t *)&codeblock[block_current].data[block_pos] = val;
uint64_t *p = (uint64_t *)&codeblock[block_current].data[block_pos];
*p = val;
block_pos += 8;
if (block_pos >= BLOCK_MAX)
{

348
src/CPU/codegen_ops_arith.h
View File

@@ -2,15 +2,15 @@ static uint32_t ropINC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{
int host_reg;
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -21,15 +21,15 @@ static uint32_t ropINC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{
int host_reg;
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -40,15 +40,15 @@ static uint32_t ropDEC_rw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{
int host_reg;
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_W(opcode & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -59,15 +59,15 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
{
int host_reg;
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
host_reg = LOAD_REG_L(opcode & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -93,12 +93,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_B_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
src_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
@@ -133,12 +133,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE_W(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_W_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
src_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
@@ -173,12 +173,12 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
MEM_CHECK_WRITE_L(target_seg); \
dst_reg = MEM_LOAD_ADDR_EA_L_NO_ABRT(target_seg); \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
src_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) \
{ \
if ((fetchdat & 0xc0) == 0xc0) \
@@ -215,11 +215,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 8); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_B(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_B_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@@ -244,11 +244,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 16); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_W(dst_reg, src_reg); \
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_W_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@@ -273,11 +273,11 @@ static uint32_t ropDEC_rl(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
} \
\
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ ## op ## 32); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg); \
op ## _HOST_REG_L(dst_reg, src_reg); \
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg); \
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg); \
if (writeback) STORE_REG_L_RELEASE(dst_reg); \
else RELEASE_REG(dst_reg); \
RELEASE_REG(src_reg); \
@@ -308,11 +308,11 @@ static uint32_t ropCMP_b_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -336,11 +336,11 @@ static uint32_t ropCMP_w_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -364,11 +364,11 @@ static uint32_t ropCMP_l_rm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
}
dst_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -392,12 +392,12 @@ static uint32_t ropCMP_b_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
}
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
src_reg = LOAD_REG_B((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_B(dst_reg, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -420,12 +420,12 @@ static uint32_t ropCMP_w_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
src_reg = LOAD_REG_W((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_W(dst_reg, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -448,12 +448,12 @@ static uint32_t ropCMP_l_rmw(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
dst_reg = 0;
}
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
src_reg = LOAD_REG_L((fetchdat >> 3) & 7);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, dst_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, dst_reg);
dst_reg = CMP_HOST_REG_L(dst_reg, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, dst_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op2, src_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, dst_reg);
RELEASE_REG(dst_reg);
RELEASE_REG(src_reg);
@@ -466,11 +466,11 @@ static uint32_t ropADD_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -480,11 +480,11 @@ static uint32_t ropADD_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -494,12 +494,12 @@ static uint32_t ropADD_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
ADD_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -510,11 +510,11 @@ static uint32_t ropCMP_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@@ -524,11 +524,11 @@ static uint32_t ropCMP_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@@ -538,12 +538,12 @@ static uint32_t ropCMP_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
host_reg = CMP_HOST_REG_IMM_L(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
RELEASE_REG(host_reg);
codegen_flags_changed = 1;
@@ -554,11 +554,11 @@ static uint32_t ropSUB_AL_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_B(REG_AL);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_B_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -568,11 +568,11 @@ static uint32_t ropSUB_AX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
{
int host_reg = LOAD_REG_W(REG_AX);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat & 0xffff);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_W_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -582,12 +582,12 @@ static uint32_t ropSUB_EAX_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32
{
int host_reg = LOAD_REG_L(REG_EAX);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
fetchdat = fastreadl(cs + op_pc);
SUB_HOST_REG_IMM(host_reg, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, fetchdat);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
STORE_REG_L_RELEASE(host_reg);
codegen_flags_changed = 1;
@@ -598,7 +598,7 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -629,38 +629,38 @@ static uint32_t rop80(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD8);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffffff00);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN8);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_B(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB8);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB8);
break;
}
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -684,7 +684,7 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -715,38 +715,38 @@ static uint32_t rop81_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -769,7 +769,7 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -799,38 +799,38 @@ static uint32_t rop81_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -854,7 +854,7 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -888,38 +888,38 @@ static uint32_t rop83_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD16);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm | 0xffff0000);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN16);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_W(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB16);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB16);
break;
}
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)
@@ -942,7 +942,7 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
{
int host_reg;
uint32_t imm;
x86seg *target_seg;
x86seg *target_seg = NULL;
if ((fetchdat & 0x30) == 0x10)
return 0;
@@ -976,38 +976,38 @@ static uint32_t rop83_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
switch (fetchdat & 0x38)
{
case 0x00: /*ADD*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ADD32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ADD32);
break;
case 0x08: /*OR*/
OR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x20: /*AND*/
AND_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x28: /*SUB*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
case 0x30: /*XOR*/
XOR_HOST_REG_IMM(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_ZN32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_ZN32);
break;
case 0x38: /*CMP*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
host_reg = CMP_HOST_REG_IMM_L(host_reg, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SUB32);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, imm);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SUB32);
break;
}
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0x38) != 0x38)
{
if ((fetchdat & 0xc0) != 0xc0)

70
src/CPU/codegen_ops_fpu.h
View File

@@ -200,30 +200,30 @@ static uint32_t ropF ## name ## size(uint8_t opcode, uint32_t fetchdat, uint32_t
return op_pc + 1; \
}
ropFarith(ADD, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(DIV, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(DIVR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(MUL, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(SUB, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(SUBR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S)
ropFarith(ADD, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(DIV, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(DIVR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(MUL, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(SUB, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(SUBR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D)
ropFarith(ADD, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(DIV, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(DIVR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(MUL, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(SUB, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(SUBR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW)
ropFarith(ADD, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(DIV, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(DIVR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(MUL, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(SUB, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(SUBR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL)
ropFarith(ADD, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(DIV, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(DIVR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(MUL, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(SUB, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(SUBR, s, MEM_LOAD_ADDR_EA_L, FP_OP_S);
ropFarith(ADD, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(DIV, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(DIVR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(MUL, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(SUB, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(SUBR, d, MEM_LOAD_ADDR_EA_Q, FP_OP_D);
ropFarith(ADD, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(DIV, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(DIVR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(MUL, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(SUB, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(SUBR, iw, MEM_LOAD_ADDR_EA_W, FP_OP_IW);
ropFarith(ADD, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(DIV, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(DIVR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(MUL, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUB, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
ropFarith(SUBR, il, MEM_LOAD_ADDR_EA_L, FP_OP_IL);
#define ropFcompare(name, size, load, op) \
static uint32_t ropF ## name ## size(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
@@ -252,10 +252,10 @@ static uint32_t ropF ## name ## P ## size(uint8_t opcode, uint32_t fetchdat, uin
return new_pc; \
}
ropFcompare(COM, s, MEM_LOAD_ADDR_EA_L, FP_COMPARE_S)
ropFcompare(COM, d, MEM_LOAD_ADDR_EA_Q, FP_COMPARE_D)
ropFcompare(COM, iw, MEM_LOAD_ADDR_EA_W, FP_COMPARE_IW)
ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL)
ropFcompare(COM, s, MEM_LOAD_ADDR_EA_L, FP_COMPARE_S);
ropFcompare(COM, d, MEM_LOAD_ADDR_EA_Q, FP_COMPARE_D);
ropFcompare(COM, iw, MEM_LOAD_ADDR_EA_W, FP_COMPARE_IW);
ropFcompare(COM, il, MEM_LOAD_ADDR_EA_L, FP_COMPARE_IL);
/*static uint32_t ropFADDs(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
@@ -491,7 +491,7 @@ static uint32_t ropFSTSW_AX(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, u
int host_reg;
FP_ENTER();
host_reg = LOAD_VAR_W((uintptr_t) &cpu_state.npxs);
host_reg = LOAD_VAR_W((uintptr_t)&cpu_state.npxs);
STORE_REG_TARGET_W_RELEASE(host_reg, REG_AX);
return op_pc;
@@ -622,17 +622,19 @@ static uint32_t ropFCHS(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropFLD ## name(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block) \
{ \
static double fp_imm = v; \
static uint64_t *fpp; \
\
FP_ENTER(); \
FP_LOAD_IMM_Q(*(uint64_t *)&fp_imm); \
fpp = (uint64_t *)&fp_imm; \
FP_LOAD_IMM_Q(*fpp); \
\
return op_pc; \
}
opFLDimm(1, 1.0)
opFLDimm(L2T, 3.3219280948873623)
opFLDimm(L2E, 1.4426950408889634)
opFLDimm(PI, 3.141592653589793)
opFLDimm(EG2, 0.3010299956639812)
opFLDimm(LN2, 0.693147180559945)
opFLDimm(L2E, 1.4426950408889634);
opFLDimm(PI, 3.141592653589793);
opFLDimm(EG2, 0.3010299956639812);
opFLDimm(LN2, 0.693147180559945);
opFLDimm(Z, 0.0)

10
src/CPU/codegen_ops_jump.h
View File

@@ -77,7 +77,7 @@ static uint32_t ropLOOP(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static void BRANCH_COND_B(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
CALL_FUNC((void *) CF_SET);
CALL_FUNC((uintptr_t)CF_SET);
if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else
@@ -122,7 +122,7 @@ static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
case FLAGS_UNKNOWN:
CALL_FUNC((void *) ZF_SET);
CALL_FUNC((uintptr_t)ZF_SET);
if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else
@@ -133,7 +133,7 @@ static void BRANCH_COND_E(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_O(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
CALL_FUNC((void *) VF_SET);
CALL_FUNC((uintptr_t)VF_SET);
if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else
@@ -142,7 +142,7 @@ static void BRANCH_COND_O(int pc_offset, uint32_t op_pc, uint32_t offset, int no
static void BRANCH_COND_P(int pc_offset, uint32_t op_pc, uint32_t offset, int not)
{
CALL_FUNC((void *) PF_SET);
CALL_FUNC((uintptr_t)PF_SET);
if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else
@@ -204,7 +204,7 @@ static void BRANCH_COND_S(int pc_offset, uint32_t op_pc, uint32_t offset, int no
break;
case FLAGS_UNKNOWN:
CALL_FUNC((void *) NF_SET);
CALL_FUNC((uintptr_t)NF_SET);
if (not)
TEST_ZERO_JUMP_L(0, op_pc+pc_offset+offset, timing_bt);
else

68
src/CPU/codegen_ops_misc.h
View File

@@ -27,13 +27,13 @@ static uint32_t ropSTI(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32
static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00)
return 0;
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_B(fetchdat & 7);
@@ -50,18 +50,18 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
break;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_B(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC8);
STORE_HOST_REG_ADDR_BL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC8);
STORE_HOST_REG_ADDR_BL((uintptr_t)&cpu_state.flags_res, host_reg);
break;
}
@@ -79,14 +79,14 @@ static uint32_t ropFE(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
static uint32_t codegen_temp;
static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_W(fetchdat & 7);
@@ -111,11 +111,11 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg);
else
@@ -126,11 +126,11 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
codegen_flags_changed = 1;
return op_pc + 1;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM_W(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC16);
STORE_HOST_REG_ADDR_WL((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_W_RELEASE(host_reg);
else
@@ -167,21 +167,19 @@ static uint32_t ropFF_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
MEM_STORE_ADDR_EA_W(&_ss, host_reg);
SP_MODIFY(-2);
return op_pc + 1;
default:
return -1;
}
return 0;
}
static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int host_reg;
if ((fetchdat & 0x30) != 0x00 && (fetchdat & 0x08))
return 0;
if ((fetchdat & 0x30) == 0x00)
CALL_FUNC((void *) flags_rebuild_c);
CALL_FUNC((uintptr_t)flags_rebuild_c);
if ((fetchdat & 0xc0) == 0xc0)
host_reg = LOAD_REG_L(fetchdat & 7);
@@ -206,11 +204,11 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
switch (fetchdat & 0x38)
{
case 0x00: /*INC*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
ADD_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_INC32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg);
else
@@ -221,11 +219,11 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
codegen_flags_changed = 1;
return op_pc + 1;
case 0x08: /*DEC*/
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_op1, host_reg);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_op1, host_reg);
SUB_HOST_REG_IMM(host_reg, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uint32_t)&cpu_state.flags_res, host_reg);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, 1);
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_DEC32);
STORE_HOST_REG_ADDR((uintptr_t)&cpu_state.flags_res, host_reg);
if ((fetchdat & 0xc0) == 0xc0)
STORE_REG_L_RELEASE(host_reg);
else
@@ -262,8 +260,6 @@ static uint32_t ropFF_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint
MEM_STORE_ADDR_EA_L(&_ss, host_reg);
SP_MODIFY(-4);
return op_pc + 1;
default:
return -1;
}
return 0;
}

36
src/CPU/codegen_ops_mmx.h
View File

@@ -154,22 +154,22 @@ MMX_OP(ropPSUBSW, MMX_SUBSW)
MMX_OP(ropPSUBUSB, MMX_SUBUSB)
MMX_OP(ropPSUBUSW, MMX_SUBUSW)
MMX_OP(ropPUNPCKLBW, MMX_PUNPCKLBW)
MMX_OP(ropPUNPCKLWD, MMX_PUNPCKLWD)
MMX_OP(ropPUNPCKLDQ, MMX_PUNPCKLDQ)
MMX_OP(ropPACKSSWB, MMX_PACKSSWB)
MMX_OP(ropPCMPGTB, MMX_PCMPGTB)
MMX_OP(ropPCMPGTW, MMX_PCMPGTW)
MMX_OP(ropPCMPGTD, MMX_PCMPGTD)
MMX_OP(ropPACKUSWB, MMX_PACKUSWB)
MMX_OP(ropPUNPCKHBW, MMX_PUNPCKHBW)
MMX_OP(ropPUNPCKHWD, MMX_PUNPCKHWD)
MMX_OP(ropPUNPCKHDQ, MMX_PUNPCKHDQ)
MMX_OP(ropPACKSSDW, MMX_PACKSSDW)
MMX_OP(ropPUNPCKLBW, MMX_PUNPCKLBW);
MMX_OP(ropPUNPCKLWD, MMX_PUNPCKLWD);
MMX_OP(ropPUNPCKLDQ, MMX_PUNPCKLDQ);
MMX_OP(ropPACKSSWB, MMX_PACKSSWB);
MMX_OP(ropPCMPGTB, MMX_PCMPGTB);
MMX_OP(ropPCMPGTW, MMX_PCMPGTW);
MMX_OP(ropPCMPGTD, MMX_PCMPGTD);
MMX_OP(ropPACKUSWB, MMX_PACKUSWB);
MMX_OP(ropPUNPCKHBW, MMX_PUNPCKHBW);
MMX_OP(ropPUNPCKHWD, MMX_PUNPCKHWD);
MMX_OP(ropPUNPCKHDQ, MMX_PUNPCKHDQ);
MMX_OP(ropPACKSSDW, MMX_PACKSSDW);
MMX_OP(ropPCMPEQB, MMX_PCMPEQB)
MMX_OP(ropPCMPEQW, MMX_PCMPEQW)
MMX_OP(ropPCMPEQD, MMX_PCMPEQD)
MMX_OP(ropPCMPEQB, MMX_PCMPEQB);
MMX_OP(ropPCMPEQW, MMX_PCMPEQW);
MMX_OP(ropPCMPEQD, MMX_PCMPEQD);
MMX_OP(ropPSRLW, MMX_PSRLW)
MMX_OP(ropPSRLD, MMX_PSRLD)
@@ -180,9 +180,9 @@ MMX_OP(ropPSLLW, MMX_PSLLW)
MMX_OP(ropPSLLD, MMX_PSLLD)
MMX_OP(ropPSLLQ, MMX_PSLLQ)
MMX_OP(ropPMULLW, MMX_PMULLW)
MMX_OP(ropPMULHW, MMX_PMULHW)
MMX_OP(ropPMADDWD, MMX_PMADDWD)
MMX_OP(ropPMULLW, MMX_PMULLW);
MMX_OP(ropPMULHW, MMX_PMULHW);
MMX_OP(ropPMADDWD, MMX_PMADDWD);
static uint32_t ropPSxxW_imm(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{

12
src/CPU/codegen_ops_mov.h
View File

@@ -512,22 +512,22 @@ static uint32_t ropMOV_w_seg(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
switch (fetchdat & 0x38)
{
case 0x00: /*ES*/
host_reg = LOAD_VAR_WL((uintptr_t) &ES);
host_reg = LOAD_VAR_WL((uintptr_t)&ES);
break;
case 0x08: /*CS*/
host_reg = LOAD_VAR_WL((uintptr_t) &CS);
host_reg = LOAD_VAR_WL((uintptr_t)&CS);
break;
case 0x18: /*DS*/
host_reg = LOAD_VAR_WL((uintptr_t) &DS);
host_reg = LOAD_VAR_WL((uintptr_t)&DS);
break;
case 0x10: /*SS*/
host_reg = LOAD_VAR_WL((uintptr_t) &SS);
host_reg = LOAD_VAR_WL((uintptr_t)&SS);
break;
case 0x20: /*FS*/
host_reg = LOAD_VAR_WL((uintptr_t) &FS);
host_reg = LOAD_VAR_WL((uintptr_t)&FS);
break;
case 0x28: /*GS*/
host_reg = LOAD_VAR_WL((uintptr_t) &GS);
host_reg = LOAD_VAR_WL((uintptr_t)&GS);
break;
default:
return 0;

24
src/CPU/codegen_ops_shift.h
View File

@@ -13,29 +13,29 @@
reg = MEM_LOAD_ADDR_EA_ ## size ## _NO_ABRT(target_seg); \
if (immediate) count = fastreadb(cs + op_pc + 1) & 0x1f; \
} \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op2, count); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op2, count); \
\
res_store((uint32_t)&cpu_state.flags_op1, reg); \
res_store((uintptr_t)&cpu_state.flags_op1, reg); \
\
switch (fetchdat & 0x38) \
{ \
case 0x20: case 0x30: /*SHL*/ \
SHL_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHL ## size2); \
break; \
\
case 0x28: /*SHR*/ \
SHR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SHR ## size2); \
break; \
\
case 0x38: /*SAR*/ \
SAR_ ## size ## _IMM(reg, count); \
STORE_IMM_ADDR_L((uint32_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.flags_op, FLAGS_SAR ## size2); \
break; \
} \
\
res_store((uint32_t)&cpu_state.flags_res, reg); \
res_store((uintptr_t)&cpu_state.flags_res, reg); \
if ((fetchdat & 0xc0) == 0xc0) \
STORE_REG_ ## size ## _RELEASE(reg); \
else \
@@ -46,7 +46,7 @@
static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count;
int reg;
@@ -59,7 +59,7 @@ static uint32_t ropC0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count;
int reg;
@@ -72,7 +72,7 @@ static uint32_t ropC1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count;
int reg;
@@ -86,7 +86,7 @@ static uint32_t ropC1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count = 1;
int reg;
@@ -99,7 +99,7 @@ static uint32_t ropD0(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_
}
static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count = 1;
int reg;
@@ -112,7 +112,7 @@ static uint32_t ropD1_w(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint3
}
static uint32_t ropD1_l(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
x86seg *target_seg;
x86seg *target_seg = NULL;
int count = 1;
int reg;

10
src/CPU/codegen_ops_stack.h
View File

@@ -85,8 +85,6 @@ static uint32_t ropPUSH_imm_b32(uint8_t opcode, uint32_t fetchdat, uint32_t op_3
static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss);
@@ -97,8 +95,6 @@ static uint32_t ropPOP_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
}
static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss);
@@ -110,8 +106,6 @@ static uint32_t ropPOP_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_W(&_ss);
@@ -122,8 +116,6 @@ static uint32_t ropRET_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
}
static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
MEM_LOAD_ADDR_EA_L(&_ss);
@@ -136,7 +128,6 @@ static uint32_t ropRET_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uin
static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);
@@ -149,7 +140,6 @@ static uint32_t ropRET_imm_16(uint8_t opcode, uint32_t fetchdat, uint32_t op_32,
static uint32_t ropRET_imm_32(uint8_t opcode, uint32_t fetchdat, uint32_t op_32, uint32_t op_pc, codeblock_t *block)
{
uint16_t offset = fetchdat & 0xffff;
/* int host_reg; */
STORE_IMM_ADDR_L((uintptr_t)&cpu_state.oldpc, op_old_pc);
LOAD_STACK_TO_EA(0);

894
src/CPU/codegen_ops_x86-64.h
View File

File diff suppressed because it is too large Load Diff

1040
src/CPU/codegen_ops_x86.h
View File

File diff suppressed because it is too large Load Diff

7
src/CPU/codegen_timing_686.c
View File

@@ -7,12 +7,13 @@
- FPU queue
- Out of order execution (beyond most simplistic approximation)
*/
#include "../ibm.h"
#include "../mem.h"
#include "cpu.h"
#include "x86.h"
#include "x86_ops.h"
#include "x87.h"
#include "../mem.h"
#include "codegen.h"
/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
@@ -818,7 +819,7 @@ static uint32_t opcode_timings_8x[8] =
static int decode_delay;
static uint8_t last_prefix;
static __inline int COUNT(uint32_t c, int op_32)
static inline int COUNT(uint32_t c, int op_32)
{
if (c & CYCLES_HAS_MULTI)
{
@@ -854,7 +855,7 @@ void codegen_timing_686_prefix(uint8_t prefix, uint32_t fetchdat)
void codegen_timing_686_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
int *timings;
uint32_t *timings;
int mod3 = ((fetchdat & 0xc0) == 0xc0);
int bit8 = !(opcode & 1);

7
src/CPU/codegen_timing_pentium.c
View File

@@ -8,12 +8,13 @@
- FPU latencies
- MMX latencies
*/
#include "../ibm.h"
#include "../mem.h"
#include "cpu.h"
#include "x86.h"
#include "x86_ops.h"
#include "x87.h"
#include "../mem.h"
#include "codegen.h"
/*Instruction has different execution time for 16 and 32 bit data. Does not pair */
@@ -818,7 +819,7 @@ static uint32_t opcode_timings_8x[8] =
static int decode_delay;
static uint8_t last_prefix;
static __inline int COUNT(uint32_t c, int op_32)
static inline int COUNT(uint32_t c, int op_32)
{
if (c & CYCLES_HAS_MULTI)
{
@@ -886,7 +887,7 @@ void codegen_timing_pentium_prefix(uint8_t prefix, uint32_t fetchdat)
void codegen_timing_pentium_opcode(uint8_t opcode, uint32_t fetchdat, int op_32)
{
int *timings;
uint32_t *timings;
int mod3 = ((fetchdat & 0xc0) == 0xc0);
int bit8 = !(opcode & 1);

206
src/CPU/codegen_x86.c
View File

@@ -1,12 +1,13 @@
#if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined WIN32 || defined _WIN32 || defined _WIN32
#include <stdlib.h>
#include "../ibm.h"
#include "../mem.h"
#include "cpu.h"
#include "x86.h"
#include "x86_flags.h"
#include "x86_ops.h"
#include "x87.h"
#include "../mem.h"
#include "386_common.h"
@@ -115,7 +116,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B()
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AL*/
addbyte(0xb6);
@@ -170,7 +171,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W()
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*MOVZX EAX, AX*/
addbyte(0xb7);
@@ -224,7 +225,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L()
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -279,7 +280,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_Q()
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -327,7 +328,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B()
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -381,7 +382,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W()
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -434,7 +435,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L()
addbyte(12);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -492,7 +493,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_Q()
addbyte(16);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -543,7 +544,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_B_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
#endif
addbyte(0x0f); /*MOVZX ECX, AL*/
@@ -612,7 +613,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_W_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
#endif
addbyte(0x0f); /*MOVZX ECX, AX*/
@@ -658,7 +659,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
addbyte(0x14);
addbyte(0x95);
addlong((uint32_t)readlookup2);
addbyte(0x75); /*JNE slowpath*/
addbyte(0x75); /*JE slowpath*/
addbyte(3+2+3+1);
addbyte(0x83); /*CMP EDX, -1*/
addbyte(0xfa);
@@ -682,7 +683,7 @@ static uint32_t gen_MEM_LOAD_ADDR_EA_L_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
@@ -745,7 +746,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_B_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
@@ -811,7 +812,7 @@ static uint32_t gen_MEM_STORE_ADDR_EA_W_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
@@ -876,17 +877,17 @@ static uint32_t gen_MEM_STORE_ADDR_EA_L_NO_ABRT()
#ifndef RELEASE_BUILD
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x75); /*JNE mem_abrt_rout*/
addbyte(1);
#endif
addbyte(0xc3); /*RET*/
#ifndef RELEASE_BUILD
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err*/
addbyte(0xc7); /*MOV [ESP], gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err*/
addbyte(0x04);
addbyte(0x24);
addlong((uint32_t)gen_MEM_STORE_ADDR_EA_W_NO_ABRT_err);
addlong((uint32_t)gen_MEM_STORE_ADDR_EA_L_NO_ABRT_err);
addbyte(0xe8); /*CALL fatal*/
addlong((uint32_t)fatal - (uint32_t)(&codeblock[block_current].data[block_pos + 4]));
/*Should not return!*/
@@ -941,7 +942,7 @@ static uint32_t gen_MEM_CHECK_WRITE()
addbyte(8);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -1022,7 +1023,7 @@ static uint32_t gen_MEM_CHECK_WRITE_W()
addbyte(1);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -1104,7 +1105,7 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
addbyte(3);
addbyte(0x80); /*CMP abrt, 0*/
addbyte(0x7d);
addbyte(cpu_state_offset(abrt));
addbyte((uint8_t)cpu_state_offset(abrt));
addbyte(0);
addbyte(0x0f); /*JNE mem_abrt_rout*/
addbyte(0x85);
@@ -1122,7 +1123,6 @@ static uint32_t gen_MEM_CHECK_WRITE_L()
void codegen_init()
{
int c;
#ifdef __linux__
void *start;
size_t len;
@@ -1149,7 +1149,6 @@ void codegen_init()
exit(-1);
}
#endif
/* pclog("Codegen is %p\n", (void *)pages[0xfab12 >> 12].block); */
block_current = BLOCK_SIZE;
block_pos = 0;
@@ -1163,50 +1162,44 @@ void codegen_init()
addbyte(0x5b); /*POP EDX*/
addbyte(0xC3); /*RET*/
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l = gen_MEM_LOAD_ADDR_EA_L();
mem_load_addr_ea_l = (uint32_t)gen_MEM_LOAD_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w = gen_MEM_LOAD_ADDR_EA_W();
mem_load_addr_ea_w = (uint32_t)gen_MEM_LOAD_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b = gen_MEM_LOAD_ADDR_EA_B();
mem_load_addr_ea_b = (uint32_t)gen_MEM_LOAD_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_q = gen_MEM_LOAD_ADDR_EA_Q();
mem_load_addr_ea_q = (uint32_t)gen_MEM_LOAD_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l = gen_MEM_STORE_ADDR_EA_L();
mem_store_addr_ea_l = (uint32_t)gen_MEM_STORE_ADDR_EA_L();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w = gen_MEM_STORE_ADDR_EA_W();
mem_store_addr_ea_w = (uint32_t)gen_MEM_STORE_ADDR_EA_W();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b = gen_MEM_STORE_ADDR_EA_B();
mem_store_addr_ea_b = (uint32_t)gen_MEM_STORE_ADDR_EA_B();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_q = gen_MEM_STORE_ADDR_EA_Q();
mem_store_addr_ea_q = (uint32_t)gen_MEM_STORE_ADDR_EA_Q();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_b_no_abrt = gen_MEM_LOAD_ADDR_EA_B_NO_ABRT();
mem_load_addr_ea_b_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_b_no_abrt = gen_MEM_STORE_ADDR_EA_B_NO_ABRT();
mem_store_addr_ea_b_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_B_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_w_no_abrt = gen_MEM_LOAD_ADDR_EA_W_NO_ABRT();
mem_load_addr_ea_w_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_w_no_abrt = gen_MEM_STORE_ADDR_EA_W_NO_ABRT();
mem_store_addr_ea_w_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_W_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_load_addr_ea_l_no_abrt = gen_MEM_LOAD_ADDR_EA_L_NO_ABRT();
mem_load_addr_ea_l_no_abrt = (uint32_t)gen_MEM_LOAD_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_store_addr_ea_l_no_abrt = gen_MEM_STORE_ADDR_EA_L_NO_ABRT();
mem_store_addr_ea_l_no_abrt = (uint32_t)gen_MEM_STORE_ADDR_EA_L_NO_ABRT();
block_pos = (block_pos + 15) & ~15;
mem_check_write = gen_MEM_CHECK_WRITE();
mem_check_write = (uint32_t)gen_MEM_CHECK_WRITE();
block_pos = (block_pos + 15) & ~15;
mem_check_write_w = gen_MEM_CHECK_WRITE_W();
mem_check_write_w = (uint32_t)gen_MEM_CHECK_WRITE_W();
block_pos = (block_pos + 15) & ~15;
mem_check_write_l = gen_MEM_CHECK_WRITE_L();
mem_check_write_l = (uint32_t)gen_MEM_CHECK_WRITE_L();
#ifdef __MSC__
__asm {
fstcw cpu_state.old_npxc
}
#else
__asm(
asm(
"fstcw %0\n"
: "=m" (cpu_state.old_npxc)
);
#endif
}
void codegen_reset()
@@ -1218,6 +1211,20 @@ void codegen_reset()
void dump_block()
{
/* codeblock_t *block = pages[0x119000 >> 12].block;
pclog("dump_block:\n");
while (block)
{
uint32_t start_pc = (block->pc & 0xffc) | (block->phys & ~0xfff);
uint32_t end_pc = (block->endpc & 0xffc) | (block->phys & ~0xfff);
pclog(" %p : %08x-%08x %08x-%08x %p %p\n", (void *)block, start_pc, end_pc, block->pc, block->endpc, (void *)block->prev, (void *)block->next);
if (!block->pc)
fatal("Dead PC=0\n");
block = block->next;
}
pclog("dump_block done\n");*/
}
static void add_to_block_list(codeblock_t *block)
@@ -1297,7 +1304,6 @@ static void remove_from_block_list(codeblock_t *block, uint32_t pc)
}
else
{
/* pclog(" pages.block_2=%p 3 %p %p\n", (void *)block->next_2, (void *)block, (void *)pages[block->phys_2 >> 12].block_2); */
pages[block->phys_2 >> 12].block_2[(block->phys_2 >> 10) & 3] = block->next_2;
if (block->next_2)
block->next_2->prev_2 = NULL;
@@ -1355,7 +1361,6 @@ void codegen_check_flush(page_t *page, uint64_t mask, uint32_t phys_addr)
void codegen_block_init(uint32_t phys_addr)
{
codeblock_t *block;
int has_evicted = 0;
page_t *page = &pages[phys_addr >> 12];
if (!page->block[(phys_addr >> 10) & 3])
@@ -1366,7 +1371,6 @@ void codegen_block_init(uint32_t phys_addr)
if (block->pc != 0)
{
/* pclog("Reuse block : was %08x now %08x\n", block->pc, cs+pc); */
delete_block(block);
cpu_recomp_reuse++;
}
@@ -1384,7 +1388,7 @@ void codegen_block_init(uint32_t phys_addr)
block->next_2 = block->prev_2 = NULL;
block->page_mask = 0;
block->flags = CODEBLOCK_STATIC_TOP;
block->status = cpu_cur_status;
block->status = cpu_cur_status;
block->was_recompiled = 0;
@@ -1395,7 +1399,6 @@ void codegen_block_init(uint32_t phys_addr)
void codegen_block_start_recompile(codeblock_t *block)
{
int has_evicted = 0;
page_t *page = &pages[block->phys >> 12];
if (!page->block[(block->phys >> 10) & 3])
@@ -1440,8 +1443,6 @@ void codegen_block_start_recompile(codeblock_t *block)
addbyte(0xBD); /*MOVL EBP, &cpu_state*/
addlong(((uintptr_t)&cpu_state) + 128);
/* pclog("New block %i for %08X %03x\n", block_current, cs+pc, block_num); */
last_op32 = -1;
last_ea_seg = NULL;
last_ssegs = -1;
@@ -1499,11 +1500,9 @@ void codegen_block_generate_end_mask()
start_pc >>= PAGE_MASK_SHIFT;
end_pc >>= PAGE_MASK_SHIFT;
/* pclog("block_end: %08x %08x\n", start_pc, end_pc); */
for (; start_pc <= end_pc; start_pc++)
{
block->page_mask |= ((uint64_t)1 << start_pc);
/* pclog(" %08x %llx\n", start_pc, block->page_mask); */
}
pages[block->phys >> 12].code_present_mask[(block->phys >> 10) & 3] |= block->page_mask;
@@ -1531,7 +1530,6 @@ void codegen_block_generate_end_mask()
fatal("!page_mask2\n");
if (block->next_2)
{
/* pclog(" next_2->pc=%08x\n", block->next_2->pc); */
if (!block->next_2->pc)
fatal("block->next_2->pc=0 %p\n", (void *)block->next_2);
}
@@ -1540,7 +1538,6 @@ void codegen_block_generate_end_mask()
}
}
/* pclog("block_end: %08x %08x %016llx\n", block->pc, block->endpc, block->page_mask); */
recomp_page = -1;
}
@@ -1560,14 +1557,14 @@ void codegen_block_end_recompile(codeblock_t *block)
{
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte(cpu_state_offset(_cycles));
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(codegen_block_cycles);
}
if (codegen_block_ins)
{
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins));
addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins);
}
#if 0
@@ -1596,7 +1593,6 @@ void codegen_block_end_recompile(codeblock_t *block)
block->next_2 = block->prev_2 = NULL;
codegen_block_generate_end_mask();
add_to_block_list(block);
/* pclog("End block %i\n", block_num); */
if (!(block->flags & CODEBLOCK_HAS_FPU))
block->flags &= ~CODEBLOCK_STATIC_TOP;
@@ -1607,29 +1603,6 @@ void codegen_flush()
return;
}
static int opcode_conditional_jump[256] =
{
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, /*00*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*10*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*20*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*30*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*40*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*50*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*60*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*70*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*90*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*a0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*b0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*d0*/
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*e0*/
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*f0*/
};
static int opcode_modrm[256] =
{
1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, /*00*/
@@ -1666,7 +1639,7 @@ int opcode_0f_modrm[256] =
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /*80*/
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /*90*/
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, /*a0*/
0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, /*a0*/
1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, /*b0*/
1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, /*c0*/
@@ -1689,7 +1662,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
{
addbyte(0xC7); /*MOVL $0,(ssegs)*/
addbyte(0x45);
addbyte(cpu_state_offset(eaaddr));
addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong((fetchdat >> 8) & 0xffff);
(*op_pc) += 2;
}
@@ -1706,7 +1679,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
break;
case 1:
addbyte(0xb8); /*MOVL ,%eax*/
addlong((uint32_t)(int8_t)(rmdat >> 8)); /* pc++; */
addlong((uint32_t)(int8_t)(rmdat >> 8));
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t)mod1add[0][cpu_rm]);
@@ -1717,7 +1690,7 @@ static x86seg *codegen_generate_ea_16_long(x86seg *op_ea_seg, uint32_t fetchdat,
break;
case 2:
addbyte(0xb8); /*MOVL ,%eax*/
addlong((fetchdat >> 8) & 0xffff); /* pc++; */
addlong((fetchdat >> 8) & 0xffff);
addbyte(0x03); /*ADDL *mod1add[0][cpu_rm], %eax*/
addbyte(0x05);
addlong((uint32_t)mod1add[0][cpu_rm]);
@@ -1754,14 +1727,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
{
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xb8); /*MOVL ,%eax*/
addlong(new_eaaddr); /* pc++; */
addlong(new_eaaddr);
(*op_pc) += 4;
}
else
{
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l));
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
}
break;
case 1:
@@ -1770,7 +1743,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l));
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
(*op_pc)++;
break;
case 2:
@@ -1779,7 +1752,7 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
addlong(new_eaaddr);
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte(cpu_state_offset(regs[sib & 7].l));
addbyte((uint8_t)cpu_state_offset(regs[sib & 7].l));
(*op_pc) += 4;
break;
}
@@ -1797,20 +1770,20 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
case 0:
addbyte(0x03); /*ADDL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l));
addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l));
break;
case 1:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 2:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(2); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
case 3:
addbyte(0x8B); addbyte(0x5D); addbyte(cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0x8B); addbyte(0x5D); addbyte((uint8_t)cpu_state_offset(regs[(sib >> 3) & 7].l)); /*MOVL armregs[RD],%ebx*/
addbyte(0xC1); addbyte(0xE3); addbyte(3); /*SHL $2,%ebx*/
addbyte(0x01); addbyte(0xD8); /*ADDL %ebx,%eax*/
break;
@@ -1826,18 +1799,14 @@ static x86seg *codegen_generate_ea_32_long(x86seg *op_ea_seg, uint32_t fetchdat,
new_eaaddr = fastreadl(cs + (*op_pc) + 1);
addbyte(0xC7); /*MOVL $new_eaaddr,(eaaddr)*/
addbyte(0x45);
addbyte(cpu_state_offset(eaaddr));
addbyte((uint8_t)cpu_state_offset(eaaddr));
addlong(new_eaaddr);
(*op_pc) += 4;
return op_ea_seg;
}
addbyte(0x8b); /*MOVL regs[sib&7].l, %eax*/
addbyte(0x45);
addbyte(cpu_state_offset(regs[cpu_rm].l));
#if 0
addbyte(0xa1); /*MOVL regs[cpu_rm].l, %eax*/
addlong((uint32_t)&cpu_state.regs[cpu_rm].l);
#endif
addbyte((uint8_t)cpu_state_offset(regs[cpu_rm].l));
cpu_state.eaaddr = cpu_state.regs[cpu_rm].l;
if (cpu_mod)
{
@@ -2025,19 +1994,19 @@ void codegen_generate_call(uint8_t opcode, OpFn op, uint32_t fetchdat, uint32_t
generate_call:
codegen_timing_opcode(opcode, fetchdat, op_32);
if ((op_table == x86_dynarec_opcodes &&
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
((opcode & 0xf0) == 0x70 || (opcode & 0xfc) == 0xe0 || opcode == 0xc2 ||
(opcode & 0xfe) == 0xca || (opcode & 0xfc) == 0xcc || (opcode & 0xfc) == 0xe8 ||
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80))))
(opcode == 0xff && ((fetchdat & 0x38) >= 0x10 && (fetchdat & 0x38) < 0x30)))) ||
(op_table == x86_dynarec_opcodes_0f && ((opcode & 0xf0) == 0x80)))
{
/*Opcode is likely to cause block to exit, update cycle count*/
if (codegen_block_cycles)
{
addbyte(0x81); /*SUB $codegen_block_cycles, cyclcs*/
addbyte(0x6d);
addbyte(cpu_state_offset(_cycles));
addbyte((uint8_t)cpu_state_offset(_cycles));
addlong(codegen_block_cycles);
codegen_block_cycles = 0;
}
@@ -2045,7 +2014,7 @@ generate_call:
{
addbyte(0x81); /*ADD $codegen_block_ins,ins*/
addbyte(0x45);
addbyte(cpu_state_offset(cpu_recomp_ins));
addbyte((uint8_t)cpu_state_offset(cpu_recomp_ins));
addlong(codegen_block_ins);
codegen_block_ins = 0;
}
@@ -2079,17 +2048,13 @@ generate_call:
}
op = op_table[((opcode >> opcode_shift) | op_32) & opcode_mask];
#if 0
if (output)
pclog("Generate call at %08X %02X %08X %02X %08X %08X %08X %08X %08X %02X %02X %02X %02X\n", &codeblock[block_current][block_pos], opcode, new_pc, ram[old_pc], EAX, EBX, ECX, EDX, ESI, ram[0x7bd2+6],ram[0x7bd2+7],ram[0x7bd2+8],ram[0x7bd2+9]);
#endif
if (op_ssegs != last_ssegs)
{
last_ssegs = op_ssegs;
addbyte(0xC6); /*MOVB [ssegs],op_ssegs*/
addbyte(0x45);
addbyte(cpu_state_offset(ssegs));
addbyte((uint8_t)cpu_state_offset(ssegs));
addbyte(op_pc + pc_off);
}
@@ -2108,7 +2073,7 @@ generate_call:
addbyte(0xC7); /*MOVL $rm | mod | reg,(rm_mod_reg_data)*/
addbyte(0x45);
addbyte(cpu_state_offset(rm_data.rm_mod_reg_data));
addbyte((uint8_t)cpu_state_offset(rm_data.rm_mod_reg_data));
addlong(cpu_rm | (cpu_mod << 8) | (cpu_reg << 16));
op_pc += pc_off;
@@ -2124,18 +2089,18 @@ generate_call:
last_ea_seg = op_ea_seg;
addbyte(0xC7); /*MOVL $&_ds,(ea_seg)*/
addbyte(0x45);
addbyte(cpu_state_offset(ea_seg));
addbyte((uint8_t)cpu_state_offset(ea_seg));
addlong((uint32_t)op_ea_seg);
}
addbyte(0xC7); /*MOVL pc,new_pc*/
addbyte(0x45);
addbyte(cpu_state_offset(pc));
addbyte((uint8_t)cpu_state_offset(pc));
addlong(op_pc + pc_off);
addbyte(0xC7); /*MOVL $old_pc,(oldpc)*/
addbyte(0x45);
addbyte(cpu_state_offset(oldpc));
addbyte((uint8_t)cpu_state_offset(oldpc));
addlong(old_pc);
if (op_32 != last_op32)
@@ -2143,7 +2108,7 @@ generate_call:
last_op32 = op_32;
addbyte(0xC7); /*MOVL $use32,(op32)*/
addbyte(0x45);
addbyte(cpu_state_offset(op32));
addbyte((uint8_t)cpu_state_offset(op32));
addlong(op_32);
}
@@ -2164,11 +2129,6 @@ generate_call:
addbyte(0x0F); addbyte(0x85); /*JNZ 0*/
addlong((uint32_t)&block->data[BLOCK_EXIT_OFFSET] - (uint32_t)(&block->data[block_pos + 4]));
#if 0
addbyte(0xE8); /*CALL*/
addlong(((uint8_t *)codegen_debug - (uint8_t *)(&block->data[block_pos + 4])));
#endif
codegen_endpc = (cs + cpu_state.pc) + 8;
}

16
src/CPU/x86_ops_call.h
View File

@@ -61,7 +61,7 @@ static int opCALL_far_w(uint32_t fetchdat)
{
uint32_t old_cs, old_pc;
uint16_t new_cs, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
new_pc = getwordf();
new_cs = getword(); if (cpu_state.abrt) return 1;
@@ -77,7 +77,7 @@ static int opCALL_far_l(uint32_t fetchdat)
{
uint32_t old_cs, old_pc;
uint32_t new_cs, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
new_pc = getlong();
new_cs = getword(); if (cpu_state.abrt) return 1;
@@ -95,7 +95,7 @@ static int opFF_w_a16(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
uint16_t temp;
@@ -163,6 +163,7 @@ static int opFF_w_a16(uint32_t fetchdat)
break;
default:
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
x86illegal();
}
return cpu_state.abrt;
@@ -171,7 +172,7 @@ static int opFF_w_a32(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
uint16_t temp;
@@ -239,6 +240,7 @@ static int opFF_w_a32(uint32_t fetchdat)
break;
default:
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
x86illegal();
}
return cpu_state.abrt;
@@ -248,7 +250,7 @@ static int opFF_l_a16(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
uint32_t temp;
@@ -316,6 +318,7 @@ static int opFF_l_a16(uint32_t fetchdat)
break;
default:
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
x86illegal();
}
return cpu_state.abrt;
@@ -324,7 +327,7 @@ static int opFF_l_a32(uint32_t fetchdat)
{
uint16_t old_cs, new_cs;
uint32_t old_pc, new_pc;
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
uint32_t temp;
@@ -391,6 +394,7 @@ static int opFF_l_a32(uint32_t fetchdat)
break;
default:
// fatal("Bad FF opcode %02X\n",rmdat&0x38);
x86illegal();
}
return cpu_state.abrt;

14
src/CPU/x86_ops_i686.h
View File

@@ -166,6 +166,7 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
uint8_t ftwb = 0;
uint16_t rec_ftw = 0;
uint16_t fpus = 0;
uint64_t *p;
if (CPUID < 0x650) return ILLEGAL(fetchdat);
@@ -258,9 +259,10 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
cpu_state.ismmx = 0;
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
something like this is needed*/
p = (uint64_t *)cpu_state.tag;
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
!cpu_state.TOP && !(*(uint64_t *)cpu_state.tag))
!cpu_state.TOP && !(*p))
cpu_state.ismmx = 1;
x87_settag(rec_ftw);
@@ -321,7 +323,8 @@ static int opFXSAVESTOR_a16(uint32_t fetchdat)
cpu_state.npxc = 0x37F;
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
cpu_state.npxs = 0;
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
p = (uint64_t *)cpu_state.tag;
*p = 0x0303030303030303ll;
cpu_state.TOP = 0;
cpu_state.ismmx = 0;
@@ -341,6 +344,7 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
uint8_t ftwb = 0;
uint16_t rec_ftw = 0;
uint16_t fpus = 0;
uint64_t *p;
if (CPUID < 0x650) return ILLEGAL(fetchdat);
@@ -433,9 +437,10 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
cpu_state.ismmx = 0;
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
something like this is needed*/
p = (uint64_t *)cpu_state.tag;
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
!cpu_state.TOP && !(*(uint64_t *)cpu_state.tag))
!cpu_state.TOP && !(*p))
cpu_state.ismmx = 1;
x87_settag(rec_ftw);
@@ -496,7 +501,8 @@ static int opFXSAVESTOR_a32(uint32_t fetchdat)
cpu_state.npxc = 0x37F;
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
cpu_state.npxs = 0;
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
p = (uint64_t *)cpu_state.tag;
*p = 0x0303030303030303ll;
cpu_state.TOP = 0;
cpu_state.ismmx = 0;

40
src/CPU/x86_ops_int.h
View File

@@ -1,6 +1,6 @@
static int opINT3(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@@ -14,7 +14,7 @@ static int opINT3(uint32_t fetchdat)
static int opINT1(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
x86gpf(NULL,0);
@@ -28,7 +28,7 @@ static int opINT1(uint32_t fetchdat)
static int opINT(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
uint8_t temp;
/*if (msw&1) pclog("INT %i %i %i\n",cr0&1,eflags&VM_FLAG,IOPL);*/
@@ -38,6 +38,38 @@ static int opINT(uint32_t fetchdat)
return 1;
}
temp = getbytef();
// /*if (temp == 0x10 && AH == 0xe) */pclog("INT %02X : %04X %04X %04X %04X %c %04X:%04X\n", temp, AX, BX, CX, DX, (AL < 32) ? ' ' : AL, CS, pc);
// if (CS == 0x0028 && pc == 0xC03813C0)
// output = 3;
/* if (pc == 0x8028009A)
output = 3;
if (pc == 0x80282B6F)
{
__times++;
if (__times == 2)
fatal("WRONG\n");
}
if (pc == 0x802809CE)
fatal("RIGHT\n");*/
// if (CS == 0x0028 && pc == 0x80037FE9)
// output = 3;
//if (CS == 0x9087 && pc == 0x3763)
// fatal("Here\n");
//if (CS==0x9087 && pc == 0x0850)
// output = 1;
/* if (output && pc == 0x80033008)
{
__times++;
if (__times == 2)
fatal("WRONG\n");
}*/
/* if (output && pc == 0x80D8)
{
__times++;
if (__times == 2)
fatal("RIGHT\n");
}*/
x86_int_sw(temp);
PREFETCH_RUN(cycles_old-cycles, 2, -1, 0,0,0,0, 0);
@@ -46,7 +78,7 @@ static int opINT(uint32_t fetchdat)
static int opINTO(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{

14
src/CPU/x86_ops_ret.h
View File

@@ -44,7 +44,7 @@
static int opRETF_a16(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
CPU_BLOCK_END();
RETF_a16(0);
@@ -55,7 +55,7 @@ static int opRETF_a16(uint32_t fetchdat)
}
static int opRETF_a32(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
CPU_BLOCK_END();
RETF_a32(0);
@@ -67,8 +67,8 @@ static int opRETF_a32(uint32_t fetchdat)
static int opRETF_a16_imm(uint32_t fetchdat)
{
int cycles_old = cycles;
uint16_t offset = getwordf();
int cycles_old = cycles; UNUSED(cycles_old);
CPU_BLOCK_END();
RETF_a16(offset);
@@ -79,8 +79,8 @@ static int opRETF_a16_imm(uint32_t fetchdat)
}
static int opRETF_a32_imm(uint32_t fetchdat)
{
int cycles_old = cycles;
uint16_t offset = getwordf();
int cycles_old = cycles; UNUSED(cycles_old);
CPU_BLOCK_END();
RETF_a32(offset);
@@ -92,7 +92,7 @@ static int opRETF_a32_imm(uint32_t fetchdat)
static int opIRET_286(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
@@ -137,7 +137,7 @@ static int opIRET_286(uint32_t fetchdat)
static int opIRET(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{
@@ -182,7 +182,7 @@ static int opIRET(uint32_t fetchdat)
static int opIRETD(uint32_t fetchdat)
{
int cycles_old = cycles;
int cycles_old = cycles; UNUSED(cycles_old);
if ((cr0 & 1) && (eflags & VM_FLAG) && (IOPL != 3))
{

8
src/CPU/x87_ops.h
View File

@@ -54,14 +54,18 @@ static int rounding_modes[4] = {FE_TONEAREST, FE_DOWNWARD, FE_UPWARD, FE_TOWARDZ
static __inline void x87_set_mmx()
{
uint64_t *p;
cpu_state.TOP = 0;
*(uint64_t *)cpu_state.tag = 0;
p = (uint64_t *)cpu_state.tag;
*p = 0;
cpu_state.ismmx = 1;
}
static __inline void x87_emms()
{
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
uint64_t *p;
p = (uint64_t *)cpu_state.tag;
*p = 0x0303030303030303ll;
cpu_state.ismmx = 0;
}

5
src/CPU/x87_ops_arith.h
View File

@@ -165,11 +165,14 @@ static int opFCOMP(uint32_t fetchdat)
static int opFCOMPP(uint32_t fetchdat)
{
uint64_t *p, *q;
FP_ENTER();
cpu_state.pc++;
if (fplog) pclog("FCOMPP\n");
cpu_state.npxs &= ~(C0|C2|C3);
if ((*(uint64_t *)&ST(0) == ((uint64_t)1 << 63) && *(uint64_t *)&ST(1) == 0) && is386)
p = (uint64_t *)&ST(0);
q = (uint64_t *)&ST(1);
if ((*p == ((uint64_t)1 << 63) && *q == 0) && is386)
cpu_state.npxs |= C0; /*Nasty hack to fix 80387 detection*/
else
cpu_state.npxs |= x87_compare(ST(0), ST(1));

13
src/CPU/x87_ops_misc.h
View File

@@ -29,12 +29,14 @@ static int opFCLEX(uint32_t fetchdat)
static int opFINIT(uint32_t fetchdat)
{
uint64_t *p;
FP_ENTER();
cpu_state.pc++;
cpu_state.npxc = 0x37F;
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
cpu_state.npxs = 0;
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
p = (uint64_t *)cpu_state.tag;
*p = 0x0303030303030303ll;
cpu_state.TOP = 0;
cpu_state.ismmx = 0;
CLOCK_CYCLES(17);
@@ -91,6 +93,7 @@ static int opFSTP(uint32_t fetchdat)
static int FSTOR()
{
uint64_t *p;
FP_ENTER();
switch ((cr0 & 1) | (cpu_state.op32 & 0x100))
{
@@ -125,9 +128,10 @@ static int FSTOR()
cpu_state.ismmx = 0;
/*Horrible hack, but as PCem doesn't keep the FPU stack in 80-bit precision at all times
something like this is needed*/
p = (uint64_t *)cpu_state.tag;
if (cpu_state.MM_w4[0] == 0xffff && cpu_state.MM_w4[1] == 0xffff && cpu_state.MM_w4[2] == 0xffff && cpu_state.MM_w4[3] == 0xffff &&
cpu_state.MM_w4[4] == 0xffff && cpu_state.MM_w4[5] == 0xffff && cpu_state.MM_w4[6] == 0xffff && cpu_state.MM_w4[7] == 0xffff &&
!cpu_state.TOP && !(*(uint64_t *)cpu_state.tag))
!cpu_state.TOP && !(*p))
cpu_state.ismmx = 1;
CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
@@ -151,6 +155,8 @@ static int opFSTOR_a32(uint32_t fetchdat)
static int FSAVE()
{
uint64_t *p;
FP_ENTER();
if (fplog) pclog("FSAVE %08X:%08X %i\n", easeg, cpu_state.eaaddr, cpu_state.ismmx);
cpu_state.npxs = (cpu_state.npxs & ~(7 << 11)) | (cpu_state.TOP << 11);
@@ -287,7 +293,8 @@ static int FSAVE()
cpu_state.npxc = 0x37F;
cpu_state.new_npxc = (cpu_state.old_npxc & ~0xc00);
cpu_state.npxs = 0;
*(uint64_t *)cpu_state.tag = 0x0303030303030303ll;
p = (uint64_t *)cpu_state.tag;
*p = 0x0303030303030303ll;
cpu_state.TOP = 0;
cpu_state.ismmx = 0;

2
src/Makefile.mingw
View File

@@ -102,7 +102,7 @@ else
endif
AFLAGS = -msse -msse2 -mfpmath=sse
CFLAGS = $(OPTS) $(DFLAGS) $(COPTIM) $(AOPTIM) $(AFLAGS) \
-fomit-frame-pointer -mstackrealign
-fomit-frame-pointer -mstackrealign -Wall
RFLAGS = --input-format=rc -O coff
ifeq ($(RELEASE), y)
CFLAGS += -DRELEASE_BUILD

10
src/NETWORK/net_ne2000.c
View File

@@ -1591,8 +1591,8 @@ nic_pci_write(int func, int addr, uint8_t val, void *priv)
val |= 0x01; /* re-enable IOIN bit */
/*FALLTHROUGH*/
case 0x11: /* PCI_BAR
case 0x12: /* PCI_BAR
case 0x11: /* PCI_BAR */
case 0x12: /* PCI_BAR */
case 0x13: /* PCI_BAR */
/* Remove old I/O. */
nic_ioremove(dev, dev->base_address);
@@ -1819,6 +1819,11 @@ nic_rom_init(nic_t *dev, wchar_t *s)
uint32_t temp;
FILE *f;
if (s == NULL)
{
return;
}
if (dev->bios_addr > 0) {
if ((f = romfopen(s, L"rb")) != NULL) {
fseek(f, 0L, SEEK_END);
@@ -1864,6 +1869,7 @@ nic_init(int board)
dev = malloc(sizeof(nic_t));
memset(dev, 0x00, sizeof(nic_t));
dev->board = board;
rom = NULL;
switch(dev->board) {
case NE2K_NE1000:
strcpy(dev->name, "NE1000");

3
src/NETWORK/net_slirp.c
View File

@@ -67,7 +67,6 @@ slirp_tic(void)
static void
poll_thread(void *arg)
{
uint8_t *mac = (uint8_t *)arg;
struct queuepacket *qp;
event_t *evt;
@@ -112,8 +111,6 @@ poll_thread(void *arg)
int
network_slirp_setup(uint8_t *mac, NETRXCB func, void *arg)
{
int rc;
pclog("SLiRP: initializing..\n");
if (slirp_init() != 0) {

2
src/NETWORK/network.c
View File

@@ -153,8 +153,6 @@ network_close(void)
void
network_reset(void)
{
int i = 0;
pclog("NETWORK: reset (type=%d, card=%d)\n", network_type, network_card);
/* Just in case.. */

5
src/NETWORK/pcap_if.c
View File

@@ -90,7 +90,7 @@ hex_dump(unsigned char *bufp, int len)
while (len-- > 0) {
c = bufp[addr];
if ((addr % 16) == 0)
printf("%04x %02x", addr, c);
printf("%04lx %02x", addr, c);
else
printf(" %02x", c);
asci[(addr & 15)] = (uint8_t)isprint(c) ? c : '.';
@@ -175,7 +175,7 @@ start_cap(char *dev)
strftime(temp, sizeof(temp), "%H:%M:%S", ltime);
/* Process and print the packet. */
printf("\n<< %s,%.6d len=%d\n",
printf("\n<< %s,%.6ld len=%u\n",
temp, hdr->ts.tv_usec, hdr->len);
rc = eth_prhdr((unsigned char *)pkt);
hex_dump((unsigned char *)pkt+rc, hdr->len-rc);
@@ -227,7 +227,6 @@ int
main(int argc, char **argv)
{
dev_t interfaces[32];
dev_t *dev = interfaces;
int numdev, i;
/* Try loading the DLL. */

6
src/SOUND/dbopl.cpp
View File

@@ -869,6 +869,9 @@ Channel* Channel::BlockTemplate( Chip* chip, Bit32u samples, Bit32s* output ) {
return (this + 2);
}
break;
case sm2Percussion:
case sm3Percussion:
break;
}
//Init the operators with the the current vibrato and tremolo values
Op( 0 )->Prepare( chip );
@@ -940,6 +943,9 @@ Channel* Channel::BlockTemplate( Chip* chip, Bit32u samples, Bit32s* output ) {
output[ i * 2 + 0 ] += sample & maskLeft;
output[ i * 2 + 1 ] += sample & maskRight;
break;
case sm2Percussion:
case sm3Percussion:
break;
}
}
switch( mode ) {

14
src/VIDEO/vid_ega_render.c
View File

@@ -180,17 +180,15 @@ void ega_jega_render_blit_text(ega_t *ega, int x, int dl, int start, int width,
void ega_render_text_jega(ega_t *ega, int drawcursor)
{
int x_add = (enable_overscan) ? 8 : 0;
int dl = ega_display_line(ega);
uint8_t chr, attr;
uint16_t dat, dat2;
uint32_t charaddr;
int x, xx;
uint32_t fg, bg;
uint16_t dat = 0, dat2;
int x;
uint32_t fg = 0, bg = 0;
/* Temporary for DBCS. */
unsigned int chr_left;
unsigned int bsattr;
unsigned int chr_left = 0;
unsigned int bsattr = 0;
int chr_wide = 0;
uint32_t bg_ex = 0;
uint32_t fg_ex = 0;
@@ -208,7 +206,7 @@ void ega_render_text_jega(ega_t *ega, int drawcursor)
chr = ega->vram[(ega->ma << 1) & ega->vrammask];
attr = ega->vram[((ega->ma << 1) + 1) & ega->vrammask];
if (chr_wide = 0)
if (chr_wide == 0)
{
if (ega->RMOD2 & 0x80)
{

1
src/VIDEO/vid_et4000w32.c
View File

@@ -212,7 +212,6 @@ uint8_t et4000w32p_in(uint16_t addr, void *p)
{
et4000w32p_t *et4000 = (et4000w32p_t *)p;
svga_t *svga = &et4000->svga;
uint8_t temp;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;

2
src/VIDEO/vid_s3.c
View File

@@ -1464,7 +1464,7 @@ uint8_t s3_accel_read(uint32_t addr, void *p)
void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3)
{
svga_t *svga = &s3->svga;
uint32_t src_dat, dest_dat;
uint32_t src_dat = 0, dest_dat;
int frgd_mix, bkgd_mix;
int clip_t = s3->accel.multifunc[1] & 0xfff;
int clip_l = s3->accel.multifunc[2] & 0xfff;

8
src/VIDEO/vid_s3_virge.c
View File

@@ -22,10 +22,10 @@ static int reg_writes = 0, reg_reads = 0;
static int dither[4][4] =
{
0, 4, 1, 5,
6, 2, 7, 3,
1, 5, 0, 4,
7, 3, 6, 2,
{0, 4, 1, 5},
{6, 2, 7, 3},
{1, 5, 0, 4},
{7, 3, 6, 2},
};
#define RB_SIZE 256

40
src/VIDEO/vid_svga_render.c
View File

@@ -511,15 +511,20 @@ void svga_render_2bpp_highres(svga_t *svga)
void svga_render_4bpp_lowres(svga_t *svga)
{
int x;
int y_add = (enable_overscan) ? 16 : 0;
int x_add = y_add >> 1;
int dl = svga_display_line(svga);
int offset;
uint32_t *p;
uint32_t *r, *q;
uint8_t edat[4];
uint8_t dat;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange)
{
int x;
int offset = ((8 - svga->scrollcache) << 1) + 16;
uint32_t *p = &((uint32_t *)buffer32->line[dl])[offset + x_add];
offset = ((8 - svga->scrollcache) << 1) + 16;
p = &((uint32_t *)buffer32->line[dl])[offset + x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
@@ -527,10 +532,9 @@ void svga_render_4bpp_lowres(svga_t *svga)
for (x = 0; x <= svga->hdisp; x += 16)
{
uint8_t edat[4];
uint8_t dat;
*(uint32_t *)(&edat[0]) = *(uint32_t *)(&svga->vram[svga->ma]);
r = (uint32_t *)(&edat[0]);
q = (uint32_t *)(&svga->vram[svga->ma]);
*r = *q;
svga->ma += 4;
svga->ma = svga_mask_addr(svga->ma, svga);
@@ -559,6 +563,12 @@ void svga_render_4bpp_highres(svga_t *svga)
int y_add = (enable_overscan) ? 16 : 0;
int x_add = y_add >> 1;
int dl = svga_display_line(svga);
int x;
int offset;
uint32_t *p;
uint8_t edat[4];
uint8_t dat;
uint32_t *r, *q;
if (svga->sc & 1 && !(svga->crtc[0x17] & 1))
changed_offset = svga_mask_addr(svga->ma | 0x8000, svga) >> 12;
@@ -572,9 +582,8 @@ void svga_render_4bpp_highres(svga_t *svga)
if (svga->changedvram[changed_offset] || svga->changedvram[changed_offset2] || svga->fullchange)
{
int x;
int offset = (8 - svga->scrollcache) + 24;
uint32_t *p = &((uint32_t *)buffer32->line[dl])[offset + x_add];
offset = (8 - svga->scrollcache) + 24;
p = &((uint32_t *)buffer32->line[dl])[offset + x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
@@ -582,13 +591,12 @@ void svga_render_4bpp_highres(svga_t *svga)
for (x = 0; x <= svga->hdisp; x += 8)
{
uint8_t edat[4];
uint8_t dat;
if (svga->sc & 1 && !(svga->crtc[0x17] & 1))
*(uint32_t *)(&edat[0]) = *(uint32_t *)(&svga->vram[svga_mask_addr(svga->ma | 0x8000, svga)]);
r = (uint32_t *)(&edat[0]);
if (svga->sc & 1 && !(svga->crtc[0x17] & 1))
q = (uint32_t *)(&svga->vram[svga_mask_addr(svga->ma | 0x8000, svga)]);
else
*(uint32_t *)(&edat[0]) = *(uint32_t *)(&svga->vram[svga->ma]);
q = (uint32_t *)(&svga->vram[svga->ma]);
*r = *q;
svga->ma += 4;
svga->ma = svga_mask_addr(svga->ma, svga);

12
src/VIDEO/vid_voodoo_codegen_x86.h
View File

@@ -759,10 +759,14 @@ static inline void voodoo_generate(uint8_t *code_block, voodoo_t *voodoo, voodoo
addbyte(0x47);
addbyte(0xc3);
if (depth_jump_pos)
*(uint8_t *)&code_block[depth_jump_pos] = (block_pos - depth_jump_pos) - 1;
if (depth_jump_pos)
*(uint8_t *)&code_block[depth_jump_pos2] = (block_pos - depth_jump_pos2) - 1;
if (depth_jump_pos)
{
*(uint8_t *)&code_block[depth_jump_pos] = (block_pos - depth_jump_pos) - 1;
}
if (depth_jump_pos2)
{
*(uint8_t *)&code_block[depth_jump_pos2] = (block_pos - depth_jump_pos2) - 1;
}
if ((params->fogMode & (FOG_ENABLE|FOG_CONSTANT|FOG_Z|FOG_ALPHA)) == FOG_ENABLE)
{

1
src/WIN/win_d3d.cc
View File

@@ -71,7 +71,6 @@ static CUSTOMVERTEX d3d_verts[] =
int d3d_init(HWND h)
{
int c;
int ret;
for (c = 0; c < 256; c++)
pal_lookup[c] = makecol(cgapal[c].r << 2, cgapal[c].g << 2, cgapal[c].b << 2);

2
src/WIN/win_deviceconfig.c
View File

@@ -30,8 +30,6 @@ static BOOL CALLBACK deviceconfig_dlgproc(HWND hdlg, UINT message, WPARAM wParam
{
HWND h;
int val_int;
int num;
char s[80];
switch (message)
{

2
src/WIN/win_dynld.c
View File

@@ -29,7 +29,7 @@ dynld_module(const char *name, dllimp_t *table)
HMODULE h;
dllimp_t *imp;
void *func;
char **foo;
/* char **foo; */
/* See if we can load the desired module. */
if ((h = LoadLibrary(name)) == NULL) {

23
src/WIN/win_midi.c
View File

@@ -113,25 +113,8 @@ void midi_get_dev_name(int num, char *s)
strcpy(s, caps.szPname);
}
static int midi_pos, midi_len;
static uint32_t midi_command;
static int midi_lengths[8] = {3, 3, 3, 3, 2, 2, 3, 1};
static int midi_insysex;
static char midi_sysex_data[1024+2];
static void midi_send_sysex()
{
MIDIHDR hdr;
hdr.lpData = midi_sysex_data;
hdr.dwBufferLength = midi_pos;
hdr.dwFlags = 0;
midiOutPrepareHeader(midi_out_device, &hdr, sizeof(MIDIHDR));
midiOutLongMsg(midi_out_device, &hdr, sizeof(MIDIHDR));
midi_insysex = 0;
}
static int midi_pos;
static uint8_t midi_sysex_data[1024+2];
void PlayMsg(uint8_t *msg)
{
@@ -262,7 +245,7 @@ void midi_write(uint8_t val)
void midi_reset()
{
uint8_t buf[64], used;
uint8_t buf[64];
/* Flush buffers */
midiOutReset(midi_out_device);

7
src/WIN/win_serial.c
View File

@@ -87,8 +87,6 @@ pclog("%s: queued byte %02x (%d)\n", pp->name, b, pp->icnt+1);
int
bhtty_sstate(BHTTY *pp, void *arg)
{
int i = 0;
/* Make sure we can do this. */
if (arg == NULL) {
pclog("%s: invalid argument\n", pp->name);
@@ -109,8 +107,6 @@ bhtty_sstate(BHTTY *pp, void *arg)
int
bhtty_gstate(BHTTY *pp, void *arg)
{
int i = 0;
/* Make sure we can do this. */
if (arg == NULL) {
pclog("%s: invalid argument\n", pp->name);
@@ -304,8 +300,6 @@ bhtty_raw(BHTTY *pp, void *arg)
int
bhtty_speed(BHTTY *pp, long speed)
{
int i;
/* Get the current mode and speed. */
if (bhtty_gstate(pp, &pp->dcb) < 0) return(-1);
@@ -331,7 +325,6 @@ bhtty_flush(BHTTY *pp)
{
DWORD dwErrs;
COMSTAT cs;
int i = 0;
/* First, clear any errors. */
(void)ClearCommError(pp->handle, &dwErrs, &cs);

5
src/WIN/win_settings.c
View File

@@ -3130,12 +3130,9 @@ int hard_disk_was_added(void)
void hard_disk_add_open(HWND hwnd, int is_existing)
{
BOOL ret;
existing = is_existing;
hard_disk_added = 0;
ret = DialogBox(hinstance, (LPCWSTR)DLG_CFG_HARD_DISKS_ADD,
hwnd, win_settings_hard_disks_add_proc);
DialogBox(hinstance, (LPCWSTR)DLG_CFG_HARD_DISKS_ADD, hwnd, win_settings_hard_disks_add_proc);
}
int ignore_change = 0;

12
src/cdrom_dosbox.cpp
View File

@@ -51,8 +51,6 @@ using namespace std;
CDROM_Interface_Image::BinaryFile::BinaryFile(const char *filename, bool &error)
{
// file = fopen64(filename, "rb");
// error = (file == NULL);
memset(fn, 0, sizeof(fn));
strcpy(fn, filename);
error = false;
@@ -60,19 +58,16 @@ CDROM_Interface_Image::BinaryFile::BinaryFile(const char *filename, bool &error)
CDROM_Interface_Image::BinaryFile::~BinaryFile()
{
// delete file;
memset(fn, 0, sizeof(fn));
}
bool CDROM_Interface_Image::BinaryFile::read(Bit8u *buffer, uint64_t seek, uint64_t count)
{
uint64_t offs = 0;
file = fopen64(fn, "rb");
if (file == NULL) return 0;
fseeko64(file, seek, SEEK_SET);
offs = fread(buffer, 1, count, file);
fread(buffer, 1, count, file);
fclose(file);
// return (offs == count);
return 1;
}
@@ -179,7 +174,7 @@ bool CDROM_Interface_Image::LoadUnloadMedia(bool unload)
return true;
}
int CDROM_Interface_Image::GetTrack(int sector)
int CDROM_Interface_Image::GetTrack(unsigned int sector)
{
vector<Track>::iterator i = tracks.begin();
vector<Track>::iterator end = tracks.end() - 1;
@@ -225,9 +220,6 @@ bool CDROM_Interface_Image::IsMode2(unsigned long sector)
bool CDROM_Interface_Image::LoadIsoFile(char* filename)
{
int shift = 0;
int totalPregap = 0;
tracks.clear();
// data track

2
src/cdrom_dosbox.h
View File

@@ -149,7 +149,7 @@ public:
bool HasDataTrack (void);
bool HasAudioTracks (void);
int GetTrack (int sector);
int GetTrack (unsigned int sector);
private:
// player

17
src/cdrom_image.cc
View File

@@ -108,7 +108,6 @@ static void image_playaudio(uint8_t id, uint32_t pos, uint32_t len, int ismsf)
unsigned char attr;
TMSF tmsf;
int m = 0, s = 0, f = 0;
uint32_t start_msf = 0, end_msf = 0;
cdimg[id]->GetAudioTrackInfo(cdimg[id]->GetTrack(pos), number, tmsf, attr);
if (attr == DATA_TRACK)
{
@@ -185,13 +184,6 @@ static void image_stop(uint8_t id)
cdrom_image[id].cd_state = CD_STOPPED;
}
static void image_seek(uint8_t id, uint32_t pos)
{
if (!cdimg[id] || cdrom_image[id].image_is_iso) return;
cdrom_image[id].cd_pos = pos;
cdrom_image[id].cd_state = CD_STOPPED;
}
static int image_ready(uint8_t id)
{
if (!cdimg[id])
@@ -771,14 +763,6 @@ read_mode2:
}
static void lba_to_msf(uint8_t *buf, int lba)
{
lba += 150;
buf[0] = (lba / 75) / 60;
buf[1] = (lba / 75) % 60;
buf[2] = lba % 75;
}
static uint32_t image_size(uint8_t id)
{
return cdrom_image[id].cdrom_capacity;
@@ -905,7 +889,6 @@ static int image_readtoc_raw(uint8_t id, unsigned char *b, int maxlen)
int number;
unsigned char attr;
TMSF tmsf;
int lb;
if (!cdimg[id]) return 0;

4
src/cdrom_ioctl.c
View File

@@ -1047,7 +1047,7 @@ split_block_read_iterate:
static int ioctl_readtoc(uint8_t id, unsigned char *b, unsigned char starttrack, int msf, int maxlen, int single)
{
int len=4;
long size;
DWORD size;
int c,d;
uint32_t temp;
uint32_t last_block;
@@ -1156,9 +1156,7 @@ static int ioctl_readtoc_raw(uint8_t id, uint8_t *b, int maxlen)
{
int len=4;
int size;
uint32_t temp;
int i;
int BytesRead = 0;
CDROM_READ_TOC_EX toc_ex;
CDROM_TOC_FULL_TOC_DATA toc;
if (!cdrom_drives[id].host_drive)

3
src/config.c
View File

@@ -109,6 +109,7 @@ void config_dump(void)
}
#if 0
static void config_free(void)
{
section_t *current_section;
@@ -133,6 +134,7 @@ static void config_free(void)
current_section = next_section;
}
}
#endif
static wchar_t cfgbuffer[1024];
@@ -477,7 +479,6 @@ void config_delete_var(char *head, char *name)
void config_delete_section_if_empty(char *head)
{
section_t *section;
entry_t *entry;
section = find_section(head);

6
src/disc_imd.c
View File

@@ -508,10 +508,10 @@ void imd_seek(int drive, int track)
int real_sector = 0;
int actual_sector = 0;
char *c_map;
char *h_map;
char *c_map = NULL;
char *h_map = NULL;
char *r_map;
char *n_map;
char *n_map = NULL;
uint8_t *data;
uint32_t track_buf_pos[2] = { 0, 0 };

52
src/disc_img.c
View File

@@ -61,38 +61,38 @@ uint8_t xdf_gap3_sizes[2][2] = { { 60, 69 }, { 60, 50 } };
uint16_t xdf_trackx_spos[2][8] = { { 0xA7F, 0xF02, 0x11B7, 0xB66, 0xE1B, 0x129E }, { 0x302, 0x7E2, 0xA52, 0x12DA, 0x572, 0xDFA, 0x106A, 0x154A } };
/* XDF: Layout of the sectors in the image. */
xdf_sector_t xdf_img_layout[2][2][46] = { { { 0x8100, 0x8200, 0x8300, 0x8400, 0x8500, 0x8600, 0x8700, 0x8800,
0x8101, 0x8201, 0x0100, 0x0200, 0x0300, 0x0400, 0x0500, 0x0600,
0x0700, 0x0800, 0,
0x8301, 0x8401, 0x8501, 0x8601, 0x8701, 0x8801, 0x8901, 0x8A01,
0x8B01, 0x8C01, 0x8D01, 0x8E01, 0x8F01, 0x9001, 0, 0,
0, 0, 0 },
{ 0x8300, 0x8600, 0x8201, 0x8200, 0x8601, 0x8301 }
xdf_sector_t xdf_img_layout[2][2][46] = { { { {0x8100}, {0x8200}, {0x8300}, {0x8400}, {0x8500}, {0x8600}, {0x8700}, {0x8800},
{0x8101}, {0x8201}, {0x0100}, {0x0200}, {0x0300}, {0x0400}, {0x0500}, {0x0600},
{0x0700}, {0x0800}, { 0},
{0x8301}, {0x8401}, {0x8501}, {0x8601}, {0x8701}, {0x8801}, {0x8901}, {0x8A01},
{0x8B01}, {0x8C01}, {0x8D01}, {0x8E01}, {0x8F01}, {0x9001}, { 0}, { 0},
{ 0}, { 0}, { 0} },
{ {0x8300}, {0x8600}, {0x8201}, {0x8200}, {0x8601}, {0x8301} }
}, /* 5.25" 2HD */
{ { 0x8100, 0x8200, 0x8300, 0x8400, 0x8500, 0x8600, 0x8700, 0x8800,
0x8900, 0x8A00, 0x8B00, 0x8101, 0x0100, 0x0200, 0x0300, 0x0400,
0x0500, 0x0600, 0x0700, 0x0800, 0, 0, 0,
0x8201, 0x8301, 0x8401, 0x8501, 0x8601, 0x8701, 0x8801, 0x8901,
0x8A01, 0x8B01, 0x8C01, 0x8D01, 0x8E01, 0x8F01, 0, 0,
0, 0, 0, 0x9001, 0x9101, 0x9201, 0x9301 },
{ 0x8300, 0x8400, 0x8601, 0x8200, 0x8201, 0x8600, 0x8401, 0x8301 }
{ { {0x8100}, {0x8200}, {0x8300}, {0x8400}, {0x8500}, {0x8600}, {0x8700}, {0x8800},
{0x8900}, {0x8A00}, {0x8B00}, {0x8101}, {0x0100}, {0x0200}, {0x0300}, {0x0400},
{0x0500}, {0x0600}, {0x0700}, {0x0800}, { 0}, { 0}, { 0},
{0x8201}, {0x8301}, {0x8401}, {0x8501}, {0x8601}, {0x8701}, {0x8801}, {0x8901},
{0x8A01}, {0x8B01}, {0x8C01}, {0x8D01}, {0x8E01}, {0x8F01}, { 0}, { 0},
{ 0}, { 0}, { 0}, {0x9001}, {0x9101}, {0x9201}, {0x9301} },
{ {0x8300}, {0x8400}, {0x8601}, {0x8200}, {0x8201}, {0x8600}, {0x8401}, {0x8301} }
} /* 3.5" 2HD */
};
/* XDF: Layout of the sectors on the disk's track. */
xdf_sector_t xdf_disk_layout[2][2][38] = { { { 0x0100, 0x0200, 0x8100, 0x8800, 0x8200, 0x0300, 0x8300, 0x0400,
0x8400, 0x0500, 0x8500, 0x0600, 0x8600, 0x0700, 0x8700, 0x0800,
0x8D01, 0x8501, 0x8E01, 0x8601, 0x8F01, 0x8701, 0x9001, 0x8801,
0x8101, 0x8901, 0x8201, 0x8A01, 0x8301, 0x8B01, 0x8401, 0x8C01 },
{ 0x8300, 0x8200, 0x8600, 0x8201, 0x8301, 0x8601 }
xdf_sector_t xdf_disk_layout[2][2][38] = { { { {0x0100}, {0x0200}, {0x8100}, {0x8800}, {0x8200}, {0x0300}, {0x8300}, {0x0400},
{0x8400}, {0x0500}, {0x8500}, {0x0600}, {0x8600}, {0x0700}, {0x8700}, {0x0800},
{0x8D01}, {0x8501}, {0x8E01}, {0x8601}, {0x8F01}, {0x8701}, {0x9001}, {0x8801},
{0x8101}, {0x8901}, {0x8201}, {0x8A01}, {0x8301}, {0x8B01}, {0x8401}, {0x8C01} },
{ {0x8300}, {0x8200}, {0x8600}, {0x8201}, {0x8301}, {0x8601} }
}, /* 5.25" 2HD */
{ { 0x0100, 0x8A00, 0x8100, 0x8B00, 0x8200, 0x0200, 0x8300, 0x0300,
0x8400, 0x0400, 0x8500, 0x0500, 0x8600, 0x0600, 0x8700, 0x0700,
0x8800, 0x0800, 0x8900,
0x9001, 0x8701, 0x9101, 0x8801, 0x9201, 0x8901, 0x9301, 0x8A01,
0x8101, 0x8B01, 0x8201, 0x8C01, 0x8301, 0x8D01, 0x8401, 0x8E01,
0x8501, 0x8F01, 0x8601 },
{ 0x8300, 0x8200, 0x8400, 0x8600, 0x8401, 0x8201, 0x8301, 0x8601 },
{ { {0x0100}, {0x8A00}, {0x8100}, {0x8B00}, {0x8200}, {0x0200}, {0x8300}, {0x0300},
{0x8400}, {0x0400}, {0x8500}, {0x0500}, {0x8600}, {0x0600}, {0x8700}, {0x0700},
{0x8800}, {0x0800}, {0x8900},
{0x9001}, {0x8701}, {0x9101}, {0x8801}, {0x9201}, {0x8901}, {0x9301}, {0x8A01},
{0x8101}, {0x8B01}, {0x8201}, {0x8C01}, {0x8301}, {0x8D01}, {0x8401}, {0x8E01},
{0x8501}, {0x8F01}, {0x8601} },
{ {0x8300}, {0x8200}, {0x8400}, {0x8600}, {0x8401}, {0x8201}, {0x8301}, {0x8601} },
}, /* 3.5" 2HD */
};

2
src/ibm.h
View File

@@ -795,3 +795,5 @@ extern void status_settext(char *str);
#define SB_RDISK 0x20
#define SB_HDD 0x40
#define SB_TEXT 0x50
#define UNUSED(x) (void)x

8
src/intel_flash.c
View File

@@ -85,17 +85,21 @@ static uint8_t flash_read(uint32_t addr, void *p)
static uint16_t flash_readw(uint32_t addr, void *p)
{
flash_t *flash = (flash_t *)p;
uint16_t *q;
addr &= 0x1ffff;
if (flash->invert_high_pin) addr ^= 0x10000;
return *(uint16_t *)&(flash->array[addr]);
q = (uint16_t *)&(flash->array[addr]);
return *q;
}
static uint32_t flash_readl(uint32_t addr, void *p)
{
flash_t *flash = (flash_t *)p;
uint32_t *q;
addr &= 0x1ffff;
if (flash->invert_high_pin) addr ^= 0x10000;
return *(uint32_t *)&(flash->array[addr]);
q = (uint32_t *)&(flash->array[addr]);
return *q;
}
static void flash_write(uint32_t addr, uint8_t val, void *p)

2
src/keyboard_amstrad.c
View File

@@ -112,7 +112,7 @@ void keyboard_amstrad_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_amstrad_read(uint16_t port, void *priv)
{
uint8_t temp;
uint8_t temp = 0xff;
switch (port)
{
case 0x60:

14
src/keyboard_olim24.c
View File

@@ -45,7 +45,6 @@ static uint8_t mouse_scancodes[7];
void keyboard_olim24_poll()
{
keybsenddelay += (1000 * TIMER_USEC);
//pclog("poll %i\n", keyboard_olim24.wantirq);
if (keyboard_olim24.wantirq)
{
keyboard_olim24.wantirq = 0;
@@ -108,8 +107,6 @@ void keyboard_olim24_write(uint16_t port, uint8_t val, void *priv)
default:
pclog("Bad keyboard command complete %02X\n", keyboard_olim24.command);
// dumpregs();
// exit(-1);
}
}
}
@@ -137,8 +134,6 @@ void keyboard_olim24_write(uint16_t port, uint8_t val, void *priv)
default:
pclog("Bad keyboard command %02X\n", val);
// dumpregs();
// exit(-1);
}
}
@@ -162,8 +157,7 @@ void keyboard_olim24_write(uint16_t port, uint8_t val, void *priv)
uint8_t keyboard_olim24_read(uint16_t port, void *priv)
{
uint8_t temp;
// pclog("keyboard_olim24 : read %04X ", port);
uint8_t temp = 0xff;
switch (port)
{
case 0x60:
@@ -193,10 +187,7 @@ uint8_t keyboard_olim24_read(uint16_t port, void *priv)
default:
pclog("\nBad olim24 keyboard read %04X\n", port);
// dumpregs();
// exit(-1);
}
// pclog("%02X\n", temp);
return temp;
}
@@ -231,8 +222,6 @@ uint8_t mouse_olim24_poll(int x, int y, int z, int b, void *p)
mouse->x += x;
mouse->y += y;
// pclog("mouse_poll - %i, %i %i, %i\n", x, y, mouse->x, mouse->y);
if (((key_queue_end - key_queue_start) & 0xf) > 14)
return(0xff);
if ((b & 1) && !(mouse->b & 1))
@@ -342,7 +331,6 @@ mouse_t mouse_olim24 =
void keyboard_olim24_init()
{
//return;
io_sethandler(0x0060, 0x0002, keyboard_olim24_read, NULL, NULL, keyboard_olim24_write, NULL, NULL, NULL);
io_sethandler(0x0064, 0x0001, keyboard_olim24_read, NULL, NULL, keyboard_olim24_write, NULL, NULL, NULL);
keyboard_olim24_reset();

6
src/mem.c
View File

@@ -1785,11 +1785,13 @@ uint8_t mem_read_romext(uint32_t addr, void *priv)
}
uint16_t mem_read_romextw(uint32_t addr, void *priv)
{
return *(uint16_t *)&romext[addr & 0x7fff];
uint16_t *p = (uint16_t *)&romext[addr & 0x7fff];
return *p;
}
uint32_t mem_read_romextl(uint32_t addr, void *priv)
{
return *(uint32_t *)&romext[addr & 0x7fff];
uint32_t *p = (uint32_t *)&romext[addr & 0x7fff];
return *p;
}
void mem_write_null(uint32_t addr, uint8_t val, void *p)

139
src/model.c
View File

@@ -159,78 +159,77 @@ int romset;
MODEL models[] =
{
{"IBM PC", ROM_IBMPC, "ibmpc", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"IBM XT", ROM_IBMXT, "ibmxt", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Compaq Portable", ROM_PORTABLE, "portable", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 128, 640, 128, 0, xt_init, NULL},
{"IBM PCjr", ROM_IBMPCJR, "ibmpcjr", { "", cpus_pcjr, "", NULL, "", NULL, "", NULL, "", NULL}, 1, 0, 128, 640, 128, 0, pcjr_init, &pcjr_device},
{"Generic XT clone", ROM_GENXT, "genxt", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"AMI XT clone", ROM_AMIXT, "amixt", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"DTK XT clone", ROM_DTKXT, "dtk", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"VTech Laser Turbo XT", ROM_LTXT, "ltxt", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL},
{"VTech Laser XT3", ROM_LXT3, "lxt3", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL},
{"Phoenix XT clone", ROM_PXXT, "pxxt", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Juko XT clone", ROM_JUKOPC, "jukopc", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Tandy 1000", ROM_TANDY, "tandy", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 1, 0, 128, 640, 128, 0, tandy1k_init, &tandy1000_device},
{"Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", { "", cpus_8088, "", NULL, "", NULL, "", NULL, "", NULL}, 1, 0, 256, 640, 128, 0, tandy1k_init, &tandy1000hx_device},
{"Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, 0, 512, 768, 128, 0, tandy1ksl2_init, NULL},
{"Amstrad PC1512", ROM_PC1512, "pc1512", { "", cpus_pc1512, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL},
{"Sinclair PC200", ROM_PC200, "pc200", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL},
{"Schneider EuroPC", ROM_EUROPC, "europc", { "", cpus_europc, "", NULL, "", NULL, "", NULL, "", NULL}, 0, 0, 512, 640, 128, 0, europc_init, NULL},
{"Olivetti M24", ROM_OLIM24, "olivetti_m24", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_OLIM24, 128, 640, 128, 0, olim24_init, NULL},
{"Amstrad PC1640", ROM_PC1640, "pc1640", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"Amstrad PC2086", ROM_PC2086, "pc2086", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"Amstrad PC3086", ROM_PC3086, "pc3086", { "", cpus_8086, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"IBM AT", ROM_IBMAT, "ibmat", { "", cpus_ibmat, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT, 1, 16, 1, 63, ibm_at_init, NULL},
{"Compaq Portable II", ROM_PORTABLEII, "portableii", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"Compaq Portable III", ROM_PORTABLEIII, "portableiii", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_ide_init, NULL},
{"AMI 286 clone", ROM_AMI286, "ami286", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_neat_init, NULL},
{"Award 286 clone", ROM_AWARD286, "award286", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_scat_init, NULL},
{"Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT, 1, 16, 1, 127, at_scat_init, NULL},
{"Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", { "", cpus_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT, 1, 16, 1, 127, at_scat_init, NULL},
{"IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", { "", cpus_ps1_m2011, "", NULL, "", NULL, "", NULL, "", NULL}, 1, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps1_m2011_init, NULL},
{"IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", { "", cpus_ps2_m30_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps2_m30_286_init, NULL},
{"IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", { "", cpus_ps2_m30_286, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 16, 1, 63, ps2_model_50_init, NULL},
{"IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC, "", NULL, "", NULL}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL},
{"IBM PS/1 m.2121 + ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL},
{"IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 8, 1, 63, ps2_model_55sx_init, NULL},
{"Compaq Deskpro 386", ROM_DESKPRO_386, "dekspro386", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT, 1, 15, 1, 63, deskpro386_init, NULL},
{"Compaq Portable III 386", ROM_PORTABLEIII386, "portableiii386", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"DTK 386SX clone", ROM_DTK386, "dtk386", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_neat_init, NULL},
{"Amstrad MegaPC", ROM_MEGAPC, "megapc", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC, "", NULL, "", NULL}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL},
{"AMI 386SX clone", ROM_AMI386SX, "ami386", { "Intel", cpus_i386SX, "AMD", cpus_Am386SX, "Cyrix", cpus_486SLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_headland_init, NULL},
{"IBM PS/2 Model 80", ROM_IBMPS2_M80, "ibmps2_m80", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 12, 1, 63, ps2_model_80_init, NULL},
/* The MegaPC manual says 386DX model of the Amstrad PC70386 exists, but Sarah Walker just *had* to remove 386DX CPU's from some boards. */
{"Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL},
{"MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL},
{"AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", { "Intel", cpus_i386DX, "AMD", cpus_Am386DX, "Cyrix", cpus_486DLC, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL},
{"IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 64, 1, 127, ps1_m2133_init, NULL},
{"AMI 486 clone", ROM_AMI486, "ami486", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL},
{"AMI WinBIOS 486", ROM_WIN486, "win486", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL},
{"DTK PKM-0038S E-2", ROM_DTK486, "dtk486", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_dtk486_init, NULL},
{"Rise Computer R418", ROM_R418, "r418", { "Intel", cpus_i486, "AMD", cpus_Am486, "Cyrix", cpus_Cx486, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 64, 1, 127, at_r418_init, NULL},
{"Intel Premiere/PCI", ROM_REVENGE, "revenge", { "Intel", cpus_Pentium5V, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_batman_init, NULL},
{"IBM PC", ROM_IBMPC, "ibmpc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"IBM XT", ROM_IBMXT, "ibmxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Compaq Portable", ROM_PORTABLE, "portable", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 128, 640, 128, 0, xt_init, NULL},
{"IBM PCjr", ROM_IBMPCJR, "ibmpcjr", {{"", cpus_pcjr}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, pcjr_init, &pcjr_device},
{"Generic XT clone", ROM_GENXT, "genxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"AMI XT clone", ROM_AMIXT, "amixt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"DTK XT clone", ROM_DTKXT, "dtk", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"VTech Laser Turbo XT", ROM_LTXT, "ltxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL},
{"VTech Laser XT3", ROM_LXT3, "lxt3", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 1152, 64, 0, xt_laserxt_init, NULL},
{"Phoenix XT clone", ROM_PXXT, "pxxt", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Juko XT clone", ROM_JUKOPC, "jukopc", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 64, 640, 64, 0, xt_init, NULL},
{"Tandy 1000", ROM_TANDY, "tandy", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 128, 640, 128, 0, tandy1k_init, &tandy1000_device},
{"Tandy 1000 HX", ROM_TANDY1000HX, "tandy1000hx", {{"", cpus_8088}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 256, 640, 128, 0, tandy1k_init, &tandy1000hx_device},
{"Tandy 1000 SL/2", ROM_TANDY1000SL2, "tandy1000sl2", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, 0, 512, 768, 128, 0, tandy1ksl2_init, NULL},
{"Amstrad PC1512", ROM_PC1512, "pc1512", {{"", cpus_pc1512}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL},
{"Sinclair PC200", ROM_PC200, "pc200", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 512, 640, 128, 63, ams_init, NULL},
{"Schneider EuroPC", ROM_EUROPC, "europc", {{"", cpus_europc}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, 0, 512, 640, 128, 0, europc_init, NULL},
{"Olivetti M24", ROM_OLIM24, "olivetti_m24", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_OLIM24, 128, 640, 128, 0, olim24_init, NULL},
{"Amstrad PC1640", ROM_PC1640, "pc1640", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"Amstrad PC2086", ROM_PC2086, "pc2086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"Amstrad PC3086", ROM_PC3086, "pc3086", {{"", cpus_8086}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AMSTRAD, 640, 640, 0, 63, ams_init, NULL},
{"IBM AT", ROM_IBMAT, "ibmat", {{"", cpus_ibmat}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 16, 1, 63, ibm_at_init, NULL},
{"Compaq Portable II", ROM_PORTABLEII, "portableii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"Compaq Portable III", ROM_PORTABLEIII, "portableiii", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"Commodore PC 30 III", ROM_CMDPC30, "cmdpc30", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_ide_init, NULL},
{"AMI 286 clone", ROM_AMI286, "ami286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_neat_init, NULL},
{"Award 286 clone", ROM_AWARD286, "award286", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_scat_init, NULL},
{"Hyundai Super-286TR", ROM_SUPER286TR, "super286tr", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 16, 1, 127, at_scat_init, NULL},
{"Samsung SPC-4200P", ROM_SPC4200P, "spc4200p", {{"", cpus_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 16, 1, 127, at_scat_init, NULL},
{"IBM PS/1 model 2011", ROM_IBMPS1_2011, "ibmps1es", {{"", cpus_ps1_m2011}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps1_m2011_init, NULL},
{"IBM PS/2 Model 30-286", ROM_IBMPS2_M30_286, "ibmps2_m30_286", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD, 1, 16, 1, 127, ps2_m30_286_init, NULL},
{"IBM PS/2 Model 50", ROM_IBMPS2_M50, "ibmps2_m50", {{"", cpus_ps2_m30_286}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 16, 1, 63, ps2_model_50_init, NULL},
{"IBM PS/1 model 2121", ROM_IBMPS1_2121, "ibmps1_2121", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL},
{"IBM PS/1 m.2121 + ISA", ROM_IBMPS1_2121_ISA, "ibmps1_2121_isa", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, ps1_m2121_init, NULL},
{"IBM PS/2 Model 55SX", ROM_IBMPS2_M55SX, "ibmps2_m55sx", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 8, 1, 63, ps2_model_55sx_init, NULL},
{"DTK 386SX clone", ROM_DTK386, "dtk386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 16, 1, 127, at_neat_init, NULL},
{"Amstrad MegaPC", ROM_MEGAPC, "megapc", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL},
{"AMI 386SX clone", ROM_AMI386SX, "ami386", {{"Intel", cpus_i386SX}, {"AMD", cpus_Am386SX}, {"Cyrix", cpus_486SLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_headland_init, NULL},
{"Compaq Deskpro 386", ROM_DESKPRO_386, "dekspro386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, deskpro386_init, NULL},
{"Compaq Portable III 386", ROM_PORTABLEIII386, "portableiii386", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT, 1, 15, 1, 63, at_init, NULL},
{"IBM PS/2 Model 80", ROM_IBMPS2_M80, "ibmps2_m80", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_PS2_HDD | MODEL_MCA, 1, 12, 1, 63, ps2_model_80_init, NULL},
{"Amstrad MegaPC 386DX", ROM_MEGAPCDX, "megapcdx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 1, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 16, 1, 127, at_wd76c10_init, NULL},
{"MR 386DX clone", ROM_MR386DX_OPTI495, "mr386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL},
{"AMI 386DX clone", ROM_AMI386DX_OPTI495, "ami386dx", {{"Intel", cpus_i386DX}, {"AMD", cpus_Am386DX}, {"Cyrix", cpus_486DLC}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_opti495_init, NULL},
{"IBM PS/1 model 2133", ROM_IBMPS1_2133, "ibmps1_2133", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE, 1, 64, 1, 127, ps1_m2133_init, NULL},
{"AMI 486 clone", ROM_AMI486, "ami486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL},
{"AMI WinBIOS 486", ROM_WIN486, "win486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_ali1429_init, NULL},
{"DTK PKM-0038S E-2", ROM_DTK486, "dtk486", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE, 1, 64, 1, 127, at_dtk486_init, NULL},
{"Rise Computer R418", ROM_R418, "r418", {{"Intel", cpus_i486}, {"AMD", cpus_Am486}, {"Cyrix", cpus_Cx486}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 64, 1, 127, at_r418_init, NULL},
{"Intel Premiere/PCI", ROM_REVENGE, "revenge", {{"Intel", cpus_Pentium5V}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_batman_init, NULL},
#if 0
{"Micro Star 586MC1", ROM_586MC1, "586mc1", { "Intel", cpus_Pentium5V50, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_586mc1_init, NULL},
{"Micro Star 586MC1", ROM_586MC1, "586mc1", {{"Intel", cpus_Pentium5V50}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_586mc1_init, NULL},
#endif
{"Intel Premiere/PCI II", ROM_PLATO, "plato", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_plato_init, NULL},
{"Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL},
{"Intel Advanced/ZP", ROM_ZAPPA, "zappa", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL},
{"PC Partner MB500N", ROM_MB500N, "mb500n", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_mb500n_init, NULL},
{"President Award 430FX PCI", ROM_PRESIDENT, "president", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_president_init, NULL},
{"ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", { "Intel", cpus_PentiumS5, "IDT", cpus_WinChip, "AMD", cpus_K5, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p54tp4xe_init, NULL},
{"Intel Advanced/ATX", ROM_THOR, "thor", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL},
{"MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL},
{"AOpen AP53", ROM_AP53, "ap53", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_ap53_init, NULL},
{"ASUS P/I-P55T2S", ROM_P55T2S, "p55t2s", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2s_init, NULL},
{"Acer M3a", ROM_ACERM3A, "acerm3a", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerm3a_init, NULL},
{"Acer V35n", ROM_ACERV35N, "acerv35n", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerv35n_init, NULL},
{"ASUS P/I-P55T2P4", ROM_P55T2P4, "p55r2p4", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2p4_init, NULL},
{"Epox P55-VA", ROM_P55VA, "p55va", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55va_init, NULL},
{"ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", { "Intel", cpus_Pentium, "IDT", cpus_WinChip, "Cyrix", cpus_6x86, "AMD", cpus_K56, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55tvp4_init, NULL},
{"Tyan Titan-Pro AT", ROM_440FX, "440fx", { "Intel", cpus_PentiumPro, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_i440fx_init, NULL},
{"Tyan Titan-Pro ATX", ROM_S1668, "tpatx", { "Intel", cpus_PentiumPro, "", NULL, "", NULL, "", NULL, "", NULL}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_s1668_init, NULL},
{"", -1, "", {"", 0, "", 0, "", 0}, 0,0,0,0, 0}
{"Intel Premiere/PCI II", ROM_PLATO, "plato", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_plato_init, NULL},
{"Intel Advanced/EV", ROM_ENDEAVOR, "endeavor", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL},
{"Intel Advanced/ZP", ROM_ZAPPA, "zappa", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_endeavor_init, NULL},
{"PC Partner MB500N", ROM_MB500N, "mb500n", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_mb500n_init, NULL},
{"President Award 430FX PCI", ROM_PRESIDENT, "president", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_HAS_IDE | MODEL_PCI, 1, 128, 1, 127, at_president_init, NULL},
{"ASUS P/I-P54TP4XE", ROM_P54TP4XE, "p54tp4xe", {{ "Intel", cpus_PentiumS5}, {"IDT", cpus_WinChip}, {"AMD", cpus_K5}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p54tp4xe_init, NULL},
{"Intel Advanced/ATX", ROM_THOR, "thor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL},
{"MR Intel Advanced/ATX", ROM_MRTHOR, "mrthor", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_endeavor_init, NULL},
{"AOpen AP53", ROM_AP53, "ap53", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_ap53_init, NULL},
{"ASUS P/I-P55T2S", ROM_P55T2S, "p55t2s", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2s_init, NULL},
{"Acer M3a", ROM_ACERM3A, "acerm3a", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerm3a_init, NULL},
{"Acer V35n", ROM_ACERV35N, "acerv35n", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_acerv35n_init, NULL},
{"ASUS P/I-P55T2P4", ROM_P55T2P4, "p55r2p4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55t2p4_init, NULL},
{"Epox P55-VA", ROM_P55VA, "p55va", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55va_init, NULL},
{"ASUS P/I-P55TVP4", ROM_P55TVP4, "p55tvp4", {{"Intel", cpus_Pentium}, {"IDT", cpus_WinChip}, {"AMD", cpus_K56}, {"Cyrix", cpus_6x86},{"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_p55tvp4_init, NULL},
{"Tyan Titan-Pro AT", ROM_440FX, "440fx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_i440fx_init, NULL},
{"Tyan Titan-Pro ATX", ROM_S1668, "tpatx", {{"Intel", cpus_PentiumPro}, {"", NULL}, {"", NULL}, {"", NULL}, {"", NULL}}, 0, MODEL_AT | MODEL_PS2 | MODEL_HAS_IDE | MODEL_PCI, 1, 256, 1, 127, at_s1668_init, NULL},
{"", -1, "", {{"", 0}, {"", 0}, {"", 0}}, 0,0,0,0, 0}
};

2
src/mouse_bus.c
View File

@@ -380,7 +380,7 @@ static uint8_t
bm_read(uint16_t port, void *priv)
{
mouse_bus_t *ms = (mouse_bus_t *)priv;
uint8_t r;
uint8_t r = 0xff;
if (ms->flags & MOUSE_LOGITECH)
r = lt_read(ms, port - ms->port);

8
src/pc.c
View File

@@ -289,12 +289,15 @@ void initpc(int argc, wchar_t *argv[])
wchar_t *p;
wchar_t *config_file = NULL;
int c;
FILE *ff;
get_executable_name(pcempath, 511);
pclog("executable_name = %ws\n", pcempath);
p=get_filename_w(pcempath);
*p=L'\0';
pclog("path = %ws\n", pcempath);
#ifdef WALTJE
DIR *dir;
struct direct *dp;
#endif
for (c = 1; c < argc; c++)
{
@@ -325,9 +328,6 @@ void initpc(int argc, wchar_t *argv[])
{
/* some (undocumented) test function here.. */
#ifdef WALTJE
DIR *dir;
struct direct *dp;
dir = opendirw(pcempath);
if (dir != NULL) {
printf("Directory '%ws':\n", pcempath);

2
src/pit.c
View File

@@ -436,7 +436,7 @@ uint8_t pit_read(uint16_t addr, void *p)
{
PIT *pit = (PIT *)p;
int t;
uint8_t temp;
uint8_t temp = 0xff;
cycles -= (int)PITCONST;
switch (addr&3)
{

11
src/scsi_aha154x.c
View File

@@ -949,15 +949,6 @@ aha_reset(aha_t *dev)
}
static void
aha_softreset(void)
{
if (ResetDev != NULL) {
aha_reset(ResetDev);
}
}
static void
aha_reset_ctrl(aha_t *dev, uint8_t Reset)
{
@@ -2149,7 +2140,7 @@ uint8_t aha_mca_read(int port, void *p)
uint16_t aha_mca_get_port(uint8_t pos_port)
{
uint16_t addr;
uint16_t addr = 0;
switch (pos_port & 0xC7)
{
case 0x01:

9
src/scsi_buslogic.c
View File

@@ -623,15 +623,6 @@ BuslogicReset(Buslogic_t *bl)
}
static void
BuslogicSoftReset(void)
{
if (BuslogicResetDevice != NULL) {
BuslogicReset(BuslogicResetDevice);
}
}
static void
BuslogicResetControl(Buslogic_t *bl, uint8_t Reset)
{

4
src/serial.c
View File

@@ -116,7 +116,7 @@ enum {
#define MCR_OUT1 (0x04) /* 8250 */
#define MCR_OUT2 (0x08) /* 8250, INTEN on IBM-PC */
#define MCR_LMS (0x10)
#define MCR_AUTOFLOW (0x20) /* 16750
#define MCR_AUTOFLOW (0x20) /* 16750 */
/* LSR register bits. */
#define LSR_DR (0x01)
@@ -144,6 +144,7 @@ static SERIAL ports[NUM_SERIAL]; /* serial port data */
int serial_do_log;
#if 0
static void
serial_log(int lvl, const char *fmt, ...)
{
@@ -158,6 +159,7 @@ serial_log(int lvl, const char *fmt, ...)
}
#endif
}
#endif
static void

4
src/sio.c
View File

@@ -36,8 +36,8 @@ void sio_write(int func, int addr, uint8_t val, void *priv)
if (func > 0)
return;
if (addr >= 0x0f && addr < 0x4c)
return;
if (addr >= 0x0f && addr < 0x4c)
return;
switch (addr)
{

4
src/tandy_eeprom.c
View File

@@ -118,7 +118,7 @@ int tandy_eeprom_read()
void *tandy_eeprom_init()
{
tandy_eeprom_t *eeprom = malloc(sizeof(tandy_eeprom_t));
FILE *f;
FILE *f = NULL;
memset(eeprom, 0, sizeof(tandy_eeprom_t));
@@ -148,7 +148,7 @@ void *tandy_eeprom_init()
void tandy_eeprom_close(void *p)
{
tandy_eeprom_t *eeprom = (tandy_eeprom_t *)p;
FILE *f;
FILE *f = NULL;
switch (eeprom->romset)
{