mirror/86Box
1
0
Fork 0
mirror of https://github.com/86Box/86Box.git synced 2026-02-23 18:08:20 -07:00
Code Issues Packages Projects Releases Activity

Merge remote-tracking branch 'upstream/master' into feature/ich2

Browse Source
This commit is contained in:
Jasmine Iwanek
2022-11-05 01:06:57 -04:00
parent 0883897ad5 cfa2225732
commit 8075bdd9e2
7 changed files with 114 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
.github/workflows/c-cpp.yml vendored
View File

@@ -1,4 +1,4 @@
name: MinGW64 Makefile
name: MSYS2 Makefile
on:
@@ -16,7 +16,7 @@ on:
jobs:
build:
name: ${{ matrix.environment.msystem }} Makefile build (DEV_BUILD=${{ matrix.dev-build }}, NEW_DYNAREC=${{ matrix.new-dynarec }})
name: MSYS2 Makefile build ${{ matrix.build.name }} ${{ matrix.dynarec.name }} build (${{ matrix.environment.msystem }})
runs-on: windows-latest
@@ -27,8 +27,22 @@ jobs:
strategy:
fail-fast: true
matrix:
dev-build: ['y', 'n']
new-dynarec: ['y', 'n']
build:
- name: Debug
debug: y
dev: n
slug: -Debug
- name: Dev
debug: y
dev: y
slug: -Dev
dynarec:
- name: ODR
new: n
slug: -ODR
- name: NDR
new: y
slug: -NDR
environment:
- msystem: MINGW32
prefix: mingw-w64-i686
@@ -54,5 +68,9 @@ jobs:
${{ matrix.environment.prefix }}-rtmidi
- uses: actions/checkout@v3
- name: make
run: make -fwin/makefile.mingw -j DEV_BUILD=${{ matrix.dev-build }} NEW_DYNAREC=${{ matrix.new-dynarec }} X64=${{ matrix.environment.x64 }} VNC=n
run: make -fwin/makefile.mingw -j DEV_BUILD=${{ matrix.build.dev }} DEBUG=${{ matrix.build.debug }} NEW_DYNAREC=${{ matrix.dynarec.new }} X64=${{ matrix.environment.x64 }} VNC=n
working-directory: ./src
- uses: actions/upload-artifact@v3
with:
name: '86Box${{ matrix.dynarec.slug }}${{ matrix.build.slug }}-Windows-${{ matrix.environment.msystem }}-gha${{ github.run_number }}'
path: src/86Box.exe

1
src/include/86box/machine.h
View File

@@ -798,6 +798,7 @@ extern int machine_xt_v20xt_init(const machine_t *);
extern int machine_xt_iskra3104_init(const machine_t *);
extern int machine_xt_pravetz16_imko4_init(const machine_t *);
extern int machine_xt_micoms_xl7turbo_init(const machine_t *);
/* m_xt_compaq.c */
extern int machine_xt_compaq_deskpro_init(const machine_t *);

34
src/machine/m_xt.c
View File

@@ -334,25 +334,24 @@ machine_xt_pravetz16_imko4_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pravetz16/BIOS_IMKO4_FE00.bin",
ret = bios_load_linear("roms/machines/pravetz16/BIOS_IMKO4_FE00.BIN",
0x000fe000, 65536, 0);
if (ret) {
ret = bios_load_aux_linear("roms/machines/pravetz16/IMKO4-D34_SGS-M2764ADIP28.BIN",
0x000f4000, 8192, 0);
if (ret)
{
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F400.BIN",
0x000f4000, 8192, 0);
if (ret) {
bios_load_aux_linear("roms/machines/pravetz16/1.bin",
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F600.BIN",
0x000f6000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/2.bin",
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_FA00.BIN",
0x000fa000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/5.bin",
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_F800.BIN",
0x000f8000, 8192, 0);
bios_load_aux_linear("roms/machines/pravetz16/6.bin",
bios_load_aux_linear("roms/machines/pravetz16/BIOS_IMKO4_FC00.BIN",
0x000fc000, 8192, 0);
}
}
if (bios_only || !ret)
@@ -365,6 +364,21 @@ machine_xt_pravetz16_imko4_init(const machine_t *model)
return ret;
}
int
machine_xt_micoms_xl7turbo_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/mxl7t/XL7_TURBO.BIN",
0x000fe000, 8192, 0);
if (bios_only || !ret)
return ret;
machine_xt_init_ex(model);
return ret;
}
int
machine_xt_pc4i_init(const machine_t *model)
{

36
src/machine/machine_table.c
View File

@@ -924,6 +924,42 @@ const machine_t machines[] = {
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] Micoms XL-7 Turbo",
.internal_name = "mxl7t",
.type = MACHINE_TYPE_8088,
.chipset = MACHINE_CHIPSET_DISCRETE,
.init = machine_xt_micoms_xl7turbo_init,
.pad = 0,
.pad0 = 0,
.pad1 = MACHINE_AVAILABLE,
.pad2 = 0,
.cpu = {
.package = CPU_PKG_8088,
.block = CPU_BLOCK_NONE,
.min_bus = 0,
.max_bus = 0,
.min_voltage = 0,
.max_voltage = 0,
.min_multi = 0,
.max_multi = 0
},
.bus_flags = MACHINE_PC,
.flags = MACHINE_FLAGS_NONE,
.ram = {
.min = 64,
.max = 640,
.step = 64
},
.nvrmask = 0,
.kbc = KBC_IBM_PC_XT,
.kbc_p1 = 0xff00,
.gpio = 0xffffffff,
.device = NULL,
.vid_device = NULL,
.snd_device = NULL,
.net_device = NULL
},
{
.name = "[8088] NCR PC4i",
.internal_name = "pc4i",

38
src/scsi/scsi_pcscsi.c
View File

@@ -1251,6 +1251,7 @@ static void
esp_pci_soft_reset(esp_t *dev)
{
esp_irq(dev, 0);
dev->rregs[ESP_RSTAT] &= ~STAT_INT;
esp_pci_hard_reset(dev);
}
@@ -1632,9 +1633,11 @@ esp_pci_read(int func, int addr, void *p)
case 0x03:
return 0x20;
case 0x04:
return esp_pci_regs[0x04] & 3; /*Respond to IO*/
return esp_pci_regs[0x04] | 0x80; /*Respond to IO*/
case 0x05:
return esp_pci_regs[0x05];
case 0x07:
return 2;
return esp_pci_regs[0x07] | 0x02;
case 0x08:
return 0; /*Revision ID*/
case 0x09:
@@ -1646,7 +1649,7 @@ esp_pci_read(int func, int addr, void *p)
case 0x0E:
return 0; /*Header type */
case 0x10:
return 1; /*I/O space*/
return (esp_pci_bar[0].addr_regs[1] & 0x80) | 0x01; /*I/O space*/
case 0x11:
return esp_pci_bar[0].addr_regs[1];
case 0x12:
@@ -1707,10 +1710,25 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
valxor = (val & 3) ^ esp_pci_regs[addr];
if (valxor & PCI_COMMAND_IO) {
esp_io_remove(dev, dev->PCIBase, 0x80);
if ((dev->PCIBase != 0) && (val & PCI_COMMAND_IO))
if ((val & PCI_COMMAND_IO) && (dev->PCIBase != 0))
esp_io_set(dev, dev->PCIBase, 0x80);
}
esp_pci_regs[addr] = val & 3;
if (dev->has_bios && (valxor & PCI_COMMAND_MEM)) {
esp_bios_disable(dev);
if ((val & PCI_COMMAND_MEM) && (esp_pci_bar[1].addr & 0x00000001))
esp_bios_set_addr(dev, dev->BIOSBase);
}
if (dev->has_bios)
esp_pci_regs[addr] = val & 0x47;
else
esp_pci_regs[addr] = val & 0x45;
break;
case 0x05:
esp_pci_regs[addr] = val & 0x01;
break;
case 0x07:
esp_pci_regs[addr] &= ~(val & 0xf9);
break;
case 0x10:
@@ -1723,7 +1741,7 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
/* Then let's set the PCI regs. */
esp_pci_bar[0].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
esp_pci_bar[0].addr &= 0xff00;
esp_pci_bar[0].addr &= 0xff80;
dev->PCIBase = esp_pci_bar[0].addr;
/* Log the new base. */
// esp_log("ESP PCI: New I/O base is %04X\n" , dev->PCIBase);
@@ -1747,16 +1765,16 @@ esp_pci_write(int func, int addr, uint8_t val, void *p)
/* Then let's set the PCI regs. */
esp_pci_bar[1].addr_regs[addr & 3] = val;
/* Then let's calculate the new I/O base. */
esp_pci_bar[1].addr &= 0xfff80001;
dev->BIOSBase = esp_pci_bar[1].addr & 0xfff80000;
esp_pci_bar[1].addr &= 0xffff0001;
dev->BIOSBase = esp_pci_bar[1].addr & 0xffff0000;
/* Log the new base. */
// esp_log("ESP PCI: New BIOS base is %08X\n" , dev->BIOSBase);
/* We're done, so get out of the here. */
if (esp_pci_bar[1].addr & 0x00000001)
if ((esp_pci_regs[0x04] & PCI_COMMAND_MEM) && (esp_pci_bar[1].addr & 0x00000001))
esp_bios_set_addr(dev, dev->BIOSBase);
return;
case 0x3C:
case 0x3c:
esp_pci_regs[addr] = val;
dev->irq = val;
esp_log("ESP IRQ now: %i\n", val);

2
src/video/vid_cga.c
View File

@@ -540,7 +540,7 @@ cga_pravetz_init(const device_t *info)
{
cga_t *cga = cga_standalone_init(info);
loadfont("roms/video/cga/CGA - PRAVETZ.BIN", 10);
loadfont("roms/video/cga/PRAVETZ-VDC2.BIN", 10);
io_removehandler(0x03dd, 0x0001, cga_in, NULL, NULL, cga_out, NULL, NULL, cga);
io_sethandler(0x03dd, 0x0001, cga_pravetz_in, NULL, NULL, cga_pravetz_out, NULL, NULL, cga);

2
src/video/vid_voodoo_banshee.c
View File

@@ -527,7 +527,7 @@ banshee_recalctimings(svga_t *svga)
svga->bpp = 32;
break;
default:
fatal("Unknown pixel format %08x\n", banshee->vgaInit0);
fatal("Unknown pixel format %08x (vgaInit0=%08x)\n", VIDPROCCFG_DESKTOP_PIX_FORMAT, banshee->vgaInit0);
}
if (!(banshee->vidProcCfg & VIDPROCCFG_DESKTOP_TILE) && (banshee->vidProcCfg & VIDPROCCFG_HALF_MODE))
svga->rowcount = 1;