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Merge branch 'master' of https://github.com/86Box/86Box

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This commit is contained in:
RichardG867
2021-04-13 14:10:48 -03:00
parent b02e346943 3746b722c7
commit 80b1340454
51 changed files with 4565 additions and 4526 deletions
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64
src/chipset/intel_4x0.c
View File

@@ -120,20 +120,22 @@ i4x0_smram_handler_phase0(i4x0_t *dev)
static void
i4x0_smram_handler_phase1(i4x0_t *dev)
{
uint8_t *regs = (uint8_t *) dev->regs;
uint32_t tom = (mem_size << 10);
uint8_t *reg = (dev->type >= INTEL_430LX) ? &(regs[0x72]) : &(regs[0x57]);
uint8_t *ext_reg = (dev->type >= INTEL_440BX) ? &(regs[0x73]) : &(regs[0x71]);
uint32_t s, base[2] = { 0x000a0000, 0x00000000 };
uint32_t size[2] = { 0x00010000, 0x00000000 };
if (dev->type >= INTEL_430FX) {
if ((dev->type <= INTEL_420ZX) || (dev->type >= INTEL_430FX)) {
/* Set temporary bases and sizes. */
if (((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) &&
(*ext_reg & 0x80)) {
base[0] = 0x100a0000;
size[0] = 0x00060000;
} else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((regs[0x72] & 0x07) == 0x04)) {
} else if (((dev->type == INTEL_440LX) || (dev->type == INTEL_440EX)) && ((*reg & 0x07) == 0x04)) {
base[0] = 0x000c0000;
size[0] = 0x00010000;
} else {
@@ -141,11 +143,11 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
size[0] = 0x00020000;
}
if (regs[0x72] & 0x08)
if (*reg & 0x08)
smram_enable(dev->smram_low, base[0], base[0] & 0x000f0000, size[0],
((regs[0x72] & 0x78) == 0x48), (regs[0x72] & 0x08));
((*reg & 0x78) == 0x48), (*reg & 0x08));
if ((regs[0x72] & 0x28) == 0x28) {
if ((*reg & 0x28) == 0x28) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
@@ -153,7 +155,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
/* TSEG mapping. */
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
if ((regs[0x72] & 0x08) && (*ext_reg & 0x01)) {
if ((*reg & 0x08) && (*ext_reg & 0x01)) {
size[1] = (1 << (17 + ((*ext_reg >> 1) & 0x03)));
tom -= size[1];
base[1] = tom;
@@ -169,7 +171,7 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
}
} else {
size[0] = 0x00010000;
switch (regs[0x72] & 0x03) {
switch (*reg & 0x03) {
case 0:
default:
base[0] = (mem_size << 10) - size[0];
@@ -191,9 +193,9 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
if (size[0] != 0x00000000) {
smram_enable(dev->smram_low, base[0], base[0], size[0],
(((regs[0x72] & 0x38) == 0x20) || s), 1);
(((*reg & 0x38) == 0x20) || s), 1);
if (regs[0x72] & 0x10) {
if (*reg & 0x10) {
/* If SMRAM is enabled and DCLS is set, then data goes to PCI, but
code still goes to DRAM. */
mem_set_mem_state_smram_ex(1, base[0], size[0], 0x02);
@@ -517,7 +519,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x57:
switch (dev->type) {
/* On the 420TX and 420ZX, this is the SMRAM space register. */
case INTEL_420TX: case INTEL_420ZX:
i4x0_smram_handler_phase0(dev);
if (dev->smram_locked)
regs[0x57] = (regs[0x57] & 0xdf) | (val & 0x20);
else {
regs[0x57] = (regs[0x57] & 0x87) | (val & 0x78);
dev->smram_locked = (val & 0x10);
if (dev->smram_locked)
regs[0x57] &= 0xbf;
}
i4x0_smram_handler_phase1(dev);
break;
case INTEL_430LX: default:
regs[0x57] = val & 0x3f;
break;
@@ -824,6 +838,9 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
}
break;
case 0x72: /* SMRAM */
if (dev->type <= INTEL_420ZX)
break;
i4x0_smram_handler_phase0(dev);
if (dev->type >= INTEL_430FX) {
if (dev->smram_locked)
@@ -1215,6 +1232,10 @@ i4x0_reset(void *priv)
i4x0_t *dev = (i4x0_t *)priv;
int i;
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) ||
(dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x59, 0x00, priv);
else
@@ -1229,14 +1250,18 @@ i4x0_reset(void *priv)
if (dev->type >= INTEL_430FX) {
dev->regs[0x72] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x02, priv);
} else {
} else if (dev->type >= INTEL_430LX) {
dev->regs[0x72] &= 0xf7; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x72, 0x00, priv);
} else {
dev->regs[0x57] &= 0xef; /* Forcibly unlock the SMRAM register. */
i4x0_write(0, 0x57, 0x02, priv);
}
if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) ||
(dev->type == INTEL_440ZX))
memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, priv);
}
}
@@ -1554,7 +1579,18 @@ static void
i4x0_write(regs[0x5d], 0x5d, 0x00, dev);
i4x0_write(regs[0x5e], 0x5e, 0x00, dev);
i4x0_write(regs[0x5f], 0x5f, 0x00, dev);
i4x0_write(regs[0x72], 0x72, 0x00, dev);
if (dev->type >= INTEL_430FX)
i4x0_write(0, 0x72, 0x02, dev);
else if (dev->type >= INTEL_430LX)
i4x0_write(0, 0x72, 0x00, dev);
else
i4x0_write(0, 0x57, 0x02, dev);
if ((dev->type == INTEL_430TX) || (dev->type >= INTEL_440BX)) {
i4x0_write(0, (dev->type >= INTEL_440BX) ? 0x73 : 0x71,
(dev->type >= INTEL_440BX) ? 0x38 : 0x00, dev);
}
pci_add_card(PCI_ADD_NORTHBRIDGE, i4x0_read, i4x0_write, dev);

27
src/chipset/intel_i450kx.c
View File

@@ -66,9 +66,9 @@ i450kx_log(const char *fmt, ...)
/* SMRAM */
#define SMRAM_ADDR (((dev->pb_pci_conf[0xb9] << 8) | dev->pb_pci_conf[0xb8]) << 17)
#define SMRAM_SIZE (1 << (((dev->pb_pci_conf[0xbb] >> 4) + 1) * 16))
#define SMRAM_ADDR_MC (((dev->mc_pci_conf[0xb9] << 8) | dev->mc_pci_conf[0xb8]) << 16)
#define SMRAM_SIZE_MC (1 << (((dev->mc_pci_conf[0xbb] >> 4) + 1) * 16))
#define SMRAM_SIZE (((dev->pb_pci_conf[0xbb] >> 4) + 1) * 64)
#define SMRAM_SIZE_MC (((dev->mc_pci_conf[0xbb] >> 4) + 1) * 64)
/* Miscellaneous */
#define ENABLE_SEGMENT (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
@@ -101,10 +101,7 @@ void i450kx_smm(uint32_t smram_addr, uint32_t smram_size, i450kx_t *dev)
smram_disable_all();
if ((smram_addr != 0) && !!(dev->mc_pci_conf[0x57] & 8))
{
smram_enable(dev->smram, smram_addr, smram_addr, smram_size, !!(dev->pb_pci_conf[0x57] & 8), 1);
mem_set_mem_state_smram_ex(1, smram_addr, smram_size, 0x03);
}
flushmmucache();
}
@@ -263,11 +260,7 @@ pb_write(int func, int addr, uint8_t val, void *priv)
case 0xb8:
case 0xb9:
case 0xbb:
if (addr == 0xbb)
dev->pb_pci_conf[addr] = val & 0xf0;
else
dev->pb_pci_conf[addr] = val;
dev->pb_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
i450kx_smm(SMRAM_ADDR, SMRAM_SIZE, dev);
break;
@@ -324,7 +317,6 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0x58:
dev->mc_pci_conf[addr] = val & 2;
mem_set_mem_state_both(0xa0000, 0x20000, (val & 2) ? ENABLE_SEGMENT : DISABLE_SEGMENT);
break;
case 0x59:
@@ -354,8 +346,8 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0x6d:
case 0x6e:
case 0x6f:
dev->mc_pci_conf[addr] = ((addr & 0x0f) % 2) ? val : (val & 7);
spd_write_drbs(dev->mc_pci_conf, 0x60, 0x6f, 1);
dev->mc_pci_conf[addr] = ((addr & 0x0f) % 2) ? 0 : (val & 0x7f);
spd_write_drbs(dev->mc_pci_conf, 0x60, 0x6f, 4);
break;
case 0x74:
@@ -447,10 +439,7 @@ mc_write(int func, int addr, uint8_t val, void *priv)
case 0xb8:
case 0xb9:
case 0xbb:
if (addr == 0xbb)
dev->mc_pci_conf[addr] = val & 0xf0;
else
dev->mc_pci_conf[addr] = val;
dev->mc_pci_conf[addr] = !(addr == 0xbb) ? val : (val & 0xf0);
i450kx_smm(SMRAM_ADDR_MC, SMRAM_SIZE_MC, dev);
break;
@@ -500,7 +489,7 @@ i450kx_reset(void *priv)
dev->pb_pci_conf[0x05] = 4;
dev->pb_pci_conf[0x06] = 0x40;
dev->pb_pci_conf[0x07] = 2;
dev->pb_pci_conf[0x08] = 1;
dev->pb_pci_conf[0x08] = 2;
dev->pb_pci_conf[0x0b] = 6;
dev->pb_pci_conf[0x0c] = 8;
dev->pb_pci_conf[0x0d] = 0x20;
@@ -526,7 +515,7 @@ i450kx_reset(void *priv)
dev->mc_pci_conf[0x02] = 0xc5;
dev->mc_pci_conf[0x03] = 0x84;
dev->mc_pci_conf[0x06] = 0x80;
dev->mc_pci_conf[0x08] = 1;
dev->mc_pci_conf[0x08] = 4;
dev->mc_pci_conf[0x0b] = 5;
dev->mc_pci_conf[0x49] = 0x14;
dev->mc_pci_conf[0x4c] = 0x0b;

2
src/chipset/intel_piix.c
View File

@@ -1374,6 +1374,8 @@ static void
else
dev->board_config[1] |= 0x00;
device_add(&i8254_sec_device);
return dev;
}

3
src/chipset/intel_sio.c
View File

@@ -218,7 +218,6 @@ sio_write(int func, int addr, uint8_t val, void *priv)
break;
case 0x60: case 0x61: case 0x62: case 0x63:
if (dev->id == 0x03) {
pclog("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
sio_log("Set IRQ routing: INT %c -> %02X\n", 0x41 + (addr & 0x03), val);
dev->regs[addr] = val & 0x8f;
if (val & 0x80)
@@ -540,6 +539,8 @@ sio_init(const device_t *info)
timer_add(&dev->timer, NULL, NULL, 0);
device_add(&i8254_sec_device);
return dev;
}

13
src/chipset/sis_85c496.c
View File

@@ -299,7 +299,7 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
smram_disable_all();
if (val & 0x06) {
if (val & 0x02) {
host_base = 0x00060000;
ram_base = 0x000a0000;
size = 0x00010000;
@@ -453,6 +453,12 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
uint8_t ret = dev->pci_conf[addr];
switch (addr) {
case 0xa0:
ret &= 0x10;
break;
case 0xa1:
ret = 0x00;
break;
case 0x82: /*Port 22h Mirror*/
ret = dev->cur_reg;
break;
@@ -517,6 +523,7 @@ sis_85c496_reset(void *priv)
sis_85c49x_pci_write(0, 0x58, 0x00, dev);
sis_85c49x_pci_write(0, 0x59, 0x00, dev);
sis_85c49x_pci_write(0, 0x5a, 0x00, dev);
// sis_85c49x_pci_write(0, 0x5a, 0x06, dev);
for (i = 0; i < 8; i++)
sis_85c49x_pci_write(0, 0x48 + i, 0x00, dev);
@@ -589,7 +596,7 @@ static void
pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);
sis_85c497_isa_reset(dev);
// sis_85c497_isa_reset(dev);
dev->port_92 = device_add(&port_92_device);
port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
@@ -609,6 +616,8 @@ static void
timer_add(&dev->rmsmiblk_timer, sis_85c496_rmsmiblk_count, dev, 0);
sis_85c496_reset(dev);
return dev;
}

30
src/config.c
View File

@@ -450,7 +450,9 @@ load_general(void)
char temp[512];
char *p;
vid_resize = !!config_get_int(cat, "vid_resize", 0);
vid_resize = config_get_int(cat, "vid_resize", 0);
if (vid_resize & ~3)
vid_resize &= 3;
memset(temp, '\0', sizeof(temp));
p = config_get_string(cat, "vid_renderer", "default");
@@ -488,6 +490,25 @@ load_general(void)
window_w = window_h = window_x = window_y = 0;
}
if (vid_resize & 2) {
p = config_get_string(cat, "window_fixed_res", NULL);
if (p == NULL)
p = "120x120";
sscanf(p, "%ix%i", &fixed_size_x, &fixed_size_y);
if (fixed_size_x < 120)
fixed_size_x = 120;
if (fixed_size_x > 2048)
fixed_size_x = 2048;
if (fixed_size_y < 120)
fixed_size_y = 120;
if (fixed_size_y > 2048)
fixed_size_y = 2048;
} else {
config_delete_var(cat, "window_fixed_res");
fixed_size_x = fixed_size_y = 120;
}
sound_gain = config_get_int(cat, "sound_gain", 0);
confirm_reset = config_get_int(cat, "confirm_reset", 1);
@@ -1720,6 +1741,7 @@ config_load(void)
fpu_type = fpu_get_type(cpu_f, cpu, "none");
gfxcard = video_get_video_from_internal_name("cga");
vid_api = plat_vidapi("default");
vid_resize = 0;
time_sync = TIME_SYNC_ENABLED;
hdc_current = hdc_get_from_internal_name("none");
serial_enabled[0] = 1;
@@ -1857,6 +1879,12 @@ save_general(void)
config_delete_var(cat, "window_coordinates");
}
if (vid_resize & 2) {
sprintf(temp, "%ix%i", fixed_size_x, fixed_size_y);
config_set_string(cat, "window_fixed_res", temp);
} else
config_delete_var(cat, "window_fixed_res");
if (sound_gain != 0)
config_set_int(cat, "sound_gain", sound_gain);
else

10
src/cpu/386.c
View File

@@ -134,9 +134,9 @@ static inline void fetch_ea_32_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if ( readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}
@@ -174,9 +174,9 @@ static inline void fetch_ea_16_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if ( readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}
@@ -271,7 +271,7 @@ exec386(int cycs)
CS = oldcs;
#endif
cpu_state.pc = cpu_state.oldpc;
x386_log("Double fault %i\n", ins);
x386_log("Double fault\n");
pmodeint(8, 0);
if (cpu_state.abrt) {
cpu_state.abrt = 0;

85
src/cpu/386_common.c
View File

@@ -65,10 +65,17 @@ uint32_t old_rammask = 0xffffffff;
int soft_reset_mask = 0;
int in_smm = 0, smi_line = 0, smi_latched = 0, smm_in_hlt = 0;
int smi_block = 0;
uint32_t smbase = 0x30000;
#define AMD_SYSCALL_EIP (star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((star >> 48) & 0xFFFF)
uint32_t addr64, addr64_2;
uint32_t addr64a[8], addr64a_2[8];
#define AMD_SYSCALL_EIP (msr.star & 0xFFFFFFFF)
#define AMD_SYSCALL_SB ((msr.star >> 32) & 0xFFFF)
#define AMD_SYSRET_SB ((msr.star >> 48) & 0xFFFF)
/* These #define's and enum have been borrowed from Bochs. */
@@ -1020,7 +1027,7 @@ enter_smm(int in_hlt)
uint32_t smram_state = smbase + 0x10000;
/* If it's a CPU on which SMM is not supported, do nothing. */
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cxsmm)
return;
x386_common_log("enter_smm(): smbase = %08X\n", smbase);
@@ -1059,7 +1066,7 @@ enter_smm(int in_hlt)
smram_backup_all();
smram_recalc_all(0);
if (cpu_iscyrix) {
if (is_cxsmm) {
if (!(cyrix.smhr & SMHR_VALID))
cyrix.smhr = (cyrix.arr[3].base + cyrix.arr[3].size) | SMHR_VALID;
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
@@ -1067,11 +1074,11 @@ enter_smm(int in_hlt)
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
if (cpu_iscyrix) /* Cx6x86 */
if (is_cxsmm) /* Cx6x86 */
smram_save_state_cyrix(saved_state, in_hlt);
if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
else if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
smram_save_state_p5(saved_state, in_hlt);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
else if (is_k5 || is_k6) /* AMD K5 and K6 */
smram_save_state_amd_k(saved_state, in_hlt);
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_save_state_p6(saved_state, in_hlt);
@@ -1084,8 +1091,11 @@ enter_smm(int in_hlt)
dr[7] = 0x400;
if (cpu_iscyrix) {
if (is_cxsmm) {
cpu_state.pc = 0x0000;
cpl_override = 1;
cyrix_write_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
cpl_override = 0;
cpu_state.seg_cs.seg = (cyrix.arr[3].base >> 4);
cpu_state.seg_cs.base = cyrix.arr[3].base;
cpu_state.seg_cs.limit = 0xffffffff;
@@ -1130,15 +1140,14 @@ enter_smm(int in_hlt)
cpu_state.op32 = use32;
cpl_override = 1;
if (cpu_iscyrix) {
if (is_cxsmm) {
writememl(0, smram_state - 0x04, saved_state[0]);
writememl(0, smram_state - 0x08, saved_state[1]);
writememl(0, smram_state - 0x0c, saved_state[2]);
writememl(0, smram_state - 0x10, saved_state[3]);
writememl(0, smram_state - 0x14, saved_state[4]);
writememl(0, smram_state - 0x18, saved_state[5]);
cyrix_write_seg_descriptor(smram_state - 0x20, &cpu_state.seg_cs);
writememl(0, smram_state - 0x18, saved_state[6]);
writememl(0, smram_state - 0x24, saved_state[6]);
} else {
for (n = 0; n < SMM_SAVE_STATE_MAP_SIZE; n++) {
smram_state -= 4;
@@ -1207,13 +1216,13 @@ leave_smm(void)
uint32_t smram_state = smbase + 0x10000;
/* If it's a CPU on which SMM is not supported (or not implemented in 86Box), do nothing. */
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cx6x86)
if (!is_am486 && !is_pentium && !is_k5 && !is_k6 && !is_p6 && !is_cxsmm)
return;
memset(saved_state, 0x00, SMM_SAVE_STATE_MAP_SIZE * sizeof(uint32_t));
cpl_override = 1;
if (cpu_iscyrix) {
if (is_cxsmm) {
smram_state = cyrix.smhr & SMHR_ADDR_MASK;
saved_state[0] = readmeml(0, smram_state - 0x04);
saved_state[1] = readmeml(0, smram_state - 0x08);
@@ -1239,13 +1248,13 @@ leave_smm(void)
}
x386_common_log("New SMBASE: %08X (%08X)\n", saved_state[SMRAM_FIELD_P5_SMBASE_OFFSET], saved_state[66]);
if (cpu_iscyrix) /* Cx6x86 */
if (is_cxsmm) /* Cx6x86 */
smram_restore_state_cyrix(saved_state);
else if (is_pentium) /* Intel P5 (Pentium) */
else if (is_pentium || is_am486) /* Am486 / 5x86 / Intel P5 (Pentium) */
smram_restore_state_p5(saved_state);
else if (is_k5 || is_k6) /* AMD K5 and K6 */
else if (is_k5 || is_k6) /* AMD K5 and K6 */
smram_restore_state_amd_k(saved_state);
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
else if (is_p6) /* Intel P6 (Pentium Pro, Pentium II, Celeron) */
smram_restore_state_p6(saved_state);
in_smm = 0;
@@ -1312,7 +1321,7 @@ x86_int(int num)
else {
addr = (num << 2) + idt.base;
if ((num << 2) + 3 > idt.limit) {
if ((num << 2UL) + 3UL > idt.limit) {
if (idt.limit < 35) {
cpu_state.abrt = 0;
softresetx86();
@@ -1363,7 +1372,7 @@ x86_int_sw(int num)
else {
addr = (num << 2) + idt.base;
if ((num << 2) + 3 > idt.limit)
if ((num << 2UL) + 3UL > idt.limit)
x86_int(0x0d);
else {
if (stack32) {
@@ -1447,7 +1456,7 @@ x86illegal()
int
checkio(int port)
checkio(uint32_t port)
{
uint16_t t;
uint8_t d;
@@ -1459,7 +1468,7 @@ checkio(int port)
if (cpu_state.abrt)
return 0;
if ((t + (port >> 3)) > tr.limit)
if ((t + (port >> 3UL)) > tr.limit)
return 1;
cpl_override = 1;
@@ -1599,7 +1608,7 @@ sysenter(uint32_t fetchdat)
return cpu_state.abrt;
}
if (!(cs_msr & 0xFFF8)) {
if (!(msr.sysenter_cs & 0xFFF8)) {
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSENTER: CS MSR is zero");
#endif
@@ -1611,7 +1620,7 @@ sysenter(uint32_t fetchdat)
x386_common_log("SYSENTER started:\n");
x386_common_log(" CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
x386_common_log(" SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", msr.sysenter_cs, msr.sysenter_esp, msr.sysenter_eip, pccache, pccache2);
x386_common_log(" EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
#endif
@@ -1623,25 +1632,23 @@ sysenter(uint32_t fetchdat)
oldcs = CS;
#endif
cpu_state.oldpc = cpu_state.pc;
ESP = esp_msr;
cpu_state.pc = eip_msr;
ESP = msr.sysenter_esp;
cpu_state.pc = msr.sysenter_eip;
cpu_state.seg_cs.seg = (cs_msr & 0xfffc);
cpu_state.seg_cs.seg = (msr.sysenter_cs & 0xfffc);
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0x9b;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
oldcpl = 0;
cpu_state.seg_ss.seg = ((cs_msr + 8) & 0xfffc);
cpu_state.seg_ss.seg = ((msr.sysenter_cs + 8) & 0xfffc);
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0x93;
cpu_state.seg_ss.ar_high = 0xcf;
@@ -1661,7 +1668,7 @@ sysenter(uint32_t fetchdat)
x386_common_log("SYSENTER completed:\n");
x386_common_log(" CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
x386_common_log(" SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", msr.sysenter_cs, msr.sysenter_esp, msr.sysenter_eip, pccache, pccache2);
x386_common_log(" EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
#endif
@@ -1676,7 +1683,7 @@ sysexit(uint32_t fetchdat)
x386_common_log("SYSEXIT called\n");
#endif
if (!(cs_msr & 0xFFF8)) {
if (!(msr.sysenter_cs & 0xFFF8)) {
#ifdef ENABLE_386_COMMON_LOG
x386_common_log("SYSEXIT: CS MSR is zero");
#endif
@@ -1704,7 +1711,7 @@ sysexit(uint32_t fetchdat)
x386_common_log("SYSEXIT start:\n");
x386_common_log(" CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
x386_common_log(" SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", msr.sysenter_cs, msr.sysenter_esp, msr.sysenter_eip, pccache, pccache2);
x386_common_log(" EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
#endif
@@ -1715,22 +1722,20 @@ sysexit(uint32_t fetchdat)
ESP = ECX;
cpu_state.pc = EDX;
cpu_state.seg_cs.seg = (((cs_msr + 16) & 0xfffc) | 3);
cpu_state.seg_cs.seg = (((msr.sysenter_cs + 16) & 0xfffc) | 3);
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0xfb;
cpu_state.seg_cs.ar_high = 0xcf;
cpu_state.seg_cs.checked = 1;
oldcpl = 3;
cpu_state.seg_ss.seg = (((cs_msr + 24) & 0xfffc) | 3);
cpu_state.seg_ss.seg = (((msr.sysenter_cs + 24) & 0xfffc) | 3);
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0xf3;
cpu_state.seg_ss.ar_high = 0xcf;
@@ -1751,7 +1756,7 @@ sysexit(uint32_t fetchdat)
x386_common_log("SYSEXIT completed:\n");
x386_common_log(" CS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; EIP=%08X\n", cpu_state.seg_cs.seg, !!cpu_state.seg_cs.checked, cpu_state.seg_cs.base, cpu_state.seg_cs.limit, cpu_state.seg_cs.limit_low, cpu_state.seg_cs.limit_high, cpu_state.seg_cs.ar_high, cpu_state.seg_cs.access, cpu_state.pc);
x386_common_log(" SS %04X/%i: b=%08X l=%08X (%08X-%08X) a=%02X%02X; ESP=%08X\n", cpu_state.seg_ss.seg, !!cpu_state.seg_ss.checked, cpu_state.seg_ss.base, cpu_state.seg_ss.limit, cpu_state.seg_ss.limit_low, cpu_state.seg_ss.limit_high, cpu_state.seg_ss.ar_high, cpu_state.seg_ss.access, ESP);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", cs_msr, esp_msr, eip_msr, pccache, pccache2);
x386_common_log(" Misc. : MSR (CS/ESP/EIP)=%04X/%08X/%08X pccache=%08X/%08X\n", msr.sysenter_cs, msr.sysenter_esp, msr.sysenter_eip, pccache, pccache2);
x386_common_log(" EFLAGS=%04X%04X/%i 32=%i/%i ECX=%08X EDX=%08X abrt=%02X\n", cpu_state.eflags, cpu_state.flags, !!trap, !!use32, !!stack32, ECX, EDX, cpu_state.abrt);
#endif
@@ -1782,7 +1787,6 @@ syscall_op(uint32_t fetchdat)
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0x9b;
cpu_state.seg_cs.ar_high = 0xcf;
@@ -1794,7 +1798,6 @@ syscall_op(uint32_t fetchdat)
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0x93;
cpu_state.seg_ss.ar_high = 0xcf;
@@ -1845,7 +1848,6 @@ sysret(uint32_t fetchdat)
cpu_state.seg_cs.base = 0;
cpu_state.seg_cs.limit_low = 0;
cpu_state.seg_cs.limit = 0xffffffff;
cpu_state.seg_cs.limit_raw = 0x000fffff;
cpu_state.seg_cs.limit_high = 0xffffffff;
cpu_state.seg_cs.access = 0xfb;
cpu_state.seg_cs.ar_high = 0xcf;
@@ -1857,7 +1859,6 @@ sysret(uint32_t fetchdat)
cpu_state.seg_ss.base = 0;
cpu_state.seg_ss.limit_low = 0;
cpu_state.seg_ss.limit = 0xffffffff;
cpu_state.seg_ss.limit_raw = 0x000fffff;
cpu_state.seg_ss.limit_high = 0xffffffff;
cpu_state.seg_ss.access = 0xf3;
cpu_state.seg_cs.ar_high = 0xcf;

46
src/cpu/386_common.h
View File

@@ -15,38 +15,40 @@
* Copyright 2008-2019 Sarah Walker.
* Copyright 2016-2019 Miran Grca.
*/
#ifndef _386_COMMON_H_
#define _386_COMMON_H_
#include <stddef.h>
#define readmemb_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF)?readmembl_no_mmut((s)+(a),b): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uintptr_t)((s) + (a))) )
#define readmemw_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl_no_mmut((s)+(a),b):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmeml_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll_no_mmut((s)+(a),b):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF)?readmembl((s)+(a)): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uintptr_t)((s) + (a))) )
#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 7))?readmemql((s)+(a)):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uintptr_t)((s)+(a))))
#define readmemb_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF)?readmembl_no_mmut((s)+(a),b): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uintptr_t)((s) + (a))) )
#define readmemw_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl_no_mmut((s)+(a),b):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmeml_n(s,a,b) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll_no_mmut((s)+(a),b):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemb(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF)?readmembl((s)+(a)): *(uint8_t *)(readlookup2[(uint32_t)((s)+(a))>>12] + (uintptr_t)((s) + (a))) )
#define readmemw(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1))?readmemwl((s)+(a)):*(uint16_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmeml(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3))?readmemll((s)+(a)):*(uint32_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uint32_t)((s)+(a))))
#define readmemq(s,a) ((readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 7))?readmemql((s)+(a)):*(uint64_t *)(readlookup2[(uint32_t)((s)+(a))>>12]+(uintptr_t)((s)+(a))))
#define writememb_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF) writemembl_no_mmut((s)+(a),b,v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememw_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl_no_mmut((s)+(a),b,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememl_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll_no_mmut((s)+(a),b,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF) writemembl((s)+(a),v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl((s)+(a),v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll((s)+(a),v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 7)) writememql((s)+(a),v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememb_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF) writemembl_no_mmut((s)+(a),b,v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememw_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl_no_mmut((s)+(a),b,v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememl_n(s,a,b,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll_no_mmut((s)+(a),b,v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememb(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF) writemembl((s)+(a),v); else *(uint8_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememw(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) writememwl((s)+(a),v); else *(uint16_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememl(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) writememll((s)+(a),v); else *(uint32_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define writememq(s,a,v) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 7)) writememql((s)+(a),v); else *(uint64_t *)(writelookup2[(uint32_t)((s) + (a)) >> 12] + (uintptr_t)((s) + (a))) = v
#define do_mmut_rb(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF) do_mmutranslate((s)+(a), b, 1, 0)
#define do_mmut_rw(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) do_mmutranslate((s)+(a), b, 2, 0)
#define do_mmut_rl(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) do_mmutranslate((s)+(a), b, 4, 0)
#define do_mmut_rb(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF) do_mmutranslate((s)+(a), b, 1, 0)
#define do_mmut_rw(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) do_mmutranslate((s)+(a), b, 2, 0)
#define do_mmut_rl(s,a,b) if (readlookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) do_mmutranslate((s)+(a), b, 4, 0)
#define do_mmut_rb2(s,a,b) old_rl2 = readlookup2[(uint32_t)((s)+(a))>>12]; if (old_rl2==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF) do_mmutranslate((s)+(a), b, 1, 0)
#define do_mmut_rw2(s,a,b) old_rl2 = readlookup2[(uint32_t)((s)+(a))>>12]; if (old_rl2==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) do_mmutranslate((s)+(a), b, 2, 0)
#define do_mmut_rl2(s,a,b) old_rl2 = readlookup2[(uint32_t)((s)+(a))>>12]; if (old_rl2==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) do_mmutranslate((s)+(a), b, 4, 0)
#define do_mmut_wb(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF) do_mmutranslate((s)+(a), b, 1, 1)
#define do_mmut_ww(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) do_mmutranslate((s)+(a), b, 2, 1)
#define do_mmut_wl(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) do_mmutranslate((s)+(a), b, 4, 1)
#define do_mmut_wb(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF) do_mmutranslate((s)+(a), b, 1, 1)
#define do_mmut_ww(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 1)) do_mmutranslate((s)+(a), b, 2, 1)
#define do_mmut_wl(s,a,b) if (writelookup2[(uint32_t)((s)+(a))>>12]==(uintptr_t)LOOKUP_INV || (s)==0xFFFFFFFF || (((s)+(a)) & 3)) do_mmutranslate((s)+(a), b, 4, 1)
int checkio(int port);
int checkio(uint32_t port);
#define check_io_perm(port) if (msw&1 && ((CPL > IOPL) || (cpu_state.eflags&VM_FLAG))) \

8
src/cpu/386_dynarec.c
View File

@@ -121,9 +121,9 @@ static __inline void fetch_ea_32_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if ( readlookup2[addr >> 12] != (uintptr_t) -1)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) -1)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}
@@ -161,9 +161,9 @@ static __inline void fetch_ea_16_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if (readlookup2[addr >> 12] != (uintptr_t) -1)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) -1)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}

8
src/cpu/386_dynarec_ops.c
View File

@@ -33,9 +33,9 @@ static __inline void fetch_ea_32_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if ( readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}
@@ -47,9 +47,9 @@ static __inline void fetch_ea_16_long(uint32_t rmdat)
if (easeg != 0xFFFFFFFF && ((easeg + cpu_state.eaaddr) & 0xFFF) <= 0xFFC)
{
uint32_t addr = easeg + cpu_state.eaaddr;
if ( readlookup2[addr >> 12] != -1)
if ( readlookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_r = (uint32_t *)(readlookup2[addr >> 12] + addr);
if (writelookup2[addr >> 12] != -1)
if (writelookup2[addr >> 12] != (uintptr_t) LOOKUP_INV)
eal_w = (uint32_t *)(writelookup2[addr >> 12] + addr);
}
}

94
src/cpu/386_ops.h
View File

@@ -170,9 +170,7 @@ extern void x386_dynarec_log(const char *fmt, ...);
#include "x86_ops_bcd.h"
#include "x86_ops_bit.h"
#include "x86_ops_bitscan.h"
#if defined(DEV_BRANCH) && defined(USE_CYRIX_6X86)
#include "x86_ops_cyrix.h"
#endif
#include "x86_ops_flag.h"
#include "x86_ops_fpu.h"
#include "x86_ops_inc_dec.h"
@@ -635,6 +633,98 @@ const OpFn OP_TABLE(486_0f)[1024] =
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
const OpFn OP_TABLE(c486_0f)[1024] =
{
/*16-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_w_a16, opLAR_w_a16, opLSL_w_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, ILLEGAL, ILLEGAL,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a16, opSHLD_w_i_a16, opSHLD_w_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a16, opSHRD_w_i_a16, opSHRD_w_CL_a16,ILLEGAL, opIMUL_w_w_a16,
/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_w_a16,opLSS_w_a16, opBTR_w_r_a16, opLFS_w_a16, opLGS_w_a16, opMOVZX_w_b_a16,opMOVZX_w_w_a16,ILLEGAL, ILLEGAL, opBA_w_a16, opBTC_w_r_a16, opBSF_w_a16, opBSR_w_a16, opMOVSX_w_b_a16,ILLEGAL,
/*c0*/ opXADD_b_a16, opXADD_w_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 16-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a16, op0F01_l_a16, opLAR_l_a16, opLSL_l_a16, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a16,opMOV_r_DRx_a16,opMOV_CRx_r_a16,opMOV_DRx_r_a16,opMOV_r_TRx_a16,ILLEGAL, opMOV_TRx_r_a16,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a16, opWRSHR_a16, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a16, opSETNO_a16, opSETB_a16, opSETNB_a16, opSETE_a16, opSETNE_a16, opSETBE_a16, opSETNBE_a16, opSETS_a16, opSETNS_a16, opSETP_a16, opSETNP_a16, opSETL_a16, opSETNL_a16, opSETLE_a16, opSETNLE_a16,
/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a16, opSHLD_l_i_a16, opSHLD_l_CL_a16,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a16, opSHRD_l_i_a16, opSHRD_l_CL_a16,ILLEGAL, opIMUL_l_l_a16,
/*b0*/ opCMPXCHG_b_a16,opCMPXCHG_l_a16,opLSS_l_a16, opBTR_l_r_a16, opLFS_l_a16, opLGS_l_a16, opMOVZX_l_b_a16,opMOVZX_l_w_a16,ILLEGAL, ILLEGAL, opBA_l_a16, opBTC_l_r_a16, opBSF_l_a16, opBSR_l_a16, opMOVSX_l_b_a16,opMOVSX_l_w_a16,
/*c0*/ opXADD_b_a16, opXADD_l_a16, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*16-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_w_a32, opLAR_w_a32, opLSL_w_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a32, opRSDC_a32, opSVLDT_a32, opRSLDT_a32, opSVTS_a32, opRSTS_a32, ILLEGAL, ILLEGAL,
/*80*/ opJO_w, opJNO_w, opJB_w, opJNB_w, opJE_w, opJNE_w, opJBE_w, opJNBE_w, opJS_w, opJNS_w, opJP_w, opJNP_w, opJL_w, opJNL_w, opJLE_w, opJNLE_w,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,
/*a0*/ opPUSH_FS_w, opPOP_FS_w, opCPUID, opBT_w_r_a32, opSHLD_w_i_a32, opSHLD_w_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_w, opPOP_GS_w, opRSM, opBTS_w_r_a32, opSHRD_w_i_a32, opSHRD_w_CL_a32,ILLEGAL, opIMUL_w_w_a32,
/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_w_a32,opLSS_w_a32, opBTR_w_r_a32, opLFS_w_a32, opLGS_w_a32, opMOVZX_w_b_a32,opMOVZX_w_w_a32,ILLEGAL, ILLEGAL, opBA_w_a32, opBTC_w_r_a32, opBSF_w_a32, opBSR_w_a32, opMOVSX_w_b_a32,ILLEGAL,
/*c0*/ opXADD_b_a32, opXADD_w_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*32-bit data, 32-bit addr*/
/* 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f*/
/*00*/ op0F00_a32, op0F01_l_a32, opLAR_l_a32, opLSL_l_a32, ILLEGAL, ILLEGAL, opCLTS, opLOADALL386, opINVD, opWBINVD, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*10*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*20*/ opMOV_r_CRx_a32,opMOV_r_DRx_a32,opMOV_CRx_r_a32,opMOV_DRx_r_a32,opMOV_r_TRx_a32,ILLEGAL, opMOV_TRx_r_a32,ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*30*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opRDSHR_a32, opWRSHR_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*40*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*50*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*60*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*70*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opSVDC_a16, opRSDC_a16, opSVLDT_a16, opRSLDT_a16, opSVTS_a16, opRSTS_a16, ILLEGAL, ILLEGAL,
/*80*/ opJO_l, opJNO_l, opJB_l, opJNB_l, opJE_l, opJNE_l, opJBE_l, opJNBE_l, opJS_l, opJNS_l, opJP_l, opJNP_l, opJL_l, opJNL_l, opJLE_l, opJNLE_l,
/*90*/ opSETO_a32, opSETNO_a32, opSETB_a32, opSETNB_a32, opSETE_a32, opSETNE_a32, opSETBE_a32, opSETNBE_a32, opSETS_a32, opSETNS_a32, opSETP_a32, opSETNP_a32, opSETL_a32, opSETNL_a32, opSETLE_a32, opSETNLE_a32,
/*a0*/ opPUSH_FS_l, opPOP_FS_l, opCPUID, opBT_l_r_a32, opSHLD_l_i_a32, opSHLD_l_CL_a32,ILLEGAL, ILLEGAL, opPUSH_GS_l, opPOP_GS_l, opRSM, opBTS_l_r_a32, opSHRD_l_i_a32, opSHRD_l_CL_a32,ILLEGAL, opIMUL_l_l_a32,
/*b0*/ opCMPXCHG_b_a32,opCMPXCHG_l_a32,opLSS_l_a32, opBTR_l_r_a32, opLFS_l_a32, opLGS_l_a32, opMOVZX_l_b_a32,opMOVZX_l_w_a32,ILLEGAL, ILLEGAL, opBA_l_a32, opBTC_l_r_a32, opBSF_l_a32, opBSR_l_a32, opMOVSX_l_b_a32,opMOVSX_l_w_a32,
/*c0*/ opXADD_b_a32, opXADD_l_a32, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, opBSWAP_EAX, opBSWAP_ECX, opBSWAP_EDX, opBSWAP_EBX, opBSWAP_ESP, opBSWAP_EBP, opBSWAP_ESI, opBSWAP_EDI,
/*d0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*e0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
/*f0*/ ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL, ILLEGAL,
};
const OpFn OP_TABLE(ibm486_0f)[1024] =
{
/*16-bit data, 16-bit addr*/

352
src/cpu/808x.c
View File

@@ -35,43 +35,9 @@
#include <86box/ppi.h>
#include <86box/timer.h>
/* The opcode of the instruction currently being executed. */
uint8_t opcode;
/* The tables to speed up the setting of the Z, N, and P cpu_state.flags. */
uint8_t znptable8[256];
uint16_t znptable16[65536];
/* A 16-bit zero, needed because some speed-up arrays contain pointers to it. */
uint16_t zero = 0;
/* MOD and R/M stuff. */
uint16_t *mod1add[2][8];
uint32_t *mod1seg[8];
uint32_t rmdat;
/* XT CPU multiplier. */
uint64_t xt_cpu_multi;
/* Is the CPU 8088 or 8086. */
int is8086 = 0;
/* Variables for handling the non-maskable interrupts. */
int nmi = 0, nmi_auto_clear = 0;
/* Was the CPU ever reset? */
int x86_was_reset = 0;
/* Amount of instructions executed - used to calculate the % shown in the title bar. */
int ins = 0;
/* Is the TRAP flag on? */
int trap = 0;
/* The current effective address's segment. */
uint32_t easeg;
/* The prefetch queue (4 bytes for 8088, 6 bytes for 8086). */
static uint8_t pfq[6];
@@ -148,50 +114,6 @@ x808x_log(const char *fmt, ...)
va_end(ap);
}
}
void
dumpregs(int force)
{
int c;
char *seg_names[4] = { "ES", "CS", "SS", "DS" };
/* Only dump when needed, and only once.. */
if (indump || (!force && !dump_on_exit))
return;
x808x_log("EIP=%08X CS=%04X DS=%04X ES=%04X SS=%04X FLAGS=%04X\n",
cpu_state.pc, CS, DS, ES, SS, cpu_state.flags);
x808x_log("Old CS:EIP: %04X:%08X; %i ins\n", oldcs, cpu_state.oldpc, ins);
for (c = 0; c < 4; c++) {
x808x_log("%s : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
seg_names[c], _opseg[c]->base, _opseg[c]->limit,
_opseg[c]->access, _opseg[c]->limit_low, _opseg[c]->limit_high);
}
if (is386) {
x808x_log("FS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
seg_fs, cpu_state.seg_fs.limit, cpu_state.seg_fs.access, cpu_state.seg_fs.limit_low, cpu_state.seg_fs.limit_high);
x808x_log("GS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
gs, cpu_state.seg_gs.limit, cpu_state.seg_gs.access, cpu_state.seg_gs.limit_low, cpu_state.seg_gs.limit_high);
x808x_log("GDT : base=%06X limit=%04X\n", gdt.base, gdt.limit);
x808x_log("LDT : base=%06X limit=%04X\n", ldt.base, ldt.limit);
x808x_log("IDT : base=%06X limit=%04X\n", idt.base, idt.limit);
x808x_log("TR : base=%06X limit=%04X\n", tr.base, tr.limit);
x808x_log("386 in %s mode: %i-bit data, %-i-bit stack\n",
(msw & 1) ? ((cpu_state.eflags & VM_FLAG) ? "V86" : "protected") : "real",
(use32) ? 32 : 16, (stack32) ? 32 : 16);
x808x_log("CR0=%08X CR2=%08X CR3=%08X CR4=%08x\n", cr0, cr2, cr3, cr4);
x808x_log("EAX=%08X EBX=%08X ECX=%08X EDX=%08X\nEDI=%08X ESI=%08X EBP=%08X ESP=%08X\n",
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP);
} else {
x808x_log("808x/286 in %s mode\n", (msw & 1) ? "protected" : "real");
x808x_log("AX=%04X BX=%04X CX=%04X DX=%04X DI=%04X SI=%04X BP=%04X SP=%04X\n",
AX, BX, CX, DX, DI, SI, BP, SP);
}
x808x_log("Entries in readlookup : %i writelookup : %i\n", readlnum, writelnum);
x87_dumpregs();
indump = 0;
}
#else
#define x808x_log(fmt, ...)
#endif
@@ -602,6 +524,63 @@ pfq_clear()
}
static void
load_cs(uint16_t seg)
{
cpu_state.seg_cs.base = seg << 4;
cpu_state.seg_cs.seg = seg & 0xffff;
}
static void
load_seg(uint16_t seg, x86seg *s)
{
s->base = seg << 4;
s->seg = seg & 0xffff;
}
void
reset_808x(int hard)
{
biu_cycles = 0;
in_rep = 0;
in_lock = 0;
completed = 1;
repeating = 0;
clear_lock = 0;
refresh = 0;
ovr_seg = NULL;
if (hard) {
opseg[0] = &es;
opseg[1] = &cs;
opseg[2] = &ss;
opseg[3] = &ds;
_opseg[0] = &cpu_state.seg_es;
_opseg[1] = &cpu_state.seg_cs;
_opseg[2] = &cpu_state.seg_ss;
_opseg[3] = &cpu_state.seg_ds;
pfq_size = (is8086) ? 6 : 4;
pfq_clear();
}
if (AT) {
load_cs(0xF000);
cpu_state.pc = 0xFFF0;
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
} else {
load_cs(0xFFFF);
cpu_state.pc = 0;
rammask = 0xfffff;
}
prefetching = 1;
cpu_alu_op = 0;
}
static void
set_ip(uint16_t new_ip) {
pfq_ip = cpu_state.pc = new_ip;
@@ -616,45 +595,6 @@ refreshread(void) {
}
/* Preparation of the various arrays needed to speed up the MOD and R/M work. */
static void
makemod1table(void)
{
mod1add[0][0] = &BX;
mod1add[0][1] = &BX;
mod1add[0][2] = &BP;
mod1add[0][3] = &BP;
mod1add[0][4] = &SI;
mod1add[0][5] = &DI;
mod1add[0][6] = &BP;
mod1add[0][7] = &BX;
mod1add[1][0] = &SI;
mod1add[1][1] = &DI;
mod1add[1][2] = &SI;
mod1add[1][3] = &DI;
mod1add[1][4] = &zero;
mod1add[1][5] = &zero;
mod1add[1][6] = &zero;
mod1add[1][7] = &zero;
mod1seg[0] = &ds;
mod1seg[1] = &ds;
mod1seg[2] = &ss;
mod1seg[3] = &ss;
mod1seg[4] = &ds;
mod1seg[5] = &ds;
mod1seg[6] = &ss;
mod1seg[7] = &ds;
opseg[0] = &es;
opseg[1] = &cs;
opseg[2] = &ss;
opseg[3] = &ds;
_opseg[0] = &cpu_state.seg_es;
_opseg[1] = &cpu_state.seg_cs;
_opseg[2] = &cpu_state.seg_ss;
_opseg[3] = &cpu_state.seg_ds;
}
static uint16_t
get_accum(int bits)
{
@@ -865,176 +805,6 @@ seteaq(uint64_t val)
#undef FPU_8087
/* Prepare the ZNP table needed to speed up the setting of the Z, N, and P cpu_state.flags. */
static void
makeznptable(void)
{
int c, d, e;
for (c = 0; c < 256; c++) {
d = 0;
for (e = 0; e < 8; e++) {
if (c & (1 << e))
d++;
}
if (d & 1)
znptable8[c] = 0;
else
znptable8[c] = P_FLAG;
#ifdef ENABLE_808X_LOG
if (c == 0xb1)
x808x_log("znp8 b1 = %i %02X\n", d, znptable8[c]);
#endif
if (!c)
znptable8[c] |= Z_FLAG;
if (c & 0x80)
znptable8[c] |= N_FLAG;
}
for (c = 0; c < 65536; c++) {
d = 0;
for (e = 0; e < 8; e++) {
if (c & (1 << e))
d++;
}
if (d & 1)
znptable16[c] = 0;
else
znptable16[c] = P_FLAG;
#ifdef ENABLE_808X_LOG
if (c == 0xb1)
x808x_log("znp16 b1 = %i %02X\n", d, znptable16[c]);
if (c == 0x65b1)
x808x_log("znp16 65b1 = %i %02X\n", d, znptable16[c]);
#endif
if (!c)
znptable16[c] |= Z_FLAG;
if (c & 0x8000)
znptable16[c] |= N_FLAG;
}
}
static void load_cs(uint16_t seg)
{
cpu_state.seg_cs.base = seg << 4;
CS = seg & 0xffff;
}
/* Common reset function. */
static void
reset_common(int hard)
{
/* Make sure to gracefully leave SMM. */
if (in_smm)
leave_smm();
biu_cycles = 0;
in_rep = 0;
in_lock = 0;
completed = 1;
repeating = 0;
clear_lock = 0;
refresh = 0;
if (hard) {
#ifdef ENABLE_808X_LOG
x808x_log("x86 reset\n");
#endif
ins = 0;
}
use32 = 0;
cpu_cur_status = 0;
stack32 = 0;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
msw = 0;
if (hascache)
cr0 = 1 << 30;
else
cr0 = 0;
cpu_cache_int_enabled = 0;
cpu_update_waitstates();
cr4 = 0;
cpu_state.eflags = 0;
cgate32 = 0;
if (AT) {
load_cs(0xF000);
cpu_state.pc = 0xFFF0;
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
} else {
load_cs(0xFFFF);
cpu_state.pc = 0;
rammask = 0xfffff;
}
idt.base = 0;
idt.limit = is386 ? 0x03FF : 0xFFFF;
cpu_state.flags = 2;
trap = 0;
ovr_seg = NULL;
EAX = EBX = ECX = EDX = ESI = EDI = EBP = ESP = 0;
if (hard) {
makeznptable();
resetreadlookup();
makemod1table();
pfq_clear();
cpu_set_edx();
mmu_perm = 4;
pfq_size = (is8086) ? 6 : 4;
}
x86seg_reset();
#ifdef USE_DYNAREC
if (hard)
codegen_reset();
#endif
if (!hard)
flushmmucache();
x86_was_reset = 1;
cpu_alt_reset = 0;
prefetching = 1;
cpu_ven_reset();
cpu_alu_op = 0;
in_smm = smi_latched = 0;
smi_line = smm_in_hlt = 0;
smi_block = 0;
if (hard) {
smbase = is_am486 ? 0x00060000 : 0x00030000;
ppi_reset();
}
in_sys = 0;
shadowbios = shadowbios_write = 0;
alt_access = cpu_end_block_after_ins = 0;
}
/* Hard reset. */
void
resetx86(void)
{
reset_common(1);
soft_reset_mask = 0;
}
/* Soft reset. */
void
softresetx86(void)
{
if (soft_reset_mask)
return;
reset_common(0);
}
/* Pushes a word to the stack. */
static void
push(uint16_t *val)
@@ -1867,7 +1637,7 @@ execx86(int cycs)
load_cs(pop());
pfq_pos = 0;
} else
loadseg(pop(), _opseg[(opcode >> 3) & 0x03]);
load_seg(pop(), _opseg[(opcode >> 3) & 0x03]);
wait(1, 0);
/* All POP segment instructions suppress interrupts for one instruction. */
noint = 1;
@@ -2201,7 +1971,7 @@ execx86(int cycs)
load_cs(tempw);
pfq_pos = 0;
} else
loadseg(tempw, _opseg[(rmdat & 0x18) >> 3]);
load_seg(tempw, _opseg[(rmdat & 0x18) >> 3]);
wait(1, 0);
if (cpu_mod != 3)
wait(2, 0);
@@ -2482,7 +2252,7 @@ execx86(int cycs)
cpu_state.regs[cpu_reg].w = cpu_data;
access(57, bits);
read_ea2(bits);
loadseg(cpu_data, (opcode & 0x01) ? &cpu_state.seg_ds : &cpu_state.seg_es);
load_seg(cpu_data, (opcode & 0x01) ? &cpu_state.seg_ds : &cpu_state.seg_es);
wait(1, 0);
break;
@@ -2985,7 +2755,5 @@ execx86(int cycs)
cpu_alu_op = 0;
}
ins++;
}
}

2
src/cpu/CMakeLists.txt
View File

@@ -13,7 +13,7 @@
# Copyright 2020,2021 David Hrdlička.
#
add_library(cpu OBJECT cpu.c cpu_table.c 808x.c 386.c 386_common.c 386_dynarec.c
add_library(cpu OBJECT cpu.c cpu_table.c fpu.c x86.c 808x.c 386.c 386_common.c 386_dynarec.c
386_dynarec_ops.c x86seg.c x87.c x87_timings.c)
if(AMD_K5)

6225
src/cpu/cpu.c
View File

File diff suppressed because it is too large Load Diff

115
src/cpu/cpu.h
View File

@@ -40,9 +40,9 @@ enum {
#endif
CPU_286, /* 286 class CPUs */
CPU_386SX, /* 386 class CPUs */
CPU_386DX,
CPU_IBM386SLC,
CPU_IBM486SLC,
CPU_386DX,
CPU_IBM486BL,
CPU_RAPIDCAD,
CPU_486SLC,
@@ -53,10 +53,10 @@ enum {
CPU_i486SX2,
CPU_Am486SX2,
CPU_i486DX,
CPU_i486DX2,
CPU_Am486DX,
CPU_Am486DX2,
CPU_Cx486DX,
CPU_i486DX2,
CPU_Am486DX2,
CPU_Cx486DX2,
CPU_iDX4,
CPU_Am486DX4,
@@ -218,8 +218,7 @@ typedef struct {
uint8_t access, ar_high;
int8_t checked; /*Non-zero if selector is known to be valid*/
uint16_t seg;
uint32_t base,
limit, limit_raw,
uint32_t base, limit,
limit_low, limit_high;
} x86seg;
@@ -236,10 +235,99 @@ typedef union {
} MMX_REG;
typedef struct {
uint32_t tr1, tr12;
uint32_t cesr;
uint32_t fcr;
uint64_t fcr2, fcr3;
/* IDT WinChip and WinChip 2 MSR's */
uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
uint32_t cesr; /* 0x00000011 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx17; /* 0x00000017 - Only on Pentium II Deschutes */
uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
uint64_t ecx79; /* 0x00000079 */
/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t ecx83; /* 0x00000083 - AMD K5 and K6 MSR's. */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx8x[4]; /* 0x00000088 - 0x0000008b */
uint64_t ia32_pmc[8]; /* 0x000000c1 - 0x000000c8 */
uint64_t mtrr_cap; /* 0x000000fe */
/* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III and Eden */
uint32_t fcr; /* 0x00000107 (IDT), 0x00001107 (VIA) */
uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx116; /* 0x00000116 */
uint64_t ecx11x[4]; /* 0x00000118 - 0x0000011b */
uint64_t ecx11e; /* 0x0000011e */
/* Pentium II Klamath and Pentium II Deschutes MSR's */
uint16_t sysenter_cs; /* 0x00000174 - SYSENTER/SYSEXIT MSR's */
uint32_t sysenter_esp; /* 0x00000175 - SYSENTER/SYSEXIT MSR's */
uint32_t sysenter_eip; /* 0x00000176 - SYSENTER/SYSEXIT MSR's */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
uint64_t ecx1e0; /* 0x000001e0 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
on the VIA Cyrix III and Eden */
uint64_t mtrr_physbase[8]; /* 0x00000200 - 0x0000020f */
uint64_t mtrr_physmask[8]; /* 0x00000200 - 0x0000020f (ECX & 1) */
uint64_t mtrr_fix64k_8000; /* 0x00000250 */
uint64_t mtrr_fix16k_8000; /* 0x00000258 */
uint64_t mtrr_fix16k_a000; /* 0x00000259 */
uint64_t mtrr_fix4k[8]; /* 0x00000268 - 0x0000026f */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t pat; /* 0x00000277 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
on the VIA Cyrix III and Eden */
uint64_t mtrr_deftype; /* 0x000002ff */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx404; /* 0x00000404 - Model Identification MSR's used by some Acer BIOSes */
uint64_t ecx408; /* 0x00000408 */
uint64_t ecx40c; /* 0x0000040c */
uint64_t ecx410; /* 0x00000410 */
uint64_t ecx570; /* 0x00000570 */
/* IBM 386SLC, 486SLC, and 486BL MSR's */
uint64_t ibm_por; /* 0x00001000 - Processor Operation Register */
uint64_t ibm_crcr; /* 0x00001001 - Cache Region Control Register */
/* IBM 486SLC and 486BL MSR's */
uint64_t ibm_por2; /* 0x00001002 - Processor Operation Register */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecx1002ff; /* 0x001002ff - MSR used by some Intel AMI boards */
/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_efer; /* 0xc0000080 */
/* AMD K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t star; /* 0xc0000081 */
/* AMD K5, 5k86, K6, K6-2, K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_whcr; /* 0xc0000082 */
/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_uwccr; /* 0xc0000085 */
/* AMD K6-2P and K6-3P MSR's */
uint64_t amd_epmr; /* 0xc0000086 */
/* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
/* K6-3, K6-2P, and K6-3P MSR's */
uint64_t amd_l2aar; /* 0xc0000089 */
/* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
uint64_t ecxf0f00250; /* 0xf0f00250 - Some weird long MSR's used by i686 AMI & some Phoenix BIOSes */
uint64_t ecxf0f00258; /* 0xf0f00258 */
uint64_t ecxf0f00259; /* 0xf0f00259 */
} msr_t;
typedef struct {
@@ -395,7 +483,7 @@ extern int cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
penalties when crossing 8-byte boundaries*/
extern int is8086, is286, is386, is486, is486sx, is486dx, is486sx2, is486dx2, isdx4;
extern int is_am486, is_pentium, is_k5, is_k6, is_p6, is_cx6x86;
extern int is_am486, is_486_org, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
extern int hascache;
extern int isibm486;
extern int is_rapidcad;
@@ -532,7 +620,7 @@ extern void cpu_CPUID(void);
extern void cpu_RDMSR(void);
extern void cpu_WRMSR(void);
extern int checkio(int port);
extern int checkio(uint32_t port);
extern void codegen_block_end(void);
extern void codegen_reset(void);
extern void cpu_set_edx(void);
@@ -612,9 +700,14 @@ typedef struct
} cyrix_t;
extern uint32_t addr64, addr64_2;
extern uint32_t addr64a[8], addr64a_2[8];
extern cyrix_t cyrix;
extern void (*cpu_exec)(int cycs);
extern uint8_t do_translate, do_translate2;
extern void reset_808x(int hard);
#endif /*EMU_CPU_H*/

101
src/cpu/fpu.c Normal file
View File

@@ -0,0 +1,101 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* FPU type handler.
*
* Authors: Sarah Walker, <tommowalker@tommowalker.co.uk>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2008-2018 Sarah Walker.
* Copyright 2016-2018 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#ifdef ENABLE_FPU_LOG
int fpu_do_log = ENABLE_FPU_LOG;
void
fpu_log(const char *fmt, ...)
{
va_list ap;
if (fpu_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define fpu_log(fmt, ...)
#endif
int
fpu_get_type(const cpu_family_t *cpu_family, int cpu, const char *internal_name)
{
const CPU *cpu_s = &cpu_family->cpus[cpu];
const FPU *fpus = cpu_s->fpus;
int fpu_type = fpus[0].type;
int c = 0;
while (fpus[c].internal_name) {
if (!strcmp(internal_name, fpus[c].internal_name))
fpu_type = fpus[c].type;
c++;
}
return fpu_type;
}
const char *
fpu_get_internal_name(const cpu_family_t *cpu_family, int cpu, int type)
{
const CPU *cpu_s = &cpu_family->cpus[cpu];
const FPU *fpus = cpu_s->fpus;
int c = 0;
while (fpus[c].internal_name) {
if (fpus[c].type == type)
return fpus[c].internal_name;
c++;
}
return fpus[0].internal_name;
}
const char *
fpu_get_name_from_index(const cpu_family_t *cpu_family, int cpu, int c)
{
const CPU *cpu_s = &cpu_family->cpus[cpu];
const FPU *fpus = cpu_s->fpus;
return fpus[c].name;
}
int
fpu_get_type_from_index(const cpu_family_t *cpu_family, int cpu, int c)
{
const CPU *cpu_s = &cpu_family->cpus[cpu];
const FPU *fpus = cpu_s->fpus;
return fpus[c].type;
}

315
src/cpu/x86.c Normal file
View File

@@ -0,0 +1,315 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Functions common to all emulated x86 CPU's.
*
* Authors: Andrew Jenner, <https://www.reenigne.org>
* Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2015-2020 Andrew Jenner.
* Copyright 2016-2020 Miran Grca.
*/
#include <math.h>
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include "x86.h"
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/nmi.h>
#include <86box/pic.h>
#include <86box/ppi.h>
#include <86box/timer.h>
/* The opcode of the instruction currently being executed. */
uint8_t opcode;
/* The tables to speed up the setting of the Z, N, and P cpu_state.flags. */
uint8_t znptable8[256];
uint16_t znptable16[65536];
/* A 16-bit zero, needed because some speed-up arrays contain pointers to it. */
uint16_t zero = 0;
/* MOD and R/M stuff. */
uint16_t *mod1add[2][8];
uint32_t *mod1seg[8];
uint32_t rmdat;
/* XT CPU multiplier. */
uint64_t xt_cpu_multi;
/* Variables for handling the non-maskable interrupts. */
int nmi = 0, nmi_auto_clear = 0;
/* Was the CPU ever reset? */
int x86_was_reset = 0;
/* Is the TRAP flag on? */
int trap = 0;
/* The current effective address's segment. */
uint32_t easeg;
#ifdef ENABLE_X86_LOG
void dumpregs(int);
int x86_do_log = ENABLE_X86_LOG;
int indump = 0;
static void
x808x_log(const char *fmt, ...)
{
va_list ap;
if (x808x_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
void
dumpregs(int force)
{
int c;
char *seg_names[4] = { "ES", "CS", "SS", "DS" };
/* Only dump when needed, and only once.. */
if (indump || (!force && !dump_on_exit))
return;
x808x_log("EIP=%08X CS=%04X DS=%04X ES=%04X SS=%04X FLAGS=%04X\n",
cpu_state.pc, CS, DS, ES, SS, cpu_state.flags);
x808x_log("Old CS:EIP: %04X:%08X; %i ins\n", oldcs, cpu_state.oldpc, ins);
for (c = 0; c < 4; c++) {
x808x_log("%s : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
seg_names[c], _opseg[c]->base, _opseg[c]->limit,
_opseg[c]->access, _opseg[c]->limit_low, _opseg[c]->limit_high);
}
if (is386) {
x808x_log("FS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
seg_fs, cpu_state.seg_fs.limit, cpu_state.seg_fs.access, cpu_state.seg_fs.limit_low, cpu_state.seg_fs.limit_high);
x808x_log("GS : base=%06X limit=%08X access=%02X limit_low=%08X limit_high=%08X\n",
gs, cpu_state.seg_gs.limit, cpu_state.seg_gs.access, cpu_state.seg_gs.limit_low, cpu_state.seg_gs.limit_high);
x808x_log("GDT : base=%06X limit=%04X\n", gdt.base, gdt.limit);
x808x_log("LDT : base=%06X limit=%04X\n", ldt.base, ldt.limit);
x808x_log("IDT : base=%06X limit=%04X\n", idt.base, idt.limit);
x808x_log("TR : base=%06X limit=%04X\n", tr.base, tr.limit);
x808x_log("386 in %s mode: %i-bit data, %-i-bit stack\n",
(msw & 1) ? ((cpu_state.eflags & VM_FLAG) ? "V86" : "protected") : "real",
(use32) ? 32 : 16, (stack32) ? 32 : 16);
x808x_log("CR0=%08X CR2=%08X CR3=%08X CR4=%08x\n", cr0, cr2, cr3, cr4);
x808x_log("EAX=%08X EBX=%08X ECX=%08X EDX=%08X\nEDI=%08X ESI=%08X EBP=%08X ESP=%08X\n",
EAX, EBX, ECX, EDX, EDI, ESI, EBP, ESP);
} else {
x808x_log("808x/286 in %s mode\n", (msw & 1) ? "protected" : "real");
x808x_log("AX=%04X BX=%04X CX=%04X DX=%04X DI=%04X SI=%04X BP=%04X SP=%04X\n",
AX, BX, CX, DX, DI, SI, BP, SP);
}
x808x_log("Entries in readlookup : %i writelookup : %i\n", readlnum, writelnum);
x87_dumpregs();
indump = 0;
}
#else
#define x808x_log(fmt, ...)
#endif
/* Preparation of the various arrays needed to speed up the MOD and R/M work. */
static void
makemod1table(void)
{
mod1add[0][0] = &BX;
mod1add[0][1] = &BX;
mod1add[0][2] = &BP;
mod1add[0][3] = &BP;
mod1add[0][4] = &SI;
mod1add[0][5] = &DI;
mod1add[0][6] = &BP;
mod1add[0][7] = &BX;
mod1add[1][0] = &SI;
mod1add[1][1] = &DI;
mod1add[1][2] = &SI;
mod1add[1][3] = &DI;
mod1add[1][4] = &zero;
mod1add[1][5] = &zero;
mod1add[1][6] = &zero;
mod1add[1][7] = &zero;
mod1seg[0] = &ds;
mod1seg[1] = &ds;
mod1seg[2] = &ss;
mod1seg[3] = &ss;
mod1seg[4] = &ds;
mod1seg[5] = &ds;
mod1seg[6] = &ss;
mod1seg[7] = &ds;
}
/* Prepare the ZNP table needed to speed up the setting of the Z, N, and P cpu_state.flags. */
static void
makeznptable(void)
{
int c, d, e;
for (c = 0; c < 256; c++) {
d = 0;
for (e = 0; e < 8; e++) {
if (c & (1 << e))
d++;
}
if (d & 1)
znptable8[c] = 0;
else
znptable8[c] = P_FLAG;
#ifdef ENABLE_808X_LOG
if (c == 0xb1)
x808x_log("znp8 b1 = %i %02X\n", d, znptable8[c]);
#endif
if (!c)
znptable8[c] |= Z_FLAG;
if (c & 0x80)
znptable8[c] |= N_FLAG;
}
for (c = 0; c < 65536; c++) {
d = 0;
for (e = 0; e < 8; e++) {
if (c & (1 << e))
d++;
}
if (d & 1)
znptable16[c] = 0;
else
znptable16[c] = P_FLAG;
#ifdef ENABLE_808X_LOG
if (c == 0xb1)
x808x_log("znp16 b1 = %i %02X\n", d, znptable16[c]);
if (c == 0x65b1)
x808x_log("znp16 65b1 = %i %02X\n", d, znptable16[c]);
#endif
if (!c)
znptable16[c] |= Z_FLAG;
if (c & 0x8000)
znptable16[c] |= N_FLAG;
}
}
/* Common reset function. */
static void
reset_common(int hard)
{
/* Make sure to gracefully leave SMM. */
if (in_smm)
leave_smm();
#ifdef ENABLE_808X_LOG
if (hard)
x808x_log("x86 reset\n");
#endif
use32 = 0;
cpu_cur_status = 0;
stack32 = 0;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
msw = 0;
if (hascache)
cr0 = 1 << 30;
else
cr0 = 0;
cpu_cache_int_enabled = 0;
cpu_update_waitstates();
cr4 = 0;
cpu_state.eflags = 0;
cgate32 = 0;
if (is286) {
if (AT) {
loadcs(0xF000);
cpu_state.pc = 0xFFF0;
rammask = cpu_16bitbus ? 0xFFFFFF : 0xFFFFFFFF;
} else {
loadcs(0xFFFF);
cpu_state.pc = 0;
rammask = 0xfffff;
}
}
idt.base = 0;
idt.limit = is386 ? 0x03FF : 0xFFFF;
cpu_state.flags = 2;
trap = 0;
EAX = EBX = ECX = EDX = ESI = EDI = EBP = ESP = 0;
if (hard) {
makeznptable();
resetreadlookup();
makemod1table();
cpu_set_edx();
mmu_perm = 4;
}
x86seg_reset();
#ifdef USE_DYNAREC
if (hard)
codegen_reset();
#endif
if (!hard)
flushmmucache();
x86_was_reset = 1;
cpu_alt_reset = 0;
cpu_ven_reset();
in_smm = smi_latched = 0;
smi_line = smm_in_hlt = 0;
smi_block = 0;
if (hard) {
smbase = is_486_org ? 0x00060000 : 0x00030000;
ppi_reset();
}
in_sys = 0;
shadowbios = shadowbios_write = 0;
alt_access = cpu_end_block_after_ins = 0;
if (!is286)
reset_808x(hard);
}
/* Hard reset. */
void
resetx86(void)
{
reset_common(1);
soft_reset_mask = 0;
}
/* Soft reset. */
void
softresetx86(void)
{
if (soft_reset_mask)
return;
reset_common(0);
}

2
src/cpu/x86_ops.h
View File

@@ -79,6 +79,7 @@ extern const OpFn dynarec_ops_386[1024];
extern const OpFn dynarec_ops_386_0f[1024];
extern const OpFn dynarec_ops_486_0f[1024];
extern const OpFn dynarec_ops_c486_0f[1024];
extern const OpFn dynarec_ops_ibm486_0f[1024];
extern const OpFn dynarec_ops_winchip_0f[1024];
@@ -176,6 +177,7 @@ extern const OpFn ops_386[1024];
extern const OpFn ops_386_0f[1024];
extern const OpFn ops_486_0f[1024];
extern const OpFn ops_c486_0f[1024];
extern const OpFn ops_ibm486_0f[1024];
extern const OpFn ops_winchip_0f[1024];

4
src/cpu/x86_ops_amd.h
View File

@@ -18,7 +18,7 @@ opSYSCALL(uint32_t fetchdat)
{
int ret;
ILLEGAL_ON(!(amd_efer & 0x0000000000000001));
ILLEGAL_ON(!(msr.amd_efer & 0x0000000000000001));
ret = syscall_op(fetchdat);
@@ -38,7 +38,7 @@ opSYSRET(uint32_t fetchdat)
{
int ret;
ILLEGAL_ON(!(amd_efer & 0x0000000000000001));
ILLEGAL_ON(!(msr.amd_efer & 0x0000000000000001));
ret = sysret(fetchdat);

102
src/cpu/x86_ops_arith.h
View File

@@ -309,8 +309,8 @@ static int opCMP_b_rmw_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteab(); if (cpu_state.abrt) return 1;
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
@@ -322,8 +322,8 @@ static int opCMP_b_rmw_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteab(); if (cpu_state.abrt) return 1;
setsub8(dst, getr8(cpu_reg));
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -336,8 +336,8 @@ static int opCMP_w_rmw_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteaw(); if (cpu_state.abrt) return 1;
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
@@ -349,8 +349,8 @@ static int opCMP_w_rmw_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteaw(); if (cpu_state.abrt) return 1;
setsub16(dst, cpu_state.regs[cpu_reg].w);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -363,8 +363,8 @@ static int opCMP_l_rmw_a16(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteal(); if (cpu_state.abrt) return 1;
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
@@ -376,8 +376,8 @@ static int opCMP_l_rmw_a32(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg);
dst = geteal(); if (cpu_state.abrt) return 1;
setsub32(dst, cpu_state.regs[cpu_reg].l);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0, (cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@@ -493,8 +493,8 @@ static int opTEST_b_a16(uint32_t fetchdat)
temp = geteab(); if (cpu_state.abrt) return 1;
temp2 = getr8(cpu_reg);
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
@@ -507,8 +507,8 @@ static int opTEST_b_a32(uint32_t fetchdat)
temp = geteab(); if (cpu_state.abrt) return 1;
temp2 = getr8(cpu_reg);
setznp8(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -522,8 +522,8 @@ static int opTEST_w_a16(uint32_t fetchdat)
temp = geteaw(); if (cpu_state.abrt) return 1;
temp2 = cpu_state.regs[cpu_reg].w;
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 0);
return 0;
}
@@ -536,8 +536,8 @@ static int opTEST_w_a32(uint32_t fetchdat)
temp = geteaw(); if (cpu_state.abrt) return 1;
temp2 = cpu_state.regs[cpu_reg].w;
setznp16(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, (cpu_mod == 3) ? 0 : 1,0,0,0, 1);
return 0;
}
@@ -551,8 +551,8 @@ static int opTEST_l_a16(uint32_t fetchdat)
temp = geteal(); if (cpu_state.abrt) return 1;
temp2 = cpu_state.regs[cpu_reg].l;
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 0);
return 0;
}
@@ -565,8 +565,8 @@ static int opTEST_l_a32(uint32_t fetchdat)
temp = geteal(); if (cpu_state.abrt) return 1;
temp2 = cpu_state.regs[cpu_reg].l;
setznp32(temp & temp2);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 2, rmdat, 0,(cpu_mod == 3) ? 0 : 1,0,0, 1);
return 0;
}
@@ -643,8 +643,8 @@ static int opTEST_EAX(uint32_t fetchdat)
break; \
case 0x38: /*CMP ea, #*/ \
setsub ## flag_width(dst, src); \
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); \
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); \
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); } \
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 7); } \
break; \
}
@@ -658,10 +658,11 @@ static int op80_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
}
return 0;
}
@@ -674,10 +675,11 @@ static int op80_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getbyte(); if (cpu_state.abrt) return 1;
ARITH_MULTI(b, 8);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
}
return 0;
}
@@ -690,10 +692,11 @@ static int op81_w_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
}
return 0;
}
@@ -706,10 +709,11 @@ static int op81_w_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getword(); if (cpu_state.abrt) return 1;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 4, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
}
return 0;
}
@@ -722,10 +726,11 @@ static int op81_l_a16(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
}
return 0;
}
@@ -738,10 +743,11 @@ static int op81_l_a32(uint32_t fetchdat)
SEG_CHECK_WRITE(cpu_state.ea_seg);
src = getlong(); if (cpu_state.abrt) return 1;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 6, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
}
return 0;
}
@@ -756,10 +762,11 @@ static int op83_w_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 0);
}
return 0;
}
@@ -773,10 +780,11 @@ static int op83_w_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xff00;
ARITH_MULTI(w, 16);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, (cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1,0, 1);
}
return 0;
}
@@ -791,10 +799,11 @@ static int op83_l_a16(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 0);
}
return 0;
}
@@ -808,10 +817,11 @@ static int op83_l_a32(uint32_t fetchdat)
src = getbyte(); if (cpu_state.abrt) return 1;
if (src & 0x80) src |= 0xffffff00;
ARITH_MULTI(l, 32);
if ((rmdat & 0x38) == 0x38)
if ((rmdat & 0x38) == 0x38) {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_mr, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
else
} else {
PREFETCH_RUN((cpu_mod == 3) ? timing_rr : timing_rm, 3, rmdat, 0,(cpu_mod == 3) ? 0:1,0,(cpu_mod == 3) ? 0:1, 1);
}
return 0;
}

32
src/cpu/x86_ops_call.h
View File

@@ -186,8 +186,8 @@ static int opFF_w_a16(uint32_t fetchdat)
PUSH_W(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 0);
PREFETCH_FLUSH();
break;
@@ -208,8 +208,8 @@ static int opFF_w_a16(uint32_t fetchdat)
new_pc = geteaw(); if (cpu_state.abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
PREFETCH_FLUSH();
break;
@@ -285,8 +285,8 @@ static int opFF_w_a32(uint32_t fetchdat)
PUSH_W(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, (cpu_mod == 3) ? 0:1,0,1,0, 1);
PREFETCH_FLUSH();
break;
@@ -307,8 +307,8 @@ static int opFF_w_a32(uint32_t fetchdat)
new_pc = geteaw(); if (cpu_state.abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,0,0,0, 1);
PREFETCH_FLUSH();
break;
@@ -385,8 +385,8 @@ static int opFF_l_a16(uint32_t fetchdat)
PUSH_L(cpu_state.pc);
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 0);
PREFETCH_FLUSH();
break;
@@ -407,8 +407,8 @@ static int opFF_l_a16(uint32_t fetchdat)
new_pc = geteal(); if (cpu_state.abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 0,1,0,0, 0);
PREFETCH_FLUSH();
break;
@@ -484,8 +484,8 @@ static int opFF_l_a32(uint32_t fetchdat)
PUSH_L(cpu_state.pc); if (cpu_state.abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN((cpu_mod == 3) ? 7 : 10, 2, rmdat, 0,(cpu_mod == 3) ? 0:1,0,1, 1);
PREFETCH_FLUSH();
break;
@@ -506,8 +506,8 @@ static int opFF_l_a32(uint32_t fetchdat)
new_pc = geteal(); if (cpu_state.abrt) return 1;
cpu_state.pc = new_pc;
CPU_BLOCK_END();
if (is486) CLOCK_CYCLES(5);
else CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10);
if (is486) { CLOCK_CYCLES(5); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 7 : 10); }
PREFETCH_RUN(cycles_old-cycles, 2, rmdat, 1,1,0,0, 1);
PREFETCH_FLUSH();
break;

36
src/cpu/x86_ops_cyrix.h
View File

@@ -29,13 +29,12 @@ static void opSVDC_common(uint32_t fetchdat)
writememw(0, easeg+cpu_state.eaaddr+8, GS);
break;
default:
pclog("opSVDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}
static int opSVDC_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -48,7 +47,7 @@ static int opSVDC_a16(uint32_t fetchdat)
}
static int opSVDC_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -80,13 +79,12 @@ static void opRSDC_common(uint32_t fetchdat)
cyrix_load_seg_descriptor(easeg+cpu_state.eaaddr, &cpu_state.seg_gs);
break;
default:
pclog("opRSDC: unknown rmdat %02x\n", rmdat);
x86illegal();
}
}
static int opRSDC_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
@@ -99,7 +97,7 @@ static int opRSDC_a16(uint32_t fetchdat)
}
static int opRSDC_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
@@ -113,7 +111,7 @@ static int opRSDC_a32(uint32_t fetchdat)
static int opSVLDT_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -127,7 +125,7 @@ static int opSVLDT_a16(uint32_t fetchdat)
}
static int opSVLDT_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -142,7 +140,7 @@ static int opSVLDT_a32(uint32_t fetchdat)
static int opRSLDT_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
@@ -155,7 +153,7 @@ static int opRSLDT_a16(uint32_t fetchdat)
}
static int opRSLDT_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_READ(cpu_state.ea_seg);
@@ -169,7 +167,7 @@ static int opRSLDT_a32(uint32_t fetchdat)
static int opSVTS_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -183,7 +181,7 @@ static int opSVTS_a16(uint32_t fetchdat)
}
static int opSVTS_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -198,7 +196,7 @@ static int opSVTS_a32(uint32_t fetchdat)
static int opRSTS_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_16(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -212,7 +210,7 @@ static int opRSTS_a16(uint32_t fetchdat)
}
static int opRSTS_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
{
fetch_ea_32(fetchdat);
SEG_CHECK_WRITE(cpu_state.ea_seg);
@@ -227,7 +225,7 @@ static int opRSTS_a32(uint32_t fetchdat)
static int opSMINT(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
fatal("opSMINT\n");
else
x86illegal();
@@ -237,7 +235,7 @@ static int opSMINT(uint32_t fetchdat)
static int opRDSHR_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
fatal("opRDSHR_a16\n");
else
x86illegal();
@@ -246,7 +244,7 @@ static int opRDSHR_a16(uint32_t fetchdat)
}
static int opRDSHR_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
fatal("opRDSHR_a32\n");
else
x86illegal();
@@ -256,7 +254,7 @@ static int opRDSHR_a32(uint32_t fetchdat)
static int opWRSHR_a16(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
fatal("opWRSHR_a16\n");
else
x86illegal();
@@ -265,7 +263,7 @@ static int opWRSHR_a16(uint32_t fetchdat)
}
static int opWRSHR_a32(uint32_t fetchdat)
{
if (cpu_cur_status & CPU_STATUS_SMM)
if (in_smm)
fatal("opWRSHR_a32\n");
else
x86illegal();

6
src/cpu/x86_ops_i686.h
View File

@@ -153,9 +153,6 @@ fx_save_stor_common(uint32_t fetchdat, int bits)
x87_settag(rec_ftw);
CLOCK_CYCLES((cr0 & 1) ? 34 : 44);
if (cpu_state.abrt)
x386_dynarec_log("FXRSTOR: abrt != 0\n");
} else {
/* FXSAVE */
if ((twd & 0x0003) == 0x0003) ftwb |= 0x01;
@@ -217,9 +214,6 @@ fx_save_stor_common(uint32_t fetchdat, int bits)
cpu_state.ismmx = 0;
CLOCK_CYCLES((cr0 & 1) ? 56 : 67);
if (cpu_state.abrt)
x386_dynarec_log("FXSAVE: abrt != 0\n");
}
return cpu_state.abrt;

27
src/cpu/x86_ops_misc.h
View File

@@ -63,8 +63,8 @@ static int opF6_a16(uint32_t fetchdat)
case 0x08:
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
setznp8(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x10: /*NOT b*/
@@ -167,8 +167,8 @@ static int opF6_a32(uint32_t fetchdat)
case 0x08:
src = readmemb(cs, cpu_state.pc); cpu_state.pc++; if (cpu_state.abrt) return 1;
setznp8(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 3, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x10: /*NOT b*/
@@ -274,8 +274,8 @@ static int opF7_w_a16(uint32_t fetchdat)
case 0x08:
src = getword(); if (cpu_state.abrt) return 1;
setznp16(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 0);
break;
case 0x10: /*NOT w*/
@@ -371,8 +371,8 @@ static int opF7_w_a32(uint32_t fetchdat)
case 0x08:
src = getword(); if (cpu_state.abrt) return 1;
setznp16(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 4, rmdat, (cpu_mod == 3) ? 0:1,0,0,0, 1);
break;
case 0x10: /*NOT w*/
@@ -469,8 +469,8 @@ static int opF7_l_a16(uint32_t fetchdat)
case 0x08:
src = getlong(); if (cpu_state.abrt) return 1;
setznp32(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 0);
break;
case 0x10: /*NOT l*/
@@ -544,8 +544,8 @@ static int opF7_l_a32(uint32_t fetchdat)
case 0x08:
src = getlong(); if (cpu_state.abrt) return 1;
setznp32(src & dst);
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2);
else CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 2); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 2 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 2 : 5, 5, rmdat, 0,(cpu_mod == 3) ? 0:1,0,0, 1);
break;
case 0x10: /*NOT l*/
@@ -620,8 +620,9 @@ static int opHLT(uint32_t fetchdat)
if (!((cpu_state.flags & I_FLAG) && pic.int_pending))
cpu_state.pc--;
}
else
else {
CLOCK_CYCLES(5);
}
CPU_BLOCK_END();
PREFETCH_RUN(100, 1, -1, 0,0,0,0, 0);

8
src/cpu/x86_ops_mov.h
View File

@@ -281,7 +281,7 @@ static int opMOV_AX_a16(uint32_t fetchdat)
uint16_t temp;
uint16_t addr = getwordf();
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, addr, addr+1);
CHECK_READ(cpu_state.ea_seg, addr, addr + 1UL);
temp = readmemw(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
AX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
@@ -305,7 +305,7 @@ static int opMOV_EAX_a16(uint32_t fetchdat)
uint32_t temp;
uint16_t addr = getwordf();
SEG_CHECK_READ(cpu_state.ea_seg);
CHECK_READ(cpu_state.ea_seg, addr, addr+3);
CHECK_READ(cpu_state.ea_seg, addr, addr + 3UL);
temp = readmeml(cpu_state.ea_seg->base, addr); if (cpu_state.abrt) return 1;
EAX = temp;
CLOCK_CYCLES((is486) ? 1 : 4);
@@ -349,7 +349,7 @@ static int opMOV_a16_AX(uint32_t fetchdat)
{
uint16_t addr = getwordf();
SEG_CHECK_WRITE(cpu_state.ea_seg);
CHECK_WRITE_COMMON(cpu_state.ea_seg, addr, addr + 1);
CHECK_WRITE_COMMON(cpu_state.ea_seg, addr, addr + 1UL);
writememw(cpu_state.ea_seg->base, addr, AX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 3, -1, 0,0,1,0, 0);
@@ -369,7 +369,7 @@ static int opMOV_a16_EAX(uint32_t fetchdat)
{
uint16_t addr = getwordf();
SEG_CHECK_WRITE(cpu_state.ea_seg);
CHECK_WRITE_COMMON(cpu_state.ea_seg, addr, addr + 3);
CHECK_WRITE_COMMON(cpu_state.ea_seg, addr, addr + 3UL);
writememl(cpu_state.ea_seg->base, addr, EAX);
CLOCK_CYCLES((is486) ? 1 : 2);
PREFETCH_RUN(2, 3, -1, 0,0,0,1, 0);

2
src/cpu/x86_ops_pmode.h
View File

@@ -198,7 +198,6 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
granularity = readmemb(0, addr + 6) & 0x80;
if (cpu_state.abrt) return 1;
ldt.limit = limit;
ldt.limit_raw = limit;
ldt.access = access;
ldt.ar_high = ar_high;
if (granularity)
@@ -232,7 +231,6 @@ static int op0F00_common(uint32_t fetchdat, int ea32)
if (cpu_state.abrt) return 1;
tr.seg = sel;
tr.limit = limit;
tr.limit_raw = limit;
tr.access = access;
tr.ar_high = ar_high;
if (granularity)

156
src/cpu/x86_ops_rep.h
View File

@@ -2,7 +2,8 @@
static int opREP_INSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64 = 0x0000000000000000ULL; \
\
addr64 = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -11,6 +12,7 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG); \
high_page = 0; \
do_mmut_wb(es, DEST_REG, &addr64); \
if (cpu_state.abrt) return 1; \
temp = inb(DX); \
@@ -34,7 +36,8 @@ static int opREP_INSB_ ## size(uint32_t fetchdat)
static int opREP_INSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64[2]; \
\
addr64a[0] = addr64a[1] = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -43,11 +46,12 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
check_io_perm(DX); \
check_io_perm(DX+1); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_ww(es, DEST_REG, addr64); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
high_page = 0; \
do_mmut_ww(es, DEST_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = inw(DX); \
writememw_n(es, DEST_REG, addr64, temp); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64a, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
@@ -67,7 +71,8 @@ static int opREP_INSW_ ## size(uint32_t fetchdat)
static int opREP_INSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, writes = 0, total_cycles = 0; \
uint64_t addr64[4]; \
\
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
\
if (CNT_REG > 0) \
{ \
@@ -78,11 +83,12 @@ static int opREP_INSL_ ## size(uint32_t fetchdat)
check_io_perm(DX+1); \
check_io_perm(DX+2); \
check_io_perm(DX+3); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_wl(es, DEST_REG, addr64); \
CHECK_WRITE(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
high_page = 0; \
do_mmut_wl(es, DEST_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = inl(DX); \
writememl_n(es, DEST_REG, addr64, temp); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64a, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
@@ -135,7 +141,7 @@ static int opREP_OUTSW_ ## size(uint32_t fetchdat)
{ \
uint16_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
temp = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
@@ -163,7 +169,7 @@ static int opREP_OUTSL_ ## size(uint32_t fetchdat)
{ \
uint32_t temp; \
SEG_CHECK_READ(cpu_state.ea_seg); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
temp = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
check_io_perm(DX); \
check_io_perm(DX+1); \
@@ -190,27 +196,27 @@ static int opREP_MOVSB_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r = 0x0000000000000000ULL; \
uint64_t addr64w = 0x0000000000000000ULL; \
addr64 = addr64_2 = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint8_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG); \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64r); \
high_page = 0; \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64) ; \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_wb(es, DEST_REG, &addr64w); \
do_mmut_wb(es, DEST_REG, &addr64_2); \
if (cpu_state.abrt) break; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememb_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); if (cpu_state.abrt) return 1; \
writememb_n(es, DEST_REG, addr64_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
@@ -233,27 +239,28 @@ static int opREP_MOVSW_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r[2]; \
uint64_t addr64w[2]; \
addr64a[0] = addr64a[1] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint16_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64r); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
high_page = 0; \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_ww(es, DEST_REG, addr64w); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
do_mmut_ww(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) break; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
writememw_n(es, DEST_REG, addr64a_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
@@ -276,27 +283,28 @@ static int opREP_MOVSL_ ## size(uint32_t fetchdat)
{ \
int reads = 0, writes = 0, total_cycles = 0; \
int cycles_end = cycles - ((is386 && cpu_use_dynarec) ? 1000 : 100); \
uint64_t addr64r[4]; \
uint64_t addr64w[4]; \
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; \
if (trap) \
cycles_end = cycles+1; /*Force the instruction to end after only one iteration when trap flag set*/ \
if (CNT_REG > 0) \
{ \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_WRITE(&cpu_state.seg_es); \
} \
} \
while (CNT_REG > 0) \
{ \
uint32_t temp; \
\
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64r); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
high_page = 0; \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) break; \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_wl(es, DEST_REG, addr64w); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
do_mmut_wl(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) break; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64r); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64w, temp); if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
writememl_n(es, DEST_REG, addr64a_2, temp); if (cpu_state.abrt) return 1; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
@@ -356,7 +364,7 @@ static int opREP_STOSW_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
writememw(es, DEST_REG, AX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 2; \
else DEST_REG += 2; \
@@ -385,7 +393,7 @@ static int opREP_STOSL_ ## size(uint32_t fetchdat)
SEG_CHECK_WRITE(&cpu_state.seg_es); \
while (CNT_REG > 0) \
{ \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
CHECK_WRITE_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
writememl(es, DEST_REG, EAX); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) DEST_REG -= 4; \
else DEST_REG += 4; \
@@ -444,7 +452,7 @@ static int opREP_LODSW_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
AX = readmemw(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 2; \
else SRC_REG += 2; \
@@ -473,7 +481,7 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
while (CNT_REG > 0) \
{ \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
CHECK_READ_REP(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
EAX = readmeml(cpu_state.ea_seg->base, SRC_REG); if (cpu_state.abrt) return 1; \
if (cpu_state.flags & D_FLAG) SRC_REG -= 4; \
else SRC_REG += 4; \
@@ -501,8 +509,8 @@ static int opREP_LODSL_ ## size(uint32_t fetchdat)
static int opREP_CMPSB_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64 = 0x0000000000000000ULL; \
uint64_t addr642 = 0x0000000000000000ULL; \
\
addr64 = addr64_2 = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -511,12 +519,18 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG); \
high_page = uncached = 0; \
do_mmut_rb(cpu_state.ea_seg->base, SRC_REG, &addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_rb(es, DEST_REG, &addr642); \
if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmemb_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG); \
do_mmut_rb2(es, DEST_REG, &addr64_2); \
if (cpu_state.abrt) return 1; \
temp = readmemb_n(cpu_state.ea_seg->base, SRC_REG, addr64); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = old_rl2; \
temp2 = readmemb_n(es, DEST_REG, addr64_2); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = (uintptr_t) LOOKUP_INV; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG--; SRC_REG--; } \
else { DEST_REG++; SRC_REG++; } \
@@ -538,8 +552,9 @@ static int opREP_CMPSB_ ## size(uint32_t fetchdat)
static int opREP_CMPSW_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64[2]; \
uint64_t addr642[2]; \
\
addr64a[0] = addr64a[1] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -547,13 +562,19 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
uint16_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1); \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
do_mmut_rw(es, DEST_REG, addr642); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 1UL); \
high_page = uncached = 0; \
do_mmut_rw(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmemw_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
do_mmut_rw2(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) return 1; \
temp = readmemw_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = old_rl2; \
temp2 = readmemw_n(es, DEST_REG, addr64a_2); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = (uintptr_t) LOOKUP_INV; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 2; SRC_REG -= 2; } \
else { DEST_REG += 2; SRC_REG += 2; } \
@@ -575,8 +596,9 @@ static int opREP_CMPSW_ ## size(uint32_t fetchdat)
static int opREP_CMPSL_ ## size(uint32_t fetchdat) \
{ \
int reads = 0, total_cycles = 0, tempz; \
uint64_t addr64[4]; \
uint64_t addr642[4]; \
\
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000; \
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000; \
\
tempz = FV; \
if ((CNT_REG > 0) && (FV == tempz)) \
@@ -584,13 +606,19 @@ static int opREP_CMPSL_ ## size(uint32_t fetchdat)
uint32_t temp, temp2; \
SEG_CHECK_READ(cpu_state.ea_seg); \
SEG_CHECK_READ(&cpu_state.seg_es); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3); \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64); \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
do_mmut_rl(es, DEST_REG, addr642); \
CHECK_READ(cpu_state.ea_seg, SRC_REG, SRC_REG + 3UL); \
high_page = uncached = 0; \
do_mmut_rl(cpu_state.ea_seg->base, SRC_REG, addr64a); \
if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64); \
temp2 = readmeml_n(es, DEST_REG, addr642); if (cpu_state.abrt) return 1; \
CHECK_READ(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
do_mmut_rl2(es, DEST_REG, addr64a_2); \
if (cpu_state.abrt) return 1; \
temp = readmeml_n(cpu_state.ea_seg->base, SRC_REG, addr64a); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = old_rl2; \
temp2 = readmeml_n(es, DEST_REG, addr64a_2); if (cpu_state.abrt) return 1; \
if (uncached) \
readlookup2[(uint32_t)(es+DEST_REG)>>12] = (uintptr_t) LOOKUP_INV; \
\
if (cpu_state.flags & D_FLAG) { DEST_REG -= 4; SRC_REG -= 4; } \
else { DEST_REG += 4; SRC_REG += 4; } \
@@ -653,7 +681,7 @@ static int opREP_SCASW_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1); \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 1UL); \
uint16_t temp = readmemw(es, DEST_REG); if (cpu_state.abrt) break;\
setsub16(AX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \
@@ -685,7 +713,7 @@ static int opREP_SCASL_ ## size(uint32_t fetchdat)
SEG_CHECK_READ(&cpu_state.seg_es); \
while ((CNT_REG > 0) && (FV == tempz)) \
{ \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3); \
CHECK_READ_REP(&cpu_state.seg_es, DEST_REG, DEST_REG + 3UL); \
uint32_t temp = readmeml(es, DEST_REG); if (cpu_state.abrt) break;\
setsub32(EAX, temp); \
tempz = (ZF_SET()) ? 1 : 0; \

37
src/cpu/x86_ops_stack.h
View File

@@ -245,8 +245,8 @@ static int opPOPW_a16(uint32_t fetchdat)
else SP -= 2;
}
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 1,0,(cpu_mod == 3) ? 0:1,0, 0);
return cpu_state.abrt;
}
@@ -266,8 +266,8 @@ static int opPOPW_a32(uint32_t fetchdat)
else SP -= 2;
}
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 1,0,(cpu_mod == 3) ? 0:1,0, 1);
return cpu_state.abrt;
}
@@ -288,8 +288,8 @@ static int opPOPL_a16(uint32_t fetchdat)
else SP -= 4;
}
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 0,1,0,(cpu_mod == 3) ? 0:1, 0);
return cpu_state.abrt;
}
@@ -309,8 +309,8 @@ static int opPOPL_a32(uint32_t fetchdat)
else SP -= 4;
}
if (is486) CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6);
else CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5);
if (is486) { CLOCK_CYCLES((cpu_mod == 3) ? 1 : 6); }
else { CLOCK_CYCLES((cpu_mod == 3) ? 4 : 5); }
PREFETCH_RUN((cpu_mod == 3) ? 4 : 5, 2, rmdat, 0,1,0,(cpu_mod == 3) ? 0:1, 1);
return cpu_state.abrt;
}
@@ -470,17 +470,16 @@ static int opLEAVE_l(uint32_t fetchdat)
}
PUSH_SEG_OPS(CS);
PUSH_SEG_OPS(DS);
PUSH_SEG_OPS(ES);
PUSH_SEG_OPS(FS);
PUSH_SEG_OPS(GS);
PUSH_SEG_OPS(SS);
POP_SEG_OPS(DS, &cpu_state.seg_ds);
POP_SEG_OPS(ES, &cpu_state.seg_es);
POP_SEG_OPS(FS, &cpu_state.seg_fs);
POP_SEG_OPS(GS, &cpu_state.seg_gs);
PUSH_SEG_OPS(CS)
PUSH_SEG_OPS(DS)
PUSH_SEG_OPS(ES)
PUSH_SEG_OPS(FS)
PUSH_SEG_OPS(GS)
PUSH_SEG_OPS(SS)
POP_SEG_OPS(DS, &cpu_state.seg_ds)
POP_SEG_OPS(ES, &cpu_state.seg_es)
POP_SEG_OPS(FS, &cpu_state.seg_fs)
POP_SEG_OPS(GS, &cpu_state.seg_gs)
static int opPOP_SS_w(uint32_t fetchdat)

224
src/cpu/x86_ops_string.h
View File

@@ -1,17 +1,18 @@
static int opMOVSB_a16(uint32_t fetchdat)
{
uint8_t temp;
uint64_t addr64r;
uint64_t addr64w;
addr64 = addr64_2 = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64r);
high_page = 0;
do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_wb(es, DI, &addr64w);
do_mmut_wb(es, DI, &addr64_2);
if (cpu_state.abrt) return 1;
temp = readmemb_n(cpu_state.ea_seg->base, SI, addr64r); if (cpu_state.abrt) return 1;
writememb_n(es, DI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmemb_n(cpu_state.ea_seg->base, SI, addr64); if (cpu_state.abrt) return 1;
writememb_n(es, DI, addr64_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
CLOCK_CYCLES(7);
@@ -21,17 +22,18 @@ static int opMOVSB_a16(uint32_t fetchdat)
static int opMOVSB_a32(uint32_t fetchdat)
{
uint8_t temp;
uint64_t addr64r;
uint64_t addr64w;
addr64 = addr64_2 = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64r);
high_page = 0;
do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_wb(es, EDI, &addr64w);
do_mmut_wb(es, EDI, &addr64_2);
if (cpu_state.abrt) return 1;
temp = readmemb_n(cpu_state.ea_seg->base, ESI, addr64r); if (cpu_state.abrt) return 1;
writememb_n(es, EDI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmemb_n(cpu_state.ea_seg->base, ESI, addr64); if (cpu_state.abrt) return 1;
writememb_n(es, EDI, addr64_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
CLOCK_CYCLES(7);
@@ -42,17 +44,19 @@ static int opMOVSB_a32(uint32_t fetchdat)
static int opMOVSW_a16(uint32_t fetchdat)
{
uint16_t temp;
uint64_t addr64r[2];
uint64_t addr64w[2];
addr64a[0] = addr64a[1] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rw(cpu_state.ea_seg->base, SI, addr64r);
high_page = 0;
do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_ww(es, DI, addr64w);
do_mmut_ww(es, DI, addr64a_2);
if (cpu_state.abrt) return 1;
temp = readmemw_n(cpu_state.ea_seg->base, SI, addr64r); if (cpu_state.abrt) return 1;
writememw_n(es, DI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmemw_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
writememw_n(es, DI, addr64a_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
CLOCK_CYCLES(7);
@@ -62,17 +66,19 @@ static int opMOVSW_a16(uint32_t fetchdat)
static int opMOVSW_a32(uint32_t fetchdat)
{
uint16_t temp;
uint64_t addr64r[2];
uint64_t addr64w[2];
addr64a[0] = addr64a[1] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64r);
high_page = 0;
do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_ww(es, EDI, addr64w);
do_mmut_ww(es, EDI, addr64a_2);
if (cpu_state.abrt) return 1;
temp = readmemw_n(cpu_state.ea_seg->base, ESI, addr64r); if (cpu_state.abrt) return 1;
writememw_n(es, EDI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
writememw_n(es, EDI, addr64a_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
CLOCK_CYCLES(7);
@@ -83,17 +89,19 @@ static int opMOVSW_a32(uint32_t fetchdat)
static int opMOVSL_a16(uint32_t fetchdat)
{
uint32_t temp;
uint64_t addr64r[4];
uint64_t addr64w[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rl(cpu_state.ea_seg->base, SI, addr64r);
high_page = 0;
do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_wl(es, DI, addr64w);
do_mmut_wl(es, DI, addr64a_2);
if (cpu_state.abrt) return 1;
temp = readmeml_n(cpu_state.ea_seg->base, SI, addr64r); if (cpu_state.abrt) return 1;
writememl_n(es, DI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmeml_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
writememl_n(es, DI, addr64a_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
CLOCK_CYCLES(7);
@@ -103,17 +111,19 @@ static int opMOVSL_a16(uint32_t fetchdat)
static int opMOVSL_a32(uint32_t fetchdat)
{
uint32_t temp;
uint64_t addr64r[4];
uint64_t addr64w[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64r);
high_page = 0;
do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_WRITE(&cpu_state.seg_es);
do_mmut_wl(es, EDI, addr64w);
do_mmut_wl(es, EDI, addr64a_2);
if (cpu_state.abrt) return 1;
temp = readmeml_n(cpu_state.ea_seg->base, ESI, addr64r); if (cpu_state.abrt) return 1;
writememl_n(es, EDI, addr64w, temp); if (cpu_state.abrt) return 1;
temp = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
writememl_n(es, EDI, addr64a_2, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
CLOCK_CYCLES(7);
@@ -125,17 +135,22 @@ static int opMOVSL_a32(uint32_t fetchdat)
static int opCMPSB_a16(uint32_t fetchdat)
{
uint8_t src, dst;
uint64_t addr64;
uint64_t addr642;
addr64 = addr64_2 = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
high_page = uncached = 0;
do_mmut_rb(cpu_state.ea_seg->base, SI, &addr64);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rb(es, DI, &addr642);
do_mmut_rb2(es, DI, &addr64_2);
if (cpu_state.abrt) return 1;
src = readmemb_n(cpu_state.ea_seg->base, SI, addr64);
dst = readmemb_n(es, DI, addr642); if (cpu_state.abrt) return 1;
src = readmemb_n(cpu_state.ea_seg->base, SI, addr64); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = old_rl2;
dst = readmemb_n(es, DI, addr64_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = (uintptr_t) LOOKUP_INV;
setsub8(src, dst);
if (cpu_state.flags & D_FLAG) { DI--; SI--; }
else { DI++; SI++; }
@@ -146,17 +161,22 @@ static int opCMPSB_a16(uint32_t fetchdat)
static int opCMPSB_a32(uint32_t fetchdat)
{
uint8_t src, dst;
uint64_t addr64;
uint64_t addr642;
addr64 = addr64_2 = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
high_page = uncached = 0;
do_mmut_rb(cpu_state.ea_seg->base, ESI, &addr64);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rb(es, EDI, &addr642);
do_mmut_rb2(es, EDI, &addr64_2);
if (cpu_state.abrt) return 1;
src = readmemb_n(cpu_state.ea_seg->base, ESI, addr64);
dst = readmemb_n(es, EDI, addr642); if (cpu_state.abrt) return 1;
src = readmemb_n(cpu_state.ea_seg->base, ESI, addr64); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = old_rl2;
dst = readmemb_n(es, EDI, addr64_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = (uintptr_t) LOOKUP_INV;
setsub8(src, dst);
if (cpu_state.flags & D_FLAG) { EDI--; ESI--; }
else { EDI++; ESI++; }
@@ -168,17 +188,23 @@ static int opCMPSB_a32(uint32_t fetchdat)
static int opCMPSW_a16(uint32_t fetchdat)
{
uint16_t src, dst;
uint64_t addr64[2];
uint64_t addr642[2];
addr64a[0] = addr64a[1] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rw(cpu_state.ea_seg->base, SI, addr64);
high_page = uncached = 0;
do_mmut_rw(cpu_state.ea_seg->base, SI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rw(es, DI, addr642);
do_mmut_rw2(es, DI, addr64a_2);
if (cpu_state.abrt) return 1;
src = readmemw_n(cpu_state.ea_seg->base, SI, addr64);
dst = readmemw_n(es, DI, addr642); if (cpu_state.abrt) return 1;
src = readmemw_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = old_rl2;
dst = readmemw_n(es, DI, addr64a_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = (uintptr_t) LOOKUP_INV;
setsub16(src, dst);
if (cpu_state.flags & D_FLAG) { DI -= 2; SI -= 2; }
else { DI += 2; SI += 2; }
@@ -189,17 +215,23 @@ static int opCMPSW_a16(uint32_t fetchdat)
static int opCMPSW_a32(uint32_t fetchdat)
{
uint16_t src, dst;
uint64_t addr64[2];
uint64_t addr642[2];
addr64a[0] = addr64a[1] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64);
high_page = uncached = 0;
do_mmut_rw(cpu_state.ea_seg->base, ESI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rw(es, EDI, addr642);
do_mmut_rw2(es, EDI, addr64a_2);
if (cpu_state.abrt) return 1;
src = readmemw_n(cpu_state.ea_seg->base, ESI, addr64);
dst = readmemw_n(es, EDI, addr642); if (cpu_state.abrt) return 1;
src = readmemw_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = old_rl2;
dst = readmemw_n(es, EDI, addr64a_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = (uintptr_t) LOOKUP_INV;
setsub16(src, dst);
if (cpu_state.flags & D_FLAG) { EDI -= 2; ESI -= 2; }
else { EDI += 2; ESI += 2; }
@@ -211,17 +243,23 @@ static int opCMPSW_a32(uint32_t fetchdat)
static int opCMPSL_a16(uint32_t fetchdat)
{
uint32_t src, dst;
uint64_t addr64[4];
uint64_t addr642[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rl(cpu_state.ea_seg->base, SI, addr64);
high_page = uncached = 0;
do_mmut_rl(cpu_state.ea_seg->base, SI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rl(es, DI, addr642);
do_mmut_rl2(es, DI, addr64a_2);
if (cpu_state.abrt) return 1;
src = readmeml_n(cpu_state.ea_seg->base, SI, addr64);
dst = readmeml_n(es, DI, addr642); if (cpu_state.abrt) return 1;
src = readmeml_n(cpu_state.ea_seg->base, SI, addr64a); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = old_rl2;
dst = readmeml_n(es, DI, addr64a_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+DI)>>12] = (uintptr_t) LOOKUP_INV;
setsub32(src, dst);
if (cpu_state.flags & D_FLAG) { DI -= 4; SI -= 4; }
else { DI += 4; SI += 4; }
@@ -232,17 +270,23 @@ static int opCMPSL_a16(uint32_t fetchdat)
static int opCMPSL_a32(uint32_t fetchdat)
{
uint32_t src, dst;
uint64_t addr64[4];
uint64_t addr642[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
addr64a_2[0] = addr64a_2[1] = addr64a_2[2] = addr64a_2[3] = 0x00000000;
SEG_CHECK_READ(cpu_state.ea_seg);
do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64);
high_page = uncached = 0;
do_mmut_rl(cpu_state.ea_seg->base, ESI, addr64a);
if (cpu_state.abrt) return 1;
SEG_CHECK_READ(&cpu_state.seg_es);
do_mmut_rl(es, EDI, addr642);
do_mmut_rl2(es, EDI, addr64a_2);
if (cpu_state.abrt) return 1;
src = readmeml_n(cpu_state.ea_seg->base, ESI, addr64);
dst = readmeml_n(es, EDI, addr642); if (cpu_state.abrt) return 1;
src = readmeml_n(cpu_state.ea_seg->base, ESI, addr64a); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = old_rl2;
dst = readmeml_n(es, EDI, addr64a_2); if (cpu_state.abrt) return 1;
if (uncached)
readlookup2[(uint32_t)(es+EDI)>>12] = (uintptr_t) LOOKUP_INV;
setsub32(src, dst);
if (cpu_state.flags & D_FLAG) { EDI -= 4; ESI -= 4; }
else { EDI += 4; ESI += 4; }
@@ -481,10 +525,12 @@ static int opSCASL_a32(uint32_t fetchdat)
static int opINSB_a16(uint32_t fetchdat)
{
uint8_t temp;
uint64_t addr64 = 0x0000000000000000ULL;
addr64 = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
high_page = 0;
do_mmut_wb(es, DI, &addr64); if (cpu_state.abrt) return 1;
temp = inb(DX);
writememb_n(es, DI, addr64, temp); if (cpu_state.abrt) return 1;
@@ -497,10 +543,12 @@ static int opINSB_a16(uint32_t fetchdat)
static int opINSB_a32(uint32_t fetchdat)
{
uint8_t temp;
uint64_t addr64 = 0x0000000000000000ULL;
addr64 = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
high_page = 0;
do_mmut_wb(es, EDI, &addr64); if (cpu_state.abrt) return 1;
temp = inb(DX);
writememb_n(es, EDI, addr64, temp); if (cpu_state.abrt) return 1;
@@ -514,14 +562,16 @@ static int opINSB_a32(uint32_t fetchdat)
static int opINSW_a16(uint32_t fetchdat)
{
uint16_t temp;
uint64_t addr64[2];
addr64a[0] = addr64a[1] = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
do_mmut_ww(es, DI, addr64); if (cpu_state.abrt) return 1;
high_page = 0;
do_mmut_ww(es, DI, addr64a); if (cpu_state.abrt) return 1;
temp = inw(DX);
writememw_n(es, DI, addr64, temp); if (cpu_state.abrt) return 1;
writememw_n(es, DI, addr64a, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) DI -= 2;
else DI += 2;
CLOCK_CYCLES(15);
@@ -531,14 +581,16 @@ static int opINSW_a16(uint32_t fetchdat)
static int opINSW_a32(uint32_t fetchdat)
{
uint16_t temp;
uint64_t addr64[2];
addr64a[0] = addr64a[1] = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
high_page = 0;
check_io_perm(DX);
check_io_perm(DX + 1);
do_mmut_ww(es, EDI, addr64); if (cpu_state.abrt) return 1;
do_mmut_ww(es, EDI, addr64a); if (cpu_state.abrt) return 1;
temp = inw(DX);
writememw_n(es, EDI, addr64, temp); if (cpu_state.abrt) return 1;
writememw_n(es, EDI, addr64a, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) EDI -= 2;
else EDI += 2;
CLOCK_CYCLES(15);
@@ -549,16 +601,18 @@ static int opINSW_a32(uint32_t fetchdat)
static int opINSL_a16(uint32_t fetchdat)
{
uint32_t temp;
uint64_t addr64[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
do_mmut_wl(es, DI, addr64); if (cpu_state.abrt) return 1;
high_page = 0;
do_mmut_wl(es, DI, addr64a); if (cpu_state.abrt) return 1;
temp = inl(DX);
writememl_n(es, DI, addr64, temp); if (cpu_state.abrt) return 1;
writememl_n(es, DI, addr64a, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) DI -= 4;
else DI += 4;
CLOCK_CYCLES(15);
@@ -568,16 +622,18 @@ static int opINSL_a16(uint32_t fetchdat)
static int opINSL_a32(uint32_t fetchdat)
{
uint32_t temp;
uint64_t addr64[4];
addr64a[0] = addr64a[1] = addr64a[2] = addr64a[3] = 0x00000000;
SEG_CHECK_WRITE(&cpu_state.seg_es);
check_io_perm(DX);
check_io_perm(DX + 1);
check_io_perm(DX + 2);
check_io_perm(DX + 3);
do_mmut_wl(es, DI, addr64); if (cpu_state.abrt) return 1;
high_page = 0;
do_mmut_wl(es, DI, addr64a); if (cpu_state.abrt) return 1;
temp = inl(DX);
writememl_n(es, EDI, addr64, temp); if (cpu_state.abrt) return 1;
writememl_n(es, EDI, addr64a, temp); if (cpu_state.abrt) return 1;
if (cpu_state.flags & D_FLAG) EDI -= 4;
else EDI += 4;
CLOCK_CYCLES(15);

12
src/cpu/x86seg.c
View File

@@ -227,7 +227,6 @@ void
do_seg_load(x86seg *s, uint16_t *segdat)
{
s->limit = segdat[0] | ((segdat[3] & 0x000f) << 16);
s->limit_raw = s->limit;
if (segdat[3] & 0x0080)
s->limit = (s->limit << 12) | 0xfff;
s->base = segdat[1] | ((segdat[2] & 0x00ff) << 16);
@@ -281,7 +280,7 @@ check_seg_valid(x86seg *s)
int valid = 1;
x86seg *dt = (s->seg & 0x0004) ? &ldt : &gdt;
if (((s->seg & 0xfff8) + 7) > dt->limit)
if (((s->seg & 0xfff8UL) + 7UL) > dt->limit)
valid = 0;
switch (s->access & 0x1f) {
@@ -2382,9 +2381,14 @@ taskswitch286(uint16_t seg, uint16_t *segdat, int is32)
void
cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg)
{
writememl(0, addr, (seg->limit_raw & 0xffff) | (seg->base << 16));
uint32_t limit_raw = seg->limit;
if (seg->ar_high & 0x80)
limit_raw >>= 12;
writememl(0, addr, (limit_raw & 0xffff) | (seg->base << 16));
writememl(0, addr + 4, ((seg->base >> 16) & 0xff) | (seg->access << 8) |
(seg->limit_raw & 0xf0000) | (seg->ar_high << 16) |
(limit_raw & 0xf0000) | (seg->ar_high << 16) |
(seg->base & 0xff000000));
}

8
src/device/keyboard_at.c
View File

@@ -1059,8 +1059,9 @@ write_output(atkbd_t *dev, uint8_t val)
if ((dev->output_port ^ val) & 0x01) { /*Reset*/
if (! (val & 0x01)) {
/* Pin 0 selected. */
resetx86(); /*Pulse reset!*/
softresetx86(); /*Pulse reset!*/
cpu_set_edx();
smbase = is_486_org ? 0x00060000 : 0x00030000;
}
}
/* Mask off the A20 stuff because we use mem_a20_key directly for that. */
@@ -1325,6 +1326,11 @@ write64_ami(void *priv, uint8_t val)
dev->want60 = 1;
return 0;
case 0xa0: /* copyright message */
add_data(dev, 0x28);
add_data(dev, 0x00);
break;
case 0xa1: /* get controller version */
kbd_log("ATkbc: AMI - get controller version\n");
add_data(dev, 'H');

1
src/include/86box/86box.h
View File

@@ -120,6 +120,7 @@ extern int enable_crashdump; /* (C) enable crash dump */
extern int is_pentium; /* TODO: Move back to cpu/cpu.h when it's figured out,
how to remove that hack from the ET4000/W32p. */
extern int fixed_size_x, fixed_size_y;
#ifdef ENABLE_LOG_TOGGLES

2
src/include/86box/machine.h
View File

@@ -381,6 +381,8 @@ extern const device_t *at_cpqiii_get_device(void);
/* m_at_socket4_5.c */
extern int machine_at_excalibur_init(const machine_t *);
extern int machine_at_pat54pv_init(const machine_t *);
extern int machine_at_hot543_init(const machine_t *);
extern int machine_at_p54vl_init(const machine_t *);

23
src/include/86box/mem.h
View File

@@ -189,12 +189,12 @@ extern uint32_t rammask;
extern uint8_t *rom;
extern uint32_t biosmask, biosaddr;
extern int readlookup[256],
readlookupp[256];
extern int readlookup[256];
extern uintptr_t * readlookup2;
extern uintptr_t old_rl2;
extern uint8_t uncached;
extern int readlnext;
extern int writelookup[256],
writelookupp[256];
extern int writelookup[256];
extern uintptr_t * writelookup2;
extern int writelnext;
extern uint32_t ram_mapped_addr[64];
@@ -224,6 +224,7 @@ extern int readlnum,
extern int memspeed[11];
extern int mmu_perm;
extern uint8_t high_page; /* if a high (> 4 gb) page was detected */
extern int mem_a20_state,
mem_a20_alt,
@@ -244,14 +245,14 @@ extern void writememll(uint32_t addr, uint32_t val);
extern uint64_t readmemql(uint32_t addr);
extern void writememql(uint32_t addr, uint64_t val);
extern uint8_t readmembl_no_mmut(uint32_t addr, uint64_t addr64);
extern void writemembl_no_mmut(uint32_t addr, uint64_t addr64, uint8_t val);
extern uint16_t readmemwl_no_mmut(uint32_t addr, uint64_t *addr64);
extern void writememwl_no_mmut(uint32_t addr, uint64_t *addr64, uint16_t val);
extern uint32_t readmemll_no_mmut(uint32_t addr, uint64_t *addr64);
extern void writememll_no_mmut(uint32_t addr, uint64_t *addr64, uint32_t val);
extern uint8_t readmembl_no_mmut(uint32_t addr, uint32_t a64);
extern void writemembl_no_mmut(uint32_t addr, uint32_t a64, uint8_t val);
extern uint16_t readmemwl_no_mmut(uint32_t addr, uint32_t *a64);
extern void writememwl_no_mmut(uint32_t addr, uint32_t *a64, uint16_t val);
extern uint32_t readmemll_no_mmut(uint32_t addr, uint32_t *a64);
extern void writememll_no_mmut(uint32_t addr, uint32_t *a64, uint32_t val);
extern void do_mmutranslate(uint32_t addr, uint64_t *addr64, int num, int write);
extern void do_mmutranslate(uint32_t addr, uint32_t *a64, int num, int write);
extern uint8_t *getpccache(uint32_t a);
extern uint64_t mmutranslatereal(uint32_t addr, int rw);

1
src/include/86box/pit.h
View File

@@ -109,6 +109,7 @@ extern void pit_handler(int set, uint16_t base, int size, void *priv);
#ifdef EMU_DEVICE_H
extern const device_t i8253_device;
extern const device_t i8254_device;
extern const device_t i8254_sec_device;
extern const device_t i8254_ext_io_device;
extern const device_t i8254_ps2_device;
#endif

10
src/include/86box/resource.h
View File

@@ -28,6 +28,7 @@
#define DLG_STATUS 102 /* top-level dialog */
#define DLG_SND_GAIN 103 /* top-level dialog */
#define DLG_NEW_FLOPPY 104 /* top-level dialog */
#define DLG_SPECIFY_DIM 105 /* top-level dialog */
#define DLG_CONFIG 110 /* top-level dialog */
#define DLG_CFG_MACHINE 111 /* sub-dialog of config */
#define DLG_CFG_VIDEO 112 /* sub-dialog of config */
@@ -256,7 +257,6 @@
#define IDC_COMBO_DISK_SIZE 1201
#define IDC_COMBO_RPM_MODE 1202
/* For the DeviceConfig code, re-do later. */
#define IDC_CONFIG_BASE 1300
#define IDC_CONFIGURE_VID 1300
@@ -277,6 +277,11 @@
#define IDC_RENDER 1381
#define IDC_STATUS 1382
#define IDC_EDIT_WIDTH 1400 /* specify main window dimensions dialog */
#define IDC_WIDTHSPIN 1401
#define IDC_EDIT_HEIGHT 1402
#define IDC_HEIGHTSPIN 1403
#define IDC_CHECK_LOCK_SIZE 1404
#define IDM_ABOUT 40001
#define IDC_ABOUT_ICON 65535
@@ -308,12 +313,13 @@
#define IDM_VID_SCALE_2X 40056
#define IDM_VID_SCALE_3X 40057
#define IDM_VID_SCALE_4X 40058
#define IDM_VID_HIDPI 40059
#define IDM_VID_HIDPI 40059
#define IDM_VID_FULLSCREEN 40060
#define IDM_VID_FS_FULL 40061
#define IDM_VID_FS_43 40062
#define IDM_VID_FS_KEEPRATIO 40063
#define IDM_VID_FS_INT 40064
#define IDM_VID_SPECIFY_DIM 40065
#define IDM_VID_FORCE43 40066
#define IDM_VID_OVERSCAN 40067
#define IDM_VID_INVERT 40069

4
src/include/86box/win.h
View File

@@ -174,6 +174,10 @@ extern void SoundGainDialogCreate(HWND hwnd);
extern void NewFloppyDialogCreate(HWND hwnd, int id, int part);
/* Functions in win_specify_dim.c: */
extern void SpecifyDimensionsDialogCreate(HWND hwnd);
/* Functions in win_settings.c: */
#define SETTINGS_PAGE_MACHINE 0
#define SETTINGS_PAGE_VIDEO 1

2
src/machine/m_at_386dx_486.c
View File

@@ -887,7 +887,7 @@ machine_at_4sa2_init(const machine_t *model)
pci_register_slot(0x0F, PCI_CARD_NORMAL, 3, 4, 1, 2);
pci_register_slot(0x11, PCI_CARD_NORMAL, 4, 1, 2, 3);
device_add(&pc87332_device);
device_add(&w83787f_device);
device_add(&keyboard_ps2_pci_device);
device_add(&intel_flash_bxt_device);

20
src/machine/m_at_socket4_5.c
View File

@@ -62,7 +62,27 @@ machine_at_excalibur_init(const machine_t *model)
return ret;
}
int
machine_at_pat54pv_init(const machine_t *model)
{
int ret;
ret = bios_load_linear("roms/machines/pat54pv/pat54pv.bin",
0x000f0000, 65536, 0);
if (bios_only || !ret)
return ret;
machine_at_common_init(model);
device_add(&opti5x7_device);
device_add(&keyboard_at_ami_device);
if (fdc_type == FDC_INTERNAL)
device_add(&fdc_at_device);
return ret;
}
int
machine_at_hot543_init(const machine_t *model)
{

2
src/machine/machine.c
View File

@@ -81,7 +81,7 @@ machine_init_ex(int m)
/* Reset the memory state. */
mem_reset();
smbase = is_am486 ? 0x00060000 : 0x00030000;
smbase = is_486_org ? 0x00060000 : 0x00030000;
lpt_init();
}

7
src/machine/machine_table.c
View File

@@ -233,8 +233,8 @@ const machine_t machines[] = {
{ "[ALi M1489] AMI WinBIOS 486 PCI", "win486pci", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 65536, 1024, 255, machine_at_win486pci_init, NULL },
{ "[OPTi 802G] IBM PC 330 (type 6573)", "pc330_6573", MACHINE_TYPE_486, CPU_PKG_SOCKET3_PC330, 0, 25000000, 33333333, 0, 0, 2.0, 3.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE, 1024, 65536, 1024, 127, machine_at_pc330_6573_init, NULL },
{ "[i420EX] ASUS PVI-486AP4", "486ap4", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_486ap4_init, NULL },
{ "[i420ZX] ASUS PCI/I-486SP3G", "486sp3g", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_486sp3g_init, NULL },
{ "[i420TX] ASUS PCI/I-486SP3", "486sp3", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 127, machine_at_486sp3_init, NULL },
{ "[i420ZX] ASUS PCI/I-486SP3G", "486sp3g", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL | MACHINE_SCSI, 1024, 131072, 1024, 127, machine_at_486sp3g_init, NULL },
{ "[i420TX] ASUS PCI/I-486SP3", "486sp3", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL | MACHINE_SCSI, 1024, 131072, 1024, 127, machine_at_486sp3_init, NULL },
{ "[i420TX] Intel Classic/PCI", "alfredo", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 2048, 131072, 2048, 127, machine_at_alfredo_init, NULL },
{ "[SiS 496] ASUS PVI-486SP3C", "486sp3c", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCIV | MACHINE_IDE_DUAL, 1024, 261120, 1024, 255, machine_at_486sp3c_init, NULL },
{ "[SiS 496] Lucky Star LS-486E", "ls486e", MACHINE_TYPE_486, CPU_PKG_SOCKET3, 0, 0, 0, 0, 0, 0, 0, MACHINE_PCI | MACHINE_IDE_DUAL, 1024, 131072, 1024, 255, machine_at_ls486e_init, NULL },
@@ -284,6 +284,9 @@ const machine_t machines[] = {
{ "[i430FX] NEC PowerMate V", "powermate_v", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 2.0, MACHINE_PCI | MACHINE_BUS_PS2 | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_powermate_v_init, NULL },
{ "[i430FX] PC Partner MB500N", "mb500n", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 50000000, 66666667, 3380, 3520, 1.5, 3.0, MACHINE_PCI | MACHINE_IDE_DUAL, 8192, 131072, 8192, 127, machine_at_mb500n_init, NULL },
/* OPTi 596/597 */
{ "[OPTi 597] TMC PAT54PV", "pat54pv", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, CPU_BLOCK(CPU_K5, CPU_5K86), 50000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_VLB, 2048, 65536, 2048, 127, machine_at_pat54pv_init, NULL },
/* OPTi 596/597/822 */
{ "[OPTi 597] Shuttle HOT-543", "hot543", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_hot543_init, NULL },
{ "[OPTi 597] Supermicro P54VL-PCI", "p54vl", MACHINE_TYPE_SOCKET5, CPU_PKG_SOCKET5_7, 0, 60000000, 66666667, 3520, 3520, 1.5, 1.5, MACHINE_PCI | MACHINE_VLB, 8192, 131072, 8192, 127, machine_at_p54vl_init, NULL },

466
src/mem/mem.c
View File

File diff suppressed because it is too large Load Diff

20
src/pit.c
View File

@@ -63,6 +63,7 @@ int64_t firsttime = 1;
#define PIT_PS2 16 /* The PIT is the PS/2's second PIT. */
#define PIT_EXT_IO 32 /* The PIT has externally specified port I/O. */
#define PIT_CUSTOM_CLOCK 64 /* The PIT uses custom clock inputs provided by another provider. */
#define PIT_SECONDARY 128 /* The PIT is secondary (ports 0048-004B). */
enum {
@@ -647,6 +648,8 @@ pit_read(uint16_t addr, void *priv)
break;
case 3: case 0x83:
/* Yes, wm is correct here - this is to ensure correct readout while the
count is being written. */
if (ctr->wm & 0x80)
ret = ~(ctr->l & 0xff);
else
@@ -824,8 +827,10 @@ pit_init(const device_t *info)
dev->flags = info->local;
if (!(dev->flags & PIT_EXT_IO))
io_sethandler(0x0040, 0x0004, pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
if (!(dev->flags & PIT_EXT_IO)) {
io_sethandler((dev->flags & PIT_SECONDARY) ? 0x0048 : 0x0040, 0x0004,
pit_read, NULL, NULL, pit_write, NULL, NULL, dev);
}
return dev;
}
@@ -853,6 +858,17 @@ const device_t i8254_device =
};
const device_t i8254_sec_device =
{
"Intel 8254 Programmable Interval Timer (Secondary)",
DEVICE_ISA,
PIT_8254 | PIT_SECONDARY,
pit_init, pit_close, NULL,
{ NULL }, NULL, NULL,
NULL
};
const device_t i8254_ext_io_device =
{
"Intel 8254 Programmable Interval Timer (External I/O)",

22
src/win/86Box.rc
View File

@@ -71,6 +71,7 @@ BEGIN
#endif
END
MENUITEM SEPARATOR
MENUITEM "Specify dimensions", IDM_VID_SPECIFY_DIM
MENUITEM "F&orce 4:3 display ratio", IDM_VID_FORCE43
POPUP "&Window scale factor"
BEGIN
@@ -342,6 +343,27 @@ BEGIN
#endif
END
DLG_SPECIFY_DIM DIALOG DISCARDABLE 0, 0, 175, 66
STYLE DS_MODALFRAME | WS_POPUP | WS_CAPTION | WS_SYSMENU
CAPTION "Specify Main Window Dimensions"
FONT 9, "Segoe UI"
BEGIN
LTEXT "Width:",IDT_1709,7,9,24,12
EDITTEXT IDC_EDIT_WIDTH,33,7,45,12,ES_AUTOHSCROLL | ES_NUMBER
CONTROL "",IDC_WIDTHSPIN,"msctls_updown32",UDS_SETBUDDYINT |
UDS_ALIGNRIGHT | UDS_ARROWKEYS | UDS_NOTHOUSANDS,76,6,
12,12
LTEXT "Height:",IDT_1710,97,9,24,12
EDITTEXT IDC_EDIT_HEIGHT,123,7,45,12,ES_AUTOHSCROLL | ES_NUMBER
CONTROL "",IDC_HEIGHTSPIN,"msctls_updown32",UDS_SETBUDDYINT |
UDS_ALIGNRIGHT | UDS_ARROWKEYS | UDS_NOTHOUSANDS,166,6,
12,12
CONTROL "Lock to this size",IDC_CHECK_LOCK_SIZE,"Button",
BS_AUTOCHECKBOX | WS_TABSTOP,7,26,94,10
DEFPUSHBUTTON "OK",IDOK,30,45,50,14
PUSHBUTTON "Cancel",IDCANCEL,99,45,50,14
END
DLG_CFG_MACHINE DIALOG DISCARDABLE 107, 0, 305, 200
STYLE DS_CONTROL | WS_CHILD
FONT 9, "Segoe UI"

2
src/win/CMakeLists.txt
View File

@@ -19,7 +19,7 @@ add_library(plat OBJECT win.c win_dynld.c win_thread.c win_cdrom.c
win_keyboard.c win_crashdump.c win_midi.c win_mouse.c)
add_library(ui OBJECT win_ui.c win_stbar.c win_sdl.c win_dialog.c win_about.c
win_settings.c win_devconf.c win_snd_gain.c win_new_floppy.c
win_settings.c win_devconf.c win_snd_gain.c win_specify_dim.c win_new_floppy.c
win_jsconf.c win_media_menu.c 86Box.rc)
if(MSVC)

10
src/win/Makefile.mingw
View File

@@ -447,7 +447,7 @@ else
UIOBJ := win_ui.o win_stbar.o \
win_sdl.o \
win_dialog.o win_about.o \
win_settings.o win_devconf.o win_snd_gain.o \
win_settings.o win_devconf.o win_snd_gain.o win_specify_dim.o \
win_new_floppy.o win_jsconf.o win_media_menu.o
endif
@@ -616,7 +616,7 @@ MAINOBJ := 86box.o config.o random.o timer.o io.o acpi.o apm.o dma.o ddma.o \
MEMOBJ := catalyst_flash.o i2c_eeprom.o intel_flash.o mem.o rom.o smram.o spd.o sst_flash.o
CPUOBJ := cpu.o cpu_table.o \
CPUOBJ := cpu.o cpu_table.o fpu.o x86.o \
808x.o 386.o 386_common.o 386_dynarec.o 386_dynarec_ops.o $(CGTOBJ) \
x86seg.o x87.o x87_timings.o \
$(DYNARECOBJ)
@@ -876,9 +876,9 @@ all: $(PROG).exe
$(PROG).exe: $(OBJ) 86Box.res
@echo Linking $(PROG).exe ..
@$(CC) $(LDFLAGS) -o $(PROG).exe $(OBJ) 86Box.res $(LIBS) -pipe
#ifneq ($(DEBUG), y)
# @$(STRIP) $(PROG).exe
#endif
ifneq ($(DEBUG), y)
@$(STRIP) $(PROG).exe
endif
pcap_if.res: pcap_if.rc
@echo Processing $<

14
src/win/win.c
View File

@@ -1032,7 +1032,7 @@ plat_setfullscreen(int on)
plat_resize(scrnsz_x, scrnsz_y);
if (vid_resize) {
/* scale the screen base on DPI */
if (window_remember) {
if (!(vid_resize & 2) && window_remember) {
MoveWindow(hwndMain, window_x, window_y, window_w, window_h, TRUE);
GetClientRect(hwndMain, &rect);
@@ -1040,11 +1040,11 @@ plat_setfullscreen(int on)
temp_y = rect.bottom - rect.top + 1 - sbar_height;
} else {
if (dpi_scale) {
temp_x = MulDiv(unscaled_size_x, dpi, 96);
temp_y = MulDiv(unscaled_size_y, dpi, 96);
temp_x = MulDiv((vid_resize & 2) ? fixed_size_x : unscaled_size_x, dpi, 96);
temp_y = MulDiv((vid_resize & 2) ? fixed_size_y : unscaled_size_y, dpi, 96);
} else {
temp_x = unscaled_size_x;
temp_y = unscaled_size_y;
temp_x = (vid_resize & 2) ? fixed_size_x : unscaled_size_x;
temp_y = (vid_resize & 2) ? fixed_size_y : unscaled_size_y;
}
/* Main Window. */
@@ -1061,8 +1061,8 @@ plat_setfullscreen(int on)
if (mouse_capture)
ClipCursor(&rect);
scrnsz_x = unscaled_size_x;
scrnsz_y = unscaled_size_y;
scrnsz_x = (vid_resize & 2) ? fixed_size_x : unscaled_size_x;
scrnsz_y = (vid_resize & 2) ? fixed_size_y : unscaled_size_y;
}
}
video_fullscreen &= 1;

179
src/win/win_specify_dim.c Normal file
View File

@@ -0,0 +1,179 @@
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Handle the dialog for specifying the dimensions of the main window.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
* Copyright 2016-2018 Miran Grca.
*/
#define UNICODE
#define BITMAP WINDOWS_BITMAP
#include <windows.h>
#include <windowsx.h>
#undef BITMAP
#include <commctrl.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/config.h>
#include <86box/plat.h>
#include <86box/sound.h>
#include <86box/win.h>
#if defined(__amd64__) || defined(__aarch64__)
static LRESULT CALLBACK
#else
static BOOL CALLBACK
#endif
SpecifyDimensionsDialogProcedure(HWND hdlg, UINT message, WPARAM wParam, LPARAM lParam)
{
HWND h, h2;
HMENU hmenu;
UDACCEL accel, accel2;
RECT r;
uint32_t temp_x = 0, temp_y = 0;
int dpi = 96, lock;
LPTSTR lptsTemp;
char *stransi;
switch (message) {
case WM_INITDIALOG:
GetWindowRect(hwndRender, &r);
h = GetDlgItem(hdlg, IDC_WIDTHSPIN);
h2 = GetDlgItem(hdlg, IDC_EDIT_WIDTH);
SendMessage(h, UDM_SETBUDDY, (WPARAM)h2, 0);
SendMessage(h, UDM_SETRANGE, 0, (120 << 16) | 2048);
accel.nSec = 0;
accel.nInc = 8;
SendMessage(h, UDM_SETACCEL, 1, (LPARAM)&accel);
SendMessage(h, UDM_SETPOS, 0, r.right - r.left);
h = GetDlgItem(hdlg, IDC_HEIGHTSPIN);
h2 = GetDlgItem(hdlg, IDC_EDIT_HEIGHT);
SendMessage(h, UDM_SETBUDDY, (WPARAM)h2, 0);
SendMessage(h, UDM_SETRANGE, 0, (120 << 16) | 2048);
accel2.nSec = 0;
accel2.nInc = 8;
SendMessage(h, UDM_SETACCEL, 1, (LPARAM)&accel2);
SendMessage(h, UDM_SETPOS, 0, r.bottom - r.top);
h = GetDlgItem(hdlg, IDC_CHECK_LOCK_SIZE);
SendMessage(h, BM_SETCHECK, !!(vid_resize & 2), 0);
break;
case WM_COMMAND:
switch (LOWORD(wParam)) {
case IDOK:
lptsTemp = (LPTSTR) malloc(512 * sizeof(WCHAR));
stransi = (char *)malloc(512);
h = GetDlgItem(hdlg, IDC_EDIT_WIDTH);
SendMessage(h, WM_GETTEXT, 255, (LPARAM) lptsTemp);
wcstombs(stransi, lptsTemp, 512);
sscanf(stransi, "%u", &temp_x);
fixed_size_x = temp_x;
h = GetDlgItem(hdlg, IDC_EDIT_HEIGHT);
SendMessage(h, WM_GETTEXT, 255, (LPARAM) lptsTemp);
wcstombs(stransi, lptsTemp, 512);
sscanf(stransi, "%u", &temp_y);
fixed_size_y = temp_y;
h = GetDlgItem(hdlg, IDC_CHECK_LOCK_SIZE);
lock = SendMessage(h, BM_GETCHECK, 0, 0);
if (lock) {
vid_resize = 2;
window_remember = 0;
} else {
vid_resize = 1;
window_remember = 1;
}
hmenu = GetMenu(hwndMain);
CheckMenuItem(hmenu, IDM_VID_REMEMBER, (window_remember == 1) ? MF_CHECKED : MF_UNCHECKED);
CheckMenuItem(hmenu, IDM_VID_RESIZE, (vid_resize == 1) ? MF_CHECKED : MF_UNCHECKED);
EnableMenuItem(hmenu, IDM_VID_RESIZE, (vid_resize & 2) ? MF_GRAYED : MF_ENABLED);
if (vid_resize == 1)
SetWindowLongPtr(hwndMain, GWL_STYLE, (WS_OVERLAPPEDWINDOW) | WS_VISIBLE);
else
SetWindowLongPtr(hwndMain, GWL_STYLE, (WS_OVERLAPPEDWINDOW & ~WS_SIZEBOX & ~WS_MAXIMIZEBOX) | WS_VISIBLE);
/* scale the screen base on DPI */
if (dpi_scale) {
dpi = win_get_dpi(hwndMain);
temp_x = MulDiv(temp_x, dpi, 96);
temp_y = MulDiv(temp_y, dpi, 96);
} else {
temp_x = temp_x;
temp_y = temp_y;
}
ResizeWindowByClientArea(hwndMain, temp_x, temp_y + sbar_height);
if (vid_resize) {
CheckMenuItem(hmenu, IDM_VID_SCALE_1X + scale, MF_UNCHECKED);
CheckMenuItem(hmenu, IDM_VID_SCALE_2X, MF_CHECKED);
scale = 1;
}
EnableMenuItem(hmenu, IDM_VID_SCALE_1X, vid_resize ? MF_GRAYED : MF_ENABLED);
EnableMenuItem(hmenu, IDM_VID_SCALE_2X, vid_resize ? MF_GRAYED : MF_ENABLED);
EnableMenuItem(hmenu, IDM_VID_SCALE_3X, vid_resize ? MF_GRAYED : MF_ENABLED);
EnableMenuItem(hmenu, IDM_VID_SCALE_4X, vid_resize ? MF_GRAYED : MF_ENABLED);
scrnsz_x = fixed_size_x;
scrnsz_y = fixed_size_y;
doresize = 1;
GetWindowRect(hwndMain, &r);
if (mouse_capture)
ClipCursor(&r);
if (!(vid_resize & 2) && window_remember) {
window_x = r.left;
window_y = r.top;
window_w = r.right - r.left;
window_h = r.bottom - r.top;
}
config_save();
free(stransi);
free(lptsTemp);
EndDialog(hdlg, 0);
return TRUE;
case IDCANCEL:
EndDialog(hdlg, 0);
return TRUE;
default:
break;
}
break;
}
return(FALSE);
}
void
SpecifyDimensionsDialogCreate(HWND hwnd)
{
DialogBox(hinstance, (LPCTSTR)DLG_SPECIFY_DIM, hwnd, SpecifyDimensionsDialogProcedure);
}

58
src/win/win_stbar.c
View File

@@ -434,7 +434,8 @@ ui_sb_set_ready(int ready)
void
ui_sb_update_panes(void)
{
int i, id, hdint;
int i, id;
int mfm_int, xta_int, esdi_int, ide_int, scsi_int;
int edge = 0;
int c_mfm, c_esdi, c_xta;
int c_ide, c_scsi;
@@ -448,7 +449,12 @@ ui_sb_update_panes(void)
sb_ready = 0;
}
hdint = (machines[machine].flags & MACHINE_HDC) ? 1 : 0;
mfm_int = (machines[machine].flags & MACHINE_MFM) ? 1 : 0;
xta_int = (machines[machine].flags & MACHINE_XTA) ? 1 : 0;
esdi_int = (machines[machine].flags & MACHINE_ESDI) ? 1 : 0;
ide_int = (machines[machine].flags & MACHINE_IDE_QUAD) ? 1 : 0;
scsi_int = (machines[machine].flags & MACHINE_SCSI_DUAL) ? 1 : 0;
c_mfm = hdd_count(HDD_BUS_MFM);
c_esdi = hdd_count(HDD_BUS_ESDI);
c_xta = hdd_count(HDD_BUS_XTA);
@@ -489,11 +495,11 @@ ui_sb_update_panes(void)
for (i=0; i<CDROM_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3)))
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
if ((cdrom[i].bus_type == CDROM_BUS_SCSI) &&
(scsi_card_current == 0))
!scsi_int && (scsi_card_current == 0))
continue;
if (cdrom[i].bus_type != 0)
sb_parts++;
@@ -501,40 +507,40 @@ ui_sb_update_panes(void)
for (i=0; i<ZIP_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3)))
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
if ((zip_drives[i].bus_type == ZIP_BUS_SCSI) &&
(scsi_card_current == 0))
!scsi_int && (scsi_card_current == 0))
continue;
if (zip_drives[i].bus_type != 0)
sb_parts++;
}
for (i=0; i<MO_NUM; i++) {
for (i=0; i<MO_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3)))
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
if ((mo_drives[i].bus_type == MO_BUS_SCSI) &&
(scsi_card_current == 0))
!scsi_int && (scsi_card_current == 0))
continue;
if (mo_drives[i].bus_type != 0)
sb_parts++;
}
if (c_mfm && (hdint || !memcmp(hdc_name, "st506", 5))) {
if (c_mfm && (mfm_int || !memcmp(hdc_name, "st506", 5))) {
/* MFM drives, and MFM or Internal controller. */
sb_parts++;
}
if (c_esdi && (hdint || !memcmp(hdc_name, "esdi", 4))) {
if (c_esdi && (esdi_int || !memcmp(hdc_name, "esdi", 4))) {
/* ESDI drives, and ESDI or Internal controller. */
sb_parts++;
}
if (c_xta && (hdint || !memcmp(hdc_name, "xta", 3)))
if (c_xta && (xta_int || !memcmp(hdc_name, "xta", 3)))
sb_parts++;
if (c_ide && (hdint || !memcmp(hdc_name, "xtide", 5) || !memcmp(hdc_name, "ide", 3)))
if (c_ide && (ide_int || !memcmp(hdc_name, "xtide", 5) || !memcmp(hdc_name, "ide", 3)))
sb_parts++;
if (c_scsi && (scsi_card_current != 0))
if (c_scsi && (scsi_int || (scsi_card_current != 0)))
sb_parts++;
if (do_net)
sb_parts++;
@@ -562,10 +568,10 @@ ui_sb_update_panes(void)
for (i=0; i<CDROM_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((cdrom[i].bus_type == CDROM_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3))) {
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
}
if ((cdrom[i].bus_type == CDROM_BUS_SCSI) && (scsi_card_current == 0))
if ((cdrom[i].bus_type == CDROM_BUS_SCSI) &&
!scsi_int && (scsi_card_current == 0))
continue;
if (cdrom[i].bus_type != 0) {
edge += icon_width;
@@ -578,9 +584,10 @@ ui_sb_update_panes(void)
for (i=0; i<ZIP_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((zip_drives[i].bus_type == ZIP_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3)))
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
if ((zip_drives[i].bus_type == ZIP_BUS_SCSI) && (scsi_card_current == 0))
if ((zip_drives[i].bus_type == ZIP_BUS_SCSI) &&
!scsi_int && (scsi_card_current == 0))
continue;
if (zip_drives[i].bus_type != 0) {
edge += icon_width;
@@ -593,9 +600,10 @@ ui_sb_update_panes(void)
for (i=0; i<MO_NUM; i++) {
/* Could be Internal or External IDE.. */
if ((mo_drives[i].bus_type == MO_BUS_ATAPI) &&
!(hdint || !memcmp(hdc_name, "ide", 3)))
!ide_int && memcmp(hdc_name, "ide", 3))
continue;
if ((mo_drives[i].bus_type == MO_BUS_SCSI) && (scsi_card_current == 0))
if ((mo_drives[i].bus_type == MO_BUS_SCSI) &&
!scsi_int && (scsi_card_current == 0))
continue;
if (mo_drives[i].bus_type != 0) {
edge += icon_width;
@@ -605,28 +613,28 @@ ui_sb_update_panes(void)
sb_parts++;
}
}
if (c_mfm && (hdint || !memcmp(hdc_name, "st506", 5))) {
if (c_mfm && (mfm_int || !memcmp(hdc_name, "st506", 5))) {
edge += icon_width;
iStatusWidths[sb_parts] = edge;
sb_part_meanings[sb_parts] = SB_HDD | HDD_BUS_MFM;
sb_map[SB_HDD | HDD_BUS_MFM] = sb_parts;
sb_parts++;
}
if (c_esdi && (hdint || !memcmp(hdc_name, "esdi", 4))) {
if (c_esdi && (esdi_int || !memcmp(hdc_name, "esdi", 4))) {
edge += icon_width;
iStatusWidths[sb_parts] = edge;
sb_part_meanings[sb_parts] = SB_HDD | HDD_BUS_ESDI;
sb_map[SB_HDD | HDD_BUS_ESDI] = sb_parts;
sb_parts++;
}
if (c_xta && (hdint || !memcmp(hdc_name, "xta", 3))) {
if (c_xta && (xta_int || !memcmp(hdc_name, "xta", 3))) {
edge += icon_width;
iStatusWidths[sb_parts] = edge;
sb_part_meanings[sb_parts] = SB_HDD | HDD_BUS_XTA;
sb_map[SB_HDD | HDD_BUS_XTA] = sb_parts;
sb_parts++;
}
if (c_ide && (hdint || !memcmp(hdc_name, "xtide", 5) || !memcmp(hdc_name, "ide", 3))) {
if (c_ide && (ide_int || !memcmp(hdc_name, "xtide", 5) || !memcmp(hdc_name, "ide", 3))) {
edge += icon_width;
iStatusWidths[sb_parts] = edge;
sb_part_meanings[sb_parts] = SB_HDD | HDD_BUS_IDE;

92
src/win/win_ui.c
View File

@@ -61,11 +61,12 @@ HWND hwndMain, /* application main window */
HMENU menuMain; /* application main menu */
HICON hIcon[256]; /* icon data loaded from resources */
RECT oldclip; /* mouse rect */
int sbar_height = 23; /* statusbar height */
int sbar_height = 23; /* statusbar height */
int minimized = 0;
int infocus = 1;
int infocus = 1, button_down = 0;
int rctrl_is_lalt = 0;
int user_resize = 0;
int fixed_size_x = 0, fixed_size_y = 0;
extern char openfilestring[512];
extern WCHAR wopenfilestring[512];
@@ -125,7 +126,7 @@ int win_get_system_metrics(int index, int dpi) {
void
ResizeWindowByClientArea(HWND hwnd, int width, int height)
{
if (vid_resize || padded_frame) {
if ((vid_resize == 1) || padded_frame) {
int padding = win_get_system_metrics(SM_CXPADDEDBORDER, dpi);
width += (win_get_system_metrics(SM_CXFRAME, dpi) + padding) * 2;
height += (win_get_system_metrics(SM_CYFRAME, dpi) + padding) * 2;
@@ -279,13 +280,13 @@ ResetAllMenus(void)
CheckMenuItem(menuMain, IDM_VID_OVERSCAN, enable_overscan?MF_CHECKED:MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_INVERT, invert_display ? MF_CHECKED : MF_UNCHECKED);
if (vid_resize)
if (vid_resize == 1)
CheckMenuItem(menuMain, IDM_VID_RESIZE, MF_CHECKED);
CheckMenuItem(menuMain, IDM_VID_SDL_SW+vid_api, MF_CHECKED);
CheckMenuItem(menuMain, IDM_VID_FS_FULL+video_fullscreen_scale, MF_CHECKED);
CheckMenuItem(menuMain, IDM_VID_REMEMBER, window_remember?MF_CHECKED:MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_SCALE_1X+scale, MF_CHECKED);
CheckMenuItem(menuMain, IDM_VID_HIDPI, dpi_scale?MF_CHECKED:MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_HIDPI, dpi_scale?MF_CHECKED:MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_CGACON, vid_cga_contrast?MF_CHECKED:MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_GRAYCT_601+video_graytype, MF_CHECKED);
@@ -300,6 +301,20 @@ ResetAllMenus(void)
#ifdef MTR_ENABLED
EnableMenuItem(menuMain, IDM_ACTION_END_TRACE, MF_DISABLED);
#endif
if (vid_resize) {
if (vid_resize >= 2) {
CheckMenuItem(menuMain, IDM_VID_RESIZE, MF_UNCHECKED);
EnableMenuItem(menuMain, IDM_VID_RESIZE, MF_GRAYED);
}
CheckMenuItem(menuMain, IDM_VID_SCALE_1X + scale, MF_UNCHECKED);
CheckMenuItem(menuMain, IDM_VID_SCALE_2X, MF_CHECKED);
EnableMenuItem(menuMain, IDM_VID_SCALE_1X, MF_GRAYED);
EnableMenuItem(menuMain, IDM_VID_SCALE_2X, MF_GRAYED);
EnableMenuItem(menuMain, IDM_VID_SCALE_3X, MF_GRAYED);
EnableMenuItem(menuMain, IDM_VID_SCALE_4X, MF_GRAYED);
}
}
@@ -456,10 +471,14 @@ input_proc(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
#endif
break;
case WM_LBUTTONDOWN:
button_down |= 1;
break;
case WM_LBUTTONUP:
pclog("video_fullscreen = %i\n", video_fullscreen);
if (! video_fullscreen)
if ((button_down & 1) && !video_fullscreen)
plat_mouse_capture(1);
button_down &= ~1;
break;
case WM_MBUTTONUP:
@@ -511,12 +530,12 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
break;
#ifdef MTR_ENABLED
case IDM_ACTION_BEGIN_TRACE:
case IDM_ACTION_END_TRACE:
case IDM_ACTION_TRACE:
tracing_on = !tracing_on;
handle_trace(hmenu, tracing_on);
break;
case IDM_ACTION_BEGIN_TRACE:
case IDM_ACTION_END_TRACE:
case IDM_ACTION_TRACE:
tracing_on = !tracing_on;
handle_trace(hmenu, tracing_on);
break;
#endif
case IDM_ACTION_HRESET:
@@ -595,10 +614,10 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
break;
case IDM_VID_RESIZE:
vid_resize = !vid_resize;
CheckMenuItem(hmenu, IDM_VID_RESIZE, (vid_resize)? MF_CHECKED : MF_UNCHECKED);
vid_resize ^= 1;
CheckMenuItem(hmenu, IDM_VID_RESIZE, (vid_resize & 1) ? MF_CHECKED : MF_UNCHECKED);
if (vid_resize)
if (vid_resize == 1)
SetWindowLongPtr(hwnd, GWL_STYLE, (WS_OVERLAPPEDWINDOW) | WS_VISIBLE);
else
SetWindowLongPtr(hwnd, GWL_STYLE, (WS_OVERLAPPEDWINDOW & ~WS_SIZEBOX & ~WS_MAXIMIZEBOX) | WS_VISIBLE);
@@ -638,7 +657,7 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
window_remember = !window_remember;
CheckMenuItem(hmenu, IDM_VID_REMEMBER, window_remember ? MF_CHECKED : MF_UNCHECKED);
GetWindowRect(hwnd, &rect);
if (window_remember) {
if (!(vid_resize & 2) && window_remember) {
window_x = rect.left;
window_y = rect.top;
window_w = rect.right - rect.left;
@@ -696,6 +715,10 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
config_save();
break;
case IDM_VID_SPECIFY_DIM:
SpecifyDimensionsDialogCreate(hwnd);
break;
case IDM_VID_FORCE43:
video_toggle_option(hmenu, &force_43, IDM_VID_FORCE43);
video_force_resize_set(1);
@@ -829,9 +852,19 @@ MainWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
GetWindowRect(hwndSBAR, &rect);
sbar_height = rect.bottom - rect.top;
rect_p = (RECT*)lParam;
if (vid_resize)
if (vid_resize == 1)
MoveWindow(hwnd, rect_p->left, rect_p->top, rect_p->right - rect_p->left, rect_p->bottom - rect_p->top, TRUE);
else if (!user_resize)
else if (vid_resize >= 2) {
temp_x = fixed_size_x;
temp_y = fixed_size_y;
if (dpi_scale) {
temp_x = MulDiv(temp_x, dpi, 96);
temp_y = MulDiv(temp_y, dpi, 96);
}
/* Main Window. */
ResizeWindowByClientArea(hwndMain, temp_x, temp_y + sbar_height);
} else if (!user_resize)
doresize = 1;
break;
@@ -1063,9 +1096,14 @@ static LRESULT CALLBACK
SubWindowProcedure(HWND hwnd, UINT message, WPARAM wParam, LPARAM lParam)
{
switch (message) {
case WM_LBUTTONDOWN:
button_down |= 2;
break;
case WM_LBUTTONUP:
if (! video_fullscreen)
if ((button_down & 2) && !video_fullscreen)
plat_mouse_capture(1);
button_down &= ~2;
break;
case WM_MBUTTONUP:
@@ -1230,10 +1268,10 @@ ui_init(int nCmdShow)
sbar_height = sbar_rect.bottom - sbar_rect.top;
/* Set up main window for resizing if configured. */
if (vid_resize)
if (vid_resize == 1)
SetWindowLongPtr(hwnd, GWL_STYLE,
(WS_OVERLAPPEDWINDOW));
else
else
SetWindowLongPtr(hwnd, GWL_STYLE,
(WS_OVERLAPPEDWINDOW&~WS_SIZEBOX&~WS_THICKFRAME&~WS_MAXIMIZEBOX));
@@ -1243,10 +1281,15 @@ ui_init(int nCmdShow)
/* Initiate a resize in order to properly arrange all controls.
Move to the last-saved position if needed. */
if (window_remember)
if ((vid_resize < 2) && window_remember)
MoveWindow(hwnd, window_x, window_y, window_w, window_h, TRUE);
else
else {
if (vid_resize >= 2) {
scrnsz_x = fixed_size_x;
scrnsz_y = fixed_size_y;
}
ResizeWindowByClientArea(hwndMain, scrnsz_x, scrnsz_y + sbar_height);
}
/* Reset all menus to their defaults. */
ResetAllMenus();
@@ -1466,7 +1509,6 @@ plat_resize(int x, int y)
{
/* First, see if we should resize the UI window. */
if (!vid_resize) {
/* scale the screen base on DPI */
if (dpi_scale) {
x = MulDiv(x, dpi, 96);