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hash lookup fixes

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This commit is contained in:
starfrost013
2025-02-21 22:57:04 +00:00
parent a0d313f37d
commit 8cf57fdc14
6 changed files with 46 additions and 33 deletions
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26
doc/nvidia_notes/nv3 driver init status_2025-02-10.txt
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@@ -46,7 +46,7 @@ DrvEnablePDEV SUCCESS 23:28 09/02/2025
EngDeviceIoControl IOCTL 0x232044 (CHECK mini) SUCCESS (eax=0)
DrvCompletePDEV SUCCESS 23:52 09/02/2025
DrvEnableSurface
bEnableHardware call
bEnableHardware call SUCCESS 22:36 13/02/2025
EngCreateSemaphore call #1 csCrtc SUCCESS 00:55 10/02/2025
EngCreateSemaphore call #2 csFifo SUCCESS 00:57 10/02/2025
EngDeviceIoControl IOCTL 0x230460 SUCCESS 00:57 10/02/2025
@@ -54,8 +54,8 @@ DrvEnableSurface
NvAllocRoot SUCCESS 01:03 10/02/2025
NvAllocDevice SUCCESS 01:04 10/02/2025
NV3/NV4 architecture check SUCCESS 01:14 10/02/2025
bAssertModeHardware call (bEnable=1) FAILURE - HANG/LOOP
EngDeviceIoControl IOCTL 0x23040C] FAILURE 01:27 10/02/2025
bAssertModeHardware call (bEnable=1) SUCCESS Passing starting with build at 02:23 10/02/2025
EngDeviceIoControl IOCTL 0x23040C] SUCCESS Passing starting with build at 02:23 10/02/2025
nv3_mini NVStartIO ioctlcode=0x23040C
NVSetMode
NV3SetMode SUCCESS 01:53 10/02/2025
@@ -65,19 +65,19 @@ DrvEnableSurface
UpdateArbitrationSettings SUCCESS 01:52 10/02/2025
RmLoadState SUCCESS 01:53 10/02/2025
NV3EnableCursor SUCCESS 01:54 10/02/2025
NV3WaitUntilFinished SUCCESS Passing 02:23 10/02/2025
NV3WaitUntilFinished SUCCESS 02:23 10/02/2025
EngDeviceIoControl IOCTL 0x230408 SUCCESS 02:26 10/02/2025
EngDeviceIoControl IOCTL 0x232024 SUCCESS 02:26 10/02/2025
NvAllocHardware SUCCESS 02:29 10/02/2025
bCreateStdPatches(?) FAILURE 02:31 10/02/2025
CHECK - NV4
vDestroyStdPatches(?)
NV3_WaitForOneVerticalRefresh
EngDeviceIoControl IOCTL 0x230410
bCreateStdPatches(?) SUCCESS (EAX=1!!!) 22:24 13/02/2025
CHECK - NV4 N/A
vDestroyStdPatches(?) N/A
NV3_WaitForOneVerticalRefresh SUCCESS
EngDeviceIoControl IOCTL 0x230410 SUCCESS
SET UP CORRECT FUNCTION POINTERS
Indirect call (call dword [edi]) to NV3_WaitWhileGraphicsEngineBusy HANG 22:14 16/02/2025
_heap_init call
bEnableOffscreenHeap call
bEnablePointer call
@@ -87,10 +87,4 @@ DrvEnableSurface
EngCreateBitmap call
EngAssociateBitmap call
DrvDisableSurface: ONLY IN THE CASE OF FAILURE

2
src/include/86box/nv/vid_nv3.h
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@@ -1446,6 +1446,8 @@ void nv3_pgraph_init();
uint32_t nv3_pgraph_read(uint32_t address);
void nv3_pgraph_write(uint32_t address, uint32_t value);
void nv3_pgraph_vblank_start(svga_t* svga);
void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t subchannel, uint8_t class_id, uint32_t context);
// NV3 PFIFO
void nv3_pfifo_init();

12
src/video/nv/nv3/subsystems/nv3_pfifo.c
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@@ -680,14 +680,14 @@ void nv3_pfifo_cache1_pull()
if (nv3->pfifo.cache1_settings.put_address == nv3->pfifo.cache1_settings.get_address)
return;
uint32_t get_address = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably
uint32_t get_index = nv3->pfifo.cache1_settings.get_address >> 2; // 32 bit aligned probably
uint8_t current_channel = nv3->pfifo.cache1_settings.channel;
uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_address].subchannel;
uint32_t current_name = nv3->pfifo.cache1_entries[get_address].data;
uint16_t current_method = nv3->pfifo.cache1_entries[get_address].method;
uint8_t current_subchannel = nv3->pfifo.cache1_entries[get_index].subchannel;
uint32_t current_name = nv3->pfifo.cache1_entries[get_index].data;
uint16_t current_method = nv3->pfifo.cache1_entries[get_index].method;
// i.e. there is no method in cache1, so we have to find the object.
// NV_ROOT
if (!current_method)
{
if (!nv3_ramin_find_object(current_name, 0, current_channel, current_subchannel))
@@ -707,7 +707,7 @@ void nv3_pfifo_cache1_pull()
}
// start by incrementing
uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_address) + 1;
uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1;
if (nv3->nvbase.gpu_revision >= NV3_BOOT_REG_REV_C00) // RIVA 128ZX#
next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1);

4
src/video/nv/nv3/subsystems/nv3_pgraph.c
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@@ -449,7 +449,7 @@ void nv3_pgraph_write(uint32_t address, uint32_t value)
// Addresses should be aligned to 4 bytes.
uint32_t entry = (address - NV3_PGRAPH_CONTEXT_CACHE(0));
nv_log("PGRAPH Context Cache Write (Entry=%04x Value=%04x)\n", entry, value);
nv_log("PGRAPH Context Cache Write (Entry=%04x Value=0x%08x)\n", entry, value);
nv3->pgraph.context_cache[entry] = value;
}
}
@@ -477,7 +477,7 @@ void nv3_pgraph_submit(uint8_t name, uint16_t method, uint8_t channel, uint8_t s
{
// This method is how we figure out which methods exist.
case NV3_ROOT_HI_IM_OBJECT_MCOBJECTYFACE:
nv_log("Hi, I'm an NV []");
nv_log("Hi, I'm an NVidia object :)\n");
break;
}
}

31
src/video/nv/nv3/subsystems/nv3_pramin.c
View File

@@ -352,13 +352,32 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u
// TODO: WRITE IT!!!
// Set the number of entries to search based on the ramht size (2*(size+1))
// Not a switch statement in case newer gpus have larger ramins
uint32_t bucket_entries = 2 * (((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_SIZE) & 0x03) + 1);
uint32_t bucket_entries = 2;
switch (nv3->pfifo.ramht_config)
{
case NV3_PFIFO_CONFIG_RAMHT_SIZE_4K:
// stays as is
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_8K:
bucket_entries = 4;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_16K:
bucket_entries = 8;
break;
case NV3_PFIFO_CONFIG_RAMHT_SIZE_32K:
bucket_entries = 16;
break;
}
// Calculate the address in the hashtable
uint32_t ramht_base = ((nv3->pfifo.ramht_config >> NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS) & 0x0F) << NV3_PFIFO_CONFIG_RAMHT_BASE_ADDRESS;
uint32_t ramht_cur_address = ramht_base;
uint32_t ramht_cur_address = ramht_base + (nv3_ramht_hash(name, channel)) * bucket_entries * 8;
nv_log("Beginning search for graphics object at RAMHT base=0x%04x, Cache%d, channel=%d, subchannel=%d)", name, cache_num, channel, subchannel);
nv_log("Beginning search for graphics object at RAMHT base=0x%04x, name=0x%08x, Cache%d, channel=%d.%d)\n",
ramht_cur_address, name, cache_num, channel, subchannel);
bool found_object = false;
@@ -385,19 +404,17 @@ bool nv3_ramin_find_object(uint32_t name, uint32_t cache_num, uint8_t channel, u
if (!found_object)
{
nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING;
if (!cache_num)
{
nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE0_ERROR_PENDING;
nv3->pfifo.cache0_settings.puller_control |= NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_FAILURE;
//It turns itself off on failure, the drivers turn it back on
nv3->pfifo.cache0_settings.puller_control &= ~NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED;
}
else
{
nv3->pfifo.debug_0 |= NV3_PFIFO_CACHE1_ERROR_PENDING;
nv3->pfifo.cache1_settings.puller_control |= NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_FAILURE;
//It turns itself off on failure, the drivers turn it back on
nv3->pfifo.cache1_settings.puller_control &= ~NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED;
}

4
src/video/nv/nv3/subsystems/nv3_pramin_ramht.c
View File

@@ -35,11 +35,11 @@ It is used to get the offset within RAMHT of a graphics object.
uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel)
{
// convert the name to an array of bytes
uint8_t* hash_bytes = (uint8_t*)name;
uint8_t* hash_bytes = (uint8_t*)&name;
// is this the right endianness?
uint32_t hash = (hash_bytes[0] ^ hash_bytes[1] ^ hash_bytes[2] ^ hash_bytes[3] ^ (uint8_t)channel);
nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, name, channel);
nv_log("Generated RAMHT hash 0x%04x (RAMHT slot=0x%04x (from name 0x%08x for DMA channel 0x%04x)\n)\n", hash, (hash/8), name, channel);
return hash;
}