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prepare for implementation of multithreaded renderer and add some of the simpler pfifo registers. e.g. debug0, which the driver writes to.

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starfrost013
2025-01-23 23:55:41 +00:00
parent 07dc73bcf8
commit 94af12da43
6 changed files with 183 additions and 24 deletions
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2
doc/nvidia_notes/nv3_object_classes_driver.txt
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@@ -47,7 +47,7 @@ object class 64/40h = video scaler
object class 65/41h = video color key (as opposed to image)
object class 66/42h = capture video to memory
object class 67/43h = Solid ROP5
object class 68/44h = zeta buffer (something to do with how the gpu internally renders 3d stuff) from CPU(?)
object class 68/44h = zeta buffer (combined z and stencil buffer) from CPU(?)
object class 69/45h = zeta buffer in VRAM
object class 70/46h = zeta buffer patchcord
object class 71/47h = render solid point into zeta buffer (Also rectangle0

2
src/include/86box/nv/classes/vid_nv3_classes.h
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@@ -660,7 +660,7 @@ typedef struct nv3_object_class_015
0x?? (drivers)
Also 0x57 in context IDs.
Direct3D 5.0 accelerated triangle with zeta buffer (Not the same as a Zbuffer...)
Direct3D 5.0 accelerated triangle with zeta buffer (combined z buffer and stencil buffer)
This is the final boss of this GPU. True horror stands below.
*/

50
src/include/86box/nv/vid_nv3.h
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@@ -200,6 +200,10 @@ extern const device_config_t nv3_config[];
#define NV3_PBUS_END 0x1FFF
#define NV3_PFIFO_START 0x2000 // FIFO for DMA Object Submission (uses hashtable to store the objects)
#define NV3_PFIFO_DEBUG_0 0x2080 // PFIFO Debug Register
#define NV3_PFIFO_CACHE0_ERROR_PENDING 0
#define NV3_PFIFO_CACHE1_ERROR_PENDING 1
#define NV3_PFIFO_INTR 0x2100 // FIFO - Interrupt Status
#define NV3_PFIFO_INTR_EN 0x2140 // FIFO - Interrupt Enable
@@ -247,7 +251,12 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE0_STATUS_LOW_MARK 4 // 1 if ramro is empty
#define NV3_PFIFO_CACHE0_STATUS_HIGH_MARK 8
#define NV3_PFIFO_CACHE0_PUT_ADDRESS 2 // 1 bit
#define NV3_PFIFO_CACHE0_PULLER 0x3040
#define NV3_PFIFO_CACHE0_PULLER_CONTROL 0x3040
#define NV3_PFIFO_CACHE0_PULLER_CONTROL_ENABLED 0
#define NV3_PFIFO_CACHE0_PULLER_CONTROL_HASH_SUCCESS 4
#define NV3_PFIFO_CACHE0_PULLER_CONTROL_DEVICE 8
#define NV3_PFIFO_CACHE0_PULLER_STATE1 0x3050
#define NV3_PFIFO_CACHE0_PULLER_STATE1_CTX_IS_CLEAN 4
#define NV3_PFIFO_CACHE0_GET 0x3070
#define NV3_PFIFO_CACHE0_GET_ADDRESS 2 // 1 bit
#define NV3_PFIFO_CACHE1_ACCESS 0x3200
@@ -267,11 +276,12 @@ extern const device_config_t nv3_config[];
#define NV3_PFIFO_CACHE1_DMA_TLB_TAG 0x3230
#define NV3_PFIFO_CACHE1_DMA_TLB_PTE 0x3234 // Base of pagetableor DMA
#define NV3_PFIFO_CACHE1_DMA_TLB_PT_BASE 0x3238 // Base of pagetable for DMA
#define NV3_PFIFO_CACHE1_PULLER_STATE0 0x3240
#define NV3_PFIFO_CACHE1_PULLER_STATE0_ENABLED 0
#define NV3_PFIFO_CACHE1_PULLER_STATE0_HASH_SUCCESS 4
#define NV3_PFIFO_CACHE1_PULLER_STATE0_DEVICE 8
#define NV3_PFIFO_CACHE1_PULLER_CONTEXT_IS_CLEAN 0x3250
#define NV3_PFIFO_CACHE1_PULLER_CONTROL 0x3240
#define NV3_PFIFO_CACHE1_PULLER_CONTROL_ENABLED 0
#define NV3_PFIFO_CACHE1_PULLER_CONTROL_HASH_SUCCESS 4
#define NV3_PFIFO_CACHE1_PULLER_CONTROL_DEVICE 8
#define NV3_PFIFO_CACHE1_PULLER_STATE1 0x3250
#define NV3_PFIFO_CACHE1_PULLER_STATE1_CTX_IS_CLEAN 4
#define NV3_PFIFO_CACHE1_GET 0x3270
#define NV3_PFIFO_CACHE1_GET_ADDRESS 2 // 6:2
#define NV3_PFIFO_END 0x3FFF
@@ -759,6 +769,26 @@ typedef struct nv3_pfifo_cache_s
{
uint8_t put_address; // Trigger a DMA into the value you put here.
uint8_t get_address; // Trigger a DMA from the value you put here into where you were going.
uint8_t channel_id;
uint32_t status;
uint32_t status_puller;
uint32_t control;
uint32_t context[8];
/* cache1 only
do we even need to emulate this?
*/
bool dma_enabled; // 0x3220 bit0
bool dma_is_busy; // 0x3220 bit4
uint32_t dma_length;
uint32_t dma_address;
uint8_t dma_target_node; // depends on card bus
uint8_t dma_tlb_tag;
uint8_t tlb_pte; // DMA Engine - Translation Lookaside Buffer
uint8_t tlb_pt_base; // DMA Engine - TLB Pagetable Base Addres
bool context_is_dirty;
/* TODO */
} nv3_pfifo_cache_t;
@@ -767,6 +797,7 @@ typedef struct nv3_pfifo_cache_entry_s
uint8_t subchannel_id : 3;
uint16_t method : 11; // method id depending on class (offset from entry channel start in ramin)
uint32_t data; // is this the context
} nv3_pfifo_cache_entry_t;
// Command submission to PGRAPH
@@ -774,14 +805,17 @@ typedef struct nv3_pfifo_s
{
uint32_t interrupt_status; // Interrupt status
uint32_t interrupt_enable; // Interrupt enable
uint32_t debug_0; // Cache Debug register
uint32_t ramht_config; // RAMHT config
uint32_t ramfc_config; // RAMFC config
uint32_t ramro_config; // RAMRO config
uint32_t cache_reassignment; // Enable automatic reassignment into CACHE0?
nv3_pfifo_cache_t cache0_settings;
nv3_pfifo_cache_t cache1_settings;
uint32_t cache0_status; // status of cache0
uint32_t cache1_status; // status of cache1
nv3_pfifo_cache_entry_t cache0_entries[1];
nv3_pfifo_cache_entry_t cache1_entries[NV3_PFIFO_CACHE1_SIZE_MAX]; // ONLY 32 USED ON REVISION A/B CARDS
} nv3_pfifo_t;
// create_object(uint32_t type) here

6
src/video/nv/nv3/nv3_core.c
View File

@@ -920,7 +920,7 @@ void* nv3_init(const device_t *info)
nv_log("NV3: initialising core\n");
// Figure out which vbios the user selected
const char* vbios_id = device_get_config_bios("VBIOS");
const char* vbios_id = device_get_config_bios("vbios");
const char* vbios_file = "";
// depends on the bus we are using
@@ -941,8 +941,8 @@ void* nv3_init(const device_t *info)
nv_log("NV3: Successfully loaded VBIOS %s located at %s\n", vbios_id, vbios_file);
// set the vram amount and gpu revision
uint32_t vram_amount = device_get_config_int("VRAM");
nv3->nvbase.gpu_revision = device_get_config_int("Chip Revision");
uint32_t vram_amount = device_get_config_int("vram_size");
nv3->nvbase.gpu_revision = device_get_config_int("chip_revision");
// set up the bus and start setting up SVGA core
if (nv3->nvbase.bus_generation == nv_bus_pci)

108
src/video/nv/nv3/nv3_core_config.c
View File

@@ -31,61 +31,105 @@ const device_config_t nv3_config[] =
{
// VBIOS type configuration
{
.name = "VBIOS",
.name = "vbios",
#ifndef RELEASE_BUILD
.description = "VBIOS",
#else
.description = "Model",
#endif
.type = CONFIG_BIOS,
.default_string = "NV3_VBIOS_ERAZOR_V15403",
.default_int = 0,
.bios =
{
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-09-30] ELSA VICTORY Erazor VBE 3.0 DDC2B DPMS Video BIOS Ver. 1.47.01 (ZZ/ A/00)", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.47.01", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_ERAZOR_V14700",
.files = {NV3_VBIOS_ERAZOR_V14700, ""}
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-02-06] ELSA VICTORY Erazor Ver. 1.54.03 [WD/VBE30/DDC2B/DPMS]", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.54.03", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_ERAZOR_V15403",
.files = {NV3_VBIOS_ERAZOR_V15403, ""}
},
{
.name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1,
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-05-04] ELSA VICTORY Erazor Ver. 1.55.00 [WD/VBE30/DDC2B/DPMS]", .files_no = 1,
#else
.name = "[RIVA 128] ELSA Victory Erazor v1.55.00", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_ERAZOR_V15500",
.files = {NV3_VBIOS_ERAZOR_V15500, ""}
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1998-01-14] Diamond Multimedia Systems, Inc. Viper V330 Version 1.62-CO", .files_no = 1,
#else
.name = "[RIVA 128] Diamond Viper V330", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_DIAMOND_V330_V162",
.files = {NV3_VBIOS_DIAMOND_V330_V162, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-09-06] ASUS AGP/3DP-V3000 BIOS 1.51B", .files_no = 1,
#else
.name = "[RIVA 128] ASUS AGP/3DP-V3000", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_ASUS_V3000_V151",
.files = {NV3_VBIOS_ASUS_V3000_V151, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3 - 1997-12-17] STB Velocity 128 (RIVA 128) Ver.1.82", .files_no = 1,
#else
.name = "[RIVA 128] STB Velocity 128", .files_no = 1,
#endif
.internal_name = "NV3_VBIOS_STB_V128_V182",
.files = {NV3_VBIOS_STB_V128_V182, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-09-15] Diamond Multimedia Viper V330 8M BIOS - Version 1.82B", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Diamond Multimedia Viper V330 8MB", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_DIAMOND_V330_V182B",
.files = {NV3T_VBIOS_DIAMOND_V330_V182B, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-08-04] ASUS AGP-V3000 ZXTV BIOS - V1.70D.03", .files_no = 1,
#else
.name = "[RIVA 128 ZX] ASUS AGP-V3000 ZXTV", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_ASUS_V170",
.files = {NV3T_VBIOS_ASUS_V170, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T - 1998-07-30] RIVA 128 ZX BIOS - V1.71B-N", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.71", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V171",
.files = {NV3T_VBIOS_REFERENCE_CEK_V171, ""},
},
{
#ifndef RELEASE_BUILD
.name = "[NV3T+SGRAM - 1998-08-15] RIVA 128 ZX BIOS - V1.72B", .files_no = 1,
#else
.name = "[RIVA 128 ZX] Nvidia Reference BIOS v1.72", .files_no = 1,
#endif
.internal_name = "NV3T_VBIOS_REFERENCE_CEK_V172",
.files = {NV3T_VBIOS_REFERENCE_CEK_V172, ""},
},
@@ -93,18 +137,19 @@ const device_config_t nv3_config[] =
},
// Memory configuration
{
.name = "VRAM",
.name = "vram_size",
.description = "VRAM Size",
.type = CONFIG_SELECTION,
.default_int = VRAM_SIZE_4MB,
.selection =
{
// This never existed officially but was planned. Same for 64-bit bus. Debug only
#ifndef RELEASE_BUILD
// This never existed officially but was planned. Debug only
{
.description = "2 MB (Never officially sold)",
.value = VRAM_SIZE_2MB,
},
#endif
{
.description = "4 MB",
.value = VRAM_SIZE_4MB,
@@ -117,26 +162,69 @@ const device_config_t nv3_config[] =
},
{
.name = "Chip Revision",
.name = "chip_revision",
.description = "Chip Revision",
.type = CONFIG_SELECTION,
.default_int = NV3_PCI_CFG_REVISION_B00,
.selection =
{
#ifndef RELEASE_BUILD
{
.description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997)",
.description = "NV3/STG3000 Engineering Sample / Stepping A0 (January 1997) with integrated PAUDIO sound card",
#else
.description = "RIVA 128 Prototype (Revision A)",
#endif
.value = NV3_PCI_CFG_REVISION_A00,
},
#ifndef RELEASE_BUILD
{
.description = "RIVA 128 (NV3) / Stepping B0 (August 1997)",
.description = "RIVA 128 / Stepping B0 (October 1997)",
#else
.description = "RIVA 128 (Revision B)",
#endif
.value = NV3_PCI_CFG_REVISION_B00,
},
#ifndef RELEASE_BUILD
{
.description = "RIVA 128 ZX (NV3T) / Stepping C0 (March 1998)",
.description = "NV3T - RIVA 128 ZX / Stepping C0 (March 1998)",
#else
.description = "RIVA 128 ZX (Revision C)",
#endif
.value = NV3_PCI_CFG_REVISION_C00,
},
}
},
// Multithreading configuration
{
.name = "pgraph_threads",
#ifndef RELEASE_BUILD
.description = "PFIFO/PGRAPH - Number of threads to split large object method execution into",
#else
.description = "Render threads",
#endif
.type = CONFIG_SELECTION,
.default_int = 1, // todo: change later
.selection =
{
{
.description = "1 thread (Only use if issues appear with more threads)",
.value = 1,
},
{
.description = "2 threads",
.value = 2,
},
{
.description = "4 threads",
.value = 4,
},
{
.description = "8 threads",
.value = 8,
},
},
},
{
.type = CONFIG_END
}

39
src/video/nv/nv3/subsystems/nv3_pfifo.c
View File

@@ -38,6 +38,11 @@ nv_register_t pfifo_registers[] = {
{ NV3_PFIFO_CONFIG_RAMFC, "PFIFO - RAMIN RAMFC Config", NULL, NULL },
{ NV3_PFIFO_CONFIG_RAMHT, "PFIFO - RAMIN RAMHT Config", NULL, NULL },
{ NV3_PFIFO_CONFIG_RAMRO, "PFIFO - RAMIN RAMRO Config", NULL, NULL },
{ NV3_PFIFO_CACHE0_PULLER_CONTROL, "PFIFO - Cache0 Puller State0", NULL, NULL},
{ NV3_PFIFO_CACHE0_PULLER_STATE1, "PFIFO - Cache0 Puller State1 (Is context clean?)", NULL, NULL},
{ NV3_PFIFO_CACHE1_PULLER_CONTROL, "PFIFO - Cache1 Puller State0", NULL, NULL},
{ NV3_PFIFO_CACHE1_PULLER_STATE1, "PFIFO - Cache1 Puller State1 (Is context clean?)", NULL, NULL},
{ NV3_PFIFO_CACHE0_STATUS, "PFIFO - Cache0 Status", NULL, NULL},
{ NV3_PFIFO_CACHE1_STATUS, "PFIFO - Cache1 Status", NULL, NULL},
{ NV3_PFIFO_CACHE0_GET, "PFIFO - Cache0 Get MUST TRIGGER DMA NOW TO OBTAIN ENTRY", NULL, NULL },
@@ -97,6 +102,10 @@ uint32_t nv3_pfifo_read(uint32_t address)
case NV3_PFIFO_INTR_EN:
ret = nv3->pfifo.interrupt_enable;
break;
// Debug
case NV3_PFIFO_DEBUG_0:
ret = nv3->pfifo.debug_0;
break;
// These may need to become functions.
case NV3_PFIFO_CONFIG_RAMFC:
ret = nv3->pfifo.ramfc_config;
@@ -110,6 +119,17 @@ uint32_t nv3_pfifo_read(uint32_t address)
case NV3_PFIFO_CACHE0_GET:
//wa
break;
// Reassignment
case NV3_PFIFO_CACHE_REASSIGNMENT:
ret = nv3->pfifo.cache_reassignment & 0x01; //1bit meaningful
break;
// Control
case NV3_PFIFO_CACHE0_PULLER_CONTROL:
ret = nv3->pfifo.cache0_settings.control & 0xFF; // 8bits meaningful
break;
case NV3_PFIFO_CACHE1_PULLER_CONTROL:
ret = nv3->pfifo.cache1_settings.control & 0xFF; // only 8bits are meaningful
break;
}
}
@@ -208,6 +228,21 @@ void nv3_pfifo_write(uint32_t address, uint32_t value)
nv_log("NV3: RAMRO Reconfiguration\n"
"Base Address in RAMIN: %d\n"
"Size: 0x%08x bytes\n", ((nv3->pfifo.ramro_config >> NV3_PFIFO_CONFIG_RAMRO_BASE_ADDRESS) & 0x7F) << 9, new_size_ramro);
break;
case NV3_PFIFO_DEBUG_0:
nv3->pfifo.debug_0 = value;
break;
// Reassignment
case NV3_PFIFO_CACHE_REASSIGNMENT:
nv3->pfifo.cache_reassignment = value & 0x01; //1bit meaningful
break;
// Control
case NV3_PFIFO_CACHE0_PULLER_CONTROL:
nv3->pfifo.cache0_settings.control = value; // 8bits meaningful
break;
case NV3_PFIFO_CACHE1_PULLER_CONTROL:
nv3->pfifo.cache1_settings.control = value; // 8bits meaningful
break;
}
}
@@ -236,8 +271,10 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val)
// shift right until we have our normla number again
while (mask)
{
val ^= mask;
// NT4 drivers v1.29
mask >>= 1;
val ^= mask;
}
return val;