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This commit is contained in:
starfrost013
2025-02-09 18:10:17 +00:00
parent fea8cd649a
commit c816f7560d
6 changed files with 103 additions and 7 deletions
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29
doc/nvidia_notes/NV3 DMA Engine.txt Normal file
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@@ -0,0 +1,29 @@
NV3 DMA Engine
(DirectDraw Driver)
Initially set CACHES, CACHE1_PULL0, CACHE1_PULL1, CACHE1_DMA0 to 1
Same for other areas
CACHE1_PUSH1 contains CHID
If it's different:
If RmFifoFlushContext failed: Do nothing
Set PULL0, PUSH0, Caches to 1, return false
If it's not:
DMA TLB PTE seems to be 1 for direct programming, maybe RM does it differently
Tag=FFFFFFFF
CACHE1_DMA1 - Number of bytes to send
CACHE1_DMA2 - Get offset
CACHE1_DMA3 - Bus address space (Area BAR0 mapped to? Or bar1?)
TO START:
To set up DMA for for Cache1 Puller: CACHE1_PULL0 -> 1, changes to 0 when done
To set up DMA Cache1 Push: CACHE1_PULL0 -> 1, changes to 0 when done
Set CACHES to 1
GO: Set DMA0 to 1

62
src/include/86box/nv/vid_nv3.h
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@@ -443,10 +443,72 @@ extern const device_config_t nv3_config[];
#define NV3_PME_END 0x200FFF
#define NV3_PGRAPH_START 0x400000 // Scene graph for 2d/3d rendering...the most important part
// PGRAPH Core
// For these debug registers, 0=Disabled, 1=Enabled
// Debug 0: General
#define NV3_PGRAPH_DEBUG_0 0x400080
#define NV3_PGRAPH_DEBUG_0_STATE_IN_RESET 0
#define NV3_PGRAPH_DEBUG_0_AP_PIPE_IN_RESET 1
#define NV3_PGRAPH_DEBUG_0_CACHE_IN_RESET 2
#define NV3_PGRAPH_DEBUG_0_3D_PIPE_IN_RESET 3
#define NV3_PGRAPH_DEBUG_0_BULK_READS 4
#define NV3_PGRAPH_DEBUG_0_TILING 16
#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_2D 20
#define NV3_PGRAPH_DEBUG_0_WRITE_ONLY_ROPS_3D 21
#define NV3_PGRAPH_DEBUG_0_DRAWDIR_AUT 24
#define NV3_PGRAPH_DEBUG_0_DRAWDIR_Y 25
#define NV3_PGRAPH_DEBUG_0_ALPHA_ABORT 28
// Debug 1: Registers
#define NV3_PGRAPH_DEBUG_1 0x400084
#define NV3_PGRAPH_DEBUG_1_VOLATILE_RESET_LAST 0
#define NV3_PGRAPH_DEBUG_1_DMA_ACTIVITY_CANCEL 4
#define NV3_PGRAPH_DEBUG_1_TURBO3D_2X 8
#define NV3_PGRAPH_DEBUG_1_TURBO3D_4X 9
#define NV3_PGRAPH_DEBUG_1_TRIANGLE_OPS 12
#define NV3_PGRAPH_DEBUG_1_TRIANGLE_CLIP_OPS 13
#define NV3_PGRAPH_DEBUG_1_INSTANCE 16
#define NV3_PGRAPH_DEBUG_1_CONTEXT 20
#define NV3_PGRAPH_DEBUG_1_CACHE_FLUSH 24
#define NV3_PGRAPH_DEBUG_1_ZCLAMP 28
// Debug 2: 3D Pipeline
#define NV3_PGRAPH_DEBUG_2 0x400088
#define NV3_PGRAPH_DEBUG_2_AVOID_READMODIFYWRITE_BLEND 0
#define NV3_PGRAPH_DEBUG_2_DPWR_FIFO 8
#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_3D 12
#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_3D 13
#define NV3_PGRAPH_DEBUG_2_FOG 14
#define NV3_PGRAPH_DEBUG_2_LIGHTING 15 // Not sure what this does, maybe hardware t&l was planned
#define NV3_PGRAPH_DEBUG_2_BILINEAR_FILTERING_2D 16
#define NV3_PGRAPH_DEBUG_2_ANISOTROPIC_FILTERING_2D 17
#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE 20 // coalesce reads/writes for d3d class 0x17
#define NV3_PGRAPH_DEBUG_2_D3D_COALESCE_POINT_ZETA 22 // class 0x18 coalesce
#define NV3_PGRAPH_DEBUG_2_PREFETCH 24
#define NV3_PGRAPH_DEBUG_2_VOLATILE_RESET 28
// Debug 3: Zeta & Alpha Buffer
#define NV3_PGRAPH_DEBUG_3 0x40008C
#define NV3_PGRAPH_DEBUG_3_CULLING 0
#define NV3_PGRAPH_DEBUG_3_FAST_DATA_D3D 4
#define NV3_PGRAPH_DEBUG_3_FAST_DATA_STRETCH 5
#define NV3_PGRAPH_DEBUG_3_ZFLUSH 7
#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_POINT_ZETA 8
#define NV3_PGRAPH_DEBUG_3_AUTOZFLUSH_D3D 9
#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_POINT_ZETA 10 // Slot conflict handling for POINT_ZETA (class 0x18)
#define NV3_PGRAPH_DEBUG_3_SLOT_CONFLICT_D3D 11 // Slot conflict handling for D3D5_TRI (class 0x17)
#define NV3_PGRAPH_DEBUG_3_EARLY_ZABORT 12
#define NV3_PGRAPH_DEBUG_3_TRIANGLE_END_FLUSH 13
#define NV3_PGRAPH_DEBUG_3_ZFIFO_NOOP 14 // ???
#define NV3_PGRAPH_DEBUG_3_DITHER 15
#define NV3_PGRAPH_DEBUG_3_FORCE_COLOR_BUFFER_READ 16
#define NV3_PGRAPH_DEBUG_3_FORCE_ZETA_BUFFER_READ 17
#define NV3_PGRAPH_DEBUG_3_DATA_CHECK 20
#define NV3_PGRAPH_DEBUG_3_DATA_CHECK_FAIL 21
#define NV3_PGRAPH_DEBUG_3_FORMAT_CHECK 22
#define NV3_PGRAPH_DEBUG_3_ALPHA_CHECK 24
#define NV3_PGRAPH_INTR_0 0x400100
#define NV3_PGRAPH_INTR_1 0x400104
#define NV3_PGRAPH_INTR_EN_0 0x400140 // Interrupt Control for PGRAPH #1

4
src/video/nv/nv3/nv3_core.c
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@@ -952,8 +952,10 @@ void* nv3_init(const device_t *info)
else
nv3->nvbase.log = log_open_cyclic("NV3");
#ifdef ENABLE_NV_LOG
// Allows nv_log to be used for multiple nvidia devices
nv_log_set_device(nv3->nvbase.log);
nv_log_set_device(nv3->nvbase.log);
#endif
nv_log("initialising core\n");
// Figure out which vbios the user selected

1
src/video/nv/nv3/subsystems/nv3_pgraph.c
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@@ -131,6 +131,7 @@ uint32_t nv3_pgraph_read(uint32_t address)
break;
case NV3_PGRAPH_DEBUG_3:
ret = nv3->pgraph.debug_3;
break;
//interrupt status and enable regs
case NV3_PGRAPH_INTR_0:
ret = nv3->pgraph.interrupt_status_0;

10
src/video/nv/nv3/subsystems/nv3_pmc.c
View File

@@ -232,10 +232,6 @@ void nv3_pmc_write(uint32_t address, uint32_t value)
// if the register actually exists...
if (reg)
{
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
// ... call its on-write function
if (reg->on_write)
@@ -266,5 +262,11 @@ void nv3_pmc_write(uint32_t address, uint32_t value)
break;
}
}
if (reg->friendly_name)
nv_log(": %s\n", reg->friendly_name);
else
nv_log("\n");
}
}

4
src/video/nv/nv3/subsystems/nv3_pme.c
View File

@@ -61,7 +61,7 @@ uint32_t nv3_pme_read(uint32_t address)
{
// Interrupt state:
// Bit 0 - Image Notifier
// Bit 4 - Vertical Blank Interfal Notifier
// Bit 4 - Vertical Blank Interval Notifier
// Bit 8 - Video Notifier
// Bit 12 - Audio Notifier
// Bit 16 - VMI Notifer
@@ -128,4 +128,4 @@ void nv3_pme_write(uint32_t address, uint32_t value)
}
}
}
}