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https://github.com/86Box/86Box.git
synced 2026-02-23 18:08:20 -07:00
Fix the timers...but they run slow.
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@@ -100,8 +100,10 @@ typedef struct nv_base_s
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uint32_t gpu_revision; // GPU Stepping
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double pixel_clock_period; // Period in seconds for pixel clock
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pc_timer_t pixel_clock_timer; // Pixel Clock Timer
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bool pixel_clock_enabled; // Pixel Clock Enabled - stupid crap used to prevent us enabling the timer multiple times
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double memory_clock_period; // Period in seconds for pixel clock
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pc_timer_t memory_clock_timer; // Memory Clock Timer
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bool memory_clock_enabled; // Memory Clock Enabled - stupid crap used to prevent us eanbling the timer multiple times
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} nv_base_t;
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#define NV_REG_LIST_END 0xD15EA5E
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@@ -29,7 +29,7 @@ extern const device_config_t nv3_config[];
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#define NV3_LFB_RAMIN_START 0xC00000 // RAMIN mapping start
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#define NV3_LFB_MAPPING_SIZE 0x400000 // Size of RAMIN
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#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 100 // The amount by which we have to ration out the memory clock because it's not fast enough...
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#define NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT 1000 // The amount by which we have to ration out the memory clock because it's not fast enough...
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// Multiply by this value to get the real clock speed.
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// various vbioses for testing
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@@ -346,6 +346,7 @@ void nv3_close(void* priv)
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{
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svga_close(&nv3->nvbase.svga);
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free(nv3);
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nv3 = NULL;
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}
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@@ -53,17 +53,20 @@ void nv3_pramdac_init()
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// This updates the 2D/3D engine PGRAPH
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void nv3_pramdac_pixel_clock_poll(void* priv)
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{
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timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period);
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nv3_t* nv3_poll = (nv3_t*)priv;
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timer_on_auto(&nv3_poll->nvbase.pixel_clock_timer, nv3_poll->nvbase.pixel_clock_period);
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}
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// Polls the memory clock.
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void nv3_pramdac_memory_clock_poll(void* poll)
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void nv3_pramdac_memory_clock_poll(void* priv)
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{
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nv3_t* nv3_poll = (nv3_t*)priv;
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// Let's hope qeeg was right here.
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nv3_ptimer_tick();
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timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period);
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timer_on_auto(&nv3_poll->nvbase.memory_clock_timer, nv3_poll->nvbase.memory_clock_period);
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}
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// Gets the vram clock register.
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@@ -110,15 +113,21 @@ void nv3_pramdac_set_vram_clock()
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// prevent division by 0
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if (nv3->pramdac.memory_clock_m == 0)
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nv3->pramdac.memory_clock_m == 1;
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else
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frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p);
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nv3->pramdac.memory_clock_m = 1;
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if (nv3->pramdac.memory_clock_n == 0)
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nv3->pramdac.memory_clock_n = 1;
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frequency = (frequency * nv3->pramdac.memory_clock_n) / (nv3->pramdac.memory_clock_m << nv3->pramdac.memory_clock_p);
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double time = (1000000.0 * NV3_86BOX_TIMER_SYSTEM_FIX_QUOTIENT) / (double)frequency; // needs to be a double for 86box
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nv_log("NV3: Memory clock = %.2f MHz\n", frequency / 1000000.0f);
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nv3->nvbase.memory_clock_period = time;
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timer_on_auto(&nv3->nvbase.memory_clock_timer, nv3->nvbase.memory_clock_period);
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//Breaks everything?
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//timer_set_delay_u64(&nv3->nvbase.memory_clock_timer, time * TIMER_USEC); // do we need to decrease
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}
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@@ -146,9 +155,12 @@ void nv3_pramdac_set_pixel_clock()
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// prevent division by 0
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if (nv3->pramdac.pixel_clock_m == 0)
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nv3->pramdac.pixel_clock_m == 1;
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else
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frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p);
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nv3->pramdac.pixel_clock_m = 1;
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if (nv3->pramdac.memory_clock_n == 0)
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nv3->pramdac.memory_clock_n = 1;
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frequency = (frequency * nv3->pramdac.pixel_clock_n) / (nv3->pramdac.pixel_clock_m << nv3->pramdac.pixel_clock_p);
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nv3->nvbase.svga.clock = cpuclock / frequency;
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@@ -157,6 +169,8 @@ void nv3_pramdac_set_pixel_clock()
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nv_log("NV3: Pixel clock = %.2f MHz\n", frequency / 1000000.0f);
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nv3->nvbase.pixel_clock_period = time;
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timer_on_auto(&nv3->nvbase.pixel_clock_timer, nv3->nvbase.pixel_clock_period);
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//Breaks everything?
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//timer_set_delay_u64(&nv3->nvbase.pixel_clock_timer, time * TIMER_USEC); // do we need to decrease
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}
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