mirror of
https://github.com/86Box/86Box.git
synced 2026-02-23 01:48:21 -07:00
Initial port of core nv3 stuff to nv4
This commit is contained in:
starfrost013
@@ -97,10 +97,19 @@ typedef enum nv_bus_generation_e
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} nv_bus_generation;
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// PCI configuration
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typedef struct nv_pci_config_s
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{
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uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability)
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bool vbios_enabled; // is the vbios enabled?
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uint8_t int_line;
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} nv_pci_config_t;
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// NV Base
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typedef struct nv_base_s
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{
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rom_t vbios; // NVIDIA/OEm VBIOS
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nv_pci_config_t pci_config; // PCI configuration
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// move to nv3_cio_t?
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svga_t svga; // SVGA core (separate to nv3) - Weitek licensed
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uint32_t vram_amount; // The amount of VRAM
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@@ -113,7 +122,7 @@ typedef struct nv_base_s
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mem_mapping_t mmio_mapping; // mmio mapping (32MB unified MMIO)
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mem_mapping_t framebuffer_mapping_mirror; // Mirror of LFB mapping
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mem_mapping_t ramin_mapping; // RAM INput area mapping
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mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored)
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mem_mapping_t ramin_mapping_mirror; // RAM INput area mapping (mirrored) - NV3 ONLY
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uint8_t pci_slot; // pci slot number
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uint8_t pci_irq_state; // current PCI irq state
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uint32_t bar0_mmio_base; // PCI Base Address Register 0 - MMIO Base
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@@ -131,6 +140,7 @@ typedef struct nv_base_s
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void* i2c; // I2C for monitor EDID
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void* ddc; // Display Data Channel for EDID
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bool agp_enabled; // AGP Enabled (for debugging)
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bool agp_sba_enabled; // AGP Sideband Addressing enabled
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//
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// DEBUG UI STUFF
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@@ -1013,15 +1013,7 @@ typedef struct nv3_pmc_s
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} nv3_pmc_t;
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typedef struct nv3_pci_config_s
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{
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uint8_t pci_regs[NV_PCI_NUM_CFG_REGS]; // The actual pci register values (not really used, just so they can be stored - they aren't very good for code readability)
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bool vbios_enabled; // is the vbios enabled?
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uint8_t int_line;
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} nv3_pci_config_t;
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// add enums for eac
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// add enums for eac
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// Chip configuration
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typedef struct nv3_straps_s
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{
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@@ -1546,7 +1538,6 @@ typedef struct nv3_s
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// Config
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nv3_straps_t straps; // OEM Configuration
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nv3_pci_config_t pci_config; // PCI Configuration
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// Subsystems
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nv3_pmc_t pmc; // Master Control
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@@ -20,11 +20,28 @@
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#include <stdint.h>
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#include <86Box/nv/vid_nv4_defines.h>
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// Structures
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typedef struct nv4_s
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//
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// PBUS/RMA
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//
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// Access the GPU from real-mode
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typedef struct nv4_pbus_rma_s
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{
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nv_base_t nvbase; // Base Nvidia structure
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} nv4_t;
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uint32_t addr; // Address to RMA to
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uint32_t data; // Data to send to MMIO
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uint8_t mode; // the current state of the rma shifting engin
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uint8_t rma_regs[NV4_RMA_NUM_REGS]; // The rma registers (saved)
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} nv4_pbus_rma_t;
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// Bus Configuration
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typedef struct nv4_pbus_s
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{
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uint32_t debug_0;
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uint32_t interrupt_status; // Interrupt status
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uint32_t interrupt_enable; // Interrupt enable
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nv4_pbus_rma_t rma;
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} nv4_pbus_t;
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//
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// PTIMER
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@@ -40,6 +57,27 @@ typedef struct nv4_ptimer_s
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uint32_t alarm; // The value of time when there should be an alarm
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} nv4_ptimer_t;
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//
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// PRAMDAC
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//
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typedef struct nv4_pramdac_s
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{
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uint32_t mclk;
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uint32_t vclk;
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uint32_t nvclk;
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uint32_t cursor_address;
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} nv4_pramdac_t;
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// Structures
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typedef struct nv4_s
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{
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nv_base_t nvbase; // Base Nvidia structure
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uint32_t straps; // Straps. See defines
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nv4_pbus_t pbus;
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nv4_ptimer_t ptimer;
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nv4_pramdac_t pramdac;
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} nv4_t;
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//
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// Globals
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@@ -58,4 +96,30 @@ void nv4_close(void* priv);
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void nv4_speed_changed(void *priv);
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void nv4_draw_cursor(svga_t* svga, int32_t drawline);
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void nv4_recalc_timings(svga_t* svga);
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void nv4_force_redraw(void* priv);
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void nv4_force_redraw(void* priv);
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// I/o
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uint8_t nv4_mmio_read8(uint32_t addr, void* priv);
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uint16_t nv4_mmio_read16(uint32_t addr, void* priv);
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uint32_t nv4_mmio_read32(uint32_t addr, void* priv);
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void nv4_mmio_write8(uint32_t addr, uint8_t val, void* priv);
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void nv4_mmio_write16(uint32_t addr, uint16_t val, void* priv);
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void nv4_mmio_write32(uint32_t addr, uint32_t val, void* priv);
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uint8_t nv4_dfb_read8(uint32_t addr, void* priv);
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uint16_t nv4_dfb_read16(uint32_t addr, void* priv);
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uint32_t nv4_dfb_read32(uint32_t addr, void* priv);
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void nv4_dfb_write8(uint32_t addr, uint8_t val, void* priv);
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void nv4_dfb_write16(uint32_t addr, uint16_t val, void* priv);
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void nv4_dfb_write32(uint32_t addr, uint32_t val, void* priv);
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uint8_t nv4_ramin_read8(uint32_t addr, void* priv);
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uint16_t nv4_ramin_read16(uint32_t addr, void* priv);
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uint32_t nv4_ramin_read32(uint32_t addr, void* priv);
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void nv4_ramin_write8(uint32_t addr, uint8_t val, void* priv);
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void nv4_ramin_write16(uint32_t addr, uint16_t val, void* priv);
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void nv4_ramin_write32(uint32_t addr, uint32_t val, void* priv);
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uint8_t nv4_svga_read(uint16_t addr, void* priv);
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void nv4_svga_write(uint16_t addr, uint8_t val, void* priv);
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void nv4_update_mappings();
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@@ -7,12 +7,12 @@
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// General
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//
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#define NV4_VRAM_SIZE_2MB 0x200000 // 2MB (never used; NV4 only)
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#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used)
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#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB
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#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB
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#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only
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#define NV4_VRAM_SIZE_4MB 0x400000 // 4MB (never used)
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#define NV4_VRAM_SIZE_8MB 0x800000 // 8MB
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#define NV4_VRAM_SIZE_16MB 0x1000000 // 16MB
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#define NV5_VRAM_SIZE_32MB 0x2000000 // NV5 only
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#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!!
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#define NV4_MMIO_SIZE 0x1000000 // not sure. May be larger!!!!
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//
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// VBIOS
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@@ -21,6 +21,12 @@
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#define NV4_PRMIO_START 0x7000
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#define NV4_PRMIO_END 0x7FFF
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// NV4 Legacy I/O space
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#define NV4_RMA_REGISTER_START 0x3D0
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#define NV4_RMA_REGISTER_END 0x3D3
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#define NV4_RMA_NUM_REGS 4
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#define NV4_PRMIO_RMA_ID 0x7100
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#define NV4_PRMIO_RMA_ID_CODE 0
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#define NV4_PRMIO_RMA_ID_CODE_VALID 0x2B16D065
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@@ -32,6 +38,7 @@
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#define NV4_PRMIO_RMA_DATA32_BYTE2 16
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#define NV4_PRMIO_RMA_DATA32_BYTE1 8
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#define NV4_PRMIO_RMA_DATA32_BYTE0 0
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#define NV4_PRMIO_RMA_MODE_MAX 0x0F
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#define NV4_PRAMDAC_START 0x680300
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#define NV4_PRAMDAC_END 0x680FFF
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@@ -261,6 +268,8 @@
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#define NV4_USER_DAC_START 0x681200
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#define NV4_USER_DAC_END 0x681FFF
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#define NV4_USER_DAC_PALETTE_START 0x6813C6
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#define NV4_USER_DAC_PALETTE_END 0x6813C9
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#define NV4_USER_DAC_PIXEL_MASK 0x6813C6
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#define NV4_USER_DAC_PIXEL_MASK_VALUE 0
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@@ -486,223 +495,181 @@
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#define NV4_PBUS_INTR_EN_0_PCI_BUS_ERROR_ENABLED 0x1
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#define NV4_PBUS_ROM_CONFIG 0x1200
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#define NV4_PBUS_ROM_CONFIG_TW1 0
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#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF
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#define NV4_PBUS_ROM_CONFIG_TW0 4
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#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3
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#define NV4_PBUS_PCI_NV_0 0x1800
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#define NV4_PBUS_PCI_NV_0_VENDOR_ID 0
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#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA_SGS 0x12D2
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#define NV4_PBUS_PCI_NV_0_VENDOR_ID_NVIDIA 0x10DE
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC 16
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_FUNC_VGA 0x0
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP 3 19
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV0 0x0
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV1 0x1
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV2 0x2
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV3 0x3
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#define NV4_PBUS_PCI_NV_0_DEVICE_ID_CHIP_NV4 0x4
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#define NV4_PBUS_PCI_NV_1 0x1804
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#define NV4_PBUS_PCI_NV_1_IO_SPACE 0
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#define NV4_PBUS_PCI_NV_1_IO_SPACE_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE 1
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#define NV4_PBUS_PCI_NV_1_MEMORY_SPACE_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_1_BUS_MASTER 2
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#define NV4_PBUS_PCI_NV_1_BUS_MASTER_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL 4
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#define NV4_PBUS_PCI_NV_1_WRITE_AND_INVAL_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP 5
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#define NV4_PBUS_PCI_NV_1_PALETTE_SNOOP_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_1_CAPLIST 20
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#define NV4_PBUS_PCI_NV_1_CAPLIST_NOT_PRESENT 0x0
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#define NV4_PBUS_PCI_NV_1_CAPLIST_PRESENT 0x1
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#define NV4_PBUS_PCI_NV_1_66MHZ 21
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#define NV4_PBUS_PCI_NV_1_66MHZ_INCAPABLE 0x0
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#define NV4_PBUS_PCI_NV_1_66MHZ_CAPABLE 0x1
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#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK 23
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#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_INCAPABLE 0x0
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#define NV4_PBUS_PCI_NV_1_FAST_BACK2BACK_CAPABLE 0x1
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#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING 25
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#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_FAST 0x0
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#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_MEDIUM 0x1
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#define NV4_PBUS_PCI_NV_1_DEVSEL_TIMING_SLOW 0x2
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#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET 27
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#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_NO_ABORT 0x0
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#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_ABORT 0x1
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#define NV4_PBUS_PCI_NV_1_SIGNALED_TARGET_CLEAR 0x1
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#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET 28
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#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_NO_ABORT 0x0
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#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_ABORT 0x1
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#define NV4_PBUS_PCI_NV_1_RECEIVED_TARGET_CLEAR 0x1
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#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER 29
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#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_NO_ABORT 0x0
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#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_ABORT 0x1
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#define NV4_PBUS_PCI_NV_1_RECEIVED_MASTER_CLEAR 0x1
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#define NV4_PBUS_PCI_NV_2 0x1808
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#define NV4_PBUS_PCI_NV_2_REVISION_ID 0
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#define NV4_PBUS_PCI_NV_2_REVISION_ID_A01 0x0
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#define NV4_PBUS_PCI_NV_2_REVISION_ID_B01 0x10
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#define NV4_PBUS_PCI_NV_2_CLASS_CODE 8
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#define NV4_PBUS_PCI_NV_2_CLASS_CODE_VGA 0x30000
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#define NV4_PBUS_PCI_NV_2_CLASS_CODE_MULTIMEDIA 0x48000
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#define NV4_PBUS_PCI_NV_3 0x180C
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#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER 11
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#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_0_CLOCKS 0x0
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#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_8_CLOCKS 0x1
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#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_240_CLOCKS 0x1E
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#define NV4_PBUS_PCI_NV_3_LATENCY_TIMER_248_CLOCKS 0x1F
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#define NV4_PBUS_PCI_NV_3_HEADER_TYPE 16
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#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_SINGLEFUNC 0x0
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#define NV4_PBUS_PCI_NV_3_HEADER_TYPE_MULTIFUNC 0x80
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#define NV4_PBUS_PCI_NV_4 0x1810
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#define NV4_PBUS_PCI_NV_4_SPACE_TYPE 0
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#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_MEMORY 0x0
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#define NV4_PBUS_PCI_NV_4_SPACE_TYPE_IO 0x1
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#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE 1
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#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_32_BIT 0x0
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#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_20_BIT 0x1
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#define NV4_PBUS_PCI_NV_4_ADDRESS_TYPE_64_BIT 0x2
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#define NV4_PBUS_PCI_NV_4_PREFETCHABLE 3
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#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_NOT 0x0
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#define NV4_PBUS_PCI_NV_4_PREFETCHABLE_MERGABLE 0x1
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#define NV4_PBUS_PCI_NV_4_BASE_ADDRESS 24
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#define NV4_PBUS_PCI_NV_5 0x1814
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#define NV4_PBUS_PCI_NV_5_SPACE_TYPE 0
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#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_MEMORY 0x0
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#define NV4_PBUS_PCI_NV_5_SPACE_TYPE_IO 0x1
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#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE 2:1
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#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_32_BIT 0x0
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#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_20_BIT 0x1
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#define NV4_PBUS_PCI_NV_5_ADDRESS_TYPE_64_BIT 0x2
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#define NV4_PBUS_PCI_NV_5_PREFETCHABLE 3
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#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_NOT 0x0
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#define NV4_PBUS_PCI_NV_5_PREFETCHABLE_MERGABLE 0x1
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#define NV4_PBUS_PCI_NV_5_BASE_ADDRESS 24
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#define NV4_PBUS_PCI_NV_6(i) (0x1818+(i)*4)
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#define NV4_PBUS_PCI_NV_6_SIZE_1 5
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#define NV4_PBUS_PCI_NV_6_RESERVED 0
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#define NV4_PBUS_PCI_NV_6_RESERVED_0 0x0
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#define NV4_PBUS_PCI_NV_11 0x182C
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#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID 0
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#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_VENDOR_ID_NONE 0x0
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#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID 16
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#define NV4_PBUS_PCI_NV_11_SUBSYSTEM_ID_NONE 0x0
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#define NV4_PBUS_PCI_NV_12 0x1830
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#define NV4_PBUS_PCI_NV_12_ROM_DECODE 0
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#define NV4_PBUS_PCI_NV_12_ROM_DECODE_ENABLED 0x1
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#define NV4_PBUS_PCI_NV_12_ROM_BASE 16
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#define NV4_PBUS_PCI_NV_13 0x1834
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#define NV4_PBUS_PCI_NV_13_CAP_PTR 0
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#define NV4_PBUS_PCI_NV_13_CAP_PTR_AGP 0x44
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#define NV4_PBUS_PCI_NV_13_CAP_PTR_POWER_MGMT 0x60
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#define NV4_PBUS_PCI_NV_14 0x1838
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#define NV4_PBUS_PCI_NV_14_RESERVED 0
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#define NV4_PBUS_PCI_NV_14_RESERVED_0 0x0
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#define NV4_PBUS_PCI_NV_15 0x183C
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#define NV4_PBUS_PCI_NV_15_INTR_LINE 0
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#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ0 0x0
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#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ1 0x1
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#define NV4_PBUS_PCI_NV_15_INTR_LINE_IRQ15 0xF
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#define NV4_PBUS_PCI_NV_15_INTR_LINE_UNKNOWN 0xFF
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#define NV4_PBUS_PCI_NV_15_INTR_PIN 8
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#define NV4_PBUS_PCI_NV_15_INTR_PIN_INTA 0x1
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#define NV4_PBUS_PCI_NV_15_MIN_GNT 16
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#define NV4_PBUS_PCI_NV_15_MIN_GNT_NO_REQUIREMENTS 0x0
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#define NV4_PBUS_PCI_NV_15_MIN_GNT_750NS 0x3
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#define NV4_PBUS_PCI_NV_15_MIN_GNT_1250NS 0x5
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#define NV4_PBUS_PCI_NV_15_MAX_LAT 24
|
||||
#define NV4_PBUS_PCI_NV_15_MAX_LAT_NO_REQUIREMENTS 0x0
|
||||
#define NV4_PBUS_PCI_NV_15_MAX_LAT_250NS 0x1
|
||||
#define NV4_PBUS_PCI_NV_16 0x1840
|
||||
#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID 0
|
||||
#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_VENDOR_ID_NONE 0x0
|
||||
#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID 16
|
||||
#define NV4_PBUS_PCI_NV_16_SUBSYSTEM_ID_NONE 0x0
|
||||
#define NV4_PBUS_PCI_NV_17 0x1844
|
||||
#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR 20
|
||||
#define NV4_PBUS_PCI_NV_17_AGP_REV_MAJOR_1 0x1
|
||||
#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR 16
|
||||
#define NV4_PBUS_PCI_NV_17_AGP_REV_MINOR_0 0x0
|
||||
#define NV4_PBUS_PCI_NV_17_NEXT_PTR 8
|
||||
#define NV4_PBUS_PCI_NV_17_NEXT_PTR_NULL 0x0
|
||||
#define NV4_PBUS_PCI_NV_17_CAP_ID 0
|
||||
#define NV4_PBUS_PCI_NV_17_CAP_ID_AGP 0x2
|
||||
#define NV4_PBUS_PCI_NV_18 0x1848
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ 24
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RQ_16 0xF
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA 9
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_NONE 0x0
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_SBA_CAPABLE 0x1
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE 0
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X 0x1
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_2X 0x2
|
||||
#define NV4_PBUS_PCI_NV_18_AGP_STATUS_RATE_1X_AND_2X 0x3
|
||||
#define NV4_PBUS_PCI_NV_19 0x184C
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH 24
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_RQ_DEPTH_0 0x0
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE 9
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_OFF 0x0
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_SBA_ENABLE_ON 0x1
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE 8
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_OFF 0x0
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_AGP_ENABLE_ON 0x1
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE 0
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_OFF 0x0
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_1X 0x1
|
||||
#define NV4_PBUS_PCI_NV_19_AGP_COMMAND_DATA_RATE_2X 0x2
|
||||
#define NV4_PBUS_PCI_NV_20 0x1850
|
||||
#define NV4_PBUS_PCI_NV_20_ROM_SHADOW 0
|
||||
#define NV4_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_NV_21 0x1854
|
||||
#define NV4_PBUS_PCI_NV_21_VGA 0
|
||||
#define NV4_PBUS_PCI_NV_21_VGA_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_NV_22 0x1858
|
||||
#define NV4_PBUS_PCI_NV_22_SCRATCH 0
|
||||
#define NV4_PBUS_PCI_NV_22_SCRATCH_DEFAULT 0x23D6CE
|
||||
#define NV4_PBUS_PCI_NV_23 0x185C
|
||||
#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT 0
|
||||
#define NV4_PBUS_PCI_NV_23_DT_TIMEOUT_16 0xF
|
||||
#define NV4_PBUS_PCI_NV_24 0x1860
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D3_COLD 31
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D3_COLD_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D3_HOT 30
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D3_HOT_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D2 29
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D2_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D1 28
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D1_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D0 27
|
||||
#define NV4_PBUS_PCI_NV_24_PME_D0_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_D2 26
|
||||
#define NV4_PBUS_PCI_NV_24_D2_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_D2_NOT_SUPPORTED 0x0
|
||||
#define NV4_PBUS_PCI_NV_24_D1 25
|
||||
#define NV4_PBUS_PCI_NV_24_D1_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_D1_NOT_SUPPORTED 0x0
|
||||
#define NV4_PBUS_PCI_NV_24_DSI 21
|
||||
#define NV4_PBUS_PCI_NV_24_DSI_NOT_REQUIRED 0x0
|
||||
#define NV4_PBUS_PCI_NV_24_PME_CLOCK 19
|
||||
#define NV4_PBUS_PCI_NV_24_PME_CLOCK_NOT_REQUIRED 0x0
|
||||
#define NV4_PBUS_PCI_NV_24_VERSION 16
|
||||
#define NV4_PBUS_PCI_NV_24_VERSION_1 0x1
|
||||
#define NV4_PBUS_PCI_NV_24_NEXT_PTR 8
|
||||
#define NV4_PBUS_PCI_NV_24_NEXT_PTR_NULL 0x0
|
||||
#define NV4_PBUS_PCI_NV_24_NEXT_PTR_AGP 0x44
|
||||
#define NV4_PBUS_PCI_NV_24_CAP_ID 0
|
||||
#define NV4_PBUS_PCI_NV_24_CAP_ID_POWER_MGMT 0x1
|
||||
#define NV4_PBUS_PCI_NV_25 0x1864
|
||||
#define NV4_PBUS_PCI_NV_25_POWER_STATE 0
|
||||
#define NV4_PBUS_PCI_NV_25_POWER_STATE_D3_HOT 0x3
|
||||
#define NV4_PBUS_PCI_NV_25_POWER_STATE_D2 0x2
|
||||
#define NV4_PBUS_PCI_NV_25_POWER_STATE_D1 0x1
|
||||
#define NV4_PBUS_PCI_NV_25_POWER_STATE_D0 0x0
|
||||
#define NV4_PBUS_PCI_NV_26(i) (0x1868+(i)*4)
|
||||
#define NV4_PBUS_PCI_NV_26_SIZE_1 38
|
||||
#define NV4_PBUS_PCI_NV_26_RESERVED 0
|
||||
#define NV4_PBUS_PCI_NV_26_RESERVED_0 0x0
|
||||
#define NV4_PBUS_ROM_CONFIG_TW1_DEFAULT 0xF
|
||||
#define NV4_PBUS_ROM_CONFIG_TW0 4
|
||||
#define NV4_PBUS_ROM_CONFIG_TW0_DEFAULT 0x3
|
||||
|
||||
// 86Box uses 8-bit PCI registers so this section was rewritten
|
||||
#define NV4_PBUS_PCI_VENDOR_ID 0x1800
|
||||
#define NV4_PBUS_PCI_DEVICE_VENDOR_NVIDIA 0x10DE
|
||||
#define NV4_PBUS_PCI_DEVICE_ID 0x1802
|
||||
#define NV4_PBUS_PCI_DEVICE_ID_NV4 0x0020 // Chip (19:17)= NV4, Func = VGA
|
||||
#define NV4_PBUS_PCI_COMMAND 0x1804
|
||||
#define NV4_PBUS_PCI_COMMAND_IO_SPACE 0
|
||||
#define NV4_PBUS_PCI_COMMAND_IO_SPACE_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE 1
|
||||
#define NV4_PBUS_PCI_COMMAND_MEMORY_SPACE_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_COMMAND_BUS_MASTER 2
|
||||
#define NV4_PBUS_PCI_COMMAND_BUS_MASTER_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL 4
|
||||
#define NV4_PBUS_PCI_COMMAND_WRITE_AND_INVAL_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP 5
|
||||
#define NV4_PBUS_PCI_COMMAND_PALETTE_SNOOP_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_STATUS 0x1806
|
||||
#define NV4_PBUS_PCI_STATUS_CAPLIST 4
|
||||
#define NV4_PBUS_PCI_STATUS_CAPLIST_NOT_PRESENT 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_CAPLIST_PRESENT 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_66MHZ 5
|
||||
#define NV4_PBUS_PCI_STATUS_66MHZ_INCAPABLE 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_66MHZ_CAPABLE 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK 7
|
||||
#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_INCAPABLE 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_FAST_BACK2BACK_CAPABLE 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2 0x1807
|
||||
#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING 1
|
||||
#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_FAST 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_MEDIUM 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_DEVSEL_TIMING_SLOW 0x2
|
||||
#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET 3
|
||||
#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_NO_ABORT 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_ABORT 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_SIGNALED_TARGET_CLEAR 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET 4
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_NO_ABORT 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_ABORT 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_TARGET_CLEAR 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER 5
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_NO_ABORT 0x0
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_ABORT 0x1
|
||||
#define NV4_PBUS_PCI_STATUS_2_RECEIVED_MASTER_CLEAR 0x1
|
||||
#define NV4_PBUS_PCI_REVISION_ID 0x1808
|
||||
#define NV4_PBUS_PCI_REVISION_ID_A01 0x0
|
||||
#define NV4_PBUS_PCI_REVISION_ID_B01 0x1
|
||||
#define NV4_PBUS_PCI_CLASS_CODE 0x180B
|
||||
#define NV4_PBUS_PCI_CLASS_CODE_VGA 0x30000
|
||||
#define NV4_PBUS_PCI_LATENCY_TIMER 0x180D
|
||||
// Shift left by 3 to get the real value in clocks. 0x0 = 0, 0x1 = 8, 0x1E = 240, 0x1F = 248 are values used.
|
||||
#define NV4_PBUS_PCI_LATENCY_TIMER_VALUE 3
|
||||
// 0x0 = single function (only value that matters)
|
||||
#define NV4_PBUS_PCI_HEADER_TYPE 0x180E
|
||||
#define NV4_PBUS_PCI_BAR_SPACE_TYPE 0
|
||||
#define NV4_PBUS_PCI_BAR_SPACE_TYPE_MEMORY 0x0
|
||||
#define NV4_PBUS_PCI_BAR_SPACE_TYPE_IO 0x1
|
||||
#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE 1
|
||||
#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_32_BIT 0x0
|
||||
#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_20_BIT 0x1
|
||||
#define NV4_PBUS_PCI_BAR_ADDRESS_TYPE_64_BIT 0x2
|
||||
#define NV4_PBUS_PCI_BAR_PREFETCHABLE 3
|
||||
#define NV4_PBUS_PCI_BAR_PREFETCHABLE_NOT 0x0
|
||||
#define NV4_PBUS_PCI_BAR_PREFETCHABLE_MERGABLE 0x1
|
||||
// Bits 23:4 are resedrved
|
||||
#define NV4_PBUS_PCI_BAR0_INFO 0x1810
|
||||
#define NV4_PBUS_PCI_BAR0_UNUSED1 0x1811
|
||||
#define NV4_PBUS_PCI_BAR0_UNUSED2 0x1812
|
||||
#define NV4_PBUS_PCI_BAR0_BASE_31_TO_24 0x1813 // Must align to 16MByte
|
||||
#define NV4_PBUS_PCI_BAR1_INFO 0x1814
|
||||
#define NV4_PBUS_PCI_BAR1_UNUSED1 0x1814
|
||||
#define NV4_PBUS_PCI_BAR1_UNUSED2 0x1815
|
||||
#define NV4_PBUS_PCI_BAR1_BASE_31_TO_24 0x1816 // Must align to 16MByte
|
||||
//BAR2-5 reserved
|
||||
#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID 0x182C
|
||||
#define NV4_PBUS_PCI_SUBSYSTEM_ID 0x182E
|
||||
#define NV4_PBUS_PCI_ROM 0x1830
|
||||
#define NV4_PBUS_PCI_ROM_DECODE 0
|
||||
#define NV4_PBUS_PCI_ROM_DECODE_ENABLED 0x1
|
||||
#define NV4_PBUS_PCI_ROM_BASE 0x1832
|
||||
#define NV4_PBUS_PCI_NEXT_PTR 0x1834
|
||||
#define NV4_PBUS_PCI_CAP_PTR_AGP 0x44
|
||||
#define NV4_PBUS_PCI_CAP_PTR_POWER_MGMT 0x60
|
||||
// 0xFF = unknown, otherwise 0x0-0xF = IRQ0-15
|
||||
#define NV4_PBUS_PCI_INTR_LINE 0x183C
|
||||
#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM 0
|
||||
#define NV4_PBUS_PCI_INTR_LINE_IRQ_NUM_UNKNOWN 0xFF
|
||||
#define NV4_PBUS_PCI_INTR_PIN 0x183D
|
||||
#define NV4_PBUS_PCI_INTR_PIN_INTA 0x1
|
||||
#define NV4_PBUS_PCI_MIN_GNT 0x183E
|
||||
#define NV4_PBUS_PCI_MIN_GNT_NO_REQUIREMENTS 0x0
|
||||
#define NV4_PBUS_PCI_MIN_GNT_750NS 0x3
|
||||
#define NV4_PBUS_PCI_MIN_GNT_1250NS 0x5
|
||||
#define NV4_PBUS_PCI_MAX_LAT 0x183F
|
||||
#define NV4_PBUS_PCI_MAX_LAT_NO_REQUIREMENTS 0x0
|
||||
#define NV4_PBUS_PCI_MAX_LAT_250NS 0x1
|
||||
#define NV4_PBUS_PCI_SUBSYSTEM_VENDOR_ID_WRITABLE 0x1840
|
||||
#define NV4_PBUS_PCI_SUBSYSTEM_ID_WRITABLE 0x1842
|
||||
#define NV4_PBUS_AGP 0x44
|
||||
#define NV4_PBUS_AGP_CAPABILITIES 0x1844
|
||||
#define NV4_PBUS_AGP_CAPABILITY_AGP 0x2
|
||||
// Should be null!
|
||||
|
||||
#define NV4_PBUS_AGP_NEXT_PTR 0x1845
|
||||
#define NV4_PBUS_AGP_REV 0x1846
|
||||
#define NV4_PBUS_AGP_REV_MINOR 0
|
||||
#define NV4_PBUS_AGP_REV_MINOR_0 0x0
|
||||
#define NV4_PBUS_AGP_REV_MAJOR 4
|
||||
#define NV4_PBUS_AGP_REV_MAJOR_1 0x1
|
||||
#define NV4_PBUS_AGP_STATUS_RATE 0x1848
|
||||
#define NV4_PBUS_AGP_STATUS_RATE_1X 0x1
|
||||
#define NV4_PBUS_AGP_STATUS_RATE_2X 0x2
|
||||
#define NV4_PBUS_AGP_STATUS_RATE_1X_AND_2X 0x3
|
||||
#define NV4_PBUS_AGP_STATUS_RQ 0x184B
|
||||
#define NV4_PBUS_AGP_STATUS_RQ_16 0xF
|
||||
#define NV4_PBUS_AGP_STATUS_SBA 0x1849
|
||||
#define NV4_PBUS_AGP_STATUS_SBA_STATUS 1
|
||||
#define NV4_PBUS_AGP_STATUS_SBA_STATUS_NONE 0x0
|
||||
#define NV4_PBUS_AGP_STATUS_SBA_STATUS_CAPABLE 0x1
|
||||
#define NV4_PBUS_AGP_COMMAND 0x184C
|
||||
#define NV4_PBUS_AGP_COMMAND_DATA_RATE 0
|
||||
#define NV4_PBUS_AGP_COMMAND_DATA_RATE_OFF 0x0
|
||||
#define NV4_PBUS_AGP_COMMAND_DATA_RATE_1X 0x1
|
||||
#define NV4_PBUS_AGP_COMMAND_DATA_RATE_2X 0x2
|
||||
#define NV4_PBUS_AGP_COMMAND_2 0x184D
|
||||
#define NV4_PBUS_AGP_COMMAND_2_AGP_ENABLED 0 // 1 = enabled, 0 = disabled
|
||||
#define NV4_PBUS_AGP_COMMAND_2_SBA_ENABLED 1 // 1 = enabled, 0 = disabled
|
||||
#define NV4_PBUS_AGP_COMMAND_RQ_DEPTH 0x184F //DEFAUlt 0
|
||||
#define NV4_PBUS_PCI_ROM_SHADOW 0x1850
|
||||
#define NV4_PBUS_PCI_ROM_SHADOW_IS_ENABLED 0 // 1 = enabled, 0 = disabled
|
||||
#define NV4_PBUS_PCI_VGA 0x1854
|
||||
#define NV4_PBUS_PCI_VGA_IS_ENABLED 0 // 1 = enabled, 0 = disabled
|
||||
#define NV4_PBUS_PCI_SCRATCH 0x1858
|
||||
#define NV4_PBUS_PCI_SCRATCH_DEFAULT 0x23D6CE
|
||||
#define NV4_PBUS_PCI_DT 0x185C
|
||||
#define NV4_PBUS_PCI_DT_TIMEOUT 0
|
||||
#define NV4_PBUS_PCI_DT_TIMEOUT_16 0xF
|
||||
//TODO: Implement
|
||||
#define NV4_PBUS_PCIPOWER 0x1860
|
||||
#define NV4_PBUS_PCIPOWER_CAP_ID 0
|
||||
#define NV4_PBUS_PCIPOWER_CAP_ID_POWER_MGMT 0x1
|
||||
#define NV4_PBUS_PCIPOWER_NEXT_PTR 0x1861 // should be 0x44=AGP
|
||||
#define NV4_PBUS_PCIPOWER_2 0x1862
|
||||
#define NV4_PBUS_PCIPOWER_2_VERSION 0
|
||||
#define NV4_PBUS_PCIPOWER_2_VERSION_1 0x1
|
||||
#define NV4_PBUS_PCIPOWER_2_CLOCK 3
|
||||
#define NV4_PBUS_PCIPOWER_2_CLOCK_NOT_REQUIRED 0x0
|
||||
#define NV4_PBUS_PCIPOWER_2_DSI 5
|
||||
#define NV4_PBUS_PCIPOWER_2_DSI_NOT_REQUIRED 0x0
|
||||
#define NV4_PBUS_PCIPOWER_SUPPORTED_STATES 0x1863
|
||||
#define NV4_PBUS_PCIPOWER_D1 1
|
||||
#define NV4_PBUS_PCIPOWER_D1_SUPPORTED 0x1 // 1 = supported
|
||||
#define NV4_PBUS_PCIPOWER_D2 2
|
||||
#define NV4_PBUS_PCIPOWER_D2_SUPPORTED 0x1 // 0 = not supported
|
||||
#define NV4_PBUS_PCIPOWER_PME_D0 3
|
||||
#define NV4_PBUS_PCIPOWER_PME_D0_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCIPOWER_PME_D1 4
|
||||
#define NV4_PBUS_PCIPOWER_PME_D1_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCIPOWER_PME_D2 5
|
||||
#define NV4_PBUS_PCIPOWER_PME_D2_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCIPOWER_PME_D3_HOT 6
|
||||
#define NV4_PBUS_PCIPOWER_PME_D3_HOT_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCIPOWER_PME_D3_COLD 7
|
||||
#define NV4_PBUS_PCIPOWER_PME_D3_COLD_SUPPORTED 0x1
|
||||
#define NV4_PBUS_PCIPOWER_STATE_CURRENT 0x1864
|
||||
#define NV4_PBUS_PCIPOWER_STATE 0
|
||||
#define NV4_PBUS_PCIPOWER_STATE_D3_HOT 0x3
|
||||
#define NV4_PBUS_PCIPOWER_STATE_D2 0x2
|
||||
#define NV4_PBUS_PCIPOWER_STATE_D1 0x1
|
||||
#define NV4_PBUS_PCIPOWER_STATE_D0 0x0
|
||||
#define NV4_PFIFO_START 0x2000
|
||||
#define NV4_PFIFO_END 0x3FFF
|
||||
|
||||
#define NV4_PFIFO_DELAY_0 0x2040
|
||||
#define NV4_PFIFO_DELAY_0_WAIT_RETRY 0
|
||||
#define NV4_PFIFO_DELAY_0_WAIT_RETRY_0 0x0
|
||||
@@ -3249,6 +3216,7 @@
|
||||
|
||||
#define NV4_CIO_START 0x3B0
|
||||
#define NV4_CIO_END 0x3DF
|
||||
#define NV4_CIO_SIZE NV4_CIO_END - NV4_CIO_START
|
||||
|
||||
|
||||
#define NV4_CIO_INP0 0x3c2
|
||||
@@ -3403,7 +3371,7 @@
|
||||
#define NV4_CIO_CRE_TREG_VCNTA_INDEX 0x6
|
||||
#define NV4_CIO_CRE_TREG_VCNTB_INDEX 0x7
|
||||
#define NV4_CIO_CRE_DDC_STATUS_INDEX 0x3E
|
||||
#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F
|
||||
#define NV4_CIO_CRE_DDC_WR_INDEX 0x3F // Write to i2c for EDID/DDC
|
||||
#define NV4_CIO_CRE_PCI_TO_INDEX 0x40
|
||||
#define NV4_CIO_CRE_PCI_TO_DELAY 0
|
||||
|
||||
@@ -3456,6 +3424,10 @@
|
||||
#define NV4_PRMVIO_GX_READ_MAP_INDEX 0x4
|
||||
#define NV4_PRMVIO_GX_MODE_INDEX 0x5
|
||||
#define NV4_PRMVIO_GX_MISC_INDEX 0x6
|
||||
#define NV4_PRMVIO_GX_MISC_BANKED_128K_A0000 0x00
|
||||
#define NV4_PRMVIO_GX_MISC_BANKED_64K_A0000 0x04
|
||||
#define NV4_PRMVIO_GX_MISC_BANKED_32K_B0000 0x08
|
||||
#define NV4_PRMVIO_GX_MISC_BANKED_32K_B8000 0x0C
|
||||
#define NV4_PRMVIO_GX_DONT_CARE_INDEX 0x7
|
||||
#define NV4_PRMVIO_GX_BIT_MASK_INDEX 0x8
|
||||
|
||||
@@ -3922,6 +3894,7 @@
|
||||
// But this part may not work
|
||||
#define NV4_PRAMIN_START 0x700000
|
||||
#define NV4_PRAMIN_END 0x7FFFFF
|
||||
#define NV4_PRAMIN_SIZE 0xFFFFF
|
||||
|
||||
#define NV4_PRAMIN_CONTEXT_0 ( 0*32+31):( 0*32+ 0)
|
||||
#define NV4_PRAMIN_CONTEXT_1 ( 1*32+31):( 1*32+ 0)
|
||||
@@ -4002,35 +3975,35 @@
|
||||
|
||||
// DFB is in BAR1. Access it as VRAM
|
||||
|
||||
#define NV4_PEXTDEV_BOOT_0 0x101000
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 2
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x3
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE 7
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x2
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x3
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x0
|
||||
#define NV4_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x1
|
||||
#define NV4_PEXTDEV_BOOT_0 0x101000
|
||||
#define NV4_STRAP_BUS_SPEED 0
|
||||
#define NV4_STRAP_BUS_SPEED_33MHZ 0x0
|
||||
#define NV4_STRAP_BUS_SPEED_66MHZ 0x1
|
||||
#define NV4_STRAP_SUB_VENDOR 1
|
||||
#define NV4_STRAP_SUB_VENDOR_NO_BIOS 0x0
|
||||
#define NV4_STRAP_SUB_VENDOR_BIOS 0x1
|
||||
#define NV4_STRAP_RAM_TYPE 2
|
||||
#define NV4_STRAP_RAM_TYPE_SGRAM_256K 0x0
|
||||
#define NV4_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x1
|
||||
#define NV4_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x2
|
||||
#define NV4_STRAP_RAM_TYPE_1024K_2BANK 0x3
|
||||
#define NV4_STRAP_RAM_WIDTH 4
|
||||
#define NV4_STRAP_RAM_WIDTH_64 0x0
|
||||
#define NV4_STRAP_RAM_WIDTH_128 0x1
|
||||
#define NV4_STRAP_BUS_TYPE 5
|
||||
#define NV4_STRAP_BUS_TYPE_PCI 0x0
|
||||
#define NV4_STRAP_BUS_TYPE_AGP 0x1
|
||||
#define NV4_STRAP_CRYSTAL 6
|
||||
#define NV4_STRAP_CRYSTAL_13500K 0x0
|
||||
#define NV4_STRAP_CRYSTAL_14318180 0x1
|
||||
#define NV4_STRAP_TVMODE 7
|
||||
#define NV4_STRAP_TVMODE_SECAM 0x0
|
||||
#define NV4_STRAP_TVMODE_NTSC 0x1
|
||||
#define NV4_STRAP_TVMODE_PAL 0x2
|
||||
#define NV4_STRAP_TVMODE_DISABLED 0x3
|
||||
#define NV4_STRAP_OVERWRITE 11
|
||||
#define NV4_STRAP_OVERWRITE_DISABLED 0x0
|
||||
#define NV4_STRAP_OVERWRITE_ENABLED 0x1
|
||||
|
||||
#define NV4_PDAC_START 0x680000
|
||||
#define NV4_PDAC_END 0x680FFF
|
||||
|
||||
@@ -199,6 +199,7 @@ add_library(vid OBJECT
|
||||
|
||||
# NVidia RIVA TNT/TNT2 - Core
|
||||
nv/nv4/nv4_core.c
|
||||
nv/nv4/nv4_core_io.c
|
||||
nv/nv4/nv4_core_config.c
|
||||
|
||||
# Generic
|
||||
|
||||
@@ -197,9 +197,7 @@ void nv3_mmio_write16(uint32_t addr, uint16_t val, void* priv)
|
||||
nv_log_verbose_only("Redirected MMIO write16 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
|
||||
|
||||
nv3_svga_write(real_address, val & 0xFF, nv3);
|
||||
|
||||
if (val > 0xFF)
|
||||
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
|
||||
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -227,15 +225,9 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
|
||||
nv_log_verbose_only("Redirected MMIO write32 to SVGA: addr=0x%04x val=0x%02x\n", addr, val);
|
||||
|
||||
nv3_svga_write(real_address, val & 0xFF, nv3);
|
||||
|
||||
if (val > 0xFF)
|
||||
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
|
||||
|
||||
if (val > 0xFFFF)
|
||||
nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3);
|
||||
|
||||
if (val > 0xFFFFFF)
|
||||
nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3);
|
||||
nv3_svga_write(real_address + 1, (val >> 8) & 0xFF, nv3);
|
||||
nv3_svga_write(real_address + 2, (val >> 16) & 0xFF, nv3);
|
||||
nv3_svga_write(real_address + 3, (val >> 24) & 0xFF, nv3);
|
||||
|
||||
return;
|
||||
}
|
||||
@@ -276,7 +268,7 @@ uint8_t nv3_agp_read(int32_t func, int32_t addr)
|
||||
ret = nv3->nvbase.agp_enabled;
|
||||
break;
|
||||
default:
|
||||
ret = nv3->pci_config.pci_regs[addr];
|
||||
ret = nv3->nvbase.pci_config.pci_regs[addr];
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -329,25 +321,25 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
// 66Mhz FSB capable
|
||||
|
||||
case PCI_REG_COMMAND_L:
|
||||
ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_L];
|
||||
ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L];
|
||||
break;
|
||||
|
||||
case PCI_REG_COMMAND_H:
|
||||
ret = nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back
|
||||
ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] & NV3_PCI_COMMAND_H_FAST_BACK2BACK; // always enable fast back2back
|
||||
break;
|
||||
|
||||
// pci status register
|
||||
case PCI_REG_STATUS_L:
|
||||
if (nv3->pextdev.straps
|
||||
& NV3_PSTRAPS_BUS_SPEED_66MHZ)
|
||||
ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE);
|
||||
ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] | NV3_PCI_STATUS_L_66MHZ_CAPABLE);
|
||||
else
|
||||
ret = nv3->pci_config.pci_regs[PCI_REG_STATUS_L];
|
||||
ret = nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L];
|
||||
|
||||
break;
|
||||
|
||||
case PCI_REG_STATUS_H:
|
||||
ret = (nv3->pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
|
||||
ret = (nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H]) & (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
|
||||
break;
|
||||
|
||||
case NV3_PCI_CFG_REVISION:
|
||||
@@ -400,7 +392,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
break;
|
||||
|
||||
case NV3_PCI_CFG_ENABLE_VBIOS:
|
||||
ret = nv3->pci_config.vbios_enabled;
|
||||
ret = nv3->nvbase.pci_config.vbios_enabled;
|
||||
break;
|
||||
|
||||
case NV3_AGP_CAPABILITIES_POINTER:
|
||||
@@ -411,7 +403,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
break;
|
||||
|
||||
case NV3_PCI_CFG_INT_LINE:
|
||||
ret = nv3->pci_config.int_line;
|
||||
ret = nv3->nvbase.pci_config.int_line;
|
||||
break;
|
||||
|
||||
case NV3_PCI_CFG_INT_PIN:
|
||||
@@ -433,7 +425,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
|
||||
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START:
|
||||
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END:
|
||||
ret = nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)];
|
||||
ret = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)];
|
||||
break;
|
||||
|
||||
case NV3_AGP_START ... NV3_AGP_END:
|
||||
@@ -446,7 +438,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
|
||||
|
||||
default: // by default just return pci_config.pci_regs
|
||||
ret = nv3->pci_config.pci_regs[addr];
|
||||
ret = nv3->nvbase.pci_config.pci_regs[addr];
|
||||
break;
|
||||
|
||||
}
|
||||
@@ -457,7 +449,7 @@ uint8_t nv3_pci_read(int32_t func, int32_t addr, void* priv)
|
||||
|
||||
void nv3_agp_write(int32_t func, int32_t addr, uint8_t val)
|
||||
{
|
||||
nv3->pci_config.pci_regs[addr] = val;
|
||||
nv3->nvbase.pci_config.pci_regs[addr] = val;
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
@@ -471,7 +463,6 @@ void nv3_agp_write(int32_t func, int32_t addr, uint8_t val)
|
||||
|
||||
void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
{
|
||||
|
||||
// sanity check
|
||||
if (!nv3)
|
||||
return;
|
||||
@@ -484,29 +475,28 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
|
||||
nv_log("nv3_pci_write func=0x%04x addr=0x%04x val=0x%04x\n", func, addr, val);
|
||||
|
||||
nv3->pci_config.pci_regs[addr] = val;
|
||||
nv3->nvbase.pci_config.pci_regs[addr] = val;
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
// standard pci command stuff
|
||||
case PCI_REG_COMMAND_L:
|
||||
nv3->pci_config.pci_regs[PCI_REG_COMMAND_L] = val;
|
||||
nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_L] = val;
|
||||
// actually update the mappings
|
||||
nv3_update_mappings();
|
||||
break;
|
||||
case PCI_REG_COMMAND_H:
|
||||
nv3->pci_config.pci_regs[PCI_REG_COMMAND_H] = val;
|
||||
nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND_H] = val;
|
||||
// actually update the mappings
|
||||
nv3_update_mappings();
|
||||
break;
|
||||
// pci status register
|
||||
case PCI_REG_STATUS_L:
|
||||
nv3->pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE);
|
||||
nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_L] = val | (NV3_PCI_STATUS_L_66MHZ_CAPABLE);
|
||||
break;
|
||||
case PCI_REG_STATUS_H:
|
||||
nv3->pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
|
||||
nv3->nvbase.pci_config.pci_regs[PCI_REG_STATUS_H] = val | (NV3_PCI_STATUS_H_FAST_DEVSEL_TIMING << NV3_PCI_STATUS_H_DEVSEL_TIMING);
|
||||
break;
|
||||
//TODO: ACTUALLY REMAP THE MMIO AND NV_USER
|
||||
case NV3_PCI_CFG_BAR0_BASE_ADDRESS:
|
||||
nv3->nvbase.bar0_mmio_base = val << 24;
|
||||
nv3_update_mappings();
|
||||
@@ -520,9 +510,9 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
|
||||
// make sure we are actually toggling the vbios, not the rom base
|
||||
if (addr == NV3_PCI_CFG_ENABLE_VBIOS)
|
||||
nv3->pci_config.vbios_enabled = (val & 0x01);
|
||||
nv3->nvbase.pci_config.vbios_enabled = (val & 0x01);
|
||||
|
||||
if (nv3->pci_config.vbios_enabled)
|
||||
if (nv3->nvbase.pci_config.vbios_enabled)
|
||||
{
|
||||
// First see if we simply wanted to change the VBIOS location
|
||||
|
||||
@@ -533,8 +523,8 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
{
|
||||
uint32_t old_addr = nv3->nvbase.vbios.mapping.base;
|
||||
// 9bit register
|
||||
uint32_t new_addr = nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 |
|
||||
nv3->pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16;
|
||||
uint32_t new_addr = nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_H] << 24 |
|
||||
nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_VBIOS_BASE_L] << 16;
|
||||
|
||||
// move it
|
||||
mem_mapping_set_addr(&nv3->nvbase.vbios.mapping, new_addr, 0x8000);
|
||||
@@ -555,7 +545,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
}
|
||||
break;
|
||||
case NV3_PCI_CFG_INT_LINE:
|
||||
nv3->pci_config.int_line = val;
|
||||
nv3->nvbase.pci_config.int_line = val;
|
||||
break;
|
||||
//bar2-5 are not used and can't be written to
|
||||
case NV3_PCI_CFG_BAR_INVALID_START ... NV3_PCI_CFG_BAR_INVALID_END:
|
||||
@@ -564,7 +554,7 @@ void nv3_pci_write(int32_t func, int32_t addr, uint8_t val, void* priv)
|
||||
// these are mirrored to the subsystem id and also stored in the ROMBIOS
|
||||
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_START:
|
||||
case NV3_PCI_CFG_SUBSYSTEM_ID_MIRROR_END:
|
||||
nv3->pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val;
|
||||
nv3->nvbase.pci_config.pci_regs[NV3_PCI_CFG_SUBSYSTEM_ID + (addr & 0x03)] = val;
|
||||
break;
|
||||
|
||||
case NV3_AGP_START ... NV3_AGP_END:
|
||||
@@ -855,16 +845,14 @@ void nv3_svga_write(uint16_t addr, uint8_t val, void* priv)
|
||||
i2c_gpio_set(nv3->nvbase.i2c, scl, sda);
|
||||
break;
|
||||
}
|
||||
/* [6:0] contains cursorAddr [23:17] */
|
||||
/* [6:0] contains cursorAddr [22:16] */
|
||||
case NV3_CRTC_REGISTER_CURSOR_ADDR0:
|
||||
nv3->pramdac.cursor_address |= val << 17; //bit7 technically ignored, but nv don't care, so neither do we
|
||||
nv3->pramdac.cursor_address |= ((val & 0x7F) << 12); //bit7 technically ignored, but nv don't care, so neither do we
|
||||
break;
|
||||
/* [7:2] contains cursorAddr [16:11] */
|
||||
case NV3_CRTC_REGISTER_CURSOR_ADDR1:
|
||||
nv3->pramdac.cursor_address |= (val >> 2) << 13; // bit0 and 1 aren't part of the address
|
||||
nv3->pramdac.cursor_address |= ((val & 0xF8) << 4); // bit0 and 1 aren't part of the address
|
||||
break;
|
||||
|
||||
|
||||
}
|
||||
|
||||
/* Recalculate the timings if we actually changed them
|
||||
@@ -1130,7 +1118,6 @@ void nv3_init_mappings_mmio(void)
|
||||
nv3_ramin_write32,
|
||||
NULL, MEM_MAPPING_EXTERNAL, nv3);
|
||||
|
||||
|
||||
mem_mapping_add(&nv3->nvbase.ramin_mapping_mirror, 0, 0,
|
||||
nv3_ramin_read8,
|
||||
nv3_ramin_read16,
|
||||
@@ -1140,14 +1127,11 @@ void nv3_init_mappings_mmio(void)
|
||||
nv3_ramin_write32,
|
||||
NULL, MEM_MAPPING_EXTERNAL, nv3);
|
||||
|
||||
|
||||
}
|
||||
|
||||
void nv3_init_mappings_svga(void)
|
||||
{
|
||||
nv_log("Initialising SVGA core memory mapping\n");
|
||||
|
||||
|
||||
// setup the svga mappings
|
||||
mem_mapping_add(&nv3->nvbase.framebuffer_mapping, 0, 0,
|
||||
nv3_dfb_read8,
|
||||
@@ -1191,20 +1175,20 @@ void nv3_update_mappings(void)
|
||||
|
||||
nv_log("\nMemory Mapping Config Change:\n");
|
||||
|
||||
(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n");
|
||||
(nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n");
|
||||
|
||||
io_removehandler(0x03c0, 0x0020,
|
||||
nv3_svga_read, NULL, NULL,
|
||||
nv3_svga_write, NULL, NULL,
|
||||
nv3);
|
||||
|
||||
if (nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
|
||||
if (nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
|
||||
io_sethandler(0x03c0, 0x0020,
|
||||
nv3_svga_read, NULL, NULL,
|
||||
nv3_svga_write, NULL, NULL,
|
||||
nv3);
|
||||
|
||||
if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
|
||||
if (!(nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
|
||||
{
|
||||
nv_log("The memory was turned off, not much is going to happen.\n");
|
||||
return;
|
||||
@@ -1412,8 +1396,8 @@ void* nv3_init(const device_t *info)
|
||||
nv3_init_mappings();
|
||||
|
||||
// make us actually exist
|
||||
nv3->pci_config.int_line = 0xFF; // per datasheet
|
||||
nv3->pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM;
|
||||
nv3->nvbase.pci_config.int_line = 0xFF; // per datasheet
|
||||
nv3->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] = PCI_COMMAND_IO | PCI_COMMAND_MEM;
|
||||
|
||||
// svga is done, so now initialise the real gpu
|
||||
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
*
|
||||
* This file is part of the 86Box distribution.
|
||||
*
|
||||
* NV3 bringup and device emulation.
|
||||
* NV4 bringup and device emulation.
|
||||
*
|
||||
*
|
||||
* Authors: Connor Hyde, <mario64crashed@gmail.com> I need a better email address ;^)
|
||||
@@ -29,9 +29,178 @@
|
||||
|
||||
nv4_t* nv4;
|
||||
|
||||
// Initialise the MMIO mappings
|
||||
void nv4_init_mappings_mmio(void)
|
||||
{
|
||||
nv_log("Initialising MMIO mapping\n");
|
||||
|
||||
// 0x0 - 1000000: regs
|
||||
// 0x1000000-2000000
|
||||
|
||||
// initialize the mmio mapping
|
||||
mem_mapping_add(&nv4->nvbase.mmio_mapping, 0, 0,
|
||||
nv4_mmio_read8,
|
||||
nv4_mmio_read16,
|
||||
nv4_mmio_read32,
|
||||
nv4_mmio_write8,
|
||||
nv4_mmio_write16,
|
||||
nv4_mmio_write32,
|
||||
NULL, MEM_MAPPING_EXTERNAL, nv4);
|
||||
|
||||
// initialize the mmio mapping
|
||||
mem_mapping_add(&nv4->nvbase.ramin_mapping, 0, 0,
|
||||
nv4_ramin_read8,
|
||||
nv4_ramin_read16,
|
||||
nv4_ramin_read32,
|
||||
nv4_ramin_write8,
|
||||
nv4_ramin_write16,
|
||||
nv4_ramin_write32,
|
||||
NULL, MEM_MAPPING_EXTERNAL, nv4);
|
||||
|
||||
}
|
||||
|
||||
void nv4_init_mappings_svga(void)
|
||||
{
|
||||
nv_log("Initialising SVGA core memory mapping\n");
|
||||
// setup the svga mappings
|
||||
mem_mapping_add(&nv4->nvbase.framebuffer_mapping, 0, 0,
|
||||
nv4_dfb_read8,
|
||||
nv4_dfb_read16,
|
||||
nv4_dfb_read32,
|
||||
nv4_dfb_write8,
|
||||
nv4_dfb_write16,
|
||||
nv4_dfb_write32,
|
||||
nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga);
|
||||
|
||||
// the SVGA/LFB mapping is also mirrored
|
||||
mem_mapping_add(&nv4->nvbase.framebuffer_mapping_mirror, 0, 0,
|
||||
nv4_dfb_read8,
|
||||
nv4_dfb_read16,
|
||||
nv4_dfb_read32,
|
||||
nv4_dfb_write8,
|
||||
nv4_dfb_write16,
|
||||
nv4_dfb_write32,
|
||||
nv4->nvbase.svga.vram, 0, &nv4->nvbase.svga);
|
||||
|
||||
io_sethandler(NV4_CIO_START, NV4_CIO_SIZE,
|
||||
nv4_svga_read, NULL, NULL,
|
||||
nv4_svga_write, NULL, NULL,
|
||||
nv4);
|
||||
}
|
||||
|
||||
void nv4_init_mappings(void)
|
||||
{
|
||||
nv4_init_mappings_mmio();
|
||||
nv4_init_mappings_svga();
|
||||
}
|
||||
|
||||
// Updates the mappings after initialisation.
|
||||
void nv4_update_mappings(void)
|
||||
{
|
||||
// sanity check
|
||||
if (!nv4)
|
||||
return;
|
||||
|
||||
// setting this to 0 doesn't seem to disable it, based on the datasheet
|
||||
|
||||
nv_log("\nMemory Mapping Config Change:\n");
|
||||
|
||||
(nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) ? nv_log("Enable I/O\n") : nv_log("Disable I/O\n");
|
||||
|
||||
io_removehandler(NV4_CIO_START, NV4_CIO_SIZE,
|
||||
nv4_svga_read, NULL, NULL,
|
||||
nv4_svga_write, NULL, NULL,
|
||||
nv4);
|
||||
|
||||
if (nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
|
||||
io_sethandler(NV4_CIO_START, NV4_CIO_SIZE,
|
||||
nv4_svga_read, NULL, NULL,
|
||||
nv4_svga_write, NULL, NULL,
|
||||
nv4);
|
||||
|
||||
if (!(nv4->nvbase.pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
|
||||
{
|
||||
nv_log("The memory was turned off, not much is going to happen.\n");
|
||||
return;
|
||||
}
|
||||
|
||||
// turn off bar0 and bar1 by defualt
|
||||
mem_mapping_disable(&nv4->nvbase.mmio_mapping);
|
||||
mem_mapping_disable(&nv4->nvbase.framebuffer_mapping);
|
||||
mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror);
|
||||
mem_mapping_disable(&nv4->nvbase.ramin_mapping);
|
||||
|
||||
// Setup BAR0 (MMIO)
|
||||
|
||||
nv_log("BAR0 (MMIO Base) = 0x%08x\n", nv4->nvbase.bar0_mmio_base);
|
||||
|
||||
if (nv4->nvbase.bar0_mmio_base)
|
||||
{
|
||||
mem_mapping_set_addr(&nv4->nvbase.mmio_mapping, nv4->nvbase.bar0_mmio_base, NV4_MMIO_SIZE);
|
||||
mem_mapping_set_addr(&nv4->nvbase.ramin_mapping, nv4->nvbase.bar0_mmio_base + NV4_PRAMIN_START, NV4_PRAMIN_SIZE);
|
||||
}
|
||||
|
||||
// if this breaks anything, remove it
|
||||
nv_log("BAR1 (Linear Framebuffer & VRAM) = 0x%08x\n", nv4->nvbase.bar1_lfb_base);
|
||||
|
||||
if (nv4->nvbase.bar1_lfb_base)
|
||||
{
|
||||
if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_16MB)
|
||||
{
|
||||
// we don't need this one in the case of 16mb,
|
||||
mem_mapping_disable(&nv4->nvbase.framebuffer_mapping_mirror);
|
||||
mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_16MB);
|
||||
}
|
||||
else if (nv4->nvbase.vram_amount == NV4_VRAM_SIZE_8MB)
|
||||
{
|
||||
mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping, nv4->nvbase.bar1_lfb_base, NV4_VRAM_SIZE_8MB);
|
||||
mem_mapping_set_addr(&nv4->nvbase.framebuffer_mapping_mirror, nv4->nvbase.bar1_lfb_base + NV4_VRAM_SIZE_8MB, NV4_VRAM_SIZE_8MB);
|
||||
}
|
||||
}
|
||||
|
||||
// Did we change the banked SVGA mode?
|
||||
switch (nv4->nvbase.svga.gdcreg[NV4_PRMVIO_GX_MISC_INDEX] & 0x0c)
|
||||
{
|
||||
case NV4_PRMVIO_GX_MISC_BANKED_128K_A0000:
|
||||
nv_log("SVGA Banked Mode = 128K @ A0000h\n");
|
||||
mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x20000); // 128kb @ 0xA0000
|
||||
nv4->nvbase.svga.banked_mask = 0x1FFFF;
|
||||
break;
|
||||
case NV4_PRMVIO_GX_MISC_BANKED_64K_A0000:
|
||||
nv_log("SVGA Banked Mode = 64K @ A0000h\n");
|
||||
mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xA0000, 0x10000); // 64kb @ 0xA0000
|
||||
nv4->nvbase.svga.banked_mask = 0xFFFF;
|
||||
break;
|
||||
case NV4_PRMVIO_GX_MISC_BANKED_32K_B0000:
|
||||
nv_log("SVGA Banked Mode = 32K @ B0000h\n");
|
||||
mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB0000, 0x8000); // 32kb @ 0xB0000
|
||||
nv4->nvbase.svga.banked_mask = 0x7FFF;
|
||||
break;
|
||||
case NV4_PRMVIO_GX_MISC_BANKED_32K_B8000:
|
||||
nv_log("SVGA Banked Mode = 32K @ B8000h\n");
|
||||
mem_mapping_set_addr(&nv4->nvbase.svga.mapping, 0xB8000, 0x8000); // 32kb @ 0xB8000
|
||||
nv4->nvbase.svga.banked_mask = 0x7FFF;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void nv4_init()
|
||||
{
|
||||
nv4 = calloc(1, sizeof(nv4_t));
|
||||
|
||||
if (!nv4->nvbase.vram_amount)
|
||||
nv4->nvbase.vram_amount = device_get_config_int("vram_size");
|
||||
|
||||
/* Set log device name based on card model */
|
||||
const char* log_device_name = "NV4";
|
||||
|
||||
if (device_get_config_int("nv_debug_fulllog"))
|
||||
nv4->nvbase.log = log_open("NV4");
|
||||
else
|
||||
nv4->nvbase.log = log_open_cyclic("NV4");
|
||||
|
||||
nv_log_set_device(nv4->nvbase.log);
|
||||
}
|
||||
|
||||
void* nv4_init_stb4400(const device_t *info)
|
||||
@@ -71,7 +240,7 @@ int32_t nv4_available(void)
|
||||
return (rom_present(NV4_VBIOS_STB_REVA));
|
||||
}
|
||||
|
||||
// NV3 (RIVA 128)
|
||||
// NV4 (RIVA 128)
|
||||
// AGP
|
||||
// 8MB or 16MB VRAM
|
||||
const device_t nv4_device_agp =
|
||||
|
||||
1310
src/video/nv/nv4/nv4_core_io.c
Normal file
1310
src/video/nv/nv4/nv4_core_io.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user