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clang format 82815/ICH2 related things

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This commit is contained in:
Jasmine Iwanek
2022-08-25 23:15:42 -04:00
parent 49c9ca3a99
commit e06a83a722
29 changed files with 1108 additions and 1224 deletions
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208
src/device/hwm_nsc366.c
View File

@@ -35,20 +35,23 @@
#include <86box/nsc366.h>
/* Fan Algorithms */
#define FAN_TO_REG(val, div) ((val) <= 100 ? 0 : 480000 / ((val) * (div)))
#define FAN_DIV_FROM_REG(val) (1 << (((val) >> 5) & 0x03))
#define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : 480000 / ((val) * (div)))
#define FAN_TO_REG(val, div) ((val) <= 100 ? 0 : 480000 / ((val) * (div)))
#define FAN_DIV_FROM_REG(val) (1 << (((val) >> 5) & 0x03))
#define FAN_FROM_REG(val, div) ((val) == 0 ? 0 : 480000 / ((val) * (div)))
/* Voltage Algorithms */
#define IN_TO_REG(val, ref) ((val) < 0 ? 0 : (val) * 256 >= (ref) * 255 ? 255 : ((val) * 256 + (ref) / 2) / (ref))
#define IN_FROM_REG(val, ref) (((val) * (ref) + 128) / 256)
#define VREF (dev->vlm_config_global[0x08] & 2) ? 3025 : 2966 //VREF taken from pc87360.c
#define VLM_BANK dev->vlm_config_global[0x09]
#define IN_TO_REG(val, ref) ((val) < 0 ? 0 : (val) *256 >= (ref) *255 ? 255 \
: ((val) *256 + (ref) / 2) / (ref))
#define IN_FROM_REG(val, ref) (((val) * (ref) + 128) / 256)
#define VREF (dev->vlm_config_global[0x08] & 2) ? 3025 : 2966 // VREF taken from pc87360.c
#define VLM_BANK dev->vlm_config_global[0x09]
/* Temperature Algorithms */
#define TEMP_TO_REG(val) ((val) < -55000 ? -55 : (val) > 127000 ? 127 : (val) < 0 ? ((val) - 500) / 1000 : ((val) + 500) / 1000)
#define TEMP_FROM_REG(val) ((val) * 1000)
#define TMS_BANK dev->tms_config_global[0x09]
#define TEMP_TO_REG(val) ((val) < -55000 ? -55 : (val) > 127000 ? 127 \
: (val) < 0 ? ((val) -500) / 1000 \
: ((val) + 500) / 1000)
#define TEMP_FROM_REG(val) ((val) *1000)
#define TMS_BANK dev->tms_config_global[0x09]
#ifdef ENABLE_NSC366_HWM_LOG
int nsc366_hwm_do_log = ENABLE_NSC366_HWM_LOG;
@@ -58,75 +61,73 @@ nsc366_hwm_log(const char *fmt, ...)
va_list ap;
if (nsc366_hwm_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define nsc366_hwm_log(fmt, ...)
# define nsc366_hwm_log(fmt, ...)
#endif
/* Fans */
static void
nsc366_fscm_write(uint16_t addr, uint8_t val, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
nsc366_hwm_log("NSC366 Fan Control: Write 0x%02x to register 0x%02x\n", val, addr);
switch(addr)
{
switch (addr) {
case 0x00:
case 0x02:
case 0x04:
dev->fscm_config[addr] = val;
break;
break;
case 0x01:
case 0x03:
case 0x05:
dev->fscm_config[addr] = val;
break;
break;
case 0x06:
case 0x09:
case 0x0c:
dev->fscm_config[addr] = val;
break;
break;
case 0x08:
case 0x0b:
case 0x0d:
dev->fscm_config[addr] = (val & 0x78) | 1;
break;
break;
}
}
static uint8_t
nsc366_fscm_read(uint16_t addr, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
switch(addr)
{
switch (addr) {
case 0x00 ... 0x06:
case 0x08 ... 0x09:
case 0x0b ... 0x0c:
return dev->fscm_config[addr];
case 0x07:
case 0x0a:
case 0x0d:
if(((addr == 0x07) && !!(dev->fscm_enable & 1)) || ((addr == 0x0a) && !!(dev->fscm_enable & 2)) || ((addr == 0x0d) && !!(dev->fscm_enable & 4))) {
if (((addr == 0x07) && !!(dev->fscm_enable & 1)) || ((addr == 0x0a) && !!(dev->fscm_enable & 2)) || ((addr == 0x0d) && !!(dev->fscm_enable & 4))) {
nsc366_hwm_log("NSC366 Fan Control: Reading %d RPM's from Bank %d\n", FAN_FROM_REG(dev->fscm_config[addr], FAN_DIV_FROM_REG(dev->fscm_config[0x06])), (addr - 7) / 3);
return dev->fscm_config[addr];
}
else return 0;
} else
return 0;
default:
return 0;
@@ -136,12 +137,12 @@ nsc366_fscm_read(uint16_t addr, void *priv)
void
nsc366_update_fscm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
{
if(dev->fscm_addr != 0)
if (dev->fscm_addr != 0)
io_removehandler(dev->fscm_addr, 15, nsc366_fscm_read, NULL, NULL, nsc366_fscm_write, NULL, NULL, dev);
dev->fscm_addr = addr;
if((addr != 0) && enable)
if ((addr != 0) && enable)
io_sethandler(addr, 15, nsc366_fscm_read, NULL, NULL, nsc366_fscm_write, NULL, NULL, dev);
}
@@ -149,83 +150,78 @@ nsc366_update_fscm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
static void
nsc366_vlm_write(uint16_t addr, uint8_t val, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
if(addr <= 9)
if (addr <= 9)
nsc366_hwm_log("NSC366 Voltage Monitor: Write 0x%02x to register 0x%02x\n", val, addr);
else
nsc366_hwm_log("NSC366 Voltage Monitor: Write 0x%02x to register 0x%02x of bank %d\n", val, addr, VLM_BANK);
switch(addr)
{
switch (addr) {
case 0x02 ... 0x04:
dev->vlm_config_global[addr] = val;
break;
break;
case 0x05:
dev->vlm_config_global[addr] = val & 0x3f;
break;
break;
case 0x06:
dev->vlm_config_global[addr] = val & 0xc0;
break;
break;
case 0x07:
dev->vlm_config_global[addr] = val & 0x3f;
break;
break;
case 0x08:
dev->vlm_config_global[addr] = val & 3;
break;
break;
case 0x09:
dev->vlm_config_global[addr] = val & 0x1f;
break;
break;
case 0x0a:
if(VLM_BANK < 13)
if (VLM_BANK < 13)
dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val & 1;
break;
break;
case 0x0c ... 0x0e:
if(VLM_BANK < 13)
dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val;
break;
if (VLM_BANK < 13)
dev->vlm_config_bank[VLM_BANK][addr - 0x0a] = val;
break;
}
}
static uint8_t
nsc366_vlm_read(uint16_t addr, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
switch(addr)
{
switch (addr) {
case 0x00 ... 0x09:
return dev->vlm_config_global[addr];
case 0x0a:
case 0x0c ... 0x0e:
if(VLM_BANK < 13)
if (VLM_BANK < 13)
return dev->vlm_config_bank[VLM_BANK][addr - 0x0a];
else
return 0;
case 0x0b:
if (VLM_BANK < 13) {
if (dev->vlm_config_bank[VLM_BANK][0] & 1) {
nsc366_hwm_log("NSC366 Voltage Monitor: Reading %d Volts from Bank %d\n", IN_FROM_REG(dev->vlm_config_bank[VLM_BANK][1], VREF), VLM_BANK);
return dev->vlm_config_bank[VLM_BANK][1];
}
else
} else
return 0;
}
else
} else
return 0;
default:
@@ -236,12 +232,12 @@ nsc366_vlm_read(uint16_t addr, void *priv)
void
nsc366_update_vlm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
{
if(dev->vlm_addr != 0)
if (dev->vlm_addr != 0)
io_removehandler(dev->vlm_addr, 15, nsc366_vlm_read, NULL, NULL, nsc366_vlm_write, NULL, NULL, dev);
dev->vlm_addr = addr;
if((addr != 0) && enable)
if ((addr != 0) && enable)
io_sethandler(addr, 15, nsc366_vlm_read, NULL, NULL, nsc366_vlm_write, NULL, NULL, dev);
}
@@ -249,71 +245,69 @@ nsc366_update_vlm_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
static void
nsc366_tms_write(uint16_t addr, uint8_t val, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
if(addr <= 9)
if (addr <= 9)
nsc366_hwm_log("NSC366 Temperature Monitor: Write 0x%02x to register 0x%02x\n", val, addr);
else
nsc366_hwm_log("NSC366 Temperature Monitor: Write 0x%02x to register 0x%02x of bank %d\n", val, addr, TMS_BANK);
switch(addr)
{
switch (addr) {
case 0x02:
dev->tms_config_global[addr] = val & 0x3f;
break;
break;
case 0x04:
dev->tms_config_global[addr] = val & 0x3f;
break;
break;
case 0x08:
dev->tms_config_global[addr] = val & 3;
break;
break;
case 0x09:
dev->tms_config_global[addr] = val & 3;
break;
break;
case 0x0a:
if(TMS_BANK < 3)
if (TMS_BANK < 3)
dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val & 1;
break;
break;
case 0x0c ... 0x0e:
if(TMS_BANK < 3)
dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val;
break;
if (TMS_BANK < 3)
dev->tms_config_bank[TMS_BANK][addr - 0x0a] = val;
break;
}
}
static uint8_t
nsc366_tms_read(uint16_t addr, void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
addr &= 0x000f;
switch(addr)
{
switch (addr) {
case 0x00 ... 0x09:
return dev->tms_config_global[addr];
case 0x0a:
case 0x0c ... 0x0e:
if(TMS_BANK < 4)
if (TMS_BANK < 4)
return dev->tms_config_bank[TMS_BANK][addr - 0x0a];
else return 0;
else
return 0;
case 0x0b:
if(TMS_BANK < 4) {
if (dev->vlm_config_bank[VLM_BANK][0] & 1) {
if (TMS_BANK < 4) {
if (dev->vlm_config_bank[VLM_BANK][0] & 1) {
nsc366_hwm_log("NSC366 Temperature Monitor: Reading %d Degrees Celsius from Bank %d\n", TEMP_FROM_REG(dev->tms_config_bank[TMS_BANK][1]), TMS_BANK);
return dev->tms_config_bank[TMS_BANK][1];
}
else return 0;
} else
return 0;
}
default:
@@ -324,24 +318,24 @@ nsc366_tms_read(uint16_t addr, void *priv)
void
nsc366_update_tms_io(int enable, uint16_t addr, nsc366_hwm_t *dev)
{
if(dev->vlm_addr != 0)
if (dev->vlm_addr != 0)
io_removehandler(dev->tms_addr, 15, nsc366_tms_read, NULL, NULL, nsc366_tms_write, NULL, NULL, dev);
dev->tms_addr = addr;
if((addr != 0) && enable)
if ((addr != 0) && enable)
io_sethandler(addr, 15, nsc366_tms_read, NULL, NULL, nsc366_tms_write, NULL, NULL, dev);
}
#define TEMP_FROM_REG(val) ((val) * 1000)
#define TEMP_FROM_REG(val) ((val) *1000)
static void
nsc366_hwm_reset(void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
memset(dev->fscm_config, 0, sizeof(dev->fscm_config));
dev->fscm_enable = 0;
dev->fscm_addr = 0;
dev->fscm_addr = 0;
/* Get fan reports from defaults */
dev->fscm_config[0x07] = FAN_TO_REG(dev->values->fans[0], FAN_DIV_FROM_REG(dev->fscm_config[0x06]));
@@ -350,38 +344,36 @@ nsc366_hwm_reset(void *priv)
memset(dev->vlm_config_global, 0, sizeof(dev->vlm_config_global));
memset(dev->vlm_config_bank, 0, sizeof(dev->vlm_config_bank));
dev->vlm_addr = 0;
dev->vlm_addr = 0;
dev->vlm_config_global[0x08] = 3;
/* Get voltage reports from defaults */
for(int i = 0; i < 13; i++) {
for (int i = 0; i < 13; i++) {
dev->vlm_config_bank[i][1] = IN_TO_REG(dev->values->voltages[i], VREF);
}
memset(dev->tms_config_global, 0, sizeof(dev->tms_config_global));
memset(dev->tms_config_bank, 0, sizeof(dev->tms_config_bank));
dev->tms_addr = 0;
dev->tms_addr = 0;
dev->tms_config_global[0x08] = 3;
/* Get temperature reports from defaults */
for(int i = 0; i < 4; i++)
for (int i = 0; i < 4; i++)
dev->tms_config_bank[i][1] = TEMP_TO_REG(dev->values->temperatures[i]);
}
static void
nsc366_hwm_close(void *priv)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)priv;
nsc366_hwm_t *dev = (nsc366_hwm_t *) priv;
free(dev);
}
static void *
nsc366_hwm_init(const device_t *info)
{
nsc366_hwm_t *dev = (nsc366_hwm_t *)malloc(sizeof(nsc366_hwm_t));
nsc366_hwm_t *dev = (nsc366_hwm_t *) malloc(sizeof(nsc366_hwm_t));
memset(dev, 0, sizeof(nsc366_hwm_t));
/* Initialize the default values (HWM is incomplete still) */
@@ -392,13 +384,13 @@ nsc366_hwm_init(const device_t *info)
3000 /* FAN 2 */
},
{
30, /* Temperatures which are broken */
30, /* Temperatures which are broken */
30,
30,
30
},
{
0, /* Voltages which are broken */
0, /* Voltages which are broken */
0,
0,
0,
@@ -412,22 +404,22 @@ nsc366_hwm_init(const device_t *info)
0
}
};
hwm_values = defaults;
hwm_values = defaults;
dev->values = &hwm_values;
return dev;
}
const device_t nsc366_hwm_device = {
.name = "National Semiconductor NSC366 Hardware Monitor",
.name = "National Semiconductor NSC366 Hardware Monitor",
.internal_name = "nsc366_hwm",
.flags = 0,
.local = 0,
.init = nsc366_hwm_init,
.close = nsc366_hwm_close,
.reset = nsc366_hwm_reset,
.flags = 0,
.local = 0,
.init = nsc366_hwm_init,
.close = nsc366_hwm_close,
.reset = nsc366_hwm_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};

57
src/device/intel_ich2_gpio.c
View File

@@ -38,16 +38,15 @@ intel_ich2_gpio_log(const char *fmt, ...)
va_list ap;
if (intel_ich2_gpio_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define intel_ich2_gpio_log(fmt, ...)
# define intel_ich2_gpio_log(fmt, ...)
#endif
static void
intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
{
@@ -57,53 +56,51 @@ intel_ich2_gpio_write(uint16_t addr, uint8_t val, void *priv)
intel_ich2_gpio_log("Intel ICH2 GPIO: Write 0x%02x on GPIO Register 0x%02x\n", val, addr);
switch(addr)
{
switch (addr) {
/* GPIO Use Enable */
case 0x00:
dev->gpio_regs[addr] = val & 0x3f;
break;
break;
case 0x01:
dev->gpio_regs[addr] = val & 8;
break;
break;
case 0x02:
dev->gpio_regs[addr] = val & 0x20;
break;
break;
/* GPIO I/O Select */
case 0x07:
dev->gpio_regs[addr] = val & 0x1b;
break;
break;
/* GPIO Level */
case 0x0e:
dev->gpio_regs[addr] = val;
break;
break;
case 0x0f:
dev->gpio_regs[addr] = val & 0x1b;
dev->gpio_regs[addr] &= dev->gpio_regs[0x1b]; // Mask out whatever change if the bits aren't programmed as outputs.
break;
break;
/* GPIO Blink which is not Utilized */
case 0x1a:
dev->gpio_regs[addr] = val & 6;
break;
break;
case 0x1b:
dev->gpio_regs[addr] = val & 0x1a;
break;
break;
/* GPIO Signal Inverter */
case 0x2d:
dev->gpio_regs[addr] = val & 0x39;
break;
break;
}
}
static uint8_t
intel_ich2_gpio_read(uint16_t addr, void *priv)
{
@@ -113,7 +110,7 @@ intel_ich2_gpio_read(uint16_t addr, void *priv)
intel_ich2_gpio_log("Intel ICH2 GPIO: Reading 0x%02x from Register 0x%02x\n", dev->gpio_regs[addr], addr);
if(addr <= 0x2f)
if (addr <= 0x2f)
return dev->gpio_regs[addr];
else
return 0xff;
@@ -122,12 +119,12 @@ intel_ich2_gpio_read(uint16_t addr, void *priv)
void
intel_ich2_gpio_base(int enable, uint16_t addr, intel_ich2_gpio_t *dev)
{
if(dev->gpio_addr != 0)
if (dev->gpio_addr != 0)
io_removehandler(dev->gpio_addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
dev->gpio_addr = addr;
if((addr != 0) && enable)
if ((addr != 0) && enable)
io_sethandler(addr, 15, intel_ich2_gpio_read, NULL, NULL, intel_ich2_gpio_write, NULL, NULL, dev);
}
@@ -135,7 +132,7 @@ static void
intel_ich2_gpio_reset(void *priv)
{
intel_ich2_gpio_t *dev = (intel_ich2_gpio_t *) priv;
dev->gpio_addr = 0;
dev->gpio_addr = 0;
/* Enabled GPIO's */
dev->gpio_regs[0x00] = 0x80;
@@ -153,7 +150,6 @@ intel_ich2_gpio_reset(void *priv)
dev->gpio_regs[0x17] = 0x06;
}
static void
intel_ich2_gpio_close(void *priv)
{
@@ -162,7 +158,6 @@ intel_ich2_gpio_close(void *priv)
free(dev);
}
static void *
intel_ich2_gpio_init(const device_t *info)
{
@@ -175,15 +170,15 @@ intel_ich2_gpio_init(const device_t *info)
}
const device_t intel_ich2_gpio_device = {
.name = "Intel ICH2 GPIO",
.name = "Intel ICH2 GPIO",
.internal_name = "intel_ich2_gpio",
.flags = 0,
.local = 0,
.init = intel_ich2_gpio_init,
.close = intel_ich2_gpio_close,
.reset = intel_ich2_gpio_reset,
.flags = 0,
.local = 0,
.init = intel_ich2_gpio_init,
.close = intel_ich2_gpio_close,
.reset = intel_ich2_gpio_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};

28
src/device/intel_ich2_trap.c
View File

@@ -43,13 +43,13 @@ intel_ich2_trap_log(const char *fmt, ...)
va_list ap;
if (intel_ich2_trap_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define intel_ich2_trap_log(fmt, ...)
# define intel_ich2_trap_log(fmt, ...)
#endif
void
@@ -70,9 +70,9 @@ void
intel_ich2_device_trap_setup(uint8_t acpi_reg, uint8_t acpi_reg_val, uint16_t addr, uint16_t size, intel_ich2_trap_t *dev)
{
uint8_t acpi_reg_recieve = dev->acpi->regs.devtrap_en >> ((acpi_reg & 1) * 8); /* Trap register is 16-bit on ranged ACPIBASE + 48h-49h */
int enable = !!(acpi_reg_recieve & acpi_reg_val); /* If enabled. Settle in the I/O trap */
int enable = !!(acpi_reg_recieve & acpi_reg_val); /* If enabled. Settle in the I/O trap */
if(enable)
if (enable)
intel_ich2_trap_log("Intel ICH2 Trap: A new trap was setted up on address 0x%x with the size of %d\n", addr, size);
io_trap_remap(dev->trap, enable, addr, size);
@@ -101,15 +101,15 @@ intel_ich2_trap_init(const device_t *info)
}
const device_t intel_ich2_trap_device = {
.name = "Intel ICH2 Trap Hander",
.name = "Intel ICH2 Trap Hander",
.internal_name = "intel_ich2_trap",
.flags = 0,
.local = 0,
.init = intel_ich2_trap_init,
.close = intel_ich2_trap_close,
.reset = NULL,
.flags = 0,
.local = 0,
.init = intel_ich2_trap_init,
.close = intel_ich2_trap_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};

3
src/device/pci_bridge.c
View File

@@ -531,8 +531,7 @@ pci_bridge_init(const device_t *info)
dev->slot = pci_add_card(AGP_BRIDGE(dev->local) ? PCI_ADD_AGPBRIDGE : PCI_ADD_BRIDGE, pci_bridge_read, pci_bridge_write, dev);
if ((info->local != PCI_BRIDGE_INTEL_ICH2) && (info->local != AGP_BRIDGE_INTEL_815EP)) /* Let the machine configuration slot handle the absurd interrupt tables */
{
if ((info->local != PCI_BRIDGE_INTEL_ICH2) && (info->local != AGP_BRIDGE_INTEL_815EP)) { /* Let the machine configuration slot handle the absurd interrupt tables */
interrupt_count = sizeof(interrupts);
interrupt_mask = interrupt_count - 1;
if (dev->slot < 32) {

36
src/device/tco.c
View File

@@ -44,16 +44,15 @@ tco_log(const char *fmt, ...)
va_list ap;
if (tco_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define tco_log(fmt, ...)
# define tco_log(fmt, ...)
#endif
void
tco_timer_handler(void *priv)
{
@@ -61,7 +60,6 @@ tco_timer_handler(void *priv)
// tco_t *dev = (tco_t *) priv;
}
void
tco_irq_update(tco_t *dev, uint16_t new_irq)
{
@@ -75,7 +73,7 @@ tco_write(uint16_t addr, uint8_t val, tco_t *dev)
addr -= 0x60;
tco_log("TCO: Write 0x%02x to Register 0x%02x\n", val, addr);
switch(addr) {
switch (addr) {
case 0x00:
dev->regs[addr] = val;
break;
@@ -133,7 +131,6 @@ tco_write(uint16_t addr, uint8_t val, tco_t *dev)
}
}
uint8_t
tco_read(uint16_t addr, tco_t *dev)
{
@@ -142,11 +139,10 @@ tco_read(uint16_t addr, tco_t *dev)
if (addr <= 0x10) {
tco_log("TCO: Read 0x%02x from Register 0x%02x\n", dev->regs[addr], addr);
return dev->regs[addr];
}
else return 0;
} else
return 0;
}
static void
tco_reset(void *priv)
{
@@ -159,7 +155,6 @@ tco_reset(void *priv)
dev->regs[0x10] = 0x03;
}
static void
tco_close(void *priv)
{
@@ -168,7 +163,6 @@ tco_close(void *priv)
free(dev);
}
static void *
tco_init(const device_t *info)
{
@@ -181,15 +175,15 @@ tco_init(const device_t *info)
}
const device_t tco_device = {
.name = "Intel TCO",
.name = "Intel TCO",
.internal_name = "tco",
.flags = 0,
.local = 0,
.init = tco_init,
.close = tco_close,
.reset = tco_reset,
.flags = 0,
.local = 0,
.init = tco_init,
.close = tco_close,
.reset = tco_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};