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clang format 82815/ICH2 related things

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This commit is contained in:
Jasmine Iwanek
2022-08-25 23:15:42 -04:00
parent 49c9ca3a99
commit e06a83a722
29 changed files with 1108 additions and 1224 deletions
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28
src/mem/815ep_spd_hack.c
View File

@@ -34,8 +34,7 @@
uint8_t
intel_815ep_get_banking()
{
switch(MEM_SIZE_MB)
{
switch (MEM_SIZE_MB) {
case 32:
return 0x02;
@@ -74,50 +73,49 @@ intel_815ep_get_banking()
void
intel_815ep_spd_init()
{
switch(MEM_SIZE_MB)
{
switch (MEM_SIZE_MB) {
case 32:
spd_register(SPD_TYPE_SDRAM, 1, 32);
break;
break;
case 64:
spd_register(SPD_TYPE_SDRAM, 3, 32);
break;
break;
case 96:
spd_register(SPD_TYPE_SDRAM, 7, 32);
break;
break;
case 128:
spd_register(SPD_TYPE_SDRAM, 3, 64);
break;
break;
case 160:
spd_register(SPD_TYPE_SDRAM, 7, 64);
break;
break;
case 192:
spd_register(SPD_TYPE_SDRAM, 3, 96);
break;
break;
case 256:
spd_register(SPD_TYPE_SDRAM, 3, 128);
break;
break;
case 320:
spd_register(SPD_TYPE_SDRAM, 7, 128);
break;
break;
case 384:
spd_register(SPD_TYPE_SDRAM, 7, 128);
break;
break;
case 512:
spd_register(SPD_TYPE_SDRAM, 3, 256);
break;
break;
default:
pclog("Intel 815EP SPD Hack: Illegal Size %dMB\n", MEM_SIZE_MB);
break;
break;
}
}

106
src/mem/spd.c
View File

@@ -203,9 +203,9 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
min_module_size = SPD_MIN_SIZE_SDRAM;
break;
case SPD_TYPE_DDR:
min_module_size = SPD_MIN_SIZE_DDR;
break;
case SPD_TYPE_DDR:
min_module_size = SPD_MIN_SIZE_DDR;
break;
default:
spd_log("SPD: unknown RAM type %02X\n", ram_type);
@@ -341,59 +341,59 @@ spd_register(uint8_t ram_type, uint8_t slot_mask, uint16_t max_module_size)
sdram_data->checksum2 += spd_modules[slot]->data[i];
break;
case SPD_TYPE_DDR:
ddr_data = &spd_modules[slot]->ddr_data;
case SPD_TYPE_DDR:
ddr_data = &spd_modules[slot]->ddr_data;
ddr_data->bytes_used = 0x80;
ddr_data->spd_size = 0x08;
ddr_data->mem_type = ram_type;
ddr_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */
ddr_data->col_bits = 9;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
ddr_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
ddr_data->col_bits |= 9 << 4; /* same as first row, but just in case */
}
ddr_data->rows = 2;
ddr_data->data_width_lsb = 64;
ddr_data->signal_level = SPD_SIGNAL_LVTTL;
ddr_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
ddr_data->tac = 0x10;
ddr_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
ddr_data->sdram_width = 8;
ddr_data->tccd = 1;
ddr_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
ddr_data->banks = 4;
ddr_data->cas = 0x7f; /* CAS Latency */
ddr_data->cslat = ddr_data->we = 0x7f;
ddr_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
ddr_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
ddr_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
ddr_data->tac2 = ddr_data->tac3 = 0x10;
ddr_data->trp = ddr_data->trrd = ddr_data->trcd = ddr_data->tras = 1;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) {
/* Utilities interpret bank_density a bit differently on asymmetric modules. */
ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */
ddr_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */
} else {
ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */
}
ddr_data->ca_setup = ddr_data->data_setup = 0x15;
ddr_data->ca_hold = ddr_data->data_hold = 0x08;
ddr_data->bytes_used = 0x80;
ddr_data->spd_size = 0x08;
ddr_data->mem_type = ram_type;
ddr_data->row_bits = SPD_ROLLUP(6 + log2i(spd_modules[slot]->row1)); /* first row */
ddr_data->col_bits = 9;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) { /* the upper 4 bits of row_bits/col_bits should be 0 on a symmetric module */
ddr_data->row_bits |= SPD_ROLLUP(6 + log2i(spd_modules[slot]->row2)) << 4; /* second row, if different from first */
ddr_data->col_bits |= 9 << 4; /* same as first row, but just in case */
}
ddr_data->rows = 2;
ddr_data->data_width_lsb = 64;
ddr_data->signal_level = SPD_SIGNAL_LVTTL;
ddr_data->tclk = 0x75; /* 7.5 ns = 133.3 MHz */
ddr_data->tac = 0x10;
ddr_data->refresh_rate = SPD_SDR_REFRESH_SELF | SPD_REFRESH_NORMAL;
ddr_data->sdram_width = 8;
ddr_data->tccd = 1;
ddr_data->burst = SPD_SDR_BURST_PAGE | 1 | 2 | 4 | 8;
ddr_data->banks = 4;
ddr_data->cas = 0x7f; /* CAS Latency */
ddr_data->cslat = ddr_data->we = 0x7f;
ddr_data->dev_attr = SPD_SDR_ATTR_EARLY_RAS | SPD_SDR_ATTR_AUTO_PC | SPD_SDR_ATTR_PC_ALL | SPD_SDR_ATTR_W1R_BURST;
ddr_data->tclk2 = 0xA0; /* 10 ns = 100 MHz */
ddr_data->tclk3 = 0xF0; /* 15 ns = 66.7 MHz */
ddr_data->tac2 = ddr_data->tac3 = 0x10;
ddr_data->trp = ddr_data->trrd = ddr_data->trcd = ddr_data->tras = 1;
if (spd_modules[slot]->row1 != spd_modules[slot]->row2) {
/* Utilities interpret bank_density a bit differently on asymmetric modules. */
ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 2); /* first row */
ddr_data->bank_density |= 1 << (log2i(spd_modules[slot]->row2 >> 1) - 2); /* second row */
} else {
ddr_data->bank_density = 1 << (log2i(spd_modules[slot]->row1 >> 1) - 1); /* symmetric module = only one bit is set */
}
ddr_data->ca_setup = ddr_data->data_setup = 0x15;
ddr_data->ca_hold = ddr_data->data_hold = 0x08;
ddr_data->spd_rev = 0x10;
for (i = spd_write_part_no(ddr_data->part_no, "DDR", rows[row]);
i < sizeof(ddr_data->part_no); i++)
ddr_data->part_no[i] = ' '; /* part number should be space-padded */
ddr_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
ddr_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
ddr_data->mfg_year = 20;
ddr_data->mfg_week = 13;
ddr_data->spd_rev = 0x10;
for (i = spd_write_part_no(ddr_data->part_no, "DDR", rows[row]);
i < sizeof(ddr_data->part_no); i++)
ddr_data->part_no[i] = ' '; /* part number should be space-padded */
ddr_data->rev_code[0] = BCD8(EMU_VERSION_MAJ);
ddr_data->rev_code[1] = BCD8(EMU_VERSION_MIN);
ddr_data->mfg_year = 20;
ddr_data->mfg_week = 13;
for (i = 0; i < 63; i++)
ddr_data->checksum += spd_modules[slot]->data[i];
for (i = 0; i < 129; i++)
ddr_data->checksum2 += spd_modules[slot]->data[i];
break;
for (i = 0; i < 63; i++)
ddr_data->checksum += spd_modules[slot]->data[i];
for (i = 0; i < 129; i++)
ddr_data->checksum2 += spd_modules[slot]->data[i];
break;
}
row++;