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clang format 82815/ICH2 related things

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This commit is contained in:
Jasmine Iwanek
2022-08-25 23:15:42 -04:00
parent 49c9ca3a99
commit e06a83a722
29 changed files with 1108 additions and 1224 deletions
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187
src/sio/sio_it8702.c
View File

@@ -45,14 +45,14 @@ typedef struct
{
int ldn, unlock;
uint8_t index, regs[15], sw_lock,
enable[11],
b_addr[4][11],
irq[11],
dma[11],
d_spec[15][11];
uint8_t index, regs[15], sw_lock,
enable[11],
b_addr[4][11],
irq[11],
dma[11],
d_spec[15][11];
fdc_t *fdc;
fdc_t *fdc;
serial_t *uart[2];
} it8702_t;
@@ -64,22 +64,21 @@ it8702_log(const char *fmt, ...)
va_list ap;
if (it8702_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define it8702_log(fmt, ...)
# define it8702_log(fmt, ...)
#endif
static void it8702_reset(void *priv);
static void
it8702_unlock(uint8_t val, it8702_t *dev)
{
if(val == 0x87) { /* The unlock mechanism of the CUSL2-C doesn't work as intended so we just unlock it with 87h only for now */
if (val == 0x87) { /* The unlock mechanism of the CUSL2-C doesn't work as intended so we just unlock it with 87h only for now */
it8702_log("IT8702 Unlock: Unlocking\n");
dev->unlock = 1;
}
@@ -88,7 +87,7 @@ it8702_unlock(uint8_t val, it8702_t *dev)
static void
it8702_sw_lock(uint8_t val, it8702_t *dev)
{
if(val & 0x80)
if (val & 0x80)
dev->sw_lock = val;
else
dev->sw_lock = 0;
@@ -98,17 +97,17 @@ static void
it8702_fdc(it8702_t *dev)
{
uint16_t base = ((dev->b_addr[0][0] & 0x0f) << 8) | (dev->b_addr[1][0] & 0xf8);
int irq = dev->irq[0];
int dma = dev->dma[0];
int irq = dev->irq[0];
int dma = dev->dma[0];
fdc_remove(dev->fdc);
if(dev->enable[0] & 1) {
if (dev->enable[0] & 1) {
it8702_log("IT8702 FDC: Enabled with Base: 0x%x IRQ: %d and DMA: %d\n", base, irq, dma);
fdc_set_base(dev->fdc, base);
fdc_set_irq(dev->fdc, irq);
fdc_set_dma_ch(dev->fdc, dma);
if(dev->d_spec[0][0] & 1)
if (dev->d_spec[0][0] & 1)
fdc_writeprotect(dev->fdc);
fdc_update_drvrate(dev->fdc, 0, dev->d_spec[1][0] & 3);
@@ -120,11 +119,10 @@ static void
it8702_uart(int uart, it8702_t *dev)
{
uint16_t base = ((dev->b_addr[0][2 + uart] & 0x0f) << 8) | (dev->b_addr[1][2 + uart] & 0xf8);
int irq = dev->irq[2 + uart];
int irq = dev->irq[2 + uart];
serial_remove(dev->uart[uart]);
if(dev->enable[2 + uart])
{
if (dev->enable[2 + uart]) {
it8702_log("IT8702 Serial %c: Enabled with Base: 0x%x IRQ: %d\n", 'A' + uart, base, irq);
serial_setup(dev->uart[uart], base, irq);
serial_set_clock_src(dev->uart[uart], 24444444 / ((dev->d_spec[0][2 + uart] >> 1) ? 12 : 13));
@@ -135,11 +133,11 @@ static void
it8702_lpt(it8702_t *dev)
{
uint16_t base = ((dev->b_addr[0][1] & 0x0f) << 8) | (dev->b_addr[1][1] & 0xf8);
int irq = dev->irq[1];
int irq = dev->irq[1];
lpt1_remove();
lpt2_remove();
if(dev->enable[1] & 1) {
if (dev->enable[1] & 1) {
it8702_log("IT8702 LPT1: Enabled with Base: 0x%x IRQ: %d\n", base, irq);
lpt1_init(base);
lpt1_irq(irq);
@@ -150,21 +148,18 @@ it8702_lpt(it8702_t *dev)
static void
it8702_ldn(it8702_t *dev)
{
switch(dev->ldn)
{
switch (dev->ldn) {
case 0:
it8702_fdc(dev);
break;
break;
case 1:
it8702_lpt(dev);
break;
break;
case 2 ... 3:
it8702_uart((dev->ldn == 3), dev);
break;
break;
}
}
@@ -173,150 +168,147 @@ it8702_write(uint16_t addr, uint8_t val, void *priv)
{
it8702_t *dev = (it8702_t *) priv;
if(addr == 0x2e) {
if(dev->unlock)
if (addr == 0x2e) {
if (dev->unlock)
dev->index = val;
else
it8702_unlock(val, dev);
}
else if(addr == 0x2f) {
switch(dev->index)
{
} else if (addr == 0x2f) {
switch (dev->index) {
/* Global Registers */
case 0x02: /* Configure Control */
if(val & 2) {
if (val & 2) {
it8702_log("IT8702 Unlock: Locking\n");
dev->unlock = 0;
}
if(val & 1) {
if (val & 1) {
it8702_log("IT8702: Resetting\n");
it8702_reset(dev);
}
break;
break;
case 0x07:
dev->ldn = val;
break;
break;
case 0x23:
if(!(dev->sw_lock & 0x80))
if (!(dev->sw_lock & 0x80))
dev->regs[dev->index - 0x20] = val & 0xd9;
break;
break;
case 0x24:
dev->regs[dev->index - 0x20] = val & 0x00;
break;
break;
case 0x25 ... 0x28:
if(dev->ldn == 7)
if (dev->ldn == 7)
dev->regs[dev->index - 0x20] = val;
break;
break;
case 0x29:
if(dev->ldn == 7)
if (dev->ldn == 7)
dev->regs[dev->index - 0x20] = val & 0x3f;
break;
break;
case 0x2a:
if(dev->ldn == 7)
if (dev->ldn == 7)
dev->regs[dev->index - 0x20] = val & 0x7f;
break;
break;
case 0x2b:
if(!(dev->sw_lock & 0x80)) {
if (!(dev->sw_lock & 0x80)) {
dev->regs[dev->index - 0x20] = val;
it8702_sw_lock(val, dev);
}
break;
break;
case 0x2c:
dev->regs[dev->index - 0x20] = val & 0x1c;
break;
break;
case 0x30:
if(dev->ldn < 11)
if (dev->ldn < 11)
dev->enable[dev->ldn] = val & 1;
it8702_ldn(dev);
break;
break;
case 0x60 ... 0x63:
if(dev->ldn < 11)
if (dev->ldn < 11)
dev->b_addr[dev->index & 3][dev->ldn] = val;
it8702_ldn(dev);
break;
break;
case 0x70:
if(dev->ldn < 11)
if (dev->ldn < 11)
dev->irq[dev->ldn] = val & 0x0f;
it8702_ldn(dev);
break;
break;
case 0x74:
if(dev->ldn < 11)
if (dev->ldn < 11)
dev->dma[dev->ldn] = val & 0x0f;
it8702_ldn(dev);
break;
break;
case 0xf0 ... 0xf0:
if(dev->ldn < 11)
if (dev->ldn < 11)
dev->d_spec[dev->index & 0x0f][dev->ldn] = val;
it8702_ldn(dev);
break;
break;
}
}
}
static uint8_t
it8702_read(uint16_t addr, void *priv)
{
it8702_t *dev = (it8702_t *) priv;
if(addr == 0x2e) {
if (addr == 0x2e) {
return dev->index;
} else if(addr == 0x2f) {
if(dev->index == 0x02) { /* The Configure Control register is Write Only */
} else if (addr == 0x2f) {
if (dev->index == 0x02) { /* The Configure Control register is Write Only */
return 0xff;
} else {
switch(dev->index) {
} else {
switch (dev->index) {
case 0x07:
return dev->ldn;
case 0x20 ... 0x2f:
return dev->regs[dev->index - 0x20];
case 0x30:
if(dev->ldn < 11)
if (dev->ldn < 11)
return dev->enable[dev->ldn];
else
return 0xff;
case 0x60 ... 0x63:
if(dev->ldn < 11)
if (dev->ldn < 11)
return dev->b_addr[dev->index & 3][dev->ldn];
else
return 0xff;
case 0x70:
if(dev->ldn < 11)
if (dev->ldn < 11)
return dev->irq[dev->ldn];
else
return 0xff;
case 0x74:
if(dev->ldn < 11)
if (dev->ldn < 11)
return dev->dma[dev->ldn];
else
return 0xff;
case 0xf0 ... 0xff:
if(dev->ldn < 11)
if (dev->ldn < 11)
return dev->d_spec[dev->index & 0x0f][dev->ldn];
else
return 0xff;
@@ -330,13 +322,12 @@ it8702_read(uint16_t addr, void *priv)
return 0xff;
}
static void
it8702_reset(void *priv)
{
it8702_t *dev = (it8702_t *) priv;
dev->ldn = 0;
dev->ldn = 0;
dev->sw_lock = 0; // Needs implementation
dev->unlock = 0; /* Lock the chip */
@@ -349,23 +340,23 @@ it8702_reset(void *priv)
/* Floppy Disk Controller */
dev->b_addr[0][0] = 0x03;
dev->b_addr[1][0] = 0xf0;
dev->irq[0] = 0x06;
dev->dma[0] = 0x02;
dev->irq[0] = 0x06;
dev->dma[0] = 0x02;
fdc_reset(dev->fdc);
it8702_fdc(dev);
/* LPT */
dev->b_addr[0][1] = 0x03;
dev->b_addr[1][1] = 0x78;
dev->irq[1] = 0x07;
dev->dma[1] = 0x03;
dev->irq[1] = 0x07;
dev->dma[1] = 0x03;
dev->d_spec[0][1] = 0x03;
it8702_lpt(dev);
/* UART Serial A */
dev->b_addr[0][2] = 0x02;
dev->b_addr[1][2] = 0xf8;
dev->irq[2] = 0x04;
dev->irq[2] = 0x04;
dev->d_spec[1][2] = 0x50;
dev->d_spec[3][2] = 0x7f;
it8702_uart(0, dev);
@@ -373,7 +364,7 @@ it8702_reset(void *priv)
/* UART Serial B */
dev->b_addr[0][3] = 0x02;
dev->b_addr[1][3] = 0x78;
dev->irq[3] = 0x04;
dev->irq[3] = 0x04;
dev->d_spec[1][3] = 0x50;
dev->d_spec[3][3] = 0x7f;
it8702_uart(1, dev);
@@ -383,18 +374,18 @@ it8702_reset(void *priv)
dev->b_addr[1][4] = 0x90;
dev->b_addr[2][4] = 0x02;
dev->b_addr[3][4] = 0x30;
dev->irq[4] = 0x09;
dev->irq[4] = 0x09;
/* Keyboard Controller */
dev->b_addr[3][5] = 0x64;
dev->irq[5] = 0x01;
dev->irq[5] = 0x01;
/* PS/2 Mouse */
dev->irq[6] = 0x0c;
/* MIDI */
dev->b_addr[0][8] = 0x03;
dev->irq[8] = 0x0a;
dev->irq[8] = 0x0a;
/* Gameport */
dev->b_addr[0][9] = 0x02;
@@ -403,10 +394,9 @@ it8702_reset(void *priv)
/* IR */
dev->b_addr[0][10] = 0x03;
dev->b_addr[1][10] = 0x10;
dev->irq[10] = 0x0b;
dev->irq[10] = 0x0b;
}
static void
it8702_close(void *priv)
{
@@ -415,7 +405,6 @@ it8702_close(void *priv)
free(dev);
}
static void *
it8702_init(const device_t *info)
{
@@ -443,15 +432,15 @@ it8702_init(const device_t *info)
}
const device_t it8702_device = {
.name = "ITE IT8702",
.name = "ITE IT8702",
.internal_name = "it8702",
.flags = 0,
.local = 0x2e,
.init = it8702_init,
.close = it8702_close,
.reset = it8702_reset,
.flags = 0,
.local = 0x2e,
.init = it8702_init,
.close = it8702_close,
.reset = it8702_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};

192
src/sio/sio_nsc366.c
View File

@@ -29,6 +29,7 @@
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/hwm.h>
#include <86box/io.h>
#include <86box/keyboard.h>
#include <86box/lpt.h>
#include <86box/nsc366.h>
@@ -39,22 +40,21 @@
#include <86box/port_92.h>
#include <86box/sio.h>
typedef struct
{
fdc_t *fdc;
serial_t *uart[2];
fdc_t *fdc;
serial_t *uart[2];
nsc366_hwm_t *hwm;
uint8_t index, ldn, sio_config[14],
ld_activate[15],
io_base0[2][15],
io_base1[2][15],
int_num_irq[15],
irq[15],
dma_select0[15],
dma_select1[15],
dev_specific_config[3][15];
ld_activate[15],
io_base0[2][15],
io_base1[2][15],
int_num_irq[15],
irq[15],
dma_select0[15],
dma_select1[15],
dev_specific_config[3][15];
int siofc_lock;
} nsc366_t;
@@ -62,29 +62,27 @@ typedef struct
#ifdef ENABLE_NSC366_LOG
int nsc366_do_log = ENABLE_NSC366_LOG;
void
nsc366_log(const char *fmt, ...)
{
va_list ap;
if (nsc366_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
#define nsc366_log(fmt, ...)
# define nsc366_log(fmt, ...)
#endif
static void
nsc366_fdc(nsc366_t *dev)
{
fdc_remove(dev->fdc);
int base = ((dev->io_base0[0][0] & 7) << 8) | (dev->io_base0[1][0] & 0xf8);
int irq = dev->int_num_irq[0] & 0x0f;
int base = ((dev->io_base0[0][0] & 7) << 8) | (dev->io_base0[1][0] & 0xf8);
int irq = dev->int_num_irq[0] & 0x0f;
int dma_ch = dev->dma_select0[0] & 7;
if (dev->ld_activate[0]) {
@@ -98,31 +96,29 @@ nsc366_fdc(nsc366_t *dev)
}
}
void
nsc366_lpt(nsc366_t *dev)
{
lpt1_remove();
int base = ((dev->io_base0[0][1] & 7) << 8) | (dev->io_base0[1][1] & 0xfc);
int irq = (dev->int_num_irq[1] & 0x0f);
int irq = (dev->int_num_irq[1] & 0x0f);
if (dev->ld_activate[1]) {
nsc366_log("NSC 366 LPT: Reconfigured with Base 0x%04x IRQ: %d\n", base ,irq);
nsc366_log("NSC 366 LPT: Reconfigured with Base 0x%04x IRQ: %d\n", base, irq);
lpt1_init(base);
lpt1_irq(irq);
}
}
static void
nsc366_uart(int uart, nsc366_t *dev)
{
serial_remove(dev->uart[uart]);
int base = ((dev->io_base0[0][2 + uart] & 7) << 8) | (dev->io_base0[1][2 + uart] & 0xf8);
int irq = (dev->int_num_irq[2 + uart] & 0x0f);
int irq = (dev->int_num_irq[2 + uart] & 0x0f);
if (dev->ld_activate[2 + uart]) {
nsc366_log("NSC 366 UART Serial %d: Reconfigured with Base 0x%04x IRQ: %d\n", uart, base ,irq);
nsc366_log("NSC 366 UART Serial %d: Reconfigured with Base 0x%04x IRQ: %d\n", uart, base, irq);
serial_setup(dev->uart[uart], base, irq);
}
}
@@ -151,7 +147,6 @@ nsc366_fscm(nsc366_t *dev)
nsc366_update_fscm_io(dev->ld_activate[9], base, dev->hwm);
}
static void
nsc366_vlm(nsc366_t *dev)
{
@@ -163,7 +158,6 @@ nsc366_vlm(nsc366_t *dev)
nsc366_update_vlm_io(dev->ld_activate[13], base, dev->hwm);
}
static void
nsc366_tms(nsc366_t *dev)
{
@@ -175,11 +169,10 @@ nsc366_tms(nsc366_t *dev)
nsc366_update_tms_io(dev->ld_activate[14], base, dev->hwm);
}
static void
nsc366_ldn_redirect(nsc366_t *dev)
{
switch(dev->ldn) {
switch (dev->ldn) {
case 0:
nsc366_fdc(dev);
break;
@@ -207,14 +200,13 @@ nsc366_ldn_redirect(nsc366_t *dev)
}
}
static void
nsc366_write(uint16_t addr, uint8_t val, void *priv)
{
nsc366_t *dev = (nsc366_t *)priv;
nsc366_t *dev = (nsc366_t *) priv;
if (addr & 1)
switch(dev->index) {
switch (dev->index) {
/* LDN */
case 0x07:
if (val <= 0x0e)
@@ -228,7 +220,7 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
if (!dev->siofc_lock) {
if (val & 0x80) {
dev->sio_config[dev->index - 0x20] = val | 0x80;
dev->siofc_lock = 1;
dev->siofc_lock = 1;
} else {
dev->sio_config[dev->index - 0x20] = val;
}
@@ -301,7 +293,7 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
nsc366_ldn_redirect(dev);
break;
case 0x74:
case 0x74:
dev->dma_select0[dev->ldn] = val & 0x1f;
nsc366_ldn_redirect(dev);
break;
@@ -315,15 +307,15 @@ nsc366_write(uint16_t addr, uint8_t val, void *priv)
dev->dev_specific_config[dev->index - 0xf0][dev->ldn] = val;
nsc366_ldn_redirect(dev);
break;
} else
}
else
dev->index = val;
}
static uint8_t
nsc366_read(uint16_t addr, void *priv)
{
nsc366_t *dev = (nsc366_t *)priv;
nsc366_t *dev = (nsc366_t *) priv;
if (addr & 1) {
switch (dev->index) {
@@ -348,7 +340,7 @@ nsc366_read(uint16_t addr, void *priv)
case 0x71:
return dev->irq[dev->ldn];
case 0x74:
case 0x74:
return dev->dma_select0[dev->ldn];
case 0x75:
@@ -360,18 +352,17 @@ nsc366_read(uint16_t addr, void *priv)
default:
return 0;
}
}
else return dev->index;
} else
return dev->index;
}
static void
nsc366_reset(void *priv)
{
nsc366_t *dev = (nsc366_t *)priv;
nsc366_t *dev = (nsc366_t *) priv;
/* Basic Configuration */
dev->ldn = 0;
dev->ldn = 0;
dev->siofc_lock = 0;
memset(dev->sio_config, 0, sizeof(dev->sio_config));
memset(dev->ld_activate, 0, sizeof(dev->ld_activate));
@@ -389,106 +380,104 @@ nsc366_reset(void *priv)
/* FDC */
fdc_reset(dev->fdc);
dev->io_base0[0][0] = 0x03;
dev->io_base0[1][0] = 0xf2;
dev->int_num_irq[0] = 0x06;
dev->irq[0] = 0x03;
dev->dma_select0[0] = 0x02;
dev->dma_select1[0] = 0x04;
dev->io_base0[0][0] = 0x03;
dev->io_base0[1][0] = 0xf2;
dev->int_num_irq[0] = 0x06;
dev->irq[0] = 0x03;
dev->dma_select0[0] = 0x02;
dev->dma_select1[0] = 0x04;
dev->dev_specific_config[0][0] = 0x24;
nsc366_fdc(dev);
/* LPT */
dev->io_base0[0][1] = 0x02;
dev->io_base0[1][1] = 0x78;
dev->int_num_irq[1] = 0x07;
dev->irq[1] = 0x02;
dev->dma_select0[1] = 0x04;
dev->dma_select1[1] = 0x04;
dev->io_base0[0][1] = 0x02;
dev->io_base0[1][1] = 0x78;
dev->int_num_irq[1] = 0x07;
dev->irq[1] = 0x02;
dev->dma_select0[1] = 0x04;
dev->dma_select1[1] = 0x04;
dev->dev_specific_config[0][1] = 0xf2;
/* UART Serial 2 */
dev->io_base0[0][2] = 0x02;
dev->io_base0[1][2] = 0xf8;
dev->int_num_irq[2] = 0x03;
dev->irq[2] = 0x03;
dev->dma_select0[2] = 0x04;
dev->dma_select1[2] = 0x04;
dev->io_base0[0][2] = 0x02;
dev->io_base0[1][2] = 0xf8;
dev->int_num_irq[2] = 0x03;
dev->irq[2] = 0x03;
dev->dma_select0[2] = 0x04;
dev->dma_select1[2] = 0x04;
dev->dev_specific_config[0][2] = 0x02;
nsc366_uart(1, dev);
/* UART Serial 1 */
dev->io_base0[0][3] = 0x03;
dev->io_base0[1][3] = 0xf8;
dev->int_num_irq[3] = 0x04;
dev->irq[3] = 0x03;
dev->dma_select0[3] = 0x04;
dev->dma_select1[3] = 0x04;
dev->io_base0[0][3] = 0x03;
dev->io_base0[1][3] = 0xf8;
dev->int_num_irq[3] = 0x04;
dev->irq[3] = 0x03;
dev->dma_select0[3] = 0x04;
dev->dma_select1[3] = 0x04;
dev->dev_specific_config[0][3] = 0x02;
/* SWC */
dev->irq[4] = 0x03;
dev->irq[4] = 0x03;
dev->dma_select0[4] = 0x04;
/* Keyboard Controller */
dev->int_num_irq[5] = 0x0c;
dev->irq[5] = 0x02;
dev->irq[5] = 0x02;
/* Mouse Controller */
dev->io_base0[1][6] = 0x60;
dev->io_base1[1][6] = 0x64;
dev->int_num_irq[6] = 0x01;
dev->irq[6] = 0x02;
dev->dma_select0[6] = 0x04;
dev->dma_select1[6] = 0x04;
dev->io_base0[1][6] = 0x60;
dev->io_base1[1][6] = 0x64;
dev->int_num_irq[6] = 0x01;
dev->irq[6] = 0x02;
dev->dma_select0[6] = 0x04;
dev->dma_select1[6] = 0x04;
dev->dev_specific_config[0][6] = 0x40;
/* GPIO */
dev->irq[7] = 0x03;
dev->irq[7] = 0x03;
dev->dma_select0[7] = 0x04;
dev->dma_select1[7] = 0x04;
/* ACB */
dev->irq[8] = 0x03;
dev->irq[8] = 0x03;
dev->dma_select0[8] = 0x04;
dev->dma_select1[8] = 0x04;
/* Fan Speed Monitor & Control */
dev->irq[9] = 0x03;
dev->irq[9] = 0x03;
dev->dma_select0[9] = 0x04;
dev->dma_select1[9] = 0x04;
nsc366_fscm_enable(dev);
nsc366_fscm(dev);
/* Voltage Level Monitor */
dev->irq[13] = 0x03;
dev->irq[13] = 0x03;
dev->dma_select0[13] = 0x04;
dev->dma_select1[13] = 0x04;
nsc366_vlm(dev);
/* Temperature Monitor */
dev->irq[14] = 0x03;
dev->irq[14] = 0x03;
dev->dma_select0[14] = 0x04;
dev->dma_select1[14] = 0x04;
nsc366_tms(dev);
}
static void
nsc366_close(void *priv)
{
nsc366_t *dev = (nsc366_t *)priv;
nsc366_t *dev = (nsc366_t *) priv;
free(dev);
}
static void *
nsc366_init(const device_t *info)
{
nsc366_t *dev = (nsc366_t *)malloc(sizeof(nsc366_t));
nsc366_t *dev = (nsc366_t *) malloc(sizeof(nsc366_t));
memset(dev, 0, sizeof(nsc366_t));
io_sethandler(info->local, 2, nsc366_read, NULL, NULL, nsc366_write, NULL, NULL, dev); /* Ports 2E-2Fh(4E-4Fh if BADDR High): National Semiconductor NSC366 */
@@ -514,31 +503,30 @@ nsc366_init(const device_t *info)
return dev;
}
const device_t nsc366_device = {
.name = "National Semiconductor NSC366",
.name = "National Semiconductor NSC366",
.internal_name = "nsc366",
.flags = 0,
.local = 0x2e,
.init = nsc366_init,
.close = nsc366_close,
.reset = nsc366_reset,
.flags = 0,
.local = 0x2e,
.init = nsc366_init,
.close = nsc366_close,
.reset = nsc366_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};
const device_t nsc366_4f_device = {
.name = "National Semiconductor NSC366 (With BADDR Pin High)",
.name = "National Semiconductor NSC366 (With BADDR Pin High)",
.internal_name = "nsc366",
.flags = 0,
.local = 0x4e,
.init = nsc366_init,
.close = nsc366_close,
.reset = nsc366_reset,
.flags = 0,
.local = 0x4e,
.init = nsc366_init,
.close = nsc366_close,
.reset = nsc366_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};

357
src/sio/sio_w83627hf.c
View File

@@ -107,7 +107,6 @@ Notes : ISAPnP is missing and the Hardware Monitor I2C is not implemented.
#ifdef ENABLE_W83627HF_LOG
int w83627hf_do_log = ENABLE_W83627HF_LOG;
static void
w83627hf_log(const char *fmt, ...)
{
@@ -120,21 +119,20 @@ w83627hf_log(const char *fmt, ...)
}
}
#else
#define w83627hf_log(fmt, ...)
# define w83627hf_log(fmt, ...)
#endif
typedef struct
{
uint8_t hwm_index, hwm_regs[256];
uint8_t index, cfg_unlocked,
regs[48], dev_regs[12][256];
uint8_t index, cfg_unlocked,
regs[48], dev_regs[12][256];
int has_hwm;
fdc_t *fdc_controller;
int has_hwm;
fdc_t *fdc_controller;
port_92_t *port_92;
serial_t *uart[2];
serial_t *uart[2];
} w83627hf_t;
/* These differ per board and must be programmed manually */
@@ -144,122 +142,117 @@ void
w83627hf_stabilizer(int vcoreb, int fan1, int fan2, int fan3)
{
vcoreb_voltage = vcoreb;
fan1_rpm = fan1;
fan2_rpm = fan2;
fan3_rpm = fan3;
fan1_rpm = fan1;
fan2_rpm = fan2;
fan3_rpm = fan3;
}
static void
w83627hf_hwm_write(uint16_t addr, uint8_t val, void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
switch(addr)
{
switch (addr) {
case 0x295:
dev->hwm_index = val;
break;
break;
case 0x296:
w83627hf_log("W83627HF-HWM: dev->regs[%02x] = %02x\n", dev->hwm_index, val);
switch(dev->hwm_index)
{
switch (dev->hwm_index) {
case 0x2b ... 0x3f:
case 0x6b ... 0x7f:
dev->hwm_regs[dev->hwm_index & 0x1f] = val;
break;
dev->hwm_regs[dev->hwm_index & 0x1f] = val;
break;
case 0x40:
dev->hwm_regs[dev->hwm_index] = val & 0x8b;
break;
break;
case 0x43:
dev->hwm_regs[dev->hwm_index] = val;
break;
break;
case 0x44:
dev->hwm_regs[dev->hwm_index] = val & 0x3f;
break;
break;
case 0x46:
dev->hwm_regs[dev->hwm_index] = val & 0x80;
if(val & 0x80)
dev->hwm_regs[dev->hwm_index] &= 0x10;
break;
if (val & 0x80)
dev->hwm_regs[dev->hwm_index] &= 0x10;
break;
case 0x47:
dev->hwm_regs[dev->hwm_index] = val & 0x3f;
break;
break;
case 0x48: /* Serial Bus Address */
dev->hwm_regs[dev->hwm_index] = val & 0x7f;
break;
break;
case 0x49:
dev->hwm_regs[dev->hwm_index] = val & 1;
break;
break;
case 0x4a:
dev->hwm_regs[dev->hwm_index] = val;
break;
break;
case 0x4b:
dev->hwm_regs[dev->hwm_index] = val & 0xfc;
break;
break;
case 0x4c:
dev->hwm_regs[dev->hwm_index] = val & 0x5c;
break;
break;
case 0x4d:
dev->hwm_regs[dev->hwm_index] = val & 0xbf;
break;
break;
case 0x4e:
dev->hwm_regs[dev->hwm_index] = val;
break;
break;
case 0x56:
dev->hwm_regs[dev->hwm_index] = val;
break;
break;
case 0x57:
dev->hwm_regs[dev->hwm_index] = val & 0xbf;
break;
break;
case 0x59:
dev->hwm_regs[dev->hwm_index] = val & 0x70;
break;
break;
case 0x5a ... 0x5b:
dev->hwm_regs[dev->hwm_index] = val;
break;
break;
case 0x5c:
dev->hwm_regs[dev->hwm_index] = val & 0x77;
break;
break;
}
break;
break;
}
}
static uint8_t
w83627hf_hwm_read(uint16_t addr, void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
switch(addr)
{
switch (addr) {
case 0x295:
return dev->hwm_index;
case 0x296:
switch(dev->hwm_index)
{
switch (dev->hwm_index) {
case 0x20 ... 0x3f:
case 0x60 ... 0x7f:
switch(dev->hwm_index & 0x1f)
{
switch (dev->hwm_index & 0x1f) {
case 0x00: /* VCOREA */
return hwm_get_vcore() + 0x78;
@@ -295,7 +288,7 @@ w83627hf_hwm_read(uint16_t addr, void *priv)
}
case 0x4f:
if(dev->hwm_regs[0x4e] & 0x80)
if (dev->hwm_regs[0x4e] & 0x80)
return 0x5c;
else
return 0xa3;
@@ -319,51 +312,49 @@ w83627hf_fdc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
fdc_remove(dev->fdc_controller);
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[0][cur_reg] = val & 1;
break;
break;
case 0x60 ... 0x61:
dev->dev_regs[0][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[0][cur_reg] = val & 0x0f;
break;
break;
case 0x74:
dev->dev_regs[0][cur_reg] = val & 7;
break;
break;
case 0xf0:
dev->dev_regs[0][cur_reg] = val;
break;
break;
case 0xf1:
dev->dev_regs[0][cur_reg] = val;
fdc_update_boot_drive(dev->fdc_controller, (val & 0xc0) >> 6);
if(val & 2)
if (val & 2)
fdc_writeprotect(dev->fdc_controller);
fdc_set_swwp(dev->fdc_controller, val & 1);
break;
break;
case 0xf2:
dev->dev_regs[0][cur_reg] = val;
break;
break;
case 0xf4:
case 0xf5:
dev->dev_regs[0][cur_reg] = val & 0x5b;
fdc_update_drvrate(dev->fdc_controller, cur_reg & 1, (val & 0x18) >> 3);
break;
break;
}
if(dev->dev_regs[0][0x30] & 1)
{
if (dev->dev_regs[0][0x30] & 1) {
fdc_set_irq(dev->fdc_controller, dev->dev_regs[0][0x70]);
fdc_set_dma_ch(dev->fdc_controller, dev->dev_regs[0][0x74]);
fdc_set_base(dev->fdc_controller, (dev->dev_regs[0][0x60] << 8) | (dev->dev_regs[0][0x61]));
@@ -377,27 +368,25 @@ w83627hf_lpt_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
lpt1_remove();
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[1][cur_reg] = val & 1;
break;
break;
case 0x60 ... 0x61:
dev->dev_regs[1][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[1][cur_reg] = val & 0x0f;
break;
break;
case 0xf0:
dev->dev_regs[1][cur_reg] = val & 0x7f;
break;
break;
}
if(dev->dev_regs[1][0x30] & 1)
{
if (dev->dev_regs[1][0x30] & 1) {
lpt1_init((dev->dev_regs[1][0x60] << 8) | (dev->dev_regs[1][0x61]));
lpt1_irq(dev->dev_regs[1][0x70]);
w83627hf_log("W83627HF-LPT: BASE: %04x IRQ: %d\n", (dev->dev_regs[1][0x60] << 8) | (dev->dev_regs[1][0x61]), dev->dev_regs[1][0x70]);
@@ -411,50 +400,47 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
serial_remove(dev->uart[uart]);
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[2 + uart][cur_reg] = val & 1;
break;
break;
case 0x60 ... 0x61:
dev->dev_regs[2 + uart][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[2 + uart][cur_reg] = val & 0x0f;
break;
break;
case 0xf0:
dev->dev_regs[2 + uart][cur_reg] = val & 3;
switch(val & 3)
{
switch (val & 3) {
case 0:
uart_clock = 24000000.0 / 13.0;
break;
break;
case 1:
uart_clock = 24000000.0 / 12.0;
break;
break;
case 2:
uart_clock = 24000000.0 / 1.625;
break;
break;
case 3:
uart_clock = 24000000.0;
break;
break;
}
break;
break;
case 0xf1:
if(uart)
if (uart)
dev->dev_regs[2 + uart][cur_reg] = val & 0x7f;
break;
break;
}
if(dev->dev_regs[2 + uart][0x30] & 1)
{
if (dev->dev_regs[2 + uart][0x30] & 1) {
serial_setup(dev->uart[uart], (dev->dev_regs[2 + uart][0x60] << 8) | (dev->dev_regs[2 + uart][0x61]), dev->dev_regs[2 + uart][0x70]);
serial_set_clock_src(dev->uart[uart], uart_clock);
w83627hf_log("W83627HF-UART%s: BASE: %04x IRQ: %d\n", uart ? "B" : "A", (dev->dev_regs[2 + uart][0x60] << 8) | (dev->dev_regs[2 + uart][0x61]), dev->dev_regs[2 + uart][0x70]);
@@ -464,35 +450,33 @@ w83627hf_uart_write(int uart, uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
static void
w83627hf_kbc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[5][cur_reg] = val & 1;
break;
break;
case 0x60 ... 0x61: /* See Notes on init */
dev->dev_regs[5][cur_reg] = val;
break;
break;
case 0x62 ... 0x63: /* See Notes on init */
dev->dev_regs[5][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[5][cur_reg] = val & 0x0f;
break;
break;
case 0x72:
dev->dev_regs[5][cur_reg] = val & 0x0f;
break;
break;
case 0xf0:
dev->dev_regs[5][cur_reg] = val & 0xc7;
break;
break;
}
if(dev->dev_regs[5][0x30] & 1)
{
if (dev->dev_regs[5][0x30] & 1) {
/* We don't disable Port 92h as intended because the BIOSes never enable it back, causing issues. */
port_92_set_features(dev->port_92, !!(dev->dev_regs[5][0xf0] & 1), !!(dev->dev_regs[5][0xf0] & 2));
w83627hf_log("W83627HF-PORT92: FASTA20: %d FASTRESET: %d\n", !!(dev->dev_regs[5][0xf0] & 2), !!(dev->dev_regs[5][0xf0] & 1));
@@ -503,159 +487,153 @@ static void
w83627hf_cir_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
/* Unimplemented Functionality */
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[6][cur_reg] = val & 1;
break;
break;
case 0x60 ... 0x61:
dev->dev_regs[6][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[6][cur_reg] = val & 0x0f;
break;
break;
}
}
static void
w83627hf_gameport_midi_gpio1_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[7][cur_reg] = val & 7;
break;
break;
case 0x60 ... 0x63:
dev->dev_regs[7][cur_reg] = val;
break;
break;
case 0x70:
dev->dev_regs[7][cur_reg] = val & 0x0f;
break;
break;
case 0xf0 ... 0xf2:
dev->dev_regs[7][cur_reg] = val;
break;
break;
}
}
static void
w83627hf_watchdog_timer_gpio2_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[8][cur_reg] = val & 1;
break;
break;
case 0xf0 ... 0xf2:
dev->dev_regs[8][cur_reg] = val;
break;
break;
case 0xf5:
dev->dev_regs[8][cur_reg] = val & 0xcc;
break;
break;
case 0xf6 ... 0xf7:
dev->dev_regs[8][cur_reg] = val;
break;
break;
}
}
static void
w83627hf_gpio3_vsb_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[9][cur_reg] = val & 1;
break;
break;
case 0xf0 ... 0xf2:
dev->dev_regs[9][cur_reg] = val;
break;
break;
case 0xf3:
dev->dev_regs[9][cur_reg] = val & 0xc0;
break;
break;
}
}
static void
w83627hf_acpi_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[0x0a][cur_reg] = val & 1;
break;
break;
case 0x70:
dev->dev_regs[0x0a][cur_reg] = val & 0x0f;
break;
break;
case 0xe0:
dev->dev_regs[0x0a][cur_reg] = val & 0xc0;
break;
break;
case 0xe1 ... 0xe2:
dev->dev_regs[0x0a][cur_reg] = val;
break;
break;
case 0xe4:
dev->dev_regs[0x0a][cur_reg] = val & 0xfc;
break;
break;
case 0xe5 ... 0xe6:
dev->dev_regs[0x0a][cur_reg] = val & 0x7f;
if(cur_reg == 0xe6)
if(val & 0x40)
if (cur_reg == 0xe6)
if (val & 0x40)
dev->hwm_regs[0x42] &= 0x10;
break;
break;
case 0xe7:
dev->dev_regs[0x0a][cur_reg] = val & 0x0f;
break;
break;
case 0xf0:
dev->dev_regs[0x0a][cur_reg] = val;
break;
break;
case 0xf1:
dev->dev_regs[0x0a][cur_reg] = val & 0xef;
break;
break;
case 0xf3 ... 0xf4:
dev->dev_regs[0x0a][cur_reg] &= val & 0x3f;
break;
break;
case 0xf5:
case 0xf7:
dev->dev_regs[0x0a][cur_reg] = val & 0x3f;
break;
break;
}
}
static void
w83627hf_hwm_lpc_write(uint16_t cur_reg, uint8_t val, w83627hf_t *dev)
{
switch(cur_reg)
{
switch (cur_reg) {
case 0x30:
dev->dev_regs[0x0b][cur_reg] = val & 1;
break;
break;
case 0x70:
dev->dev_regs[0x0b][cur_reg] = val & 0x0f;
break;
break;
case 0xf0:
dev->dev_regs[0x0b][cur_reg] = val & 1;
break;
break;
}
}
@@ -682,7 +660,7 @@ w83627hf_hwm_reset(w83627hf_t *dev)
static void
w83627hf_reset(void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
memset(dev->regs, 0, sizeof(dev->regs));
dev->cfg_unlocked = 0;
@@ -749,32 +727,29 @@ w83627hf_reset(void *priv)
dev->dev_regs[9][0xf0] = 0xff;
/* W83627HF Hardware Monitor */
if(dev->has_hwm)
if (dev->has_hwm)
w83627hf_hwm_reset(dev);
}
static void
w83627hf_write(uint16_t addr, uint8_t val, void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
switch(addr & 0x0f)
{
switch (addr & 0x0f) {
case 0x0e:
if(!dev->cfg_unlocked)
{
if (!dev->cfg_unlocked) {
dev->cfg_unlocked = (val == 0x87) && (dev->index == 0x87);
dev->index = val;
} else
dev->index = val;
}
else dev->index = val;
break;
break;
case 0x0f:
if(dev->cfg_unlocked)
switch(dev->index)
{
if (dev->cfg_unlocked)
switch (dev->index) {
case 0x02: /* LDN */
if(val & 1)
if (val & 1)
w83627hf_reset(dev);
break;
@@ -813,94 +788,92 @@ w83627hf_write(uint16_t addr, uint8_t val, void *priv)
case 0x2a:
case 0x2b:
dev->regs[dev->index] = val;
break;
break;
case 0x30: /* Device Specific Registers */
case 0x60 ... 0x63:
case 0x70: case 0x72:case 0x74:
case 0x70:
case 0x72:
case 0x74:
case 0xe0 ... 0xe7:
case 0xf0 ... 0xf6:
switch(dev->regs[7])
{
switch (dev->regs[7]) {
case 0: /* FDC */
w83627hf_fdc_write(dev->index, val, dev);
break;
break;
case 1: /* LPT */
w83627hf_lpt_write(dev->index, val, dev);
break;
break;
case 2: /* UART A */
case 3: /* UART B */
w83627hf_uart_write(dev->regs[7] & 1, dev->index, val, dev);
break;
break;
case 5: /* KBC */
w83627hf_kbc_write(dev->index, val, dev);
break;
break;
case 6: /* CIR */
w83627hf_cir_write(dev->index, val, dev);
break;
break;
case 7: /* GAMEPORT, MIDI & GPIO1 */
w83627hf_gameport_midi_gpio1_write(dev->index, val, dev);
break;
break;
case 8: /* WATCHDOG TIMER & GPIO2 */
w83627hf_watchdog_timer_gpio2_write(dev->index, val, dev);
break;
break;
case 9: /* GPIO3 & VSB */
w83627hf_gpio3_vsb_write(dev->index, val, dev);
break;
break;
case 0x0a: /* ACPI */
w83627hf_acpi_write(dev->index, val, dev);
break;
break;
case 0x0b: /* HWM LPC */
w83627hf_hwm_lpc_write(dev->index, val, dev);
break;
break;
default:
w83627hf_log("W83627HF: Writings to unknown LDN: %02x\n", dev->regs[7]);
break;
break;
}
break;
break;
}
break;
break;
}
}
static uint8_t
w83627hf_read(uint16_t addr, void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
if((dev->index >= 0x00) && (dev->index <= 0x2f))
if ((dev->index >= 0x00) && (dev->index <= 0x2f))
return dev->regs[dev->index];
else if((dev->index >= 0x30) && (dev->index <= 0xff) && (dev->regs[7] >= 0) && (dev->regs[7] <= 0x0b))
else if ((dev->index >= 0x30) && (dev->index <= 0xff) && (dev->regs[7] >= 0) && (dev->regs[7] <= 0x0b))
return dev->dev_regs[dev->regs[7]][dev->index];
else
return 0xff;
}
static void
w83627hf_close(void *priv)
{
w83627hf_t *dev = (w83627hf_t *)priv;
w83627hf_t *dev = (w83627hf_t *) priv;
free(dev);
}
static void *
w83627hf_init(const device_t *info)
{
w83627hf_t *dev = (w83627hf_t *)malloc(sizeof(w83627hf_t));
w83627hf_t *dev = (w83627hf_t *) malloc(sizeof(w83627hf_t));
memset(dev, 0, sizeof(w83627hf_t));
/* Knock out the Hardware Monitor if needed(Mainly for ASUS TUSL2-C) */
@@ -910,7 +883,7 @@ w83627hf_init(const device_t *info)
io_sethandler(0x002e, 2, w83627hf_read, NULL, NULL, w83627hf_write, NULL, NULL, dev);
io_sethandler(0x004e, 2, w83627hf_read, NULL, NULL, w83627hf_write, NULL, NULL, dev);
if(dev->has_hwm)
if (dev->has_hwm)
io_sethandler(0x0295, 2, w83627hf_hwm_read, NULL, NULL, w83627hf_hwm_write, NULL, NULL, dev);
/* Floppy Disk Controller */
@@ -934,29 +907,29 @@ w83627hf_init(const device_t *info)
}
const device_t w83627hf_device = {
.name = "Winbond W83627HF",
.name = "Winbond W83627HF",
.internal_name = "w83627hf",
.flags = 0,
.local = 1,
.init = w83627hf_init,
.close = w83627hf_close,
.reset = w83627hf_reset,
.flags = 0,
.local = 1,
.init = w83627hf_init,
.close = w83627hf_close,
.reset = w83627hf_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};
const device_t w83627hf_no_hwm_device = {
.name = "Winbond W83627HF with no Hardware Monitor",
.name = "Winbond W83627HF with no Hardware Monitor",
.internal_name = "w83627hf_nohwm",
.flags = 0,
.local = 0,
.init = w83627hf_init,
.close = w83627hf_close,
.reset = w83627hf_reset,
.flags = 0,
.local = 0,
.init = w83627hf_init,
.close = w83627hf_close,
.reset = w83627hf_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
.force_redraw = NULL,
.config = NULL
};