hopefully fix build with GHA cfg

src/include/86box/nv/vid_nv3.h

@@ -1557,7 +1557,7 @@ void        nv3_user_write(uint32_t address, uint32_t value);
 
 // NV3 PMC
 void        nv3_pmc_init(void);
-uint32_t    nv3_pmc_clear_interrupts(void);
+void        nv3_pmc_clear_interrupts(void);
 uint32_t    nv3_pmc_handle_interrupts(bool send_now);
 
 // NV3 PGRAPH

src/video/nv/nv3/nv3_core.c

@@ -616,7 +616,7 @@ uint8_t nv3_svga_in(uint16_t addr, void* priv)
             return ret;
 
         // must be dword aligned
-        uint32_t real_rma_read_addr = ((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX - 1) << 1) + (addr & 0x03); 
+        uint32_t real_rma_read_addr = (((nv3->pbus.rma.mode & NV3_CRTC_REGISTER_RMA_MODE_MAX) - 1) << 1) + (addr & 0x03); 
         ret = nv3_pbus_rma_read(real_rma_read_addr);
         return ret;
     }
@@ -869,7 +869,7 @@ uint8_t nv3_prom_read(uint32_t address)
 void nv3_prom_write(uint32_t address, uint32_t value)
 {
     uint32_t real_addr = address & 0x1FFFF;
-    nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", address, value);
+    nv_log("What's going on here? Tried to write to the Video BIOS ROM? (Address=0x%05x, value=0x%02x)", real_addr, value);
 }
 
 // Initialise the MMIO mappings
@@ -974,7 +974,7 @@ void nv3_update_mappings(void)
         nv3_svga_out, NULL, NULL, 
         nv3);   
     
-    if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND]) & PCI_COMMAND_MEM)
+    if (!(nv3->pci_config.pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))
     {
         nv_log("The memory was turned off, not much is going to happen.\n");
         return;

src/video/nv/nv3/subsystems/nv3_pextdev.c

@@ -134,7 +134,7 @@ void nv3_pextdev_write(uint32_t address, uint32_t value)
     // special consideration for straps
     if (address == NV3_PSTRAPS)
     {
-        warning("Huh? Tried to write to the straps. Something is wrong...\n", nv3->pextdev.straps);
+        warning("Huh? Tried to write to the straps (value=%d). Something is wrong...\n", nv3->pextdev.straps);
         return;
     }
 

src/video/nv/nv3/subsystems/nv3_pfb.c

@@ -29,7 +29,7 @@
 #include <86box/nv/vid_nv3.h>
 
 // Functions only used in this translation unit
-uint32_t nv3_pfb_config0_read();
+uint32_t nv3_pfb_config0_read(void);
 void nv3_pfb_config0_write(uint32_t val);
 
 nv_register_t pfb_registers[] = {
@@ -170,7 +170,7 @@ void nv3_pfb_write(uint32_t address, uint32_t value)
     }
 }
 
-uint32_t nv3_pfb_config0_read()
+uint32_t nv3_pfb_config0_read(void)
 {
     return nv3->pfb.config_0;
 }

src/video/nv/nv3/subsystems/nv3_pfifo.c

@@ -760,8 +760,7 @@ void nv3_pfifo_context_switch(uint32_t new_channel)
     if (new_channel >= NV3_DMA_CHANNELS)
         fatal("nv3_pfifo_context_switch: Tried to switch to invalid dma channel");
 
-    uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF;
-
+    //uint16_t ramfc_base = nv3->pfifo.ramfc_config >> NV3_PFIFO_CONFIG_RAMFC_BASE_ADDRESS & 0xF;
 }
 
 // NV_USER writes go here!
@@ -820,7 +819,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t param)
     {
         // Cache reassignment required
         if (!nv3->pfifo.cache_reassignment 
-        || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.get_address))
+        || (nv3->pfifo.cache1_settings.get_address != nv3->pfifo.cache1_settings.put_address))
         {
             oh_shit = true;
             oh_shit_reason = nv3_runout_reason_no_cache_available;

src/video/nv/nv3/subsystems/nv3_pmc.c

@@ -56,7 +56,7 @@ nv_register_t pmc_registers[] = {
     { NV_REG_LIST_END, NULL, NULL, NULL}, // sentinel value 
 };
 
-uint32_t nv3_pmc_clear_interrupts(void)
+void nv3_pmc_clear_interrupts(void)
 {
     nv_log_verbose_only("Clearing IRQs\n");
     pci_clear_irq(nv3->nvbase.pci_slot, PCI_INTA, &nv3->nvbase.pci_irq_state);

src/video/nv/nv3/subsystems/nv3_pramin_ramfc.c

@@ -30,7 +30,8 @@
 
 uint32_t nv3_ramfc_read(uint32_t address)
 {
-    nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x)\n", address);
+    nv_log_verbose_only("RAMFC (Unused DMA channel context) Read (0x%04x) (UNIMPLEMENTED returning 0x00)\n", address);
+    return 0x00; //temp
 }
 
 void nv3_ramfc_write(uint32_t address, uint32_t value)

src/video/nv/nv3/subsystems/nv3_pramin_ramht.c

@@ -47,6 +47,7 @@ uint32_t nv3_ramht_hash(uint32_t name, uint32_t channel)
 uint32_t nv3_ramht_read(uint32_t address)
 {
     nv_log_verbose_only("RAMHT (Graphics object storage hashtable) Read (0x%04x), I DON'T BELIEVE THIS SHOULD EVER HAPPEN - RETURNING 0x00\n", address);
+    return 0x00; 
 }
 
 void nv3_ramht_write(uint32_t address, uint32_t value)

src/video/nv/nv3/subsystems/nv3_pramin_ramro.c

@@ -31,6 +31,7 @@
 uint32_t nv3_ramro_read(uint32_t address)
 {
     nv_log("BIG Problem: RAM Runout (invalid dma object submission) Read (0x%04x)\n", address);
+    return 0x00; 
 }
 
 void nv3_ramro_write(uint32_t address, uint32_t value)