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Start working on the notifier engine and fix thecontext selection for cache1 object submission.

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This commit is contained in:
starfrost013
2025-02-14 00:38:42 +00:00
parent 93e0262132
commit f8c2c604d8
5 changed files with 58 additions and 16 deletions
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8
doc/nvidia_notes/nv3 driver init status_2025-02-10.txt
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@@ -66,10 +66,10 @@ DrvEnableSurface
RmLoadState SUCCESS 01:53 10/02/2025
NV3EnableCursor SUCCESS 01:54 10/02/2025
NV3WaitUntilFinished SUCCESS Passing 02:23 10/02/2025
EngDeviceIoControl IOCTL 0x230408
EngDeviceIoControl IOCTL 0x232024
NvAllocHardware
bCreateStdPatches(?)
EngDeviceIoControl IOCTL 0x230408 SUCCESS 02:26 10/02/2025
EngDeviceIoControl IOCTL 0x232024 SUCCESS 02:26 10/02/2025
NvAllocHardware SUCCESS 02:29 10/02/2025
bCreateStdPatches(?) FAILURE 02:31 10/02/2025
CHECK - NV4
vDestroyStdPatches(?)
NV3_WaitForOneVerticalRefresh

24
src/include/86box/nv/classes/vid_nv3_classes.h
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@@ -1038,17 +1038,33 @@ typedef struct nv3_object_class_017
nv3_d3d5_alpha_control_t alpha_control;
uint8_t reserved3[0xCE4];
nv3_d3d5_coordinate_t coordinate_points[128]; // The points wer are rendering.
nv3_d3d5_coordinate_t coordinate_points[128]; // The points we are rendering.
/* No placeholder needed, it really is that long. */
} nv3_d3d5_accelerated_triangle_with_zeta_buffer_t;
/* 0x19, 0x1A, 0x1B don't exist */
// Color and Zeta Buffer algorithm
typedef struct nv3_zeta_buffer_s
{
nv3_color_argb_32_t color;
uint32_t zeta; // 16 bits z, 8 bits stenciul
} nv3_zeta_buffer_t;
typedef struct nv3_object_class_018
{
{
nv3_class_ctx_switch_method_t set_notify_ctx_dma;
uint8_t reserved[0x100];
uint32_t set_notify;
uint8_t reserved2[0x1FC];
nv3_d3d5_control_out_t control_out;
nv3_d3d5_alpha_control_t alpha_control;
uint8_t reserved3[0x4F0];
nv3_position_16_t point;
nv3_zeta_buffer_t zeta[8];
} nv3_point_with_zeta_buffer_t;
/* 0x19, 0x1A, 0x1B don't exist */
/* WHY IS THE FORMAT DIFFERENT TO THE REST OF THE GPU?
They are making it look like a bitfield but it's hex?

21
src/include/86box/nv/vid_nv3.h
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@@ -14,7 +14,7 @@
* Also check the doc folder for some more notres
*
* vid_nv3.h: NV3 Architecture Hardware Reference (open-source)
* Last updated: 5 February 2025 (STILL WORKING ON IT!!!)
* Last updated: 13 February 2025 (STILL WORKING ON IT!!!)
*
* Authors: Connor Hyde <mario64crashed@gmail.com>
*
@@ -869,6 +869,25 @@ typedef struct nv3_pfb_s
uint32_t rtl; // Part of the memory timings
} nv3_pfb_t;
//
// DMA & Notifier Engine
//
// Not a notification status, because it's a 16-bit enum
// C23 fixes this
#define NV3_NOTIFICATION_STATUS_DONE_OK 0x0
#define NV3_NOTIFICATION_STATUS_IN_PROGRESS 0xFF
#define NV3_NOTIFICATION_STATUS_ERROR 0x100
// Core notification structure
typedef struct nv3_notification_s
{
uint64_t nanoseconds;
uint32_t info32;
uint16_t info16;
uint16_t status;
} nv3_notification_t;
#define NV3_RMA_NUM_REGS 4
// Access the GPU from real-mode
typedef struct nv3_pbus_rma_s

14
src/video/nv/nv3/subsystems/nv3_pfifo.c
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@@ -504,10 +504,9 @@ uint32_t nv3_pfifo_cache1_gray2normal(uint32_t val)
// shift right until we have our normla number again
while (mask)
{
// NT4 drivers v1.29
mask >>= 1;
// NT4 drivers v1.29 do this the other way around??
val ^= mask;
mask >>= 1;
}
return val;
@@ -588,7 +587,7 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val)
// Up to 128 per envytools?
uint32_t channel = (addr >> NV3_OBJECT_SUBMIT_CHANNEL) & 0x7F;
uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & 0x07;
uint32_t subchannel = (addr >> NV3_OBJECT_SUBMIT_SUBCHANNEL) & (NV3_DMA_CHANNELS - 1);
// first make sure there is even any cache available
if (!nv3->pfifo.cache1_settings.access_enabled)
@@ -661,6 +660,9 @@ void nv3_pfifo_cache1_push(uint32_t addr, uint32_t val)
nv3->pfifo.cache1_settings.put_address = nv3_pfifo_cache1_normal2gray(next_put_address);
nv_log("Submitted object [PIO]: Channel %d, Subchannel %d, Method ID 0x%04x (Put Address is now %d)\n",
channel, subchannel, method_offset, nv3->pfifo.cache1_settings.put_address);
// Now we're done. Phew!
}
@@ -689,7 +691,7 @@ void nv3_pfifo_cache1_pull()
return; // interrupt was fired, and we went to ramro
}
uint32_t current_context = nv3->pfifo.cache0_settings.context[0]; // only 1 entry for CACHE0 so basically ignore the other context entries?
uint32_t current_context = nv3->pfifo.cache0_settings.context[current_subchannel]; // only 1 entry for CACHE0 so basically ignore the other context entries?
// Tell the CPU if we found a software method
if (current_context & 0x800000)
@@ -711,7 +713,7 @@ void nv3_pfifo_cache1_pull()
nv3->pfifo.cache0_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2;
#ifndef RELEASE_BUILD
nv_log("***** SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - CACHE1 PULLED ****** Contextual information below\n");
nv_log("***** OBJECT PULLED, SUBMITTING GRAPHICS COMMANDS CURRENTLY UNIMPLEMENTED - ****** Contextual information below\n");
nv3_debug_ramin_print_context_info(current_name, *(nv3_ramin_context_t*)current_context);
#endif

7
src/video/nv/nv3/subsystems/nv3_user.c
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@@ -37,7 +37,12 @@ uint32_t nv3_user_read(uint32_t address)
//todo: print out the subchannel
uint8_t method_offset = (address & 0x1FFC);
nv_log("User Submission Area PIO Subchannel method_offset=0x%04x\n (Trying to read...)", method_offset);
#ifndef RELEASE_BUILD
uint8_t channel = (address - NV3_USER_START) / 0x10000;
uint8_t subchannel = ((address - NV3_USER_START)) / 0x2000 % NV3_DMA_SUBCHANNELS_PER_CHANNEL;
nv_log("User Submission Area PIO Channel %d.%d method_offset=0x%04x\n", channel, subchannel, method_offset);
#endif
// 0x10 is free CACHE1 object
// TODO: THERE ARE OTHER STUFF!