1. Add a variant of the ICS1494 clock generator specifically for the Radius HT209 card.
2. Add the ICD2047 clock generator to the HT216-32 card.
3. Add the previously missing 7.00 BIOS revision of the VGA 1024i HT208 card.
1. The S3 968-based Diamond Stealth 64 Video VRAM, using a 14mhz reference clock, now has its RGB528 fixed Pixel PLL reference divider set to its default value (0x07) per manual and reference clock. Fixes wrong refresh rates on said cards and others.
2. Added the ICS2494-324 clock generator to the ET4000AX. Fixes wrong refresh rates on this one too.
1. In the STG code, separated the STG1703 without its built-in clock as 1702 while keeping the one with the clock as 1703.
2. Added the ICS2494AN-324 clock generator used by the et4000w32 series.
3. Return 0x98 as the ID of the ATT498 ramdac.
4. Corrected the pixel clocks of the IBM RGB528 while keeping its current compatibility and exactness of the refresh rates of its clocks.
5. Added a variable reference clock of the SDAC/GenDAC for future use.
6. The clocks of the TVP3026 have been implemented for a while. Some corrections have been made (plus color key r/w).
7. Mach64 enhanced mode doesn't use scrollcache (bits 0-3 of attrregs 0x13), fixes some pixels being off (mainly in win3.1x)
8. Reorganized the cirrus 54xx built-in clock for proper refresh rates.
9. Proper reorganization of the et4000w32 series of chipsets and their cards supporting them, from cursor to clocks to ramdacs plus a 24bpp acceleration fix for the w32p series (about pixels being processed in bitblt).
10. Removed the PCI videomagic card as its bios doesn't have the PCIR header while making sure the plain ISA/VLB w32 and ISA only w32i (now named Axis Microdevice) support 2mb of vram properly.
11. Added the Hercules Dynamite VL Pro based on the w32i chip (and VLB).
12. Initialize the et4000w32 cards with misc bit 0 set as well as crtc31 bit 6 for rs2 connection to the ramdac.
13. Refactored the S3 Pre-ViRGE code to have proper refresh rates and clocks and added the 805I as a member of the chips (ID 0xa8).
14. Replaced the S3 805I Elsa Winner 1000 ISA bios with a more supported one for our code using the SDAC.
15. Added proper 24bpp acceleration to the Visionx68 chips.
16. Fixed wrong colors in the 911/924 15/16bpp acceleration when used for the first time.
17. Match the ViRGE mapping to the pre-ViRGE one per manual/datasheet.
18. Correct as best as possible the TGUI9400 clocks.
* AdLib Gold changes of the day (September 23rd, 2025)
1. Make sure the check to the Surround module is properly placed when disabled/enabled.
2. Replace local adgold_buffer with opl_buffer from its struct to improve the audio output and less clipping.
* Some fixes for the AdLib Gold of the day (September 26th, 2025)
1. Revert the sampling DMA int functions back to void but with a check that monitors the DMA FIFO whenever it's within the range or not.
2. Actually clear the IRQ properly.
* Mach64 changes of the day (October 7th, 2025)
1. Add a second call to wake_fifo_thread to reduce thread glitching.
2. Minor cosmetic fixes.
- Apply vsync_offset only during the vertical retrace period for a more accurate result
- Change the calculation of displine_offs and remove redundant checks around rendering calls
- Remove unnecessary clamping logic for crtc[7]
- Remove a hack from the previous commit by correctly triggering VSYNC processing when the vertical counter matches the actual crtc[7]
* Fix sign position of DDA accumulator registers
* S3 ViRGE: Move sign bit 1 bit further to the right for K1/K2 scaler registers
* K1 scales are 13 bits
The rework resolves around implementing the clock multiplier and multiplexing rate of the bt485 ramdac alongside existing additional flags for eventual fixes (like cr31 bit 1) as well as the true color bypass (for 16-bit and true color modes). These, together, allow proper rendering of the generic VESA S3 drivers alongside non-VESA ELSA OEM drivers on various guests.
