mirror/86Box
1
0
Fork 0
mirror of https://github.com/86Box/86Box.git synced 2026-02-23 18:08:20 -07:00
Code Issues Packages Projects Releases Activity
18,489 Commits 12 Branches 36 Tags
8f174d319167b260089f4ec2d15e4d25e1902571
Commit Graph

91 Commits

Author SHA1 Message Date
Jasmine Iwanek
891982c2c4 Align array entries in machine table and format machines (#6254) 2025-09-30 04:15:10 +02:00
Jasmine Iwanek
3c5190a0db Header cleanups (1/2) 2025-09-21 00:48:38 -04:00
OBattler
fbe69ab218 KBC P1 readout fixes. 2025-08-23 16:45:06 +02:00
OBattler
467b6b8f77 Round 2 of the clean-ups - AT vs. PS/2 KBC is now decided based on machine flags, reduces the chances of mismatch to zero. 2025-08-23 15:05:08 +02:00
OBattler
b9e294b781 Trned the LPT ports into device_t's. 2025-08-02 14:51:28 +02:00
OBattler
44fd79b78d PCjr: Correctly implement wait states, fixes #3140. 2025-07-10 02:34:26 +02:00
Jasmine Iwanek
16975c374f ISA ROM Board Support 2025-06-08 01:11:29 -04:00
OBattler
76d5fa79af Improve machine availability checking so that it absolutely never uses the legacy method if the machine has a device and the device has a CONFIG_BIOS setting. 2025-05-10 05:01:57 +02:00
TC1995
36ecc17551 Fix incompatible pointers of the generic PIT and PCjr's 
So that the build compiles fine.
 2024-03-22 23:24:58 +01:00
OBattler
3599d2bed1 Make sure all CPU's with 16-bit bus default to slow PIT. 2024-01-15 21:46:12 +01:00
OBattler
a25a17bc62 Default PIT to slow on 286 and 386. 2023-11-22 23:01:11 +01:00
OBattler
74e2437d91 808x machines with >= 8 MHz CPU speed now default to fast PIT, fixes #3776. 2023-11-06 07:05:15 +01:00
OBattler
684a842699 Some fixes, Socket 7 3 V, and the on-board Vibra 16S. 2023-10-08 05:21:12 +02:00
OBattler
63ce626f29 Phase 2. 2023-10-08 01:16:42 +02:00
OBattler
6fae975a72 PIT type selection, CD-ROM model filtering by bus, and translation updates - closes #3354. 2023-08-16 05:23:03 +02:00
OBattler
b203b28350 Assorted copyright header fixes. 2023-08-14 21:51:47 +02:00
OBattler
dbf9ef66fc Moved Voodoo initialization to the very end to minimize the likelihood of SCSI adapters ending up on the bridge. 2023-08-10 01:37:33 +02:00
OBattler
c30d5d90b7 PCI and IRQ rework, pci.c rewritten from ground up, fixes numerous issues such as the bridge being added when the number of normal PCI devices equals the number of normal PCI slots, Windows 95 PCI operation on Intel 430NX, sharing of PCI IRQ's with non-PCI level-triggered devices, having both configuration mechanisms operating at the same time (ALi M1435), etc., and makes the code much more readable. 2023-08-07 03:04:52 +02:00
Jasmine Iwanek
998cfe5cc8 Constification 2023-07-25 17:59:24 -04:00
Jasmine Iwanek
ee695e71f9 More sonarlint work 2023-07-25 17:59:22 -04:00
OBattler
78f129c8ac Rewritten the PCI Type 2 access handling. 2023-07-06 19:55:59 +02:00
Jasmine Iwanek
fea5ac681b Handful of function renames 2023-02-07 18:14:58 -05:00
Jasmine Iwanek
a7236a9022 Make dual video card code use array 2023-02-06 07:29:18 -05:00
Jasmine Iwanek
1860700eab Fix some small issues 2023-01-07 17:02:23 -05:00
Jasmine Iwanek
bd75bc141a Header cleanups 
Tabs to spaces
Consistency
 2022-11-13 21:15:47 -05:00
Jasmine Iwanek
3fddf4d488 clang-format in src/machine/ 2022-09-18 17:22:55 -04:00
Adrien Moulin
2aa5d8f5b2 PIT: add alternative faster PIT 
This is enabled by default on 486+ CPUs and can be forced disabled/enabled with pit_mode=0/1
 2022-07-23 13:38:10 +02:00
Jasmine Iwanek
9b1e90331f Beginnings of CONFIG_BIOS support 
ported from machine&kb
 2022-07-22 23:35:18 -04:00
OBattler
f4ba136b97 Machine. 2022-07-16 03:22:28 +02:00
TC1995
0999c445a3 Forgot one more thing about XGA. Fixes initialization of the card. 2022-06-18 22:15:46 +02:00
TC1995
d0335e9679 Initial emulation of the IBM 8514/A coprocessor for both the MCA and ISA buses. 
Currently the GUI option is on the QT frontend.
 2022-05-14 18:55:00 +02:00
Jasmine Iwanek
608905136f SW2 support for ISA Memory Devices 2022-01-26 16:56:30 -05:00
OBattler
4d2ed33ff2 Fixed the emulator. 2021-12-19 23:41:23 +01:00
OBattler
bc90f99350 Finally got rid of the AT and PCI global variables. 2021-12-19 20:00:27 +01:00
OBattler
67367798a7 Merged various SMC FDC67C6xx Super I/O chips into one file, re-added the UMC88xx 486 chipsets (and four machines for it) based on work by tiseno100 and my own work, various other fixes, and added quite a few machines (including the AOpen AP5VM which now works), also added the remaining ALi M6117 machine (Protech SBC with Award BIOS), and made the Intel Advanced/ATX's on-board S3 Trio64V+ work, as well as the on-board S3 Trio64/V2 of the two Compaq Presarios. 2021-08-21 18:19:10 +02:00
OBattler
949dea3524 Added IBM PCjr cartridge support. 2021-07-29 20:34:55 +02:00
OBattler
827065c0bc Ported the cassette emulation from PCE, closes #835. 2021-07-27 06:12:09 +02:00
OBattler
8c4d08e9df A number of machine fixes and PIT clock (crystal/bus speed) and CPU are now initialized before everything else, fixes Olivetti M19 with 8088 4.77 MHz and also fixes switching between 286/386SX and 386DX+ machines. 2021-07-15 20:03:19 +02:00
RichardG867
b5a295e91d Continuing the game port overhaul: added support for Super I/O game ports not being broken out 2021-06-03 16:26:07 -03:00
RichardG867
77f311b179 Game port overhaul 2021-06-03 16:26:05 -03:00
nerd73
5e89a9d775 fix more compile issues 2021-04-15 23:34:53 -06:00
nerd73
791bae3560 Add the AMD Am486DXL and DXL2. 
Has otherwise Intel-compatible SMM with an SMBase at 60000h.
 2021-04-15 23:28:07 -06:00
nerd73
8e3b09f323 Various 486 improvements 
- Added SL-Enhanced versions of Intel 486 CPUs and Enhanced AMD Am486DX2/DX4 CPUs
- Cleaned up the 486 CPU types and updated intel_4x0.c to reflect this
- Fixed some incorrect EDX reset and CPUID values
- Blacklisted non-SMM capable 486 CPUs on the Soyo 4SA2 motherboard
- Merged the non-OverDrive and OverDrive Intel DX4s because of further research confirming them to be functionally identical
- Removed SMM support on early 486 CPUs
 2021-04-15 21:38:03 -06:00
OBattler
8b6f9707d5 More CPU fixes, and SMM now implemented on Cyrix Cx486 and Cx5x86 CPU's as well as on Intel/AMI SX, DX, and SX2 CPU's. 2021-04-11 07:25:08 +02:00
OBattler
8175289c9d Am486 SMBASE is now correctly initialized to 30000, 60000 is for the Am486DXL and Am486DXL2, which we do not emulate. 2021-04-10 22:22:19 +02:00
RichardG867
d9d592c336 Change is_at checks to a new IS_AT macro which allows for ISA-less PCI machines 2020-11-30 20:10:47 -03:00
Alexander Babikov
53bb559446 Fix compilation warnings. 2020-11-14 05:46:57 +05:00
OBattler
795a6017d2 PIC rewrite, proper SMRAM API, complete SiS 471 rewrite and addition of 40x, 460, and 461, changes to mem.c/h, disabled Voodoo memory dumping on exit, bumped SDL Hardware scale quality to 2, bumped IDE/ATAPI drives to ATA-6, finally bumped emulator version to 3.0, redid the bus type ID's to allow for planned ATAPI hard disks, made SST flash set its high mappings to the correct address if the CPU is 16-bit, and added the SiS 401 AMI 486 Clone, AOpen Vi15G, and the Soyo 4SA2 (486 with SiS 496/497 that can boot from CD-ROM), assorted 286+ protected mode fixes (for slightly more accuracy), and fixes to 808x emulation (MS Word 1.0 and 1.10 for DOS now work correctly from floppy). 2020-10-14 23:15:01 +02:00
OBattler
70dd4ba3be Generic MO Device ID changes and implemented the VPCEXT instructions (on the Virtual PC 2007 VM only). 2020-07-25 05:14:06 +02:00
David Hrdlička
a505894a10 Move all include files to src/include 
- 86Box's own headers go to /86box
- munt's public interface goes to /mt32emu
- all slirp headers go to /slirp (might want to consider using only its public inteface)
- single file headers from other projects go in include root
 2020-03-29 19:53:29 +02:00