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fix an extra typo in the notifiers section

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starfrost013
2025-01-18 11:49:32 +00:00
parent 9117da862f
commit 1736f046f4
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_posts/2025-01-17-riva128-part-1.md
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@@ -162,7 +162,7 @@ _Note_: There is a wrinkle to this setup here. The VBIOS has to be able to commu
DFB means "Dumb Framebuffer" (that's what Nvidia chose to call it) and is simply a linear framebuffer. It is mapped into PCI BAR1 and has a size of 0x400000 by default (depending on the VRAM size?). In the NV3, it is mapped into BAR1 (on later GPUs it was moved to BAR0 starting at `0x1000000`). It is presumably meant for manipulating the GPU without using its DMA facilities.
#### RAMIN
Also in PCI BAR1 is the `RAMIN` region. While this area is somewhat complicated, it is the most important area to understand. RAMIN is the area of the GPU's VRAM where graphics objects and the structures containing references to them are stored. It is effectively addressed as the last megabyte of VRAM (regardless of the size of VRAM), but addressed in reverse, and aligned to a 16-byte boundary. If this is difficult to understand, you can convert an address in PRAMIN to a real VRAM address using the following formula (where reversal_unit_size is equal to 16):
Also in PCI BAR1 is the `RAMIN` region. While this area is somewhat complicated, it is the most important area to understand in order to understand how the GPU actually operates. RAMIN is the area of the GPU's VRAM where graphics objects and the structures containing references to them are stored. It is effectively addressed as the last megabyte of VRAM (regardless of the size of VRAM), but addressed in reverse, and aligned to a 16-byte boundary. If this is difficult to understand, you can convert an address in PRAMIN to a real VRAM address using the following formula (where reversal_unit_size is equal to 16):
`real VRAM address = VRAM_size - (ramin_address - (ramin_address % reversal_unit_size)) - reversal_unit_size + (ramin_address % reversal_unit_size) `
@@ -176,7 +176,7 @@ or in the form of bitwise math - code is from my in progress RIVA 128 emulatino
I'm not entirely sure why they did this, but I assume it was for providing a more convenient interface to the user and for general efficiency reasons.
#### Interrupts
Any graphics card worth its salt needs an interrupt system. So a REALLY good one must have two completely different systems for notifying other parts of the GPU about events, right? There is a traditional interrupt system, with both software and hardware support (indicated by bit 31 of the interrupt status register) controlled by a register in `PMC` that turns on and off interrupts for different components of the GPU. Each component of the GPU also allows individual interrupts to be turned on or off, and has its own interrupt status register. Each component (including the removed-in-revision-B `PAUDIO` for some reason) is represented by a bit in the `PMC` interrupt status register. If the interrupt status register of a component, ANDED with the interrupt status register, is 1, an interrupt is declared to be pending (with some minor exceptions that will be explained in later parts) and a PCI/AGP IRQ is sent. The interrupt registers are set up such that, when they are viewed in hexadecimal, an enabled interrupt appears as a 1 and a disabled interrupt as a 0. Interrupts can be turned off GPU-wide (or for one of just hardware or software) via the `PMC_INTR_EN` register (at `0x0140`)
Any graphics card worth its salt needs an interrupt system. So a REALLY good one must have two completely different systems for notifying other parts of the GPU about events, right? There is a traditional interrupt system, with both software and hardware support (indicated by bit 31 of the interrupt status register) controlled by a register in `PMC` that turns on and off interrupts for different components of the GPU. Each component of the GPU also allows individual interrupts to be turned on or off, and has its own interrupt status register. Each component (including the removed-in-revision-B `PAUDIO` for some reason) is represented by a bit in the `PMC` interrupt status register. If the interrupt status register of a component, ANDED with the interrupt status register, is 1, an interrupt is declared to be pending (with some minor exceptions that will be explained in later parts) and a PCI/AGP IRQ is sent. The interrupt registers are set up such that, when they are viewed in hexadecimal, an enabled interrupt appears as a 1 and a disabled interrupt as a 0. Interrupts can be turned off GPU-wide (or for one of just hardware or software) via the `PMC_INTR_EN` register (at `0x0140`)
This allows an interrupt to be implemented as: