[esp32_hosted] Add configurable SDIO clock frequency (#14319)

Co-authored-by: pre-commit-ci-lite[bot] <117423508+pre-commit-ci-lite[bot]@users.noreply.github.com>
Co-authored-by: Deirdre <obyrne@rk1.lan>
Co-authored-by: Jonathan Swoboda <154711427+swoboda1337@users.noreply.github.com>

esphome/components/esp32_hosted/__init__.py

@@ -23,6 +23,7 @@ CONF_D1_PIN = "d1_pin"
 CONF_D2_PIN = "d2_pin"
 CONF_D3_PIN = "d3_pin"
 CONF_SLOT = "slot"
+CONF_SDIO_FREQUENCY = "sdio_frequency"
 
 CONFIG_SCHEMA = cv.All(
     cv.Schema(
@@ -37,6 +38,9 @@ CONFIG_SCHEMA = cv.All(
             cv.Required(CONF_D3_PIN): pins.internal_gpio_output_pin_number,
             cv.Required(CONF_RESET_PIN): pins.internal_gpio_output_pin_number,
             cv.Optional(CONF_SLOT, default=1): cv.int_range(min=0, max=1),
+            cv.Optional(CONF_SDIO_FREQUENCY, default="40MHz"): cv.All(
+                cv.frequency, cv.Range(min=400e3, max=50e6)
+            ),
         }
     ),
 )
@@ -91,6 +95,10 @@ async def to_code(config):
         config[CONF_D3_PIN],
     )
     esp32.add_idf_sdkconfig_option("CONFIG_ESP_HOSTED_CUSTOM_SDIO_PINS", True)
+    esp32.add_idf_sdkconfig_option(
+        "CONFIG_ESP_HOSTED_SDIO_CLOCK_FREQ_KHZ",
+        int(config[CONF_SDIO_FREQUENCY] // 1000),
+    )
 
     framework_ver: cv.Version = CORE.data[KEY_CORE][KEY_FRAMEWORK_VERSION]
     os.environ["ESP_IDF_VERSION"] = f"{framework_ver.major}.{framework_ver.minor}"

tests/components/esp32_hosted/test-sdio-speed.esp32-p4-idf.yaml

@@ -0,0 +1,16 @@
+esp32_hosted:
+  variant: ESP32C6
+  slot: 1
+  active_high: true
+  reset_pin: GPIO15
+  cmd_pin: GPIO13
+  clk_pin: GPIO12
+  d0_pin: GPIO11
+  d1_pin: GPIO10
+  d2_pin: GPIO9
+  d3_pin: GPIO8
+  sdio_frequency: 8MHz
+
+wifi:
+  ssid: MySSID
+  password: password1