[core] Generate linker scripts based on flash layout
This commit is contained in:
Kuba Szczodrzyński
@@ -3,6 +3,7 @@
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"family": "BK7231N",
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"ldscript": "bk7231n_bsp.ld",
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"bkboot_version": "1.0.1-bk7231n",
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"bkoffset_app": "0x10000",
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"bkrbl_size_app": "0x108700"
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},
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"flash": {
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@@ -3,6 +3,7 @@
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"family": "BK7231U",
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"ldscript": "bk7231_bsp.ld",
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"bkboot_version": "1.0.8-bk7231u",
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"bkoffset_app": "0x10000",
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"bkrbl_size_app": "0x108700"
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},
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"flash": {
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@@ -4,6 +4,7 @@
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"f_cpu": "180000000L",
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"ldscript": "bk7231_bsp.ld",
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"bkboot_version": "0.1.3-bk7252",
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"bkoffset_app": "0x10000",
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"bkrbl_size_app": "0x1A0000"
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},
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"flash": {
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@@ -1,6 +1,5 @@
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{
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"build": {
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"ldscript": "rlx8711B-symbol-v02-img2_xip1_2M_468k_cpp.ld",
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"amb_boot_all": "boot_all_77F7.bin"
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},
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"flash": {
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@@ -1,6 +1,5 @@
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{
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"build": {
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"ldscript": "rlx8711B-symbol-v02-img2_xip1_2M_cpp.ld",
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"amb_boot_all": "boot_all_77F7.bin"
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},
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"flash": {
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@@ -1,6 +1,5 @@
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{
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"build": {
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"ldscript": "rlx8711B-symbol-v02-img2_xip1_4M_980k_cpp.ld",
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"amb_boot_all": "boot_all_C556.bin"
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},
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"flash": {
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@@ -1,6 +1,7 @@
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{
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"build": {
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"family": "RTL8710B",
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"ldscript": "rlx8711B-symbol-v02-img2_xip1.ld",
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"f_cpu": "125000000L",
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"prefix": "arm-none-eabi-",
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"amb_flash_addr": "0x08000000"
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@@ -507,6 +507,8 @@ env.Replace(
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SIZECHECKCMD="$SIZETOOL -A -d $SOURCES",
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SIZEPRINTCMD="$SIZETOOL -B -d $SOURCES",
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)
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# Generate linker scripts with correct flash offsets
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env.GenerateLinkerScript(board, board.get("build.ldscript"))
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def to_offset(addr: int) -> int:
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@@ -259,6 +259,9 @@ env.Replace(
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SIZECHECKCMD="$SIZETOOL -A -d $SOURCES",
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SIZEPRINTCMD="$SIZETOOL -B -d $SOURCES",
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)
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# Generate linker scripts with correct flash offsets
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env.GenerateLinkerScript(board, board.get("build.ldscript"))
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env.GenerateLinkerScript(board, board.get("build.ldscript").replace("xip1", "xip2"))
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env.Append(
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BUILDERS=dict(
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@@ -66,6 +66,7 @@ env.Append(
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found = False
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for f in family.inheritance:
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try:
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env.Prepend(LIBPATH=[join("$CORES_DIR", f.name, "misc")])
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env.SConscript(f"../family/{f.name}.py", must_exist=True)
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found = True
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except UserError:
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@@ -90,7 +91,6 @@ for f in family.inheritance:
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env.Prepend(CPPDEFINES=[(f"LT_{f.short_name}", "1")])
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if f.code:
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env.Prepend(CPPDEFINES=[(f"LT_{f.code.upper()}", "1")])
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env.Prepend(LIBPATH=[join("$CORES_DIR", f.name, "misc")])
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# Sources - external libraries
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queue.AddExternalLibrary("ltchiptool") # uf2ota source code
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@@ -1,11 +1,16 @@
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# Copyright (c) Kuba Szczodrzyński 2022-06-12.
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import re
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from os.path import isfile, join
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from ltchiptool.util.fileio import chext
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from platformio.platform.board import PlatformBoardConfig
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from SCons.Script import DefaultEnvironment, Environment
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env: Environment = DefaultEnvironment()
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def env_add_flash_layout(env: Environment, board):
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def env_add_flash_layout(env: Environment, board: PlatformBoardConfig):
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flash_layout: dict = board.get("flash")
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if flash_layout:
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defines = {}
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@@ -33,4 +38,41 @@ def env_add_flash_layout(env: Environment, board):
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env.Replace(**defines)
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def env_generate_linker_script(env: Environment, board: PlatformBoardConfig, name: str):
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template_name = chext(name, "template.ld")
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# find the linker script template in LIBPATH
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input = None
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for path in env["LIBPATH"]:
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path = env.subst(path)
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if isfile(join(path, template_name)):
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input = join(path, template_name)
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break
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if not input:
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raise FileNotFoundError(template_name)
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# load the .template.ld script
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with open(input, "r") as f:
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ldscript = f.read()
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def transform(match: re.Match[str]):
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key = match[1]
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if key in env:
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return env[key]
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if key.startswith("BOARD_"):
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key = key[6:].lower()
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return board.get(key)
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raise ValueError(f"Unrecognized template key: {key}")
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ldscript = re.sub(r"\${([A-Z0-9_.]+)}", transform, ldscript)
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# write .ld script
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output = join("${BUILD_DIR}", name)
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with open(env.subst(output), "w") as f:
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f.write(ldscript)
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env.Prepend(LIBPATH=["${BUILD_DIR}"])
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env.AddMethod(env_add_flash_layout, "AddFlashLayout")
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env.AddMethod(env_generate_linker_script, "GenerateLinkerScript")
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@@ -29,7 +29,7 @@
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/* Split memory into area for vectors and ram */
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MEMORY
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{
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flash (rx) : ORIGIN = 0x00010000, LENGTH = 1912K
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flash (rx) : ORIGIN = ${BOARD_BUILD.BKOFFSET_APP}, LENGTH = ${BOARD_BUILD.BKRBL_SIZE_APP}
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ram (rw!x): ORIGIN = 0x00400100, LENGTH = 256k - 0x100
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}
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@@ -29,7 +29,7 @@
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/* Split memory into area for vectors and ram */
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MEMORY
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{
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flash (rx) : ORIGIN = 0x00010000, LENGTH = 1912K
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flash (rx) : ORIGIN = ${BOARD_BUILD.BKOFFSET_APP}, LENGTH = ${BOARD_BUILD.BKRBL_SIZE_APP}
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tcm (rw!x): ORIGIN = 0x003F0000, LENGTH = 60k - 512
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itcm (rwx): ORIGIN = 0x003FEE00, LENGTH = 4k + 512
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ram (rw!x): ORIGIN = 0x00400100, LENGTH = 192k - 0x100
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@@ -25,8 +25,8 @@ MEMORY
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XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
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XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
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XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
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XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
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XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
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XIP1 (rx) : ORIGIN = 0x08000000+0x20+${FLASH_OTA1_OFFSET}, LENGTH = ${FLASH_OTA1_OFFSET}-0x20 /* XIP1, 32 Bytes resvd for header */
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XIP2 (rx) : ORIGIN = 0x08000000+0x20+${FLASH_OTA2_OFFSET}, LENGTH = ${FLASH_OTA2_OFFSET}-0x20 /* XIP2, 32 Bytes resvd for header */
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}
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@@ -1,222 +0,0 @@
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ENTRY(Reset_Handler)
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INCLUDE "export-rom_symbol_v01.txt"
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GROUP (
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libgcc.a
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libc.a
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libg.a
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libm.a
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libnosys.a
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)
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
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ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
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BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
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BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
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ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
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MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
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RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
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XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
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XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
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XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
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XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
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XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
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}
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SECTIONS
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{
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.rom.text : { } > ROM
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.rom.rodata : { } > ROM
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.ARM.exidx :
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{
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__exidx_start = .;
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*(.ARM.exidx*)
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*(.gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > ROM
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.hal.rom.bss : { } > ROMBSS_RAM
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/* image1 entry, this section should in RAM and fixed address for ROM */
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.ram_image1.entry :
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{
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__ram_image1_text_start__ = .;
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__ram_start_table_start__ = .;
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KEEP(*(SORT(.image1.entry.data*)))
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__ram_start_table_end__ = .;
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__image1_validate_code__ = .;
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KEEP(*(.image1.validate.rodata*))
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KEEP(*(.image1.export.symb*))
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} > BOOTLOADER_RAM
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/* Add . to assign the start address of the section */
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/* to prevent the change of the start address by ld doing section alignment */
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.ram_image1.text . :
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{
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/* image1 text */
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*(.boot.ram.text*)
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*(.boot.rodata*)
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} > BOOTLOADER_RAM
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.ram_image1.data . :
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{
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__ram_image1_data_start__ = .;
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KEEP(*(.boot.ram.data*))
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__ram_image1_data_end__ = .;
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__ram_image1_text_end__ = .;
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} > BOOTLOADER_RAM
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.ram_image1.bss . :
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{
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__image1_bss_start__ = .;
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KEEP(*(.boot.ram.bss*))
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KEEP(*(.boot.ram.end.bss*))
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__image1_bss_end__ = .;
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} > BOOTLOADER_RAM
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.ram_image2.entry :
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{
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__ram_image2_text_start__ = .;
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__image2_entry_func__ = .;
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KEEP(*(SORT(.image2.entry.data*)))
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__image2_validate_code__ = .;
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KEEP(*(.image2.validate.rodata*))
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} > BD_RAM
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.ram_image2.text :
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{
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KEEP(*(.image2.ram.text*))
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} > BD_RAM
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.ram_image2.data :
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{
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__data_start__ = .;
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*(.data*)
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__data_end__ = .;
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__ram_image2_text_end__ = .;
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. = ALIGN(16);
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} > BD_RAM
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.ram_image2.bss :
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{
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__bss_start__ = .;
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*(.bss*)
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*(COMMON)
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} > BD_RAM
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.ram_image2.skb.bss :
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{
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*(.bdsram.data*)
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__bss_end__ = .;
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} > BD_RAM
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.ram_heap.data :
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{
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*(.bfsram.data*)
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} > BD_RAM
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. = ALIGN(8);
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PROVIDE(heap_start = .);
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PROVIDE(heap_end = 0x1003CFFF);
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PROVIDE(heap_len = heap_end - heap_start);
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.rom.bss :
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{
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*(.heap.stdlib*)
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} > ROM_BSS_RAM
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.ram_rdp.text :
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{
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__rom_top_4k_start_ = .;
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__rdp_text_start__ = .;
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KEEP(*(.rdp.ram.text*))
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KEEP(*(.rdp.ram.data*))
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__rdp_text_end__ = .;
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. = ALIGN(16);
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} > RDP_RAM
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.xip_image1.text :
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{
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__flash_boot_text_start__ = .;
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*(.flashboot.text*)
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__flash_boot_text_end__ = .;
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. = ALIGN(16);
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} > XIPBOOT
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.xip_image2.text :
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{
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__flash_text_start__ = .;
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*(.img2_custom_signature*)
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*(.text)
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*(.text*)
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*(.rodata)
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*(.rodata*)
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*(.debug_trace*)
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/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
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KEEP(*crtbegin.o(.ctors))
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KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
|
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KEEP(*(SORT(.ctors.*)))
|
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KEEP(*crtend.o(.ctors))
|
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KEEP(*crtbegin.o(.dtors))
|
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KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
|
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KEEP(*(SORT(.dtors.*)))
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KEEP(*crtend.o(.dtors))
|
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*(.rodata .rodata.* .gnu.linkonce.r.*)
|
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|
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/* Add This for C++ support */
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/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
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. = ALIGN(4);
|
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__preinit_array_start = .;
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KEEP(*(.preinit_array))
|
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__preinit_array_end = .;
|
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. = ALIGN(4);
|
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__init_array_start = .;
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
|
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__init_array_end = .;
|
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. = ALIGN(4);
|
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__fini_array_start = .;
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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__fini_array_end = .;
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/*-----------------*/
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. = ALIGN (4);
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__cmd_table_start__ = .;
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KEEP(*(.cmd.table.data*))
|
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__cmd_table_end__ = .;
|
||||
|
||||
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
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KEEP(*(.init))
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KEEP(*(.fini))
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||||
*(.init)
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||||
*(.fini)
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|
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__flash_text_end__ = .;
|
||||
|
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. = ALIGN (16);
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} > XIP1
|
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}
|
||||
|
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SECTIONS
|
||||
{
|
||||
/* Bootloader symbol list */
|
||||
boot_export_symbol = 0x10002020;
|
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}
|
||||
@@ -1,222 +0,0 @@
|
||||
|
||||
|
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ENTRY(Reset_Handler)
|
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|
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INCLUDE "export-rom_symbol_v01.txt"
|
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|
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GROUP (
|
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libgcc.a
|
||||
libc.a
|
||||
libg.a
|
||||
libm.a
|
||||
libnosys.a
|
||||
)
|
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|
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MEMORY
|
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{
|
||||
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
|
||||
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
|
||||
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
|
||||
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
|
||||
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
|
||||
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
|
||||
|
||||
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
|
||||
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
|
||||
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
|
||||
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
|
||||
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.rom.text : { } > ROM
|
||||
.rom.rodata : { } > ROM
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > ROM
|
||||
.hal.rom.bss : { } > ROMBSS_RAM
|
||||
|
||||
/* image1 entry, this section should in RAM and fixed address for ROM */
|
||||
.ram_image1.entry :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.image1.entry.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.image1.export.symb*))
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
/* Add . to assign the start address of the section */
|
||||
/* to prevent the change of the start address by ld doing section alignment */
|
||||
.ram_image1.text . :
|
||||
{
|
||||
/* image1 text */
|
||||
*(.boot.ram.text*)
|
||||
*(.boot.rodata*)
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.data . :
|
||||
{
|
||||
__ram_image1_data_start__ = .;
|
||||
KEEP(*(.boot.ram.data*))
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
__ram_image1_text_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.bss . :
|
||||
{
|
||||
__image1_bss_start__ = .;
|
||||
KEEP(*(.boot.ram.bss*))
|
||||
KEEP(*(.boot.ram.end.bss*))
|
||||
__image1_bss_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image2.entry :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
KEEP(*(SORT(.image2.entry.data*)))
|
||||
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
KEEP(*(.image2.ram.text*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.skb.bss :
|
||||
{
|
||||
*(.bdsram.data*)
|
||||
__bss_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap.data :
|
||||
{
|
||||
*(.bfsram.data*)
|
||||
} > BD_RAM
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(heap_start = .);
|
||||
PROVIDE(heap_end = 0x1003CFFF);
|
||||
PROVIDE(heap_len = heap_end - heap_start);
|
||||
|
||||
.rom.bss :
|
||||
{
|
||||
*(.heap.stdlib*)
|
||||
} > ROM_BSS_RAM
|
||||
|
||||
.ram_rdp.text :
|
||||
{
|
||||
__rom_top_4k_start_ = .;
|
||||
__rdp_text_start__ = .;
|
||||
KEEP(*(.rdp.ram.text*))
|
||||
KEEP(*(.rdp.ram.data*))
|
||||
__rdp_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
|
||||
} > RDP_RAM
|
||||
|
||||
.xip_image1.text :
|
||||
{
|
||||
__flash_boot_text_start__ = .;
|
||||
|
||||
*(.flashboot.text*)
|
||||
|
||||
__flash_boot_text_end__ = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
} > XIPBOOT
|
||||
|
||||
.xip_image2.text :
|
||||
{
|
||||
__flash_text_start__ = .;
|
||||
|
||||
*(.img2_custom_signature*)
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.debug_trace*)
|
||||
|
||||
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
|
||||
KEEP(*crtbegin.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*crtend.o(.ctors))
|
||||
KEEP(*crtbegin.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*crtend.o(.dtors))
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
|
||||
/* Add This for C++ support */
|
||||
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP(*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
__init_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
/*-----------------*/
|
||||
|
||||
. = ALIGN (4);
|
||||
__cmd_table_start__ = .;
|
||||
KEEP(*(.cmd.table.data*))
|
||||
__cmd_table_end__ = .;
|
||||
|
||||
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
|
||||
__flash_text_end__ = .;
|
||||
|
||||
. = ALIGN (16);
|
||||
} > XIP1
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Bootloader symbol list */
|
||||
boot_export_symbol = 0x10002020;
|
||||
}
|
||||
@@ -25,8 +25,8 @@ MEMORY
|
||||
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
|
||||
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
|
||||
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
|
||||
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0x75000-0x20 /* XIP1: 468k, 32 Bytes resvd for header */
|
||||
XIP2 (rx) : ORIGIN = 0x08080000+0x20, LENGTH = 0x75000-0x20 /* XIP2: 468k, 32 Bytes resvd for header */
|
||||
XIP1 (rx) : ORIGIN = 0x08000000+0x20+${FLASH_OTA1_OFFSET}, LENGTH = ${FLASH_OTA1_OFFSET}-0x20 /* XIP1, 32 Bytes resvd for header */
|
||||
XIP2 (rx) : ORIGIN = 0x08000000+0x20+${FLASH_OTA2_OFFSET}, LENGTH = ${FLASH_OTA2_OFFSET}-0x20 /* XIP2, 32 Bytes resvd for header */
|
||||
}
|
||||
|
||||
|
||||
@@ -1,222 +0,0 @@
|
||||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_symbol_v01.txt"
|
||||
|
||||
GROUP (
|
||||
libgcc.a
|
||||
libc.a
|
||||
libg.a
|
||||
libm.a
|
||||
libnosys.a
|
||||
)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
|
||||
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
|
||||
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
|
||||
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
|
||||
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
|
||||
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
|
||||
|
||||
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
|
||||
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
|
||||
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
|
||||
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xC5000-0x20 /* XIP1: 788k, 32 Bytes resvd for header */
|
||||
XIP2 (rx) : ORIGIN = 0x080D0000+0x20, LENGTH = 0xC5000-0x20 /* XIP2: 788k, 32 Bytes resvd for header */
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.rom.text : { } > ROM
|
||||
.rom.rodata : { } > ROM
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > ROM
|
||||
.hal.rom.bss : { } > ROMBSS_RAM
|
||||
|
||||
/* image1 entry, this section should in RAM and fixed address for ROM */
|
||||
.ram_image1.entry :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.image1.entry.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.image1.export.symb*))
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
/* Add . to assign the start address of the section */
|
||||
/* to prevent the change of the start address by ld doing section alignment */
|
||||
.ram_image1.text . :
|
||||
{
|
||||
/* image1 text */
|
||||
*(.boot.ram.text*)
|
||||
*(.boot.rodata*)
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.data . :
|
||||
{
|
||||
__ram_image1_data_start__ = .;
|
||||
KEEP(*(.boot.ram.data*))
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
__ram_image1_text_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.bss . :
|
||||
{
|
||||
__image1_bss_start__ = .;
|
||||
KEEP(*(.boot.ram.bss*))
|
||||
KEEP(*(.boot.ram.end.bss*))
|
||||
__image1_bss_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image2.entry :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
KEEP(*(SORT(.image2.entry.data*)))
|
||||
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
KEEP(*(.image2.ram.text*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.skb.bss :
|
||||
{
|
||||
*(.bdsram.data*)
|
||||
__bss_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap.data :
|
||||
{
|
||||
*(.bfsram.data*)
|
||||
} > BD_RAM
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(heap_start = .);
|
||||
PROVIDE(heap_end = 0x1003CFFF);
|
||||
PROVIDE(heap_len = heap_end - heap_start);
|
||||
|
||||
.rom.bss :
|
||||
{
|
||||
*(.heap.stdlib*)
|
||||
} > ROM_BSS_RAM
|
||||
|
||||
.ram_rdp.text :
|
||||
{
|
||||
__rom_top_4k_start_ = .;
|
||||
__rdp_text_start__ = .;
|
||||
KEEP(*(.rdp.ram.text*))
|
||||
KEEP(*(.rdp.ram.data*))
|
||||
__rdp_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
|
||||
} > RDP_RAM
|
||||
|
||||
.xip_image1.text :
|
||||
{
|
||||
__flash_boot_text_start__ = .;
|
||||
|
||||
*(.flashboot.text*)
|
||||
|
||||
__flash_boot_text_end__ = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
} > XIPBOOT
|
||||
|
||||
.xip_image2.text :
|
||||
{
|
||||
__flash_text_start__ = .;
|
||||
|
||||
*(.img2_custom_signature*)
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.debug_trace*)
|
||||
|
||||
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
|
||||
KEEP(*crtbegin.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*crtend.o(.ctors))
|
||||
KEEP(*crtbegin.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*crtend.o(.dtors))
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
|
||||
/* Add This for C++ support */
|
||||
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP(*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
__init_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
/*-----------------*/
|
||||
|
||||
. = ALIGN (4);
|
||||
__cmd_table_start__ = .;
|
||||
KEEP(*(.cmd.table.data*))
|
||||
__cmd_table_end__ = .;
|
||||
|
||||
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
|
||||
__flash_text_end__ = .;
|
||||
|
||||
. = ALIGN (16);
|
||||
} > XIP2
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Bootloader symbol list */
|
||||
boot_export_symbol = 0x10002020;
|
||||
}
|
||||
@@ -1,222 +0,0 @@
|
||||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
INCLUDE "export-rom_symbol_v01.txt"
|
||||
|
||||
GROUP (
|
||||
libgcc.a
|
||||
libc.a
|
||||
libg.a
|
||||
libm.a
|
||||
libnosys.a
|
||||
)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x80000 /* ROM: 512k */
|
||||
ROMBSS_RAM (rw) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* ROM BSS RAM: 8K */
|
||||
BOOTLOADER_RAM (rwx) : ORIGIN = 0x10002000, LENGTH = 0x3000 /* BOOT Loader RAM: 12K */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10005000, LENGTH = 0x38000 /* MAIN RAM: 224k */
|
||||
ROM_BSS_RAM (rwx) : ORIGIN = 0x1003D000, LENGTH = 0x1000 /* ROM BSS RAM: 4K */
|
||||
MSP_RAM (wx) : ORIGIN = 0x1003E000, LENGTH = 0x1000 /* MSP RAM: 4k */
|
||||
RDP_RAM (wx) : ORIGIN = 0x1003F000, LENGTH = 0xFF0 /* RDP RAM: 4k-0x10 */
|
||||
|
||||
XIPBOOT (rx) : ORIGIN = 0x08000000+0x20, LENGTH = 0x04000-0x20 /* XIPBOOT: 16k, 32 Bytes resvd for header*/
|
||||
XIPSYS (r) : ORIGIN = 0x08009000, LENGTH = 0x1000 /* XIPSYS: 4K system data in flash */
|
||||
XIPCAL (r) : ORIGIN = 0x0800A000, LENGTH = 0x1000 /* XIPCAL: 4K calibration data in flash */
|
||||
XIP1 (rx) : ORIGIN = 0x0800B000+0x20, LENGTH = 0xF5000-0x20 /* XIP1: 980k, 32 Bytes resvd for header */
|
||||
XIP2 (rx) : ORIGIN = 0x08100000+0x20, LENGTH = 0xF5000-0x20 /* XIP2: 980k, 32 Bytes resvd for header */
|
||||
}
|
||||
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.rom.text : { } > ROM
|
||||
.rom.rodata : { } > ROM
|
||||
.ARM.exidx :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
*(.gnu.linkonce.armexidx.*)
|
||||
__exidx_end = .;
|
||||
} > ROM
|
||||
.hal.rom.bss : { } > ROMBSS_RAM
|
||||
|
||||
/* image1 entry, this section should in RAM and fixed address for ROM */
|
||||
.ram_image1.entry :
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.image1.entry.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
KEEP(*(.image1.export.symb*))
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
/* Add . to assign the start address of the section */
|
||||
/* to prevent the change of the start address by ld doing section alignment */
|
||||
.ram_image1.text . :
|
||||
{
|
||||
/* image1 text */
|
||||
*(.boot.ram.text*)
|
||||
*(.boot.rodata*)
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.data . :
|
||||
{
|
||||
__ram_image1_data_start__ = .;
|
||||
KEEP(*(.boot.ram.data*))
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
__ram_image1_text_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image1.bss . :
|
||||
{
|
||||
__image1_bss_start__ = .;
|
||||
KEEP(*(.boot.ram.bss*))
|
||||
KEEP(*(.boot.ram.end.bss*))
|
||||
__image1_bss_end__ = .;
|
||||
} > BOOTLOADER_RAM
|
||||
|
||||
.ram_image2.entry :
|
||||
{
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
KEEP(*(SORT(.image2.entry.data*)))
|
||||
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
KEEP(*(.image2.ram.text*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.skb.bss :
|
||||
{
|
||||
*(.bdsram.data*)
|
||||
__bss_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap.data :
|
||||
{
|
||||
*(.bfsram.data*)
|
||||
} > BD_RAM
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE(heap_start = .);
|
||||
PROVIDE(heap_end = 0x1003CFFF);
|
||||
PROVIDE(heap_len = heap_end - heap_start);
|
||||
|
||||
.rom.bss :
|
||||
{
|
||||
*(.heap.stdlib*)
|
||||
} > ROM_BSS_RAM
|
||||
|
||||
.ram_rdp.text :
|
||||
{
|
||||
__rom_top_4k_start_ = .;
|
||||
__rdp_text_start__ = .;
|
||||
KEEP(*(.rdp.ram.text*))
|
||||
KEEP(*(.rdp.ram.data*))
|
||||
__rdp_text_end__ = .;
|
||||
. = ALIGN(16);
|
||||
|
||||
} > RDP_RAM
|
||||
|
||||
.xip_image1.text :
|
||||
{
|
||||
__flash_boot_text_start__ = .;
|
||||
|
||||
*(.flashboot.text*)
|
||||
|
||||
__flash_boot_text_end__ = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
} > XIPBOOT
|
||||
|
||||
.xip_image2.text :
|
||||
{
|
||||
__flash_text_start__ = .;
|
||||
|
||||
*(.img2_custom_signature*)
|
||||
*(.text)
|
||||
*(.text*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.debug_trace*)
|
||||
|
||||
/* https://www.embedded.com/building-bare-metal-arm-systems-with-gnu-part-3/ */
|
||||
KEEP(*crtbegin.o(.ctors))
|
||||
KEEP(*(EXCLUDE_FILE (*ctrend.o) .ctors))
|
||||
KEEP(*(SORT(.ctors.*)))
|
||||
KEEP(*crtend.o(.ctors))
|
||||
KEEP(*crtbegin.o(.dtors))
|
||||
KEEP(*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP(*(SORT(.dtors.*)))
|
||||
KEEP(*crtend.o(.dtors))
|
||||
*(.rodata .rodata.* .gnu.linkonce.r.*)
|
||||
|
||||
/* Add This for C++ support */
|
||||
/* ambd_arduino/Arduino_package/hardware/variants/rtl8720dn_bw16/linker_scripts/gcc/rlx8721d_img2_is_arduino.ld */
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP(*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
__init_array_end = .;
|
||||
. = ALIGN(4);
|
||||
__fini_array_start = .;
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
__fini_array_end = .;
|
||||
/*-----------------*/
|
||||
|
||||
. = ALIGN (4);
|
||||
__cmd_table_start__ = .;
|
||||
KEEP(*(.cmd.table.data*))
|
||||
__cmd_table_end__ = .;
|
||||
|
||||
/* https://community.silabs.com/s/article/understand-the-gnu-linker-script-of-cortex-m4?language=en_US */
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
*(.init)
|
||||
*(.fini)
|
||||
|
||||
__flash_text_end__ = .;
|
||||
|
||||
. = ALIGN (16);
|
||||
} > XIP2
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Bootloader symbol list */
|
||||
boot_export_symbol = 0x10002020;
|
||||
}
|
||||
Reference in New Issue
Block a user