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CS423x: Always enable OPL3 on CS4232/4236 during context switch as they lack X registers
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@@ -568,7 +568,11 @@ cs423x_ctxswitch_write(uint16_t addr, UNUSED(uint8_t val), void *priv)
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{
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cs423x_t *dev = (cs423x_t *) priv;
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uint8_t ctx = (dev->regs[7] & 0x80);
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uint8_t enable_opl = (dev->ad1848.xregs[4] & 0x10) && !(dev->indirect_regs[2] & 0x85);
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uint8_t enable_opl = (dev->ad1848.xregs[4] & 0x10) && !(dev->indirect_regs[2] & 0x85); /* CS4236B+ */
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/* CS4232/4236 (non-B) doesn't have an IFM bit, always enable the OPL on these chips */
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if (dev->type <= CRYSTAL_CS4236)
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enable_opl = 1;
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/* Check if a context switch (WSS=1 <-> SBPro=0) occurred through the address being written. */
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if ((dev->regs[7] & 0x80) ? ((addr & 0xfff0) == dev->sb_base) : ((addr & 0xfffc) == dev->wss_base)) {
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