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Still increment the get address if a software method is found. This might cause slightly more cache errors and FIFO refills, but seems like the correct thing to do. It also prevents endless loops of finding bugs while debugging

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starfrost013
2025-07-15 16:45:40 +01:00
parent 383a8f468d
commit 9968645f1d
5 changed files with 17 additions and 17 deletions
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3
CMakePresets.json
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@@ -36,7 +36,8 @@
"name": "debug",
"cacheVariables": {
"CMAKE_BUILD_TYPE": "Debug",
"NV_LOG": "ON"
"NV_LOG": "ON",
"NV_LOG_ULTRA": "ON"
},
"inherits": "base"
},

3
src/include/86box/nv/vid_nv3.h
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@@ -951,9 +951,6 @@ extern const device_config_t nv3t_config[]; // Confi
#define NV3_CRTC_REGISTER_RMA_MODE_MAX 0x0F
/*
STRUCTURES FOR THE GPU START HERE
OBJECT CLASS & RENDERING RELATED STUFF IS IN VID_NV3_CLASSES.H

6
src/video/nv/nv3/nv3_core_arbiter.c
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@@ -114,8 +114,8 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address)
nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning unmapped pattern]\n", address);
#endif
// I don't know why the real hardware does this. But it does.
return (ret & 1) ? 0x20 : 0x07;
// The real hardware returns a garbage pattern
return 0x00;
}
return ret;
@@ -132,7 +132,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value)
// Ensure the addresses are dword aligned.
// I don't know why this is needed because writepriv32 is always to dword align, but it crashes if you don't do this.
// I don't know why this is needed because writepriv32 is always dword aligned in Nvidia's drivers, but it crashes if you don't do this.
// Exclude the 4bpp/8bpp CLUT for this purpose
if (!(address >= NV3_USER_DAC_PALETTE_START && address <= NV3_USER_DAC_PALETTE_END))
address &= 0xFFFFFC;

20
src/video/nv/nv3/subsystems/nv3_pfifo.c
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@@ -927,7 +927,17 @@ void nv3_pfifo_cache1_pull(void)
uint8_t class_id = ((nv3_ramin_context_t*)&current_context)->class_id;
// Tell the CPU if we found a software method
// start by incrementing
uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1;
if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX
next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1);
else
next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1);
// Tell the CPU if we found a software method
//bit23 unset=software
//bit23 set=hardware
if (!(current_context & 0x800000))
@@ -940,14 +950,6 @@ void nv3_pfifo_cache1_pull(void)
return;
}
// start by incrementing
uint32_t next_get_address = nv3_pfifo_cache1_gray2normal(get_index) + 1;
if (nv3->nvbase.gpu_revision >= NV3_PCI_CFG_REVISION_C00) // RIVA 128ZX
next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_C - 1);
else
next_get_address &= (NV3_PFIFO_CACHE1_SIZE_REV_AB - 1);
// Is this needed?
nv3->pfifo.cache1_settings.get_address = nv3_pfifo_cache1_normal2gray(next_get_address) << 2;

2
src/video/nv/nv3/subsystems/nv3_pramin.c
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@@ -508,7 +508,7 @@ void nv3_debug_ramin_print_context_info(uint32_t name, nv3_ramin_context_t conte
nv_log_verbose_only("Context:\n");
nv_log_verbose_only("DMA Channel %d (0-7 valid)\n", context.channel);
nv_log_verbose_only("Class ID: =0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]);
nv_log_verbose_only("Class ID: 0x%04x (%s)\n", context.class_id & 0x1F, nv3_class_names[context.class_id & 0x1F]);
nv_log_verbose_only("Render Engine %d (0=Software, also DMA? 1=Accelerated Renderer)\n", context.is_rendering);
nv_log_verbose_only("PRAMIN Offset 0x%08x\n", context.ramin_offset << 4);
#endif