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synced 2026-02-24 10:28:19 -07:00
Workaround for 86box dynarec design allowing the riva to overwrite old graphics objects.
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@@ -127,7 +127,14 @@ uint32_t nv3_mmio_read32(uint32_t addr, void* priv)
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}
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return nv3_mmio_arbitrate_read(addr);
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ret = nv3_mmio_arbitrate_read(addr);
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// This may get around the riva shredding its own cache
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//nv3_pfifo_cache0_pull();
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//nv3_pfifo_cache1_pull();
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return ret;
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}
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// Write 8-bit MMIO
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@@ -206,6 +213,10 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
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}
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nv3_mmio_arbitrate_write(addr, val);
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// This may get around the riva shredding its own cache
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//nv3_pfifo_cache0_pull();
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//nv3_pfifo_cache1_pull();
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}
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// PCI stuff
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@@ -267,7 +267,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
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break;
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/* Cache1 is handled below */
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/* Cache1 is handled below - cache0 only has one entry */
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case NV3_PFIFO_CACHE0_CTX:
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ret = nv3->pfifo.cache0_settings.context[0];
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break;
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@@ -293,7 +293,7 @@ uint32_t nv3_pfifo_read(uint32_t address)
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{
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nv_log("PFIFO Cache0 Read\n");
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if (address & 4)
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if (address & 4)
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return nv3->pfifo.cache0_entry.data;
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else
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return nv3->pfifo.cache0_entry.method | (nv3->pfifo.cache0_entry.subchannel << NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL);
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@@ -545,8 +545,12 @@ void nv3_pfifo_write(uint32_t address, uint32_t val)
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}
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else if (address >= NV3_PFIFO_CACHE0_METHOD_START && address <= NV3_PFIFO_CACHE0_METHOD_END)
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{
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// 3104 always written after 3100
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if (address & 4)
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{
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nv3->pfifo.cache0_entry.data = val;
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nv3_pfifo_cache0_pull(); // immediately pull out
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}
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else
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nv3->pfifo.cache0_entry.method = (val & 0x1FFC);
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nv3->pfifo.cache0_entry.subchannel = (val >> NV3_PFIFO_CACHE1_METHOD_SUBCHANNEL) & 0x07;
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@@ -66,4 +66,8 @@ uint32_t nv3_user_read(uint32_t address)
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void nv3_user_write(uint32_t address, uint32_t value)
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{
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nv3_pfifo_cache1_push(address, value);
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// This isn't ideal, but otherwise, the dynarec causes the GPU to write so many objects into CACHE1, it starts overwriting the old objects
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// This basically makes the fifo not a fifo, but oh well
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nv3_pfifo_cache1_pull();
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}
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