Merge remote-tracking branch 'upstream/master' into feature/mtrr

2026-02-22 17:45:31 -07:00 · 2023-07-11 11:19:56 -04:00
parent 0b3179fcfb 6b6ca9844b
commit cccbe17fdc
291 changed files with 7862 additions and 4659 deletions
--- a/.ci/AppImageBuilder.yml
+++ b/.ci/AppImageBuilder.yml
@@ -60,7 +60,6 @@ AppDir:
    - libslirp0 # if SLIRP_EXTERNAL:BOOL=ON
    - libsndio7.0 # if OPENAL:BOOL=ON
    - libvdeplug-dev # -dev also pulls in libvdeplug2. -dev is required to get the proper .so symlink to the library
-    - libwayland-client0 # if QT:BOOL=ON
    - libx11-6 # if QT:BOOL=ON
    - libx11-xcb1 # if QT:BOOL=ON
    - libxcb1 # if QT:BOOL=ON
--- a/.ci/build.sh
+++ b/.ci/build.sh
@@ -24,8 +24,8 @@
 # - For Windows (MSYS MinGW) builds:
 #   - Packaging requires 7-Zip on Program Files
 #   - Packaging the Ghostscript DLL requires 32-bit and/or 64-bit Ghostscript on Program Files
-#   - Packaging the FluidSynth DLL requires it to be at /home/86Box/dll32/libfluidsynth.dll
-#     and/or /home/86Box/dll64/libfluidsynth64.dll (for 32-bit and 64-bit builds respectively)
+#   - Packaging the XAudio2 DLL for FAudio requires it to be at /home/86Box/dll32/xaudio2*.dll
+#     and/or /home/86Box/dll64/xaudio2*.dll (for 32-bit and 64-bit builds respectively)
 # - For Linux builds:
 #   - Only Debian and derivatives are supported
 #   - dpkg and apt-get are called through sudo to manage dependencies; make sure those
@@ -259,6 +259,7 @@ case $arch in
 esac
 [ ! -e "cmake/$toolchain.cmake" ] && toolchain=flags-gcc
 toolchain_file="cmake/$toolchain.cmake"
+toolchain_file_libs=

 # Perform platform-specific setup.
 strip_binary=strip
@@ -577,7 +578,7 @@ else
 		pkgs="$pkgs build-essential"
 	else
 		# Add foreign architecture if required.
-		if ! dpkg --print-foreign-architectures | grep -Fx "$arch_deb"
+		if ! dpkg --print-foreign-architectures | grep -Fqx "$arch_deb"
 		then
 			sudo dpkg --add-architecture "$arch_deb"

@@ -594,7 +595,7 @@ else
 	# ...and the ones we do want listed. Non-dev packages fill missing spots on the list.
 	libpkgs=""
 	longest_libpkg=0
-	for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev
+	for pkg in libc6-dev libstdc++6 libopenal-dev libfreetype6-dev libx11-dev libsdl2-dev libpng-dev librtmidi-dev qtdeclarative5-dev libwayland-dev libevdev-dev libxkbcommon-x11-dev libglib2.0-dev libslirp-dev libfaudio-dev libaudio-dev libjack-jackd2-dev libpipewire-0.3-dev libsamplerate0-dev libsndio-dev libvdeplug-dev libfluidsynth-dev
 	do
 		libpkgs="$libpkgs $pkg:$arch_deb"
 		length=$(echo -n $pkg | sed 's/-dev$//' | sed "s/qtdeclarative/qt/" | wc -c)
@@ -615,10 +616,7 @@ else
 		*)	libdir="$arch_triplet";;
 	esac

-	# Create CMake cross toolchain file. The file is saved on a fixed location for
-	# the library builds we do later, since running CMake again on a library we've
-	# already built before will *not* update its toolchain file path; therefore, we
-	# cannot point them to our working directory, which may change across builds.
+	# Create CMake cross toolchain file.
 	toolchain_file_new="$cache_dir/toolchain.$arch_deb.cmake"
 	cat << EOF > "$toolchain_file_new"
 set(CMAKE_SYSTEM_NAME Linux)
@@ -646,6 +644,14 @@ EOF
 	toolchain_file="$toolchain_file_new"
 	strip_binary="$arch_triplet-strip"

+	# Create a separate toolchain file for library compilation without including
+	# our own toolchain files, letting libraries set their own C(XX)FLAGS instead.
+	# The file is saved on a fixed location, since running CMake again on a library
+	# we've already built before will *not* update its toolchain file path; therefore,
+	# we cannot point them to our working directory, which may change across builds.
+	toolchain_file_libs="$cache_dir/toolchain.$arch_deb.libs.cmake"
+	grep -Ev "^include\(" "$toolchain_file" > "$toolchain_file_libs"
+
 	# Install dependencies only if we're in a new build and/or architecture.
 	if check_buildtag "$arch_deb"
 	then
@@ -804,8 +810,8 @@ then
 	"$sevenzip" e -y -o"archive_tmp" "$discord_zip" "lib/$arch_discord/discord_game_sdk.dll"
 	[ ! -e "archive_tmp/discord_game_sdk.dll" ] && echo [!] No Discord Game SDK for architecture [$arch_discord]

-	# Archive other DLLs from local directory.
-	cp -p "/home/$project/dll$arch/"* archive_tmp/
+	# Archive XAudio2 DLL if required.
+	grep -q "OPENAL:BOOL=ON" build/CMakeCache.txt || cp -p "/home/$project/dll$arch/xaudio2"* archive_tmp/

 	# Archive executable, while also stripping it if requested.
 	if [ $strip -ne 0 ]
@@ -885,11 +891,6 @@ else
 	cwd_root="$(pwd)"
 	check_buildtag "libs.$arch_deb"

-	cp cmake/flags-gcc.cmake cmake/flags-gcc.cmake.old
-	sed -i -e 's/ -Werror=.*\([" ]\)/\1/g' cmake/flags-gcc.cmake # temporary hack for -Werror=old-style-definition non-compliance on FluidSynth and SDL2
-	sed -i -e 's/ C;CXX/ IGNORED/' cmake/flags-gcc.cmake # workaround for dynamic c(xx)flags system overwriting library flags and breaking (at least) openal-soft
-	sed -i -e 's/_INIT / /g' cmake/flags-gcc.cmake # still append our own flags
-
 	if grep -q "OPENAL:BOOL=ON" build/CMakeCache.txt
 	then
 		# Build openal-soft 1.23.1 manually to fix audio issues. This is a temporary
@@ -906,7 +907,7 @@ else
 		sed -i -e 's/PW_KEY_CONFIG_NAME/"config.name"/g' "$prefix/alc/backends/pipewire.cpp"

 		prefix_build="$prefix/build-$arch_deb"
-		cmake -G Ninja -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
+		cmake -G Ninja -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
 		cmake --build "$prefix_build" -j$(nproc) || exit 99
 		cmake --install "$prefix_build" || exit 99

@@ -922,7 +923,7 @@ else
 			wget -qO - https://github.com/FNA-XNA/FAudio/archive/refs/tags/22.03.tar.gz | tar zxf - -C "$cache_dir" || rm -rf "$prefix"
 		fi
 		prefix_build="$prefix/build-$arch_deb"
-		cmake -G Ninja -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
+		cmake -G Ninja -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
 		cmake --build "$prefix_build" -j$(nproc) || exit 99
 		cmake --install "$prefix_build" || exit 99

@@ -943,7 +944,7 @@ else
 		wget -qO - https://github.com/thestk/rtmidi/archive/refs/tags/4.0.0.tar.gz | tar zxf - -C "$cache_dir" || rm -rf "$prefix"
 	fi
 	prefix_build="$prefix/build-$arch_deb"
-	cmake -G Ninja -D RTMIDI_API_JACK=OFF -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
+	cmake -G Ninja -D RTMIDI_API_JACK=OFF -D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" -S "$prefix" -B "$prefix_build" || exit 99
 	cmake --build "$prefix_build" -j$(nproc) || exit 99
 	cmake --install "$prefix_build" || exit 99

@@ -957,7 +958,7 @@ else
 	fi
 	prefix_build="$prefix/build-$arch_deb"
 	cmake -G Ninja -D enable-dbus=OFF -D enable-jack=OFF -D enable-oss=OFF -D enable-sdl2=OFF -D enable-pulseaudio=OFF -D enable-pipewire=OFF -D enable-alsa=OFF \
-		-D "CMAKE_TOOLCHAIN_FILE=$toolchain_file" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" \
+		-D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" \
 		-S "$prefix" -B "$prefix_build" || exit 99
 	cmake --build "$prefix_build" -j$(nproc) || exit 99
 	cmake --install "$prefix_build" || exit 99
@@ -988,12 +989,19 @@ else
 		-D SDL_ATOMIC=OFF -D SDL_EVENTS=ON -D SDL_HAPTIC=OFF -D SDL_POWER=OFF -D SDL_THREADS=ON -D SDL_TIMERS=ON -D SDL_FILE=OFF \
 		-D SDL_LOADSO=ON -D SDL_CPUINFO=ON -D SDL_FILESYSTEM=$sdl_ui -D SDL_DLOPEN=OFF -D SDL_SENSOR=OFF -D SDL_LOCALE=OFF \
 		\
-		-D "CMAKE_TOOLCHAIN_FILE=$toolchain_file" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" \
+		-D "CMAKE_TOOLCHAIN_FILE=$toolchain_file_libs" -D "CMAKE_INSTALL_PREFIX=$cwd_root/archive_tmp/usr" \
 		-S "$prefix" -B "$prefix_build" || exit 99
 	cmake --build "$prefix_build" -j$(nproc) || exit 99
 	cmake --install "$prefix_build" || exit 99

-	mv cmake/flags-gcc.cmake.old cmake/flags-gcc.cmake
+	# We rely on the host to provide Vulkan libs to sidestep any potential
+	# dependency issues. While Qt expects libvulkan.so, at least Debian only
+	# ships libvulkan.so.1 without a symlink, so make our own as a workaround.
+	# The relative paths prevent appimage-builder from flattening the links.
+	mkdir -p "archive_tmp/usr/lib/$libdir"
+	relroot="../../../../../../../../../../../../../../../../../../../../../../../../../../../../.."
+	ln -s "$relroot/usr/lib/libvulkan.so.1" "archive_tmp/usr/lib/libvulkan.so"
+	ln -s "$relroot/usr/lib/$libdir/libvulkan.so.1" "archive_tmp/usr/lib/$libdir/libvulkan.so"

 	# Archive Discord Game SDK library.
 	7z e -y -o"archive_tmp/usr/lib" "$discord_zip" "lib/$arch_discord/discord_game_sdk.so"
--- a/.ci/dependencies_macports.txt
+++ b/.ci/dependencies_macports.txt
@@ -13,4 +13,5 @@ qt5
 wget
 fluidsynth
 ghostscript
+libslirp
 vde2
--- a/.ci/dependencies_msys.txt
+++ b/.ci/dependencies_msys.txt
@@ -8,5 +8,6 @@ SDL2
 zlib
 libpng
 rtmidi
+libslirp
 qt5-static
 qt5-translations
--- a/.github/workflows/cmake.yml
+++ b/.github/workflows/cmake.yml
@@ -104,6 +104,7 @@ jobs:
            libpng:p
            openal:p
            rtmidi:p
+            libslirp:p
            libvncserver:p
            ${{ matrix.ui.packages }}

@@ -329,6 +330,7 @@ jobs:
          librtmidi-dev
          libopenal-dev
          libvncserver-dev
+          libslirp-dev
          ${{ matrix.ui.packages }}

      - name: Checkout repository
--- a/.github/workflows/codeql.yml
+++ b/.github/workflows/codeql.yml
@@ -107,6 +107,7 @@ jobs:
            libpng:p
            openal:p
            rtmidi:p
+            libslirp:p
            libvncserver:p
            ${{ matrix.ui.packages }}

@@ -191,6 +192,7 @@ jobs:
          libc6-dev
          librtmidi-dev
          libopenal-dev
+          libslirp-dev
          libvncserver-dev
          ${{ matrix.ui.packages }}

--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -0,0 +1,13 @@
+# Contribution guidelines
+The 86Box project welcomes contributions from anyone, as long as some basic guidelines are followed.
+
+## Emulated hardware
+In order to accept new emulated hardware, the following criteria must be met:
+
+* A ROM must be available and be added to [our ROM repository](https://github.com/86Box/roms)
+* Documentation must be available or it must be feasible to reverse engineer with a reasonable amount of time and effort
+* It must be feasible to implement with a reasonable amount of time and effort
+* It has to fall inside the project's scope
+
+## Questions
+If you're unsure about any aspect of contributing, don't hesitate to get in touch via any of our official communities linked in our [readme](README.md#community) or [GitHub Discussions](https://github.com/86Box/86Box/discussions).
--- a/README.md
+++ b/README.md
@@ -45,6 +45,10 @@ We operate an IRC channel and a Discord server for discussing 86Box, its develop

 [![Visit our Discord server](https://discordapp.com/api/guilds/262614059009048590/embed.png)](https://discord.gg/QXK9XTv)

+Contributions
+---------
+We welcome all contributions to the project, as long as the [contribution guidelines](CONTRIBUTING.md) are followed.
+
 Licensing
 ---------
 86Box is released under the [GNU General Public License, version 2](https://www.gnu.org/licenses/old-licenses/gpl-2.0.html) or later. For more information, see the `COPYING` file in the root of the repository.
--- a/src/86box.c
+++ b/src/86box.c
@@ -208,16 +208,20 @@ char  exe_path[2048]; /* path (dir) of executable */
 char  usr_path[1024]; /* path (dir) of user data */
 char  cfg_path[1024]; /* full path of config file */
 FILE *stdlog = NULL;  /* file to log output to */
-// int   scrnsz_x = SCREEN_RES_X; /* current screen size, X */
-// int   scrnsz_y = SCREEN_RES_Y; /* current screen size, Y */
+#if 0
+int   scrnsz_x = SCREEN_RES_X; /* current screen size, X */
+int   scrnsz_y = SCREEN_RES_Y; /* current screen size, Y */
+#endif
 int config_changed; /* config has changed */
 int title_update;
 int framecountx        = 0;
 int hard_reset_pending = 0;

-// int unscaled_size_x = SCREEN_RES_X; /* current unscaled size X */
-// int unscaled_size_y = SCREEN_RES_Y; /* current unscaled size Y */
-// int efscrnsz_y = SCREEN_RES_Y;
+#if 0
+int unscaled_size_x = SCREEN_RES_X; /* current unscaled size X */
+int unscaled_size_y = SCREEN_RES_Y; /* current unscaled size Y */
+int efscrnsz_y = SCREEN_RES_Y;
+#endif

 static wchar_t mouse_msg[3][200];

@@ -416,7 +420,6 @@ pc_init(int argc, char *argv[])
    time_t     now;
    int        c;
    int        lvmp = 0;
-    int        i;
 #ifdef ENABLE_NG
    int ng = 0;
 #endif
@@ -467,7 +470,7 @@ pc_init(int argc, char *argv[])

        if (!strcasecmp(argv[c], "--help") || !strcasecmp(argv[c], "-?")) {
 usage:
-            for (i = 0; i < FDD_NUM; i++) {
+            for (uint8_t i = 0; i < FDD_NUM; i++) {
                if (fn[i] != NULL) {
                    free(fn[i]);
                    fn[i] = NULL;
@@ -776,7 +779,7 @@ usage:
    /* Load the configuration file. */
    config_load();

-    for (i = 0; i < FDD_NUM; i++) {
+    for (uint8_t i = 0; i < FDD_NUM; i++) {
        if (fn[i] != NULL) {
            if (strlen(fn[i]) <= 511)
                strncpy(floppyfns[i], fn[i], 511);
@@ -1272,7 +1275,9 @@ pc_run(void)
 #ifdef USE_GDBSTUB /* avoid a KBC FIFO overflow when CPU emulation is stalled */
    // if (gdbstub_step == GDBSTUB_EXEC)
 #endif
-        // mouse_process();
+#if 0
+        mouse_process();
+#endif
    joystick_process();
    endblit();

@@ -1413,6 +1418,9 @@ set_screen_size_monitor(int x, int y, int monitor_index)
            monitors[monitor_index].mon_scrnsz_x = (monitors[monitor_index].mon_unscaled_size_x << 3);
            monitors[monitor_index].mon_scrnsz_y = (monitors[monitor_index].mon_unscaled_size_y << 3);
            break;
+
+        default:
+            break;
    }

    plat_resize_request(monitors[monitor_index].mon_scrnsz_x, monitors[monitor_index].mon_scrnsz_y, monitor_index);
@@ -1433,14 +1441,14 @@ reset_screen_size_monitor(int monitor_index)
 void
 reset_screen_size(void)
 {
-    for (int i = 0; i < MONITORS_NUM; i++)
+    for (uint8_t i = 0; i < MONITORS_NUM; i++)
        set_screen_size(monitors[i].mon_unscaled_size_x, monitors[i].mon_efscrnsz_y);
 }

 void
 set_screen_size_natural(void)
 {
-    for (int i = 0; i < MONITORS_NUM; i++)
+    for (uint8_t i = 0; i < MONITORS_NUM; i++)
        set_screen_size(monitors[i].mon_unscaled_size_x, monitors[i].mon_unscaled_size_y);
 }

--- a/src/acpi.c
+++ b/src/acpi.c
@@ -169,9 +169,9 @@ acpi_raise_smi(void *priv, int do_smi)
 }

 static uint32_t
-acpi_reg_read_common_regs(int size, uint16_t addr, void *p)
+acpi_reg_read_common_regs(UNUSED(int size), uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;
    int      shift32;
@@ -211,6 +211,9 @@ acpi_reg_read_common_regs(int size, uint16_t addr, void *p)
                update_tsc();
 #endif
            break;
+
+        default:
+            break;
    }

 #ifdef ENABLE_ACPI_LOG
@@ -221,9 +224,9 @@ acpi_reg_read_common_regs(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_ali(int size, uint16_t addr, void *p)
+acpi_reg_read_ali(int size, uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;
    int      shift32;
@@ -277,7 +280,7 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
            ret = dev->regs.pmcntrl;
            break;
        default:
-            ret = acpi_reg_read_common_regs(size, addr, p);
+            ret = acpi_reg_read_common_regs(size, addr, priv);
            break;
    }

@@ -289,9 +292,9 @@ acpi_reg_read_ali(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_intel(int size, uint16_t addr, void *p)
+acpi_reg_read_intel(int size, uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;
    int      shift32;
@@ -374,7 +377,7 @@ acpi_reg_read_intel(int size, uint16_t addr, void *p)
                ret = dev->regs.gporeg[addr & 3];
            break;
        default:
-            ret = acpi_reg_read_common_regs(size, addr, p);
+            ret = acpi_reg_read_common_regs(size, addr, priv);
            break;
    }

@@ -386,9 +389,9 @@ acpi_reg_read_intel(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_via_common(int size, uint16_t addr, void *p)
+acpi_reg_read_via_common(int size, uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;
    int      shift32;
@@ -470,7 +473,7 @@ acpi_reg_read_via_common(int size, uint16_t addr, void *p)
            ret = (dev->regs.gptren >> shift32) & 0xff;
            break;
        default:
-            ret = acpi_reg_read_common_regs(size, addr, p);
+            ret = acpi_reg_read_common_regs(size, addr, priv);
            break;
    }

@@ -482,9 +485,9 @@ acpi_reg_read_via_common(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_via(int size, uint16_t addr, void *p)
+acpi_reg_read_via(int size, uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;

@@ -527,7 +530,7 @@ acpi_reg_read_via(int size, uint16_t addr, void *p)
            ret = (dev->regs.gpi_val >> shift16) & 0xff;
            break;
        default:
-            ret = acpi_reg_read_via_common(size, addr, p);
+            ret = acpi_reg_read_via_common(size, addr, priv);
            break;
    }

@@ -539,9 +542,9 @@ acpi_reg_read_via(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_via_596b(int size, uint16_t addr, void *p)
+acpi_reg_read_via_596b(int size, uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;
    int      shift32;
@@ -577,7 +580,7 @@ acpi_reg_read_via_596b(int size, uint16_t addr, void *p)
            ret = (dev->regs.gpo_val >> shift32) & 0xff;
            break;
        default:
-            ret = acpi_reg_read_via_common(size, addr, p);
+            ret = acpi_reg_read_via_common(size, addr, priv);
            break;
    }

@@ -589,13 +592,13 @@ acpi_reg_read_via_596b(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_reg_read_smc(int size, uint16_t addr, void *p)
+acpi_reg_read_smc(int size, uint16_t addr, void *priv)
 {
    uint32_t ret = 0x00000000;

    addr &= 0x0f;

-    ret = acpi_reg_read_common_regs(size, addr, p);
+    ret = acpi_reg_read_common_regs(size, addr, priv);

 #ifdef ENABLE_ACPI_LOG
    if (size != 1)
@@ -605,9 +608,9 @@ acpi_reg_read_smc(int size, uint16_t addr, void *p)
 }

 static uint32_t
-acpi_aux_reg_read_smc(int size, uint16_t addr, void *p)
+acpi_aux_reg_read_smc(UNUSED(int size), uint16_t addr, void *priv)
 {
-    acpi_t  *dev = (acpi_t *) p;
+    acpi_t  *dev = (acpi_t *) priv;
    uint32_t ret = 0x00000000;
    int      shift16;

@@ -638,6 +641,9 @@ acpi_aux_reg_read_smc(int size, uint16_t addr, void *p)
            /* Miscellaneous Control Register */
            ret = dev->regs.glbctl & 0xff;
            break;
+
+        default:
+            break;
    }

    acpi_log("(%i) ACPI Read  (%i) %02X: %02X\n", in_smm, size, addr, ret);
@@ -645,9 +651,9 @@ acpi_aux_reg_read_smc(int size, uint16_t addr, void *p)
 }

 static void
-acpi_reg_write_common_regs(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_common_regs(UNUSED(int size), uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     sus_typ;

@@ -719,13 +725,16 @@ acpi_reg_write_common_regs(int size, uint16_t addr, uint8_t val, void *p)
            }
            dev->regs.pmcntrl = ((dev->regs.pmcntrl & ~(0xff << shift16)) | (val << shift16)) & 0x3f07 /* 0x3c07 */;
            break;
+
+        default:
+            break;
    }
 }

 static void
-acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     shift32;

@@ -782,7 +791,7 @@ acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
            dev->regs.pmcntrl = val & 1;
            break;
        default:
-            acpi_reg_write_common_regs(size, addr, val, p);
+            acpi_reg_write_common_regs(size, addr, val, priv);
            /* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
            if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
                dev->regs.gpcntrl &= ~0x0002;
@@ -795,9 +804,9 @@ acpi_reg_write_ali(int size, uint16_t addr, uint8_t val, void *p)
 }

 static void
-acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     shift32;

@@ -878,7 +887,7 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
                dev->regs.gporeg[addr & 3] = val;
            break;
        default:
-            acpi_reg_write_common_regs(size, addr, val, p);
+            acpi_reg_write_common_regs(size, addr, val, priv);
            /* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
            if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
                dev->regs.glbctl &= ~0x0002;
@@ -892,9 +901,9 @@ acpi_reg_write_intel(int size, uint16_t addr, uint8_t val, void *p)
 }

 static void
-acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     shift32;

@@ -965,7 +974,7 @@ acpi_reg_write_via_common(int size, uint16_t addr, uint8_t val, void *p)
            dev->regs.gptren = ((dev->regs.gptren & ~(0xff << shift32)) | (val << shift32)) & 0x000000d9;
            break;
        default:
-            acpi_reg_write_common_regs(size, addr, val, p);
+            acpi_reg_write_common_regs(size, addr, val, priv);
            /* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
            if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
                dev->regs.glbctl &= ~0x0002;
@@ -986,9 +995,9 @@ acpi_i2c_set(acpi_t *dev)
 }

 static void
-acpi_reg_write_via(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_via(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     shift32;

@@ -1044,15 +1053,15 @@ acpi_reg_write_via(int size, uint16_t addr, uint8_t val, void *p)
            dev->regs.gpo_val = ((dev->regs.gpo_val & ~(0xff << shift16)) | (val << shift16)) & 0xffff;
            break;
        default:
-            acpi_reg_write_via_common(size, addr, val, p);
+            acpi_reg_write_via_common(size, addr, val, priv);
            break;
    }
 }

 static void
-acpi_reg_write_via_596b(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_via_596b(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;
    int     shift32;

@@ -1102,20 +1111,20 @@ acpi_reg_write_via_596b(int size, uint16_t addr, uint8_t val, void *p)
            dev->regs.gpo_val = ((dev->regs.gpo_val & ~(0xff << shift32)) | (val << shift32)) & 0x7fffffff;
            break;
        default:
-            acpi_reg_write_via_common(size, addr, val, p);
+            acpi_reg_write_via_common(size, addr, val, priv);
            break;
    }
 }

 static void
-acpi_reg_write_smc(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_smc(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;

    addr &= 0x0f;
    acpi_log("(%i) ACPI Write (%i) %02X: %02X\n", in_smm, size, addr, val);

-    acpi_reg_write_common_regs(size, addr, val, p);
+    acpi_reg_write_common_regs(size, addr, val, priv);
    /* Setting GBL_RLS also sets BIOS_STS and generates SMI. */
    if ((addr == 0x00) && !(dev->regs.pmsts & 0x20))
        dev->regs.glbctl &= ~0x0001;
@@ -1127,9 +1136,9 @@ acpi_reg_write_smc(int size, uint16_t addr, uint8_t val, void *p)
 }

 static void
-acpi_aux_reg_write_smc(int size, uint16_t addr, uint8_t val, void *p)
+acpi_aux_reg_write_smc(UNUSED(int size), uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    int     shift16;

    addr &= 0x07;
@@ -1171,76 +1180,79 @@ acpi_aux_reg_write_smc(int size, uint16_t addr, uint8_t val, void *p)
                    acpi_update_irq(dev);
            }
            break;
+
+        default:
+            break;
    }
 }

 static uint32_t
-acpi_reg_read_common(int size, uint16_t addr, void *p)
+acpi_reg_read_common(int size, uint16_t addr, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    uint8_t ret = 0xff;

    if (dev->vendor == VEN_ALI)
-        ret = acpi_reg_read_ali(size, addr, p);
+        ret = acpi_reg_read_ali(size, addr, priv);
    else if (dev->vendor == VEN_VIA)
-        ret = acpi_reg_read_via(size, addr, p);
+        ret = acpi_reg_read_via(size, addr, priv);
    else if (dev->vendor == VEN_VIA_596B)
-        ret = acpi_reg_read_via_596b(size, addr, p);
+        ret = acpi_reg_read_via_596b(size, addr, priv);
    else if (dev->vendor == VEN_INTEL)
-        ret = acpi_reg_read_intel(size, addr, p);
+        ret = acpi_reg_read_intel(size, addr, priv);
    else if (dev->vendor == VEN_SMC)
-        ret = acpi_reg_read_smc(size, addr, p);
+        ret = acpi_reg_read_smc(size, addr, priv);

    return ret;
 }

 static void
-acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
+acpi_reg_write_common(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;

    if (dev->vendor == VEN_ALI)
-        acpi_reg_write_ali(size, addr, val, p);
+        acpi_reg_write_ali(size, addr, val, priv);
    else if (dev->vendor == VEN_VIA)
-        acpi_reg_write_via(size, addr, val, p);
+        acpi_reg_write_via(size, addr, val, priv);
    else if (dev->vendor == VEN_VIA_596B)
-        acpi_reg_write_via_596b(size, addr, val, p);
+        acpi_reg_write_via_596b(size, addr, val, priv);
    else if (dev->vendor == VEN_INTEL)
-        acpi_reg_write_intel(size, addr, val, p);
+        acpi_reg_write_intel(size, addr, val, priv);
    else if (dev->vendor == VEN_SMC)
-        acpi_reg_write_smc(size, addr, val, p);
+        acpi_reg_write_smc(size, addr, val, priv);
 }

 static uint32_t
-acpi_aux_reg_read_common(int size, uint16_t addr, void *p)
+acpi_aux_reg_read_common(int size, uint16_t addr, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    uint8_t ret = 0xff;

    if (dev->vendor == VEN_SMC)
-        ret = acpi_aux_reg_read_smc(size, addr, p);
+        ret = acpi_aux_reg_read_smc(size, addr, priv);

    return ret;
 }

 static void
-acpi_aux_reg_write_common(int size, uint16_t addr, uint8_t val, void *p)
+acpi_aux_reg_write_common(int size, uint16_t addr, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;

    if (dev->vendor == VEN_SMC)
-        acpi_aux_reg_write_smc(size, addr, val, p);
+        acpi_aux_reg_write_smc(size, addr, val, priv);
 }

 static uint32_t
-acpi_reg_readl(uint16_t addr, void *p)
+acpi_reg_readl(uint16_t addr, void *priv)
 {
    uint32_t ret = 0x00000000;

-    ret = acpi_reg_read_common(4, addr, p);
-    ret |= (acpi_reg_read_common(4, addr + 1, p) << 8);
-    ret |= (acpi_reg_read_common(4, addr + 2, p) << 16);
-    ret |= (acpi_reg_read_common(4, addr + 3, p) << 24);
+    ret = acpi_reg_read_common(4, addr, priv);
+    ret |= (acpi_reg_read_common(4, addr + 1, priv) << 8);
+    ret |= (acpi_reg_read_common(4, addr + 2, priv) << 16);
+    ret |= (acpi_reg_read_common(4, addr + 3, priv) << 24);

    acpi_log("ACPI: Read L %08X from %04X\n", ret, addr);

@@ -1248,12 +1260,12 @@ acpi_reg_readl(uint16_t addr, void *p)
 }

 static uint16_t
-acpi_reg_readw(uint16_t addr, void *p)
+acpi_reg_readw(uint16_t addr, void *priv)
 {
    uint16_t ret = 0x0000;

-    ret = acpi_reg_read_common(2, addr, p);
-    ret |= (acpi_reg_read_common(2, addr + 1, p) << 8);
+    ret = acpi_reg_read_common(2, addr, priv);
+    ret |= (acpi_reg_read_common(2, addr + 1, priv) << 8);

    acpi_log("ACPI: Read W %08X from %04X\n", ret, addr);

@@ -1261,11 +1273,11 @@ acpi_reg_readw(uint16_t addr, void *p)
 }

 static uint8_t
-acpi_reg_read(uint16_t addr, void *p)
+acpi_reg_read(uint16_t addr, void *priv)
 {
    uint8_t ret = 0x00;

-    ret = acpi_reg_read_common(1, addr, p);
+    ret = acpi_reg_read_common(1, addr, priv);

    acpi_log("ACPI: Read B %02X from %04X\n", ret, addr);

@@ -1273,14 +1285,14 @@ acpi_reg_read(uint16_t addr, void *p)
 }

 static uint32_t
-acpi_aux_reg_readl(uint16_t addr, void *p)
+acpi_aux_reg_readl(uint16_t addr, void *priv)
 {
    uint32_t ret = 0x00000000;

-    ret = acpi_aux_reg_read_common(4, addr, p);
-    ret |= (acpi_aux_reg_read_common(4, addr + 1, p) << 8);
-    ret |= (acpi_aux_reg_read_common(4, addr + 2, p) << 16);
-    ret |= (acpi_aux_reg_read_common(4, addr + 3, p) << 24);
+    ret = acpi_aux_reg_read_common(4, addr, priv);
+    ret |= (acpi_aux_reg_read_common(4, addr + 1, priv) << 8);
+    ret |= (acpi_aux_reg_read_common(4, addr + 2, priv) << 16);
+    ret |= (acpi_aux_reg_read_common(4, addr + 3, priv) << 24);

    acpi_log("ACPI: Read Aux L %08X from %04X\n", ret, addr);

@@ -1288,12 +1300,12 @@ acpi_aux_reg_readl(uint16_t addr, void *p)
 }

 static uint16_t
-acpi_aux_reg_readw(uint16_t addr, void *p)
+acpi_aux_reg_readw(uint16_t addr, void *priv)
 {
    uint16_t ret = 0x0000;

-    ret = acpi_aux_reg_read_common(2, addr, p);
-    ret |= (acpi_aux_reg_read_common(2, addr + 1, p) << 8);
+    ret = acpi_aux_reg_read_common(2, addr, priv);
+    ret |= (acpi_aux_reg_read_common(2, addr + 1, priv) << 8);

    acpi_log("ACPI: Read Aux W %04X from %04X\n", ret, addr);

@@ -1301,11 +1313,11 @@ acpi_aux_reg_readw(uint16_t addr, void *p)
 }

 static uint8_t
-acpi_aux_reg_read(uint16_t addr, void *p)
+acpi_aux_reg_read(uint16_t addr, void *priv)
 {
    uint8_t ret = 0x00;

-    ret = acpi_aux_reg_read_common(1, addr, p);
+    ret = acpi_aux_reg_read_common(1, addr, priv);

    acpi_log("ACPI: Read Aux B %02X from %04X\n", ret, addr);

@@ -1313,59 +1325,59 @@ acpi_aux_reg_read(uint16_t addr, void *p)
 }

 static void
-acpi_reg_writel(uint16_t addr, uint32_t val, void *p)
+acpi_reg_writel(uint16_t addr, uint32_t val, void *priv)
 {
    acpi_log("ACPI: Write L %08X to %04X\n", val, addr);

-    acpi_reg_write_common(4, addr, val & 0xff, p);
-    acpi_reg_write_common(4, addr + 1, (val >> 8) & 0xff, p);
-    acpi_reg_write_common(4, addr + 2, (val >> 16) & 0xff, p);
-    acpi_reg_write_common(4, addr + 3, (val >> 24) & 0xff, p);
+    acpi_reg_write_common(4, addr, val & 0xff, priv);
+    acpi_reg_write_common(4, addr + 1, (val >> 8) & 0xff, priv);
+    acpi_reg_write_common(4, addr + 2, (val >> 16) & 0xff, priv);
+    acpi_reg_write_common(4, addr + 3, (val >> 24) & 0xff, priv);
 }

 static void
-acpi_reg_writew(uint16_t addr, uint16_t val, void *p)
+acpi_reg_writew(uint16_t addr, uint16_t val, void *priv)
 {
    acpi_log("ACPI: Write W %04X to %04X\n", val, addr);

-    acpi_reg_write_common(2, addr, val & 0xff, p);
-    acpi_reg_write_common(2, addr + 1, (val >> 8) & 0xff, p);
+    acpi_reg_write_common(2, addr, val & 0xff, priv);
+    acpi_reg_write_common(2, addr + 1, (val >> 8) & 0xff, priv);
 }

 static void
-acpi_reg_write(uint16_t addr, uint8_t val, void *p)
+acpi_reg_write(uint16_t addr, uint8_t val, void *priv)
 {
    acpi_log("ACPI: Write B %02X to %04X\n", val, addr);

-    acpi_reg_write_common(1, addr, val, p);
+    acpi_reg_write_common(1, addr, val, priv);
 }

 static void
-acpi_aux_reg_writel(uint16_t addr, uint32_t val, void *p)
+acpi_aux_reg_writel(uint16_t addr, uint32_t val, void *priv)
 {
    acpi_log("ACPI: Write Aux L %08X to %04X\n", val, addr);

-    acpi_aux_reg_write_common(4, addr, val & 0xff, p);
-    acpi_aux_reg_write_common(4, addr + 1, (val >> 8) & 0xff, p);
-    acpi_aux_reg_write_common(4, addr + 2, (val >> 16) & 0xff, p);
-    acpi_aux_reg_write_common(4, addr + 3, (val >> 24) & 0xff, p);
+    acpi_aux_reg_write_common(4, addr, val & 0xff, priv);
+    acpi_aux_reg_write_common(4, addr + 1, (val >> 8) & 0xff, priv);
+    acpi_aux_reg_write_common(4, addr + 2, (val >> 16) & 0xff, priv);
+    acpi_aux_reg_write_common(4, addr + 3, (val >> 24) & 0xff, priv);
 }

 static void
-acpi_aux_reg_writew(uint16_t addr, uint16_t val, void *p)
+acpi_aux_reg_writew(uint16_t addr, uint16_t val, void *priv)
 {
    acpi_log("ACPI: Write Aux W %04X to %04X\n", val, addr);

-    acpi_aux_reg_write_common(2, addr, val & 0xff, p);
-    acpi_aux_reg_write_common(2, addr + 1, (val >> 8) & 0xff, p);
+    acpi_aux_reg_write_common(2, addr, val & 0xff, priv);
+    acpi_aux_reg_write_common(2, addr + 1, (val >> 8) & 0xff, priv);
 }

 static void
-acpi_aux_reg_write(uint16_t addr, uint8_t val, void *p)
+acpi_aux_reg_write(uint16_t addr, uint8_t val, void *priv)
 {
    acpi_log("ACPI: Write Aux B %02X to %04X\n", val, addr);

-    acpi_aux_reg_write_common(1, addr, val, p);
+    acpi_aux_reg_write_common(1, addr, val, priv);
 }

 void
@@ -1374,9 +1386,9 @@ acpi_update_io_mapping(acpi_t *dev, uint32_t base, int chipset_en)
    int size;

    switch (dev->vendor) {
+        default:
        case VEN_ALI:
        case VEN_INTEL:
-        default:
            size = 0x040;
            break;
        case VEN_SMC:
@@ -1545,9 +1557,9 @@ acpi_pwrbtn_timer(void *priv)
 }

 static void
-acpi_apm_out(uint16_t port, uint8_t val, void *p)
+acpi_apm_out(uint16_t port, uint8_t val, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;

    acpi_log("[%04X:%08X] APM write: %04X = %02X (AX = %04X, BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, AX, BX, CX);

@@ -1557,7 +1569,9 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
        if (port == 0x0001) {
            acpi_log("ALi SOFT SMI# status set (%i)\n", dev->apm->do_smi);
            dev->apm->cmd = val;
-            // acpi_raise_smi(dev, dev->apm->do_smi);
+#if 0
+            acpi_raise_smi(dev, dev->apm->do_smi);
+#endif
            if (dev->apm->do_smi)
                smi_raise();
            dev->regs.ali_soft_smi = 1;
@@ -1575,9 +1589,9 @@ acpi_apm_out(uint16_t port, uint8_t val, void *p)
 }

 static uint8_t
-acpi_apm_in(uint16_t port, void *p)
+acpi_apm_in(uint16_t port, void *priv)
 {
-    acpi_t *dev = (acpi_t *) p;
+    acpi_t *dev = (acpi_t *) priv;
    uint8_t ret = 0xff;

    port &= 0x0001;
@@ -1731,6 +1745,9 @@ acpi_init(const device_t *info)
            dev->suspend_types[3] = SUS_SUSPEND | SUS_RESET_CACHE;
            dev->suspend_types[4] = SUS_SUSPEND;
            break;
+
+        default:
+            break;
    }

    timer_add(&dev->timer, acpi_timer_overflow, dev, 0);
--- a/src/apm.c
+++ b/src/apm.c
@@ -52,9 +52,9 @@ apm_set_do_smi(apm_t *dev, uint8_t do_smi)
 }

 static void
-apm_out(uint16_t port, uint8_t val, void *p)
+apm_out(uint16_t port, uint8_t val, void *priv)
 {
-    apm_t *dev = (apm_t *) p;
+    apm_t *dev = (apm_t *) priv;

    apm_log("[%04X:%08X] APM write: %04X = %02X (BX = %04X, CX = %04X)\n", CS, cpu_state.pc, port, val, BX, CX);

@@ -69,9 +69,9 @@ apm_out(uint16_t port, uint8_t val, void *p)
 }

 static uint8_t
-apm_in(uint16_t port, void *p)
+apm_in(uint16_t port, void *priv)
 {
-    apm_t  *dev = (apm_t *) p;
+    apm_t  *dev = (apm_t *) priv;
    uint8_t ret = 0xff;

    port &= 0x0001;
@@ -87,17 +87,17 @@ apm_in(uint16_t port, void *p)
 }

 static void
-apm_reset(void *p)
+apm_reset(void *priv)
 {
-    apm_t *dev = (apm_t *) p;
+    apm_t *dev = (apm_t *) priv;

    dev->cmd = dev->stat = 0x00;
 }

 static void
-apm_close(void *p)
+apm_close(void *priv)
 {
-    apm_t *dev = (apm_t *) p;
+    apm_t *dev = (apm_t *) priv;

    free(dev);
 }
--- a/src/cdrom/cdrom.c
+++ b/src/cdrom/cdrom.c
@@ -422,6 +422,8 @@ cdrom_seek(cdrom_t *dev, uint32_t pos, uint8_t vendor_type)
        case 0x80:
            pos = bcd2bin((pos >> 24) & 0xff);
            break;
+        default:
+            break;
    }

    dev->seek_pos = pos;
@@ -611,6 +613,8 @@ cdrom_audio_track_search(cdrom_t *dev, uint32_t pos, int type, uint8_t playbit)
            }
            dev->seek_pos = (pos >> 24) & 0xff;
            break;
+        default:
+            break;
    }

    /* Unlike standard commands, if there's a data track on an Audio CD (mixed mode)
@@ -652,6 +656,8 @@ cdrom_audio_play_toshiba(cdrom_t *dev, uint32_t pos, int type)
            }
            dev->cd_end = pos;
            break;
+        default:
+            break;
    }

    cdrom_log("Toshiba/NEC Play Audio: MSF = %06x, type = %02x, cdstatus = %02x\n", pos, type, dev->cd_status);
@@ -698,6 +704,8 @@ cdrom_audio_scan(cdrom_t *dev, uint32_t pos, int type)
        case 0x80:
            dev->seek_pos = (pos >> 24) & 0xff;
            break;
+        default:
+            break;
    }

    /* Do this at this point, since it's at this point that we know the
@@ -1331,13 +1339,15 @@ cdrom_read_disc_info_toc(cdrom_t *dev, unsigned char *b, unsigned char track, in
            b[2] = 0;
            b[3] = 0;
            break;
+        default:
+            break;
    }

    return 1;
 }

 static int
-track_type_is_valid(uint8_t id, int type, int flags, int audio, int mode2)
+track_type_is_valid(UNUSED(uint8_t id), int type, int flags, int audio, int mode2)
 {
    if (!(flags & 0x70) && (flags & 0xf8)) { /* 0x08/0x80/0x88 are illegal modes */
        cdrom_log("CD-ROM %i: [Any Mode] 0x08/0x80/0x88 are illegal modes\n", id);
--- a/src/cdrom/cdrom_image_backend.c
+++ b/src/cdrom/cdrom_image_backend.c
@@ -283,7 +283,7 @@ cdi_get_audio_track_pre(cd_img_t *cdi, int track)

 /* This replaces both Info and EndInfo, they are specified by a variable. */
 int
-cdi_get_audio_track_info(cd_img_t *cdi, int end, int track, int *track_num, TMSF *start, uint8_t *attr)
+cdi_get_audio_track_info(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, TMSF *start, uint8_t *attr)
 {
    track_t *trk = &cdi->tracks[track - 1];
    int      pos = trk->start + 150;
@@ -302,7 +302,7 @@ cdi_get_audio_track_info(cd_img_t *cdi, int end, int track, int *track_num, TMSF
 }

 int
-cdi_get_audio_track_info_lba(cd_img_t *cdi, int end, int track, int *track_num, uint32_t *start, uint8_t *attr)
+cdi_get_audio_track_info_lba(cd_img_t *cdi, UNUSED(int end), int track, int *track_num, uint32_t *start, uint8_t *attr)
 {
    track_t *trk = &cdi->tracks[track - 1];

--- a/src/cdrom/cdrom_image_viso.c
+++ b/src/cdrom/cdrom_image_viso.c
@@ -114,8 +114,10 @@ typedef struct _viso_entry_ {
 } viso_entry_t;

 typedef struct {
-    uint64_t vol_size_offsets[2], pt_meta_offsets[2];
-    int      format, use_version_suffix : 1;
+    uint64_t vol_size_offsets[2];
+    uint64_t pt_meta_offsets[2];
+    int      format;
+    uint8_t  use_version_suffix : 1;
    size_t   metadata_sectors, all_sectors, entry_map_size, sector_size, file_fifo_pos;
    uint8_t *metadata;

@@ -629,6 +631,9 @@ pad_susp:
            if (!(*q & 1)) /* padding for even file ID lengths */
                *p++ = 0;
            break;
+
+        default:
+            break;
    }

    if ((p - data) > 255)
--- a/src/cdrom/cdrom_mitsumi.c
+++ b/src/cdrom/cdrom_mitsumi.c
@@ -116,7 +116,9 @@ typedef struct {
 /* The addresses sent from the guest are absolute, ie. a LBA of 0 corresponds to a MSF of 00:00:00. Otherwise, the counter displayed by the guest is wrong:
   there is a seeming 2 seconds in which audio plays but counter does not move, while a data track before audio jumps to 2 seconds before the actual start
   of the audio while audio still plays. With an absolute conversion, the counter is fine. */
+#ifdef MSFtoLBA
 #undef MSFtoLBA
+#endif
 #define MSFtoLBA(m, s, f) ((((m * 60) + s) * 75) + f)

 #define CD_BCD(x)         (((x) % 10) | (((x) / 10) << 4))
@@ -242,9 +244,11 @@ mitsumi_cdrom_in(uint16_t port, void *priv)
                ret |= FLAG_NOSTAT;
            pclog("Read port 1: ret = %02x\n", ret | FLAG_UNK);
            return ret | FLAG_UNK;
+        default:
+            break;
    }

-    return (0xff);
+    return 0xff;
 }

 static void
@@ -283,6 +287,8 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
                                    case 0x10:
                                        dev->enable_irq = val;
                                        break;
+                                    default:
+                                        break;
                                }
                                dev->cmdbuf[1]    = 0;
                                dev->cmdbuf_count = 2;
@@ -297,6 +303,8 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
                                if (dev->conf == 1)
                                    dev->cmdrd_count++;
                                break;
+                            default:
+                                break;
                        }
                        break;
                    case CMD_READ1X:
@@ -320,8 +328,12 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
                            case 3:
                                dev->readmsf |= CD_DCB(val) << ((dev->cmdrd_count - 3) << 3);
                                break;
+                            default:
+                                break;
                        }
                        break;
+                    default:
+                        break;
                }
                if (!dev->cmdrd_count)
                    dev->stat = cdrom.host_drive ? (STAT_READY | (dev->change ? STAT_CHANGE : 0)) : 0;
@@ -406,11 +418,13 @@ mitsumi_cdrom_out(uint16_t port, uint8_t val, void *priv)
        case 1:
            mitsumi_cdrom_reset(dev);
            break;
+        default:
+            break;
    }
 }

 static void *
-mitsumi_cdrom_init(const device_t *info)
+mitsumi_cdrom_init(UNUSED(const device_t *info))
 {
    mcd_t *dev;

--- a/src/chipset/82c100.c
+++ b/src/chipset/82c100.c
@@ -28,23 +28,24 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/nmi.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/rom.h>
 #include <86box/chipset.h>

-typedef struct
-{
+typedef struct ems_page_t {
    int      enabled;
-    uint32_t virt, phys;
+    uint32_t virt;
+    uint32_t phys;
 } ems_page_t;

-typedef struct
-{
-    uint8_t  index, access;
-    uint16_t ems_io_base;
-    uint32_t ems_window_base;
-    uint8_t  ems_page_regs[4],
-        regs[256];
+typedef struct ct_82c100_t {
+    uint8_t       index;
+    uint8_t       access;
+    uint16_t      ems_io_base;
+    uint32_t      ems_window_base;
+    uint8_t       ems_page_regs[4];
+    uint8_t       regs[256];
    ems_page_t    ems_pages[4];
    mem_mapping_t ems_mappings[4];
 } ct_82c100_t;
@@ -119,9 +120,7 @@ ct_82c100_ems_in(uint16_t port, void *priv)
 static void
 ct_82c100_ems_update(ct_82c100_t *dev)
 {
-    int i;
-
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        ct_82c100_log("Disabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
        io_handler(0, dev->ems_io_base + (i << 14), 1,
                   ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
@@ -129,7 +128,7 @@ ct_82c100_ems_update(ct_82c100_t *dev)

    dev->ems_io_base = 0x0208 + (dev->regs[0x4c] & 0xf0);

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        ct_82c100_log("Enabling EMS I/O handler %i at %04X\n", i, dev->ems_io_base + (i << 14));
        io_handler(1, dev->ems_io_base + (i << 14), 1,
                   ct_82c100_ems_in, NULL, NULL, ct_82c100_ems_out, NULL, NULL, dev);
@@ -221,6 +220,9 @@ ct_82c100_out(uint16_t port, uint8_t val, void *priv)
                    dev->regs[0x4c] = val;
                    ct_82c100_ems_update(dev);
                    break;
+
+                default:
+                    break;
            }
            dev->access = 0;
        }
@@ -257,6 +259,9 @@ ct_82c100_in(uint16_t port, void *priv)
                case 0x4c:
                    ret = dev->regs[dev->index];
                    break;
+
+                default:
+                    break;
            }
            dev->access = 0;
        }
@@ -349,7 +354,7 @@ ct_82c100_close(void *priv)
 }

 static void *
-ct_82c100_init(const device_t *info)
+ct_82c100_init(UNUSED(const device_t *info))
 {
    ct_82c100_t *dev;

--- a/src/chipset/acc2168.c
+++ b/src/chipset/acc2168.c
@@ -30,6 +30,7 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/port_92.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

 #define ENABLED_SHADOW  (MEM_READ_INTERNAL | ((dev->regs[0x02] & 0x20) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL))
@@ -57,20 +58,21 @@ acc2168_log(const char *fmt, ...)
 #endif

 typedef struct acc2168_t {
-    uint8_t reg_idx, regs[256];
+    uint8_t reg_idx;
+    uint8_t regs[256];
 } acc2168_t;

 static void
 acc2168_shadow_recalc(acc2168_t *dev)
 {
-    for (uint32_t i = 0; i < 5; i++)
+    for (uint8_t i = 0; i < 5; i++)
        mem_set_mem_state_both(SHADOW_ADDR, SHADOW_SIZE, SHADOW_RECALC);
 }

 static void
-acc2168_write(uint16_t addr, uint8_t val, void *p)
+acc2168_write(uint16_t addr, uint8_t val, void *priv)
 {
-    acc2168_t *dev = (acc2168_t *) p;
+    acc2168_t *dev = (acc2168_t *) priv;

    switch (addr) {
        case 0xf2:
@@ -158,13 +160,15 @@ acc2168_write(uint16_t addr, uint8_t val, void *p)
                    break;
            }
            break;
+        default:
+            break;
    }
 }

 static uint8_t
-acc2168_read(uint16_t addr, void *p)
+acc2168_read(uint16_t addr, void *priv)
 {
-    acc2168_t *dev = (acc2168_t *) p;
+    acc2168_t *dev = (acc2168_t *) priv;

    return (addr == 0xf3) ? dev->regs[dev->reg_idx] : dev->reg_idx;
 }
@@ -178,7 +182,7 @@ acc2168_close(void *priv)
 }

 static void *
-acc2168_init(const device_t *info)
+acc2168_init(UNUSED(const device_t *info))
 {
    acc2168_t *dev = (acc2168_t *) malloc(sizeof(acc2168_t));
    memset(dev, 0, sizeof(acc2168_t));
--- a/src/chipset/ali1429.c
+++ b/src/chipset/ali1429.c
@@ -115,10 +115,12 @@ ali1429_log(const char *fmt, ...)
 #    define ali1429_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint8_t is_g, index, cfg_locked, reg_57h,
-        regs[90];
+typedef struct ali_1429_t {
+    uint8_t is_g;
+    uint8_t index;
+    uint8_t cfg_locked;
+    uint8_t reg_57h;
+    uint8_t regs[90];
 } ali1429_t;

 static void
@@ -239,12 +241,16 @@ ali1429_write(uint16_t addr, uint8_t val, void *priv)
                            case 6:
                                cpu_set_isa_speed(cpu_busspeed / 12);
                                break;
+                            default:
+                                break;
                        }
                        break;

                    case 0x21 ... 0x27:
                        dev->regs[dev->index] = val;
                        break;
+                    default:
+                        break;
                }

                /* M1429G Only Registers */
@@ -260,10 +266,14 @@ ali1429_write(uint16_t addr, uint8_t val, void *priv)
                        case 0x57:
                            dev->reg_57h = val;
                            break;
+                        default:
+                            break;
                    }
                }
            }
            break;
+        default:
+            break;
    }
 }

--- a/src/chipset/ali1435.c
+++ b/src/chipset/ali1435.c
@@ -31,6 +31,7 @@
 #include <86box/timer.h>
 #include <86box/pic.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc_ide.h>
 #include <86box/hdc.h>
@@ -42,10 +43,11 @@
 #define MEM_STATE_SHADOW_W 0x02
 #define MEM_STATE_SMRAM    0x04

-typedef struct
-{
-    uint8_t index, cfg_locked,
-        regs[16], pci_regs[256];
+typedef struct ali_1435_t {
+    uint8_t index;
+    uint8_t cfg_locked;
+    uint8_t regs[16];
+    uint8_t pci_regs[256];
 } ali1435_t;

 #define ENABLE_ALI1435_LOG 1
@@ -188,11 +190,12 @@ ali1435_write(uint16_t addr, uint8_t val, void *priv)
            break;

        case 0x23:
-            /* #ifdef ENABLE_ALI1435_LOG
-                            if (dev->index != 0x03)
-                                    ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
-            #endif */
-
+#if 0
+#ifdef ENABLE_ALI1435_LOG
+            if (dev->index != 0x03)
+                ali1435_log("M1435: dev->regs[%02x] = %02x\n", dev->index, val);
+#endif
+#endif
            if (dev->index == 0x03)
                dev->cfg_locked = (val != 0x69);

@@ -216,9 +219,14 @@ ali1435_write(uint16_t addr, uint8_t val, void *priv)
                    case 0x07:
                        dev->regs[dev->index] = val;
                        break;
+
+                    default:
+                        break;
                }
            }
            break;
+        default:
+            break;
    }
 }

@@ -269,15 +277,15 @@ ali1435_reset(void *priv)
 }

 static void
-ali1435_close(void *p)
+ali1435_close(void *priv)
 {
-    ali1435_t *dev = (ali1435_t *) p;
+    ali1435_t *dev = (ali1435_t *) priv;

    free(dev);
 }

 static void *
-ali1435_init(const device_t *info)
+ali1435_init(UNUSED(const device_t *info))
 {
    ali1435_t *dev = (ali1435_t *) malloc(sizeof(ali1435_t));
    memset(dev, 0, sizeof(ali1435_t));
@@ -294,10 +302,12 @@ ali1435_init(const device_t *info)

    ali1435_reset(dev);

-    /* pci_set_irq_level(PCI_INTA, 0);
+#if 0
+    pci_set_irq_level(PCI_INTA, 0);
    pci_set_irq_level(PCI_INTB, 0);
    pci_set_irq_level(PCI_INTC, 0);
-    pci_set_irq_level(PCI_INTD, 0); */
+    pci_set_irq_level(PCI_INTD, 0);
+#endif

    return dev;
 }
--- a/src/chipset/ali1489.c
+++ b/src/chipset/ali1489.c
@@ -35,6 +35,7 @@
 #include <86box/nmi.h>
 #include <86box/pic.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/smram.h>

@@ -61,10 +62,14 @@ ali1489_log(const char *fmt, ...)
 #    define ali1489_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint8_t index, ide_index, ide_chip_id, pci_slot,
-        regs[256], pci_conf[256], ide_regs[256];
+typedef struct ali1489_t {
+    uint8_t index;
+    uint8_t ide_index;
+    uint8_t ide_chip_id;
+    uint8_t pci_slot;
+    uint8_t regs[256];
+    uint8_t pci_conf[256];
+    uint8_t ide_regs[256];

    port_92_t *port_92;
    smram_t   *smram;
@@ -75,11 +80,9 @@ static void ali1489_ide_handler(ali1489_t *dev);
 static void
 ali1489_shadow_recalc(ali1489_t *dev)
 {
-    uint32_t i;
-
    shadowbios = shadowbios_write = 0;

-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        if (dev->regs[0x13] & (1 << i)) {
            ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
                        0xc0000 + (i << 14), 0xc3fff + (i << 14), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
@@ -90,7 +93,7 @@ ali1489_shadow_recalc(ali1489_t *dev)
        }
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        if (dev->regs[0x14] & (1 << i)) {
            ali1489_log("%06Xh-%06Xh region shadow enabled: read = %i, write = %i\n",
                        0xe0000 + (i << 15), 0xe7fff + (i << 15), !!(dev->regs[0x14] & 0x10), !!(dev->regs[0x14] & 0x20));
@@ -126,6 +129,8 @@ ali1489_smram_recalc(ali1489_t *dev)
            else
                smram_enable(dev->smram, 0x38000, 0xa8000, 0x08000, (dev->regs[0x19] & 0x08), 1);
            break;
+        default:
+            break;
    }

    if ((dev->regs[0x19] & 0x31) == 0x11) {
@@ -320,6 +325,8 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
                                case 0x30:
                                    picint(1 << 10);
                                    break;
+                                default:
+                                    break;
                            }
                            dev->regs[0x35] |= 0x0e;
                        } else if (!(val & 0x10))
@@ -381,6 +388,8 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
                        /* TODO: When doing the IRQ and PCI IRQ rewrite, bits 0 to 3 toggle edge/level output. */
                        dev->regs[dev->index] = val;
                        break;
+                    default:
+                        break;
                }

                if (dev->index != 0x03) {
@@ -390,6 +399,9 @@ ali1489_write(uint16_t addr, uint8_t val, void *priv)
                dev->regs[dev->index] = val;

            break;
+
+        default:
+            break;
    }
 }

@@ -409,6 +421,8 @@ ali1489_read(uint16_t addr, void *priv)
            else
                ret = dev->regs[dev->index];
            break;
+        default:
+            break;
    }

    ali1489_log("M1489: dev->regs[%02x] (%02x)\n", dev->index, ret);
@@ -417,7 +431,7 @@ ali1489_read(uint16_t addr, void *priv)
 }

 static void
-ali1489_pci_write(int func, int addr, uint8_t val, void *priv)
+ali1489_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    ali1489_t *dev = (ali1489_t *) priv;

@@ -433,11 +447,14 @@ ali1489_pci_write(int func, int addr, uint8_t val, void *priv)
        case 0x07:
            dev->pci_conf[0x07] &= ~(val & 0xb8);
            break;
+
+        default:
+            break;
    }
 }

 static uint8_t
-ali1489_pci_read(int func, int addr, void *priv)
+ali1489_pci_read(UNUSED(int func), int addr, void *priv)
 {
    ali1489_t *dev = (ali1489_t *) priv;
    uint8_t    ret = 0xff;
@@ -529,8 +546,14 @@ ali1489_ide_write(uint16_t addr, uint8_t val, void *priv)
                    dev->ide_regs[dev->ide_index] = val;
                    ali1489_ide_handler(dev);
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -548,6 +571,9 @@ ali1489_ide_read(uint16_t addr, void *priv)
            ret = dev->ide_regs[dev->ide_index];
            ali1489_log("M1489-IDE: dev->regs[%02x] (%02x)\n", dev->ide_index, ret);
            break;
+
+        default:
+            break;
    }

    return ret;
@@ -576,7 +602,7 @@ ali1489_close(void *priv)
 }

 static void *
-ali1489_init(const device_t *info)
+ali1489_init(UNUSED(const device_t *info))
 {
    ali1489_t *dev = (ali1489_t *) malloc(sizeof(ali1489_t));
    memset(dev, 0, sizeof(ali1489_t));
--- a/src/chipset/ali1531.c
+++ b/src/chipset/ali1531.c
@@ -28,6 +28,7 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/smram.h>
 #include <86box/spd.h>

@@ -82,6 +83,9 @@ ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
                if (val & 0x10)
                    mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
                break;
+
+            default:
+                break;
        }
    }

@@ -89,7 +93,7 @@ ali1531_smram_recalc(uint8_t val, ali1531_t *dev)
 }

 static void
-ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
+ali1531_shadow_recalc(UNUSED(int cur_reg), ali1531_t *dev)
 {
    int      bit;
    int      r_reg;
@@ -124,7 +128,7 @@ ali1531_shadow_recalc(int cur_reg, ali1531_t *dev)
 }

 static void
-ali1531_write(int func, int addr, uint8_t val, void *priv)
+ali1531_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    ali1531_t *dev = (ali1531_t *) priv;

@@ -228,8 +232,10 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
        case 0x57: /* H2PO */
            dev->pci_conf[addr] = val & 0x60;
            /* Find where the Shut-down Special cycle is initiated. */
-            // if (!(val & 0x20))
-            // outb(0x92, 0x01);
+#if 0
+            if (!(val & 0x20))
+                outb(0x92, 0x01);
+#endif
            break;

        case 0x58:
@@ -288,11 +294,14 @@ ali1531_write(int func, int addr, uint8_t val, void *priv)
        case 0x83:
            dev->pci_conf[addr] = val & 0x10;
            break;
+
+        default:
+            break;
    }
 }

 static uint8_t
-ali1531_read(int func, int addr, void *priv)
+ali1531_read(UNUSED(int func), int addr, void *priv)
 {
    ali1531_t *dev = (ali1531_t *) priv;
    uint8_t    ret = 0xff;
@@ -306,7 +315,6 @@ static void
 ali1531_reset(void *priv)
 {
    ali1531_t *dev = (ali1531_t *) priv;
-    int        i;

    /* Default Registers */
    dev->pci_conf[0x00] = 0xb9;
@@ -342,10 +350,10 @@ ali1531_reset(void *priv)
    ali1531_write(0, 0x47, 0x00, dev);
    ali1531_write(0, 0x48, 0x00, dev);

-    for (i = 0; i < 4; i++)
+    for (uint8_t i = 0; i < 4; i++)
        ali1531_write(0, 0x4c + i, 0x00, dev);

-    for (i = 0; i < 16; i += 2) {
+    for (uint8_t i = 0; i < 16; i += 2) {
        ali1531_write(0, 0x60 + i, 0x08, dev);
        ali1531_write(0, 0x61 + i, 0x40, dev);
    }
@@ -361,7 +369,7 @@ ali1531_close(void *priv)
 }

 static void *
-ali1531_init(const device_t *info)
+ali1531_init(UNUSED(const device_t *info))
 {
    ali1531_t *dev = (ali1531_t *) malloc(sizeof(ali1531_t));
    memset(dev, 0, sizeof(ali1531_t));
--- a/src/chipset/ali1541.c
+++ b/src/chipset/ali1541.c
@@ -28,6 +28,7 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/smram.h>
 #include <86box/spd.h>

@@ -83,6 +84,8 @@ ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
                if (val & 0x10)
                    mem_set_mem_state_smram_ex(1, 0x30000, 0x10000, 0x02);
                break;
+            default:
+                break;
        }
    }

@@ -90,7 +93,7 @@ ali1541_smram_recalc(uint8_t val, ali1541_t *dev)
 }

 static void
-ali1541_shadow_recalc(int cur_reg, ali1541_t *dev)
+ali1541_shadow_recalc(UNUSED(int cur_reg), ali1541_t *dev)
 {
    int      bit;
    int      r_reg;
@@ -131,8 +134,8 @@ ali1541_mask_bar(ali1541_t *dev)
    uint32_t mask;

    switch (dev->pci_conf[0xbc] & 0x0f) {
-        case 0x00:
        default:
+        case 0x00:
            mask = 0x00000000;
            break;
        case 0x01:
@@ -170,7 +173,7 @@ ali1541_mask_bar(ali1541_t *dev)
 }

 static void
-ali1541_write(int func, int addr, uint8_t val, void *priv)
+ali1541_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    ali1541_t *dev = (ali1541_t *) priv;

@@ -367,8 +370,10 @@ ali1541_write(int func, int addr, uint8_t val, void *priv)
        case 0x87: /* H2PO */
            dev->pci_conf[addr] = val;
            /* Find where the Shut-down Special cycle is initiated. */
-            // if (!(val & 0x20))
-            // outb(0x92, 0x01);
+#if 0
+            if (!(val & 0x20))
+                outb(0x92, 0x01);
+#endif
            break;

        case 0x88:
@@ -546,11 +551,14 @@ ali1541_write(int func, int addr, uint8_t val, void *priv)
        case 0xf7:
            dev->pci_conf[addr] = val & 0x43;
            break;
+
+        default:
+            break;
    }
 }

 static uint8_t
-ali1541_read(int func, int addr, void *priv)
+ali1541_read(UNUSED(int func), int addr, void *priv)
 {
    ali1541_t *dev = (ali1541_t *) priv;
    uint8_t    ret = 0xff;
@@ -564,7 +572,6 @@ static void
 ali1541_reset(void *priv)
 {
    ali1541_t *dev = (ali1541_t *) priv;
-    int        i;

    /* Default Registers */
    dev->pci_conf[0x00] = 0xb9;
@@ -607,12 +614,13 @@ ali1541_reset(void *priv)
    ali1541_write(0, 0x54, 0x00, dev);
    ali1541_write(0, 0x55, 0x00, dev);

-    for (i = 0; i < 4; i++)
+    for (uint8_t i = 0; i < 4; i++)
        ali1541_write(0, 0x56 + i, 0x00, dev);

-    ali1541_write(0, 0x60 + i, 0x07, dev);
-    ali1541_write(0, 0x61 + i, 0x40, dev);
-    for (i = 0; i < 14; i += 2) {
+    ali1541_write(0, 0x60, 0x07, dev);
+    ali1541_write(0, 0x61, 0x40, dev);
+
+    for (uint8_t i = 0; i < 14; i += 2) {
        ali1541_write(0, 0x62 + i, 0x00, dev);
        ali1541_write(0, 0x63 + i, 0x00, dev);
    }
@@ -628,7 +636,7 @@ ali1541_close(void *priv)
 }

 static void *
-ali1541_init(const device_t *info)
+ali1541_init(UNUSED(const device_t *info))
 {
    ali1541_t *dev = (ali1541_t *) malloc(sizeof(ali1541_t));
    memset(dev, 0, sizeof(ali1541_t));
--- a/src/chipset/ali1543.c
+++ b/src/chipset/ali1543.c
@@ -36,6 +36,7 @@
 #include <86box/nvr.h>
 #include <86box/pci.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/sio.h>
 #include <86box/smbus.h>
@@ -46,10 +47,19 @@
 #include <86box/chipset.h>

 typedef struct ali1543_t {
-    uint8_t pci_conf[256], pmu_conf[256], usb_conf[256], ide_conf[256],
-        pci_slot, ide_slot, usb_slot, pmu_slot, usb_dev_enable, ide_dev_enable,
-        pmu_dev_enable, type;
-    int offset;
+    uint8_t pci_conf[256];
+    uint8_t pmu_conf[256];
+    uint8_t usb_conf[256];
+    uint8_t ide_conf[256];
+    uint8_t pci_slot;
+    uint8_t ide_slot;
+    uint8_t usb_slot;
+    uint8_t pmu_slot;
+    uint8_t usb_dev_enable;
+    uint8_t ide_dev_enable;
+    uint8_t pmu_dev_enable;
+    uint8_t type;
+    int     offset;

    apm_t           *apm;
    acpi_t          *acpi;
@@ -95,7 +105,7 @@ ali1543_log(const char *fmt, ...)
 #endif

 static void
-ali1533_ddma_handler(ali1543_t *dev)
+ali1533_ddma_handler(UNUSED(ali1543_t *dev))
 {
    /* TODO: Find any documentation that actually explains the ALi southbridge DDMA mapping. */
 }
@@ -168,6 +178,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                case 6:
                    cpu_set_isa_pci_div((val & 7) + 1);
                    break;
+                default:
+                    break;
            }
            break;

@@ -227,8 +239,10 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                dev->pci_conf[addr] = val;

                ali1543_log("SIRQI = IRQ %i; SIRQII = IRQ %i\n", ali1533_irq_routing[(val >> 4) & 0x0f], ali1533_irq_routing[val & 0x0f]);
-                // pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
-                // pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
+#if 0
+                pci_set_mirq_routing(PCI_MIRQ0, ali1533_irq_routing[(val >> 4) & 0x0f]);
+                pci_set_mirq_routing(PCI_MIRQ1, ali1533_irq_routing[val & 0x0f]);
+#endif
            }
            break;

@@ -293,6 +307,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                case 0x30:
                    dev->ide_slot = 0x0d; /* A24 = slot 13 */
                    break;
+                default:
+                    break;
            }
            pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_IDE, ((int) dev->ide_slot) + dev->offset);
            ali1543_log("IDE slot = %02X (A%0i)\n", ((int) dev->ide_slot) + dev->offset, dev->ide_slot + 11);
@@ -364,6 +380,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                case 0x0c:
                    dev->pmu_slot = 0x04; /* A15 = slot 04 */
                    break;
+                default:
+                    break;
            }
            pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_PMU, ((int) dev->pmu_slot) + dev->offset);
            ali1543_log("PMU slot = %02X (A%0i)\n", ((int) dev->pmu_slot) + dev->offset, dev->pmu_slot + 11);
@@ -380,6 +398,8 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                case 0x03:
                    dev->usb_slot = 0x01; /* A12 = slot 01 */
                    break;
+                default:
+                    break;
            }
            pci_relocate_slot(PCI_CARD_SOUTHBRIDGE_USB, ((int) dev->usb_slot) + dev->offset);
            ali1543_log("USB slot = %02X (A%0i)\n", ((int) dev->usb_slot) + dev->offset, dev->usb_slot + 11);
@@ -437,6 +457,9 @@ ali1533_write(int func, int addr, uint8_t val, void *priv)
                dev->pmu_dev_enable = 0;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -509,6 +532,9 @@ ali5229_ide_irq_handler(ali1543_t *dev)
                sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
                sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
                break;
+
+            default:
+                break;
        }
    }

@@ -546,6 +572,9 @@ ali5229_ide_irq_handler(ali1543_t *dev)
                sff_set_irq_mode(dev->ide_controller[ctl], 0 ^ ch, 0);
                sff_set_irq_mode(dev->ide_controller[ctl], 1 ^ ch, 2);
                break;
+
+            default:
+                break;
        }
    }
 }
@@ -857,6 +886,9 @@ ali5229_write(int func, int addr, uint8_t val, void *priv)
        case 0x5f:
            dev->ide_conf[addr] = val & 0x7f;
            break;
+
+        default:
+            break;
    }
 }

@@ -942,6 +974,9 @@ ali5237_write(int func, int addr, uint8_t val, void *priv)
            if (!(dev->usb_conf[0x42] & 0x10))
                dev->usb_conf[addr] = val;
            break;
+
+        default:
+            break;
    }
 }

@@ -1426,6 +1461,9 @@ ali7101_read(int func, int addr, void *priv)
                case 0x74:
                    dev->pmu_conf[addr] &= 0xcc;
                    break;
+
+                default:
+                    break;
            }
        }
    }
--- a/src/chipset/ali1621.c
+++ b/src/chipset/ali1621.c
@@ -28,6 +28,7 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/smram.h>
 #include <86box/spd.h>

@@ -111,6 +112,8 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
                case 0x30: /* Protect. */
                    access_smm |= ACCESS_SMRAM_R;
                    break;
+                default:
+                    break;
            }
        }

@@ -122,6 +125,8 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
                case 0x30: /* Protect. */
                    access_smm |= ACCESS_SMRAM_W;
                    break;
+                default:
+                    break;
            }

        smram_enable(dev->smram[0], 0xa0000, 0xa0000, 0x20000, ((val & 0x30) == 0x10), (val & 0x30));
@@ -137,7 +142,7 @@ ali1621_smram_recalc(uint8_t val, ali1621_t *dev)
 }

 static void
-ali1621_shadow_recalc(int cur_reg, ali1621_t *dev)
+ali1621_shadow_recalc(UNUSED(int cur_reg), ali1621_t *dev)
 {
    int      r_bit;
    int      w_bit;
@@ -207,8 +212,8 @@ ali1621_mask_bar(ali1621_t *dev)
    uint32_t mask;

    switch (dev->pci_conf[0xbc] & 0x0f) {
-        case 0x00:
        default:
+        case 0x00:
            mask = 0x00000000;
            break;
        case 0x01:
@@ -246,7 +251,7 @@ ali1621_mask_bar(ali1621_t *dev)
 }

 static void
-ali1621_write(int func, int addr, uint8_t val, void *priv)
+ali1621_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    ali1621_t *dev = (ali1621_t *) priv;

@@ -565,11 +570,14 @@ ali1621_write(int func, int addr, uint8_t val, void *priv)
        case 0xf0 ... 0xff:
            dev->pci_conf[addr] = val;
            break;
+
+        default:
+            break;
    }
 }

 static uint8_t
-ali1621_read(int func, int addr, void *priv)
+ali1621_read(UNUSED(int func), int addr, void *priv)
 {
    ali1621_t *dev = (ali1621_t *) priv;
    uint8_t    ret = 0xff;
@@ -653,7 +661,7 @@ ali1621_close(void *priv)
 }

 static void *
-ali1621_init(const device_t *info)
+ali1621_init(UNUSED(const device_t *info))
 {
    ali1621_t *dev = (ali1621_t *) malloc(sizeof(ali1621_t));
    memset(dev, 0, sizeof(ali1621_t));
--- a/src/chipset/ali6117.c
+++ b/src/chipset/ali6117.c
@@ -38,7 +38,8 @@ typedef struct ali6117_t {
    uint32_t local;

    /* Main registers (port 22h/23h) */
-    uint8_t unlocked, mode;
+    uint8_t unlocked;
+    uint8_t mode;
    uint8_t reg_offset;
    uint8_t regs[256];
 } ali6117_t;
@@ -277,6 +278,9 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
                        case 0x7:
                            cpu_set_isa_speed(cpu_busspeed / 6);
                            break;
+
+                        default:
+                            break;
                    }
                    break;

@@ -372,6 +376,9 @@ ali6117_reg_write(uint16_t addr, uint8_t val, void *priv)
                case 0x71:
                    val &= 0x1f;
                    break;
+
+                default:
+                    break;
            }

        dev->regs[dev->reg_offset] = val;
--- a/src/chipset/contaq_82c59x.c
+++ b/src/chipset/contaq_82c59x.c
@@ -48,16 +48,17 @@ contaq_82c59x_log(const char *fmt, ...)
 #    define contaq_82c59x_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint32_t phys, virt;
+typedef struct mem_remapping_t {
+    uint32_t phys;
+    uint32_t virt;
 } mem_remapping_t;

-typedef struct
-{
-    uint8_t index, green,
-        smi_status_set,
-        regs[256], smi_status[2];
+typedef struct contaq_82c59x_t {
+    uint8_t index;
+    uint8_t green;
+    uint8_t smi_status_set;
+    uint8_t regs[256];
+    uint8_t smi_status[2];

    smram_t *smram[2];
 } contaq_82c59x_t;
@@ -82,6 +83,8 @@ contaq_82c59x_isa_speed_recalc(contaq_82c59x_t *dev)
            case 0x03:
                cpu_set_isa_speed(cpu_busspeed / 5);
                break;
+            default:
+                break;
        }
    }
 }
@@ -274,8 +277,14 @@ contaq_82c59x_write(uint16_t addr, uint8_t val, void *priv)
                case 0x7c:
                    dev->regs[dev->index] = val;
                    break;
+
+                default:
+                    break;
            }
            break;
+        
+        default:
+            break;
    }
 }

--- a/src/chipset/cs4031.c
+++ b/src/chipset/cs4031.c
@@ -27,13 +27,13 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t index,
-        regs[256];
+typedef struct cs4031_t {
+    uint8_t    index;
+    uint8_t    regs[256];
    port_92_t *port_92;
 } cs4031_t;

@@ -134,8 +134,14 @@ cs4031_write(uint16_t addr, uint8_t val, void *priv)
                    dev->regs[dev->index] = val & 0xb3;
                    port_92_set_features(dev->port_92, val & 0x10, val & 0x20);
                    break;
+
+                default:
+                    break;
            }
            break;
+
+            default:
+                break;
    }
 }

@@ -156,7 +162,7 @@ cs4031_close(void *priv)
 }

 static void *
-cs4031_init(const device_t *info)
+cs4031_init(UNUSED(const device_t *info))
 {
    cs4031_t *dev = (cs4031_t *) malloc(sizeof(cs4031_t));
    memset(dev, 0, sizeof(cs4031_t));
--- a/src/chipset/cs8230.c
+++ b/src/chipset/cs8230.c
@@ -25,12 +25,12 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/fdd.h>
 #include <86box/fdc.h>
 #include <86box/chipset.h>

-typedef struct
-{
+typedef struct cs8230_t {
    int     idx;
    uint8_t regs[256];
 } cs8230_t;
@@ -51,6 +51,8 @@ shadow_control(uint32_t addr, uint32_t size, int state)
        case 0x11:
            mem_set_mem_state(addr, size, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
            break;
+        default:
+            break;
    }

    flushmmucache_nopc();
@@ -59,9 +61,7 @@ shadow_control(uint32_t addr, uint32_t size, int state)
 static void
 rethink_shadow_mappings(cs8230_t *cs8230)
 {
-    int c;
-
-    for (c = 0; c < 32; c++) {
+    for (uint8_t c = 0; c < 32; c++) {
        /* Addresses 40000-bffff in 16k blocks */
        if (cs8230->regs[0xa + (c >> 3)] & (1 << (c & 7)))
            mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_EXTERNAL | MEM_WRITE_EXTERNAL); /* I/O channel */
@@ -69,7 +69,7 @@ rethink_shadow_mappings(cs8230_t *cs8230)
            mem_set_mem_state(0x40000 + (c << 14), 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL); /* System board */
    }

-    for (c = 0; c < 16; c++) {
+    for (uint8_t c = 0; c < 16; c++) {
        /* Addresses c0000-fffff in 16k blocks. System board ROM can be mapped here */
        if (cs8230->regs[0xe + (c >> 3)] & (1 << (c & 7)))
            mem_set_mem_state(0xc0000 + (c << 14), 0x4000, MEM_READ_EXTANY | MEM_WRITE_EXTANY); /* I/O channel */
@@ -79,9 +79,9 @@ rethink_shadow_mappings(cs8230_t *cs8230)
 }

 static uint8_t
-cs8230_read(uint16_t port, void *p)
+cs8230_read(uint16_t port, void *priv)
 {
-    cs8230_t *cs8230 = (cs8230_t *) p;
+    cs8230_t *cs8230 = (cs8230_t *) priv;
    uint8_t   ret    = 0xff;

    if (port & 1) {
@@ -112,6 +112,9 @@ cs8230_read(uint16_t port, void *p)
            case 0x2a:
                ret = cs8230->regs[cs8230->idx];
                break;
+
+            default:
+                break;
        }
    }

@@ -119,9 +122,9 @@ cs8230_read(uint16_t port, void *p)
 }

 static void
-cs8230_write(uint16_t port, uint8_t val, void *p)
+cs8230_write(uint16_t port, uint8_t val, void *priv)
 {
-    cs8230_t *cs8230 = (cs8230_t *) p;
+    cs8230_t *cs8230 = (cs8230_t *) priv;

    if (!(port & 1))
        cs8230->idx = val;
@@ -137,6 +140,8 @@ cs8230_write(uint16_t port, uint8_t val, void *p)
            case 0x0f: /* Address maps */
                rethink_shadow_mappings(cs8230);
                break;
+            default:
+                break;
        }
    }
 }
@@ -149,9 +154,8 @@ cs8230_close(void *priv)
    free(cs8230);
 }

-static void
-    *
-    cs8230_init(const device_t *info)
+static void *
+cs8230_init(UNUSED(const device_t *info))
 {
    cs8230_t *cs8230 = (cs8230_t *) malloc(sizeof(cs8230_t));
    memset(cs8230, 0, sizeof(cs8230_t));
--- a/src/chipset/et6000.c
+++ b/src/chipset/et6000.c
@@ -28,14 +28,15 @@
 #include <86box/device.h>
 #include <86box/mem.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

 #define INDEX (dev->index - 0x10)

-typedef struct
-{
-    uint8_t index, regs[256];
+typedef struct et6000_t {
+    uint8_t index;
+    uint8_t regs[256];
 } et6000_t;

 #ifdef ENABLE_ET6000_LOG
@@ -105,9 +106,15 @@ et6000_write(uint16_t addr, uint8_t val, void *priv)
                    et6000_shadow_control(0xe0000, 0x10000, val & 0x20, (val & 0x20) && (val & 0x10));
                    et6000_shadow_control(0xf0000, 0x10000, val & 0x40, !(val & 0x40));
                    break;
+
+                default:
+                    break;
            }
            et6000_log("ET6000: dev->regs[%02x] = %02x\n", dev->index, dev->regs[dev->index]);
            break;
+
+        default:
+            break;
    }
 }

@@ -128,7 +135,7 @@ et6000_close(void *priv)
 }

 static void *
-et6000_init(const device_t *info)
+et6000_init(UNUSED(const device_t *info))
 {
    et6000_t *dev = (et6000_t *) malloc(sizeof(et6000_t));
    memset(dev, 0, sizeof(et6000_t));
--- a/src/chipset/gc100.c
+++ b/src/chipset/gc100.c
@@ -44,8 +44,7 @@
 #include <86box/io.h>
 #include <86box/video.h>

-typedef struct
-{
+typedef struct gc100_t {
    uint8_t reg[0x10];
 } gc100_t;

@@ -70,7 +69,7 @@ gc100_log(const char *fmt, ...)
 static uint8_t
 get_fdd_switch_settings(void)
 {
-    int fdd_count = 0;
+    uint8_t fdd_count = 0;

    for (uint8_t i = 0; i < FDD_NUM; i++) {
        if (fdd_get_flags(i))
@@ -135,6 +134,9 @@ gc100_write(uint16_t port, uint8_t val, void *priv)
            /* addr 0x6 */

            /* addr 0x7 */
+
+        default:
+            break;
    }

    gc100_log("GC100: Write %02x at %02x\n", val, port);
@@ -187,6 +189,9 @@ gc100_read(uint16_t port, void *priv)
            /* addr 0x6 */

            /* addr 0x7 */
+
+        default:
+            break;
    }

    return ret;
--- a/src/chipset/headland.c
+++ b/src/chipset/headland.c
@@ -34,6 +34,7 @@
 #include <86box/device.h>
 #include <86box/fdd.h>
 #include <86box/fdc.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

@@ -52,8 +53,9 @@ enum {
 #define HEADLAND_HAS_CRI   0x10
 #define HEADLAND_HAS_SLEEP 0x20

-typedef struct {
-    uint8_t  valid, enabled;
+typedef struct headland_mr_t {
+    uint8_t  valid;
+    uint8_t  enabled;
    uint16_t mr;
    uint32_t virt_base;

@@ -62,7 +64,8 @@ typedef struct {

 typedef struct headland_t {
    uint8_t revision;
-    uint8_t has_cri, has_sleep;
+    uint8_t has_cri;
+    uint8_t  has_sleep;

    uint8_t cri;
    uint8_t cr[7];
@@ -72,8 +75,8 @@ typedef struct headland_t {

    uint8_t ems_mar;

-    headland_mr_t null_mr,
-        ems_mr[64];
+    headland_mr_t null_mr;
+    headland_mr_t ems_mr[64];

    mem_mapping_t low_mapping;
    mem_mapping_t ems_mapping[64];
@@ -205,7 +208,7 @@ hl_ems_update(headland_t *dev, uint8_t mar)
 }

 static void
-set_global_EMS_state(headland_t *dev, int state)
+set_global_EMS_state(headland_t *dev, UNUSED(int state))
 {
    for (uint8_t i = 0; i < 32; i++) {
        hl_ems_update(dev, i | (((dev->cr[0] & 0x01) << 5) ^ 0x20));
@@ -590,7 +593,6 @@ headland_init(const device_t *info)
 {
    headland_t *dev;
    int         ht386 = 0;
-    uint32_t    i;

    dev = (headland_t *) malloc(sizeof(headland_t));
    memset(dev, 0x00, sizeof(headland_t));
@@ -615,7 +617,7 @@ headland_init(const device_t *info)
    dev->null_mr.mr       = 0xff;
    dev->null_mr.headland = dev;

-    for (i = 0; i < 64; i++) {
+    for (uint8_t i = 0; i < 64; i++) {
        dev->ems_mr[i].valid    = 1;
        dev->ems_mr[i].mr       = 0x00;
        dev->ems_mr[i].headland = dev;
@@ -647,7 +649,7 @@ headland_init(const device_t *info)
        mem_mapping_enable(&dev->high_mapping);
    }

-    for (i = 0; i < 24; i++) {
+    for (uint8_t i = 0; i < 24; i++) {
        mem_mapping_add(&dev->upper_mapping[i],
                        0x40000 + (i << 14), 0x4000,
                        mem_read_b, mem_read_w, mem_read_l,
@@ -673,7 +675,7 @@ headland_init(const device_t *info)
                    MEM_MAPPING_INTERNAL, &dev->null_mr);
    mem_mapping_disable(&dev->shadow_mapping[1]);

-    for (i = 0; i < 64; i++) {
+    for (uint8_t i = 0; i < 64; i++) {
        dev->ems_mr[i].mr = 0x00;
        mem_mapping_add(&dev->ems_mapping[i],
                        ((i & 31) + ((i & 31) >= 24 ? 24 : 16)) << 14, 0x04000,
--- a/src/chipset/ims8848.c
+++ b/src/chipset/ims8848.c
@@ -31,6 +31,7 @@
 #include <86box/smram.h>
 #include <86box/pci.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

@@ -118,10 +119,11 @@
        Bit 0: HADS# Delay After LB. Cycle (1: Enabled / 0: Disable)
 */

-typedef struct
-{
-    uint8_t idx, access_data,
-        regs[256], pci_conf[256];
+typedef struct ims8848_t {
+    uint8_t idx;
+    uint8_t access_data;
+    uint8_t regs[256];
+    uint8_t pci_conf[256];

    smram_t *smram;
 } ims8848_t;
@@ -148,7 +150,6 @@ ims8848_log(const char *fmt, ...)
 static void
 ims8848_recalc(ims8848_t *dev)
 {
-    int      i;
    int      state_on;
    uint32_t base;
    ims8848_log("SHADOW: 00 = %02X, 08 = %02X, 1B = %02X, 1C = %02X\n",
@@ -157,7 +158,7 @@ ims8848_recalc(ims8848_t *dev)
    state_on = MEM_READ_INTERNAL;
    state_on |= (dev->regs[0x08] & 0x04) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY;

-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        base = 0xe0000 + (i << 16);
        if (dev->regs[0x00] & (1 << (i + 2)))
            mem_set_mem_state_both(base, 0x10000, state_on);
@@ -165,7 +166,7 @@ ims8848_recalc(ims8848_t *dev)
            mem_set_mem_state_both(base, 0x10000, MEM_READ_EXTANY | MEM_WRITE_INTERNAL);
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base = 0xc0000 + (i << 14);
        if (dev->regs[0x1c] & (1 << i))
            mem_set_mem_state_both(base, 0x4000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
@@ -244,10 +245,16 @@ ims8848_write(uint16_t addr, uint8_t val, void *priv)
                        /* Base Memory */
                        ims8848_base_memory(dev);
                        break;
+
+                    default:
+                        break;
                }
                dev->access_data = 0;
            }
            break;
+
+            default:
+                break;
    }
 }

@@ -276,6 +283,8 @@ ims8848_read(uint16_t addr, void *priv)
            }
            ims8848_log("[R] [%i] REG %02X = %02X\n", old_ad, dev->idx, ret);
            break;
+        default:
+            break;
    }

    return ret;
@@ -309,6 +318,9 @@ ims8849_pci_write(int func, int addr, uint8_t val, void *priv)
            case 0x52 ... 0x55:
                dev->pci_conf[addr] = val;
                break;
+
+            default:
+                break;
        }
 }

@@ -364,7 +376,7 @@ ims8848_close(void *priv)
 }

 static void *
-ims8848_init(const device_t *info)
+ims8848_init(UNUSED(const device_t *info))
 {
    ims8848_t *dev = (ims8848_t *) malloc(sizeof(ims8848_t));
    memset(dev, 0, sizeof(ims8848_t));
--- a/src/chipset/intel_420ex.c
+++ b/src/chipset/intel_420ex.c
@@ -34,6 +34,7 @@
 #include <86box/pic.h>
 #include <86box/timer.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc_ide.h>
 #include <86box/hdc.h>
@@ -45,19 +46,20 @@
 #define MEM_STATE_SHADOW_W 0x02
 #define MEM_STATE_SMRAM    0x04

-typedef struct
-{
-    uint8_t has_ide, smram_locked,
-        regs[256];
+typedef struct i420ex_t {
+    uint8_t has_ide;
+    uint8_t smram_locked;
+    uint8_t regs[256];

-    uint16_t timer_base,
-        timer_latch;
+    uint16_t timer_base;
+    uint16_t timer_latch;

    smram_t *smram;

    double fast_off_period;

-    pc_timer_t timer, fast_off_timer;
+    pc_timer_t timer;
+    pc_timer_t fast_off_timer;

    apm_t     *apm;
    port_92_t *port_92;
@@ -97,6 +99,8 @@ i420ex_map(uint32_t addr, uint32_t size, int state)
        case 3:
            mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
            break;
+        default:
+            break;
    }
    flushmmucache_nopc();
 }
@@ -118,9 +122,9 @@ i420ex_smram_handler_phase1(i420ex_t *dev)
    uint32_t size      = 0x00010000;

    switch (regs[0x70] & 0x07) {
+        default:
        case 0:
        case 1:
-        default:
            host_base = ram_base = 0x00000000;
            size                 = 0x00000000;
            break;
@@ -195,6 +199,8 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
                        ide_set_side(0, 0x0376);
                        ide_pri_enable();
                        break;
+                    default:
+                        break;
                }
            }
            break;
@@ -356,6 +362,8 @@ i420ex_write(int func, int addr, uint8_t val, void *priv)
            cpu_fast_off_count = val + 1;
            cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
            break;
+        default:
+            break;
    }
 }

@@ -411,9 +419,9 @@ i420ex_reset_hard(void *priv)
 }

 static void
-i420ex_apm_out(uint16_t port, uint8_t val, void *p)
+i420ex_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
 {
-    i420ex_t *dev = (i420ex_t *) p;
+    i420ex_t *dev = (i420ex_t *) priv;

    if (dev->apm->do_smi)
        dev->regs[0xaa] |= 0x80;
@@ -431,42 +439,41 @@ i420ex_fast_off_count(void *priv)
 }

 static void
-i420ex_reset(void *p)
+i420ex_reset(void *priv)
 {
-    i420ex_t *dev = (i420ex_t *) p;
-    int       i;
+    i420ex_t *dev = (i420ex_t *) priv;

-    i420ex_write(0, 0x48, 0x00, p);
+    i420ex_write(0, 0x48, 0x00, priv);

    /* Disable the PIC mouse latch. */
-    i420ex_write(0, 0x4e, 0x03, p);
+    i420ex_write(0, 0x4e, 0x03, priv);

-    for (i = 0; i < 7; i++)
-        i420ex_write(0, 0x59 + i, 0x00, p);
+    for (uint8_t i = 0; i < 7; i++)
+        i420ex_write(0, 0x59 + i, 0x00, priv);

-    for (i = 0; i <= 4; i++)
-        i420ex_write(0, 0x60 + i, 0x01, p);
+    for (uint8_t i = 0; i <= 4; i++)
+        i420ex_write(0, 0x60 + i, 0x01, priv);

    dev->regs[0x70] &= 0xef; /* Forcibly unlock the SMRAM register. */
    dev->smram_locked = 0;
-    i420ex_write(0, 0x70, 0x00, p);
+    i420ex_write(0, 0x70, 0x00, priv);

    mem_set_mem_state(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);
    mem_set_mem_state_smm(0x000a0000, 0x00060000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);

-    i420ex_write(0, 0xa0, 0x08, p);
-    i420ex_write(0, 0xa2, 0x00, p);
-    i420ex_write(0, 0xa4, 0x00, p);
-    i420ex_write(0, 0xa5, 0x00, p);
-    i420ex_write(0, 0xa6, 0x00, p);
-    i420ex_write(0, 0xa7, 0x00, p);
-    i420ex_write(0, 0xa8, 0x0f, p);
+    i420ex_write(0, 0xa0, 0x08, priv);
+    i420ex_write(0, 0xa2, 0x00, priv);
+    i420ex_write(0, 0xa4, 0x00, priv);
+    i420ex_write(0, 0xa5, 0x00, priv);
+    i420ex_write(0, 0xa6, 0x00, priv);
+    i420ex_write(0, 0xa7, 0x00, priv);
+    i420ex_write(0, 0xa8, 0x0f, priv);
 }

 static void
-i420ex_close(void *p)
+i420ex_close(void *priv)
 {
-    i420ex_t *dev = (i420ex_t *) p;
+    i420ex_t *dev = (i420ex_t *) priv;

    smram_del(dev->smram);

--- a/src/chipset/intel_4x0.c
+++ b/src/chipset/intel_4x0.c
@@ -28,6 +28,7 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>
 #include <86box/spd.h>
 #include <86box/machine.h>
@@ -50,17 +51,20 @@ enum {
    INTEL_440ZX
 };

-typedef struct
-{
-    uint8_t pm2_cntrl,
-        smram_locked, max_drb,
-        drb_unit, drb_default;
-    uint8_t    regs[256], regs_locked[256];
+typedef struct i4x0_t {
+    uint8_t    pm2_cntrl;
+    uint8_t    smram_locked;
+    uint8_t    max_drb;
+    uint8_t    drb_unit;
+    uint8_t    drb_default;
+    uint8_t    regs[256];
+    uint8_t    regs_locked[256];
    uint8_t    mem_state[256];
    int        type;
-    smram_t   *smram_low, *smram_high;
+    smram_t   *smram_low;
+    smram_t   *smram_high;
    agpgart_t *agpgart;
-    void (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
+    void     (*write_drbs)(uint8_t *regs, uint8_t reg_min, uint8_t reg_max, uint8_t drb_unit);
 } i4x0_t;

 #ifdef ENABLE_I4X0_LOG
@@ -165,8 +169,8 @@ i4x0_smram_handler_phase1(i4x0_t *dev)
    } else {
        size[0] = 0x00010000;
        switch (*reg & 0x03) {
-            case 0:
            default:
+            case 0:
                base[0] = (mem_size << 10) - size[0];
                s       = 1;
                break;
@@ -222,17 +226,17 @@ i4x0_mask_bar(uint8_t *regs, void *agpgart)
 }

 static uint8_t
-pm2_cntrl_read(uint16_t addr, void *p)
+pm2_cntrl_read(UNUSED(uint16_t addr), void *priv)
 {
-    i4x0_t *dev = (i4x0_t *) p;
+    i4x0_t *dev = (i4x0_t *) priv;

    return dev->pm2_cntrl & 0x01;
 }

 static void
-pm2_cntrl_write(uint16_t addr, uint8_t val, void *p)
+pm2_cntrl_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
 {
-    i4x0_t *dev = (i4x0_t *) p;
+    i4x0_t *dev = (i4x0_t *) priv;

    dev->pm2_cntrl = val & 0x01;
 }
@@ -251,6 +255,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
        switch (addr) {
            case 0x04: /*Command register*/
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
@@ -258,7 +263,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440BX:
                    case INTEL_440GX:
                    case INTEL_440ZX:
-                    default:
                        regs[0x04] = (regs[0x04] & ~0x42) | (val & 0x42);
                        break;
                    case INTEL_430FX:
@@ -291,16 +295,18 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[0x05] = val & 0x01;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x07:
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
                    case INTEL_430NX:
                    case INTEL_430HX:
-                    default:
                        regs[0x07] &= ~(val & 0x70);
                        break;
                    case INTEL_430FX:
@@ -343,6 +349,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430TX:
                        regs[0x0f] = (val & 0x40);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x12:
@@ -355,6 +363,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0x12] = (val & 0xc0);
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x13:
@@ -367,6 +377,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0x13] = val;
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x2c:
@@ -382,6 +394,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                            regs_l[addr] = 1;
                        }
                        break;
+                    default:
+                        break;
                }
                break;

@@ -396,14 +410,16 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430TX:
                        regs[0x4f] = (val & 0x80);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x50:
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
-                    default:
                        regs[0x50] = (val & 0xe5);
                        break;
                    case INTEL_430NX:
@@ -467,17 +483,19 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0x51] = (regs[0x51] & 0xb0) | (val & 0x4f);
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x52: /* Cache Control Register */
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
                    case INTEL_430FX:
                    case INTEL_430VX:
                    case INTEL_430TX:
-                    default:
                        regs[0x52] = (val & 0xfb);
                        break;
                    case INTEL_430NX:
@@ -515,6 +533,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        /* Not applicable to 440ZX as that does not support ECC. */
                        regs[0x53] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x54:
@@ -534,6 +554,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440FX:
                        regs[0x54] = val & 0x82;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x55:
@@ -553,6 +575,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[0x55] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x56:
@@ -577,6 +601,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[0x56] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x57:
@@ -628,10 +654,10 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                break;
            case 0x58:
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
-                    default:
                        regs[0x58] = val & 0x01;
                        break;
                    case INTEL_430NX:
@@ -720,6 +746,7 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    break;
                }
                switch (dev->type) {
+                    default:
                    case INTEL_420TX:
                    case INTEL_420ZX:
                    case INTEL_430LX:
@@ -731,7 +758,6 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440BX:
                    case INTEL_440ZX:
                    case INTEL_440GX:
-                    default:
                        regs[addr] = val;
                        break;
                    case INTEL_430FX:
@@ -768,6 +794,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430TX:
                        regs[addr] = val & 0x7f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x66:
@@ -786,6 +814,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[addr] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x67:
@@ -810,6 +840,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430TX:
                        regs[addr] = val & 0xb7;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x68:
@@ -838,6 +870,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[0x68] = (regs[0x68] & 0x3f) | (val & 0xc0);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x69:
@@ -856,6 +890,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[0x69] = val & 0x3f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x6a:
@@ -880,6 +916,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        else
                            regs[addr] = val & 0x33;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x6c:
@@ -899,6 +937,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        else if (addr == 0x6d)
                            regs[addr] = val & 0xcf;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x6f:
@@ -909,6 +949,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[addr] = val & 0xcf;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x70:
@@ -930,6 +972,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[addr] = val & 0xf8;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x71:
@@ -953,6 +997,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440LX:
                        regs[addr] = val & 0x1f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x72: /* SMRAM */
@@ -998,6 +1044,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                            i4x0_smram_handler_phase1(dev);
                        }
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x74:
@@ -1008,6 +1056,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x74] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x75:
@@ -1018,6 +1068,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                    case INTEL_440GX:
                        regs[addr] = val;
+                    default:
+                        break;
                }
                break;
            case 0x77:
@@ -1025,6 +1077,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440BX:
                    case INTEL_440ZX:
                        regs[0x77] = val & 0x03;
+                    default:
+                        break;
                }
                break;
            case 0x78:
@@ -1039,6 +1093,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x78] = val & 0x1f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x79:
@@ -1054,6 +1110,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x79] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x7a:
@@ -1066,6 +1124,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        if (val & 0x40)
                            io_sethandler(0x0022, 0x01, pm2_cntrl_read, NULL, NULL, pm2_cntrl_write, NULL, NULL, dev);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x7c:
@@ -1081,6 +1141,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[0x7c] = val & 0x1f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x7d:
@@ -1091,6 +1153,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430NX:
                        regs[0x7d] = val & 0x32;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x7e:
@@ -1102,6 +1166,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_430NX:
                        regs[addr] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x80:
@@ -1111,6 +1177,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x80] &= ~(val & 0x03);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x90:
@@ -1132,6 +1200,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x90] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x91:
@@ -1144,6 +1214,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        /* Not applicable on 82443EX and 82443ZX. */
                        regs[0x91] &= ~(val & 0x11);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x92:
@@ -1157,6 +1229,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0x92] &= ~(val & 0x1f);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0x93:
@@ -1170,6 +1244,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0x93] = (val & 0x0e);
                        trc_write(0x0093, val & 0x06, NULL);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xa7:
@@ -1178,6 +1254,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[0xa7] = val & 0x1f;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xa8:
@@ -1190,6 +1268,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[addr] = (val & 0x03);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xb0:
@@ -1201,6 +1281,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0xb0] = (val & 0x80);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xb1:
@@ -1214,6 +1296,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0xb1] = (val & 0xa0);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xb4:
@@ -1226,6 +1310,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0xb4] = (val & 0x3f);
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xb9:
@@ -1238,6 +1324,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[0xb9] = (val & 0xf0);
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;

@@ -1252,6 +1340,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        regs[addr] = val;
                        i4x0_mask_bar(regs, dev->agpgart);
                        break;
+                    default:
+                        break;
                }
                break;

@@ -1261,6 +1351,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[addr] = (val & 0xf8);
                        break;
+                    default:
+                        break;
                }
                break;

@@ -1270,6 +1362,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440EX:
                        regs[addr] = (val & 0xf8);
                        break;
+                    default:
+                        break;
                }
                break;

@@ -1287,6 +1381,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[addr] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xca:
@@ -1298,6 +1394,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[addr] = val & 0xe7;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xcb:
@@ -1309,6 +1407,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[addr] = val & 0xa7;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xcc:
@@ -1320,6 +1420,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440ZX:
                        regs[0xcc] = (val & 0x58);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xe0:
@@ -1339,6 +1441,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        if (!regs_l[addr])
                            regs[addr] = val;
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xe5:
@@ -1350,6 +1454,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                        if (!regs_l[addr])
                            regs[addr] = (val & 0x3f);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xe7:
@@ -1364,6 +1470,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                            regs[0xe7] |= (val & 0x7f);
                        }
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xf0:
@@ -1373,6 +1481,8 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0xf0] = (val & 0xc0);
                        break;
+                    default:
+                        break;
                }
                break;
            case 0xf1:
@@ -1382,8 +1492,13 @@ i4x0_write(int func, int addr, uint8_t val, void *priv)
                    case INTEL_440GX:
                        regs[0xf1] = (val & 0x03);
                        break;
+                    default:
+                        break;
                }
                break;
+
+            default:
+                break;
        }
 }

@@ -1409,7 +1524,6 @@ static void
 i4x0_reset(void *priv)
 {
    i4x0_t *dev = (i4x0_t *) priv;
-    int     i;

    if ((dev->type == INTEL_440LX) || (dev->type == INTEL_440BX) || (dev->type == INTEL_440ZX))
        memset(dev->regs_locked, 0x00, 256 * sizeof(uint8_t));
@@ -1419,10 +1533,10 @@ i4x0_reset(void *priv)
    else
        i4x0_write(0, 0x59, 0x0f, priv);

-    for (i = 0; i < 6; i++)
+    for (uint8_t i = 0; i < 6; i++)
        i4x0_write(0, 0x5a + i, 0x00, priv);

-    for (i = 0; i <= dev->max_drb; i++)
+    for (uint8_t i = 0; i <= dev->max_drb; i++)
        i4x0_write(0, 0x60 + i, dev->drb_default, priv);

    if (dev->type >= INTEL_430FX) {
@@ -1443,9 +1557,9 @@ i4x0_reset(void *priv)
 }

 static void
-i4x0_close(void *p)
+i4x0_close(void *priv)
 {
-    i4x0_t *dev = (i4x0_t *) p;
+    i4x0_t *dev = (i4x0_t *) priv;

    smram_del(dev->smram_high);
    smram_del(dev->smram_low);
@@ -1453,9 +1567,8 @@ i4x0_close(void *p)
    free(dev);
 }

-static void
-    *
-    i4x0_init(const device_t *info)
+static void *
+i4x0_init(const device_t *info)
 {
    i4x0_t  *dev = (i4x0_t *) malloc(sizeof(i4x0_t));
    uint8_t *regs;
@@ -1746,6 +1859,8 @@ static void
            dev->drb_unit                                                                                         = 8;
            dev->drb_default                                                                                      = 0x01;
            break;
+        default:
+            break;
    }

    regs[0x04] = 0x06;
--- a/src/chipset/intel_82335.c
+++ b/src/chipset/intel_82335.c
@@ -28,6 +28,7 @@
 #include <86box/device.h>
 #include <86box/mem.h>
 #include <86box/chipset.h>
+#include <86box/plat_unused.h>

 /* Shadow capabilities */
 #define DISABLED_SHADOW (MEM_READ_EXTANY | MEM_WRITE_EXTANY)
@@ -56,12 +57,10 @@
 #define DEFINE_RC1_REMAP_SIZE ((dev->regs[0x24] & 0x02) ? 128 : 256)
 #define DEFINE_RC2_REMAP_SIZE ((dev->regs[0x26] & 0x02) ? 128 : 256)

-typedef struct
-{
+typedef struct intel_82335_t {
+    uint16_t regs[256];

-    uint16_t regs[256],
-
-        cfg_locked;
+    uint16_t cfg_locked;

 } intel_82335_t;

@@ -109,7 +108,9 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
                    shadowbios_write = !!(dev->regs[0x22] & 0x01);

                    /* Base System 512/640KB set */
-                    // mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
+#if 0
+                    mem_set_mem_state_both(0x80000, 0x20000, (dev->regs[0x22] & 0x08) ? ENABLE_TOP_128KB : DISABLE_TOP_128KB);
+#endif

                    /* Video RAM shadow*/
                    mem_set_mem_state_both(0xa0000, 0x20000, (dev->regs[0x22] & (0x04 << 8)) ? DETERMINE_VIDEO_RAM_WRITE_ACCESS : DISABLED_SHADOW);
@@ -137,8 +138,11 @@ intel_82335_write(uint16_t addr, uint16_t val, void *priv)
                        shadowbios_write = (dev->regs[0x2e] & (1 << i)) && (base == romsize);
                        mem_set_mem_state_both(base, 0x8000, GRANULARITY_RECALC);
                    }
-                    break;
                }
+                break;
+
+            default:
+                break;
        }
    }

@@ -165,7 +169,7 @@ intel_82335_close(void *priv)
 }

 static void *
-intel_82335_init(const device_t *info)
+intel_82335_init(UNUSED(const device_t *info))
 {
    intel_82335_t *dev = (intel_82335_t *) malloc(sizeof(intel_82335_t));
    memset(dev, 0, sizeof(intel_82335_t));
--- a/src/chipset/intel_i450kx.c
+++ b/src/chipset/intel_i450kx.c
@@ -35,6 +35,7 @@ i450GX is way more popular of an option but needs more stuff.
 #include <86box/device.h>
 #include <86box/mem.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/smram.h>
 #include <86box/spd.h>
 #include <86box/chipset.h>
@@ -61,7 +62,8 @@ i450kx_log(const char *fmt, ...)
 typedef struct i450kx_t {
    smram_t *smram[2];

-    uint8_t pb_pci_conf[256], mc_pci_conf[256];
+    uint8_t pb_pci_conf[256];
+    uint8_t mc_pci_conf[256];
    uint8_t mem_state[2][256];

    uint8_t bus_index;
@@ -112,7 +114,9 @@ i450kx_vid_buf_recalc(i450kx_t *dev, int bus)
 {
    uint8_t *regs = bus ? dev->pb_pci_conf : dev->mc_pci_conf;

+#if 0
    // int state = (regs[0x58] & 0x02) ? (MEM_READ_EXTANY | MEM_WRITE_EXTANY) : (MEM_READ_DISABLED | MEM_WRITE_DISABLED);
+#endif
    int state = (regs[0x58] & 0x02) ? (MEM_READ_INTERNAL | MEM_WRITE_INTERNAL) : (MEM_READ_EXTANY | MEM_WRITE_EXTANY);

    if (bus)
@@ -167,8 +171,10 @@ pb_write(int func, int addr, uint8_t val, void *priv)
            case 0x4a:
            case 0x4b:
                dev->pb_pci_conf[addr] = val;
-                // if (addr == 0x4a)
-                // pci_remap_bus(dev->bus_index, val);
+#if 0
+                if (addr == 0x4a)
+                    pci_remap_bus(dev->bus_index, val);
+#endif
                break;

            case 0x4c:
@@ -366,6 +372,9 @@ pb_write(int func, int addr, uint8_t val, void *priv)
            case 0xcb:
                dev->pb_pci_conf[addr] = val;
                break;
+
+            default:
+                break;
        }
 }

@@ -590,6 +599,9 @@ mc_write(int func, int addr, uint8_t val, void *priv)
            case 0xcb:
                dev->mc_pci_conf[addr] = val;
                break;
+
+            default:
+                break;
        }
 }

@@ -613,7 +625,9 @@ i450kx_reset(void *priv)
    i450kx_t *dev = (i450kx_t *) priv;
    uint32_t  i;

+#if 0
    // pclog("i450KX: i450kx_reset()\n");
+#endif

    /* Defaults PB */
    dev->pb_pci_conf[0x00] = 0x86;
@@ -671,8 +685,10 @@ i450kx_reset(void *priv)
    dev->pb_pci_conf[0xa6] = 0xfe;
    dev->pb_pci_conf[0xa7] = 0x00;
    /* Note: Do NOT reset these two registers on programmed (TRC) hard reset! */
-    // dev->pb_pci_conf[0xb0] = 0x00;
-    // dev->pb_pci_conf[0xb1] = 0x00;
+#if 0
+    dev->pb_pci_conf[0xb0] = 0x00;
+    dev->pb_pci_conf[0xb1] = 0x00;
+#endif
    dev->pb_pci_conf[0xb4] = 0x00;
    dev->pb_pci_conf[0xb5] = 0x00;
    dev->pb_pci_conf[0xb8] = 0x05;
@@ -693,7 +709,9 @@ i450kx_reset(void *priv)
    dev->pb_pci_conf[0xca] = 0x00;
    dev->pb_pci_conf[0xcb] = 0x00;

-    // pci_remap_bus(dev->bus_index, 0x00);
+#if 0
+    pci_remap_bus(dev->bus_index, 0x00);
+#endif
    i450kx_smram_recalc(dev, 1);
    i450kx_vid_buf_recalc(dev, 1);
    pb_write(0, 0x59, 0x30, dev);
@@ -786,7 +804,7 @@ i450kx_close(void *priv)
 }

 static void *
-i450kx_init(const device_t *info)
+i450kx_init(UNUSED(const device_t *info))
 {
    i450kx_t *dev = (i450kx_t *) malloc(sizeof(i450kx_t));
    memset(dev, 0, sizeof(i450kx_t));
--- a/src/chipset/intel_piix.c
+++ b/src/chipset/intel_piix.c
@@ -40,6 +40,7 @@
 #include <86box/pci.h>
 #include <86box/pic.h>
 #include <86box/pit.h>
+#include <86box/plat.h>
 #include <86box/port_92.h>
 #include <86box/scsi_device.h>
 #include <86box/hdc.h>
@@ -50,7 +51,7 @@
 #include <86box/smbus.h>
 #include <86box/chipset.h>

-typedef struct {
+typedef struct piix_io_trap_t {
    struct _piix_ *dev;
    void          *trap;
    uint8_t        dev_id;
@@ -58,14 +59,20 @@ typedef struct {
 } piix_io_trap_t;

 typedef struct _piix_ {
-    uint8_t cur_readout_reg, rev,
-        type, func_shift,
-        max_func, pci_slot,
-        no_mirq0, pad,
-        regs[4][256],
-        readout_regs[256], board_config[2];
-    uint16_t func0_id, nvr_io_base,
-        acpi_io_base;
+    uint8_t        cur_readout_reg;
+    uint8_t        rev;
+    uint8_t        type;
+    uint8_t        func_shift;
+    uint8_t        max_func;
+    uint8_t        pci_slot;
+    uint8_t        no_mirq0;
+    uint8_t        pad;
+    uint8_t        regs[4][256];
+    uint8_t        readout_regs[256];
+    uint8_t        board_config[2];
+    uint16_t       func0_id;
+    uint16_t       nvr_io_base;
+    uint16_t       acpi_io_base;
    double         fast_off_period;
    sff8038i_t    *bm[2];
    smbus_piix4_t *smbus;
@@ -135,6 +142,8 @@ smsc_ide_irqs(piix_t *dev)
        case 0x07:
            irq_line = 15;
            break;
+        default:
+            break;
    }

    sff_set_irq_line(dev->bm[0], irq_line);
@@ -203,7 +212,7 @@ piix_ide_bm_handlers(piix_t *dev)
 }

 static uint8_t
-kbc_alias_reg_read(uint16_t addr, void *p)
+kbc_alias_reg_read(UNUSED(uint16_t addr), UNUSED(void *priv))
 {
    uint8_t ret = inb(0x61);

@@ -211,7 +220,7 @@ kbc_alias_reg_read(uint16_t addr, void *p)
 }

 static void
-kbc_alias_reg_write(uint16_t addr, uint8_t val, void *p)
+kbc_alias_reg_write(UNUSED(uint16_t addr), uint8_t val, UNUSED(void *priv))
 {
    outb(0x61, val);
 }
@@ -267,7 +276,7 @@ nvr_update_io_mapping(piix_t *dev)
 }

 static void
-piix_trap_io(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
+piix_trap_io(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
 {
    piix_io_trap_t *trap = (piix_io_trap_t *) priv;

@@ -555,8 +564,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
                break;
            case 0x6a:
                switch (dev->type) {
-                    case 1:
                    default:
+                    case 1:
                        fregs[0x6a] = (fregs[0x6a] & 0xfb) | (val & 0x04);
                        fregs[0x0e] = (val & 0x04) ? 0x80 : 0x00;
                        piix_log("PIIX: Write %02X\n", val);
@@ -791,6 +800,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
                    }
                }
                break;
+            default:
+                break;
        }
    else if (func == 1)
        switch (addr) { /* IDE */
@@ -1012,6 +1023,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
                    nvr_read_addr_set(!!(val & 0x10), dev->nvr);
                }
                break;
+            default:
+                break;
        }
    else if (func == 3)
        switch (addr) { /* Power Management */
@@ -1145,6 +1158,8 @@ piix_write(int func, int addr, uint8_t val, void *priv)
                fregs[0x91] = val;
                smbus_update_io_mapping(dev);
                break;
+            default:
+                break;
        }
 }

@@ -1409,9 +1424,9 @@ piix_reset_hard(piix_t *dev)
 }

 static void
-piix_apm_out(uint16_t port, uint8_t val, void *p)
+piix_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
 {
-    piix_t *dev = (piix_t *) p;
+    piix_t *dev = (piix_t *) priv;

    if (dev->apm->do_smi) {
        if (dev->type < 4)
@@ -1440,73 +1455,73 @@ piix_usb_update_interrupt(usb_t* usb, void *priv)
 }

 static void
-piix_reset(void *p)
+piix_reset(void *priv)
 {
-    piix_t *dev = (piix_t *) p;
+    piix_t *dev = (piix_t *) priv;

    if (dev->type > 3) {
-        piix_write(3, 0x04, 0x00, p);
-        piix_write(3, 0x5b, 0x00, p);
+        piix_write(3, 0x04, 0x00, priv);
+        piix_write(3, 0x5b, 0x00, priv);
    } else {
-        piix_write(0, 0xa0, 0x08, p);
-        piix_write(0, 0xa2, 0x00, p);
-        piix_write(0, 0xa4, 0x00, p);
-        piix_write(0, 0xa5, 0x00, p);
-        piix_write(0, 0xa6, 0x00, p);
-        piix_write(0, 0xa7, 0x00, p);
-        piix_write(0, 0xa8, 0x0f, p);
+        piix_write(0, 0xa0, 0x08, priv);
+        piix_write(0, 0xa2, 0x00, priv);
+        piix_write(0, 0xa4, 0x00, priv);
+        piix_write(0, 0xa5, 0x00, priv);
+        piix_write(0, 0xa6, 0x00, priv);
+        piix_write(0, 0xa7, 0x00, priv);
+        piix_write(0, 0xa8, 0x0f, priv);
    }

    /* Disable the PIC mouse latch. */
-    piix_write(0, 0x4e, 0x03, p);
+    piix_write(0, 0x4e, 0x03, priv);

    if (dev->type == 5)
-        piix_write(0, 0xe1, 0x40, p);
-    piix_write(1, 0x04, 0x00, p);
+        piix_write(0, 0xe1, 0x40, priv);
+    piix_write(1, 0x04, 0x00, priv);
    if (dev->type == 5) {
-        piix_write(1, 0x09, 0x8a, p);
-        piix_write(1, 0x10, 0xf1, p);
-        piix_write(1, 0x11, 0x01, p);
-        piix_write(1, 0x14, 0xf5, p);
-        piix_write(1, 0x15, 0x03, p);
-        piix_write(1, 0x18, 0x71, p);
-        piix_write(1, 0x19, 0x01, p);
-        piix_write(1, 0x1c, 0x75, p);
-        piix_write(1, 0x1d, 0x03, p);
+        piix_write(1, 0x09, 0x8a, priv);
+        piix_write(1, 0x10, 0xf1, priv);
+        piix_write(1, 0x11, 0x01, priv);
+        piix_write(1, 0x14, 0xf5, priv);
+        piix_write(1, 0x15, 0x03, priv);
+        piix_write(1, 0x18, 0x71, priv);
+        piix_write(1, 0x19, 0x01, priv);
+        piix_write(1, 0x1c, 0x75, priv);
+        piix_write(1, 0x1d, 0x03, priv);
    } else
-        piix_write(1, 0x09, 0x80, p);
-    piix_write(1, 0x20, 0x01, p);
-    piix_write(1, 0x21, 0x00, p);
-    piix_write(1, 0x41, 0x00, p);
-    piix_write(1, 0x43, 0x00, p);
+        piix_write(1, 0x09, 0x80, priv);
+    piix_write(1, 0x20, 0x01, priv);
+    piix_write(1, 0x21, 0x00, priv);
+    piix_write(1, 0x41, 0x00, priv);
+    piix_write(1, 0x43, 0x00, priv);

    ide_pri_disable();
    ide_sec_disable();

    if (dev->type >= 3) {
-        piix_write(2, 0x04, 0x00, p);
+        piix_write(2, 0x04, 0x00, priv);
        if (dev->type == 5) {
-            piix_write(2, 0x10, 0x00, p);
-            piix_write(2, 0x11, 0x00, p);
-            piix_write(2, 0x12, 0x00, p);
-            piix_write(2, 0x13, 0x00, p);
+            piix_write(2, 0x10, 0x00, priv);
+            piix_write(2, 0x11, 0x00, priv);
+            piix_write(2, 0x12, 0x00, priv);
+            piix_write(2, 0x13, 0x00, priv);
        } else {
-            piix_write(2, 0x20, 0x01, p);
-            piix_write(2, 0x21, 0x00, p);
-            piix_write(2, 0x22, 0x00, p);
-            piix_write(2, 0x23, 0x00, p);
+            piix_write(2, 0x20, 0x01, priv);
+            piix_write(2, 0x21, 0x00, priv);
+            piix_write(2, 0x22, 0x00, priv);
+            piix_write(2, 0x23, 0x00, priv);
        }
    }

    if (dev->type >= 4) {
-        piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, p);
-        piix_write(3, 0x40, 0x01, p);
-        piix_write(3, 0x41, 0x00, p);
-        piix_write(3, 0x5b, 0x00, p);
-        piix_write(3, 0x80, 0x00, p);
-        piix_write(3, 0x90, 0x01, p);
-        piix_write(3, 0x91, 0x00, p);
-        piix_write(3, 0xd2, 0x00, p);
+        piix_write(0, 0xb0, is_pentium ? 0x00 : 0x04, priv);
+        piix_write(3, 0x40, 0x01, priv);
+        piix_write(3, 0x41, 0x00, priv);
+        piix_write(3, 0x5b, 0x00, priv);
+        piix_write(3, 0x80, 0x00, priv);
+        piix_write(3, 0x90, 0x01, priv);
+        piix_write(3, 0x91, 0x00, priv);
+        piix_write(3, 0xd2, 0x00, priv);
    }

    sff_set_irq_mode(dev->bm[0], 0, 0);
@@ -1695,7 +1710,9 @@ piix_init(const device_t *info)
    else
        dev->board_config[1] |= 0x00;

-    // device_add(&i8254_sec_device);
+#if 0
+    device_add(&i8254_sec_device);
+#endif

    return dev;
 }
--- a/src/chipset/intel_sio.c
+++ b/src/chipset/intel_sio.c
@@ -33,18 +33,19 @@
 #include <86box/port_92.h>
 #include <86box/machine.h>
 #include <86box/chipset.h>
+#include <86box/plat_unused.h>

-typedef struct
-{
-    uint8_t id,
-        regs[256];
+typedef struct sio_t {
+    uint8_t id;
+    uint8_t regs[256];

-    uint16_t timer_base,
-        timer_latch;
+    uint16_t timer_base;
+    uint16_t timer_latch;

    double fast_off_period;

-    pc_timer_t timer, fast_off_timer;
+    pc_timer_t timer;
+    pc_timer_t fast_off_timer;

    apm_t     *apm;
    port_92_t *port_92;
@@ -315,6 +316,8 @@ sio_write(int func, int addr, uint8_t val, void *priv)
            cpu_fast_off_count = val + 1;
            cpu_fast_off_period_set(cpu_fast_off_val, dev->fast_off_period);
            break;
+        default:
+            break;
    }
 }

@@ -333,12 +336,13 @@ sio_read(int func, int addr, void *priv)
 }

 static void
-sio_config_write(uint16_t addr, uint8_t val, void *priv)
+sio_config_write(UNUSED(uint16_t addr), UNUSED(uint8_t val), UNUSED(void *priv))
 {
+    //
 }

 static uint8_t
-sio_config_read(uint16_t port, void *priv)
+sio_config_read(uint16_t port, UNUSED(void *priv))
 {
    uint8_t ret = 0x00;

@@ -365,6 +369,9 @@ sio_config_read(uint16_t port, void *priv)
                    break;
            }
            break;
+
+        default:
+            break;
    }

    return ret;
@@ -425,9 +432,9 @@ sio_reset_hard(void *priv)
 }

 static void
-sio_apm_out(uint16_t port, uint8_t val, void *p)
+sio_apm_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
 {
-    sio_t *dev = (sio_t *) p;
+    sio_t *dev = (sio_t *) priv;

    if (dev->apm->do_smi)
        dev->regs[0xaa] |= 0x80;
@@ -443,32 +450,32 @@ sio_fast_off_count(void *priv)
 }

 static void
-sio_reset(void *p)
+sio_reset(void *priv)
 {
-    sio_t *dev = (sio_t *) p;
+    sio_t *dev = (sio_t *) priv;

    /* Disable the PIC mouse latch. */
-    sio_write(0, 0x4d, 0x40, p);
+    sio_write(0, 0x4d, 0x40, priv);

-    sio_write(0, 0x57, 0x04, p);
+    sio_write(0, 0x57, 0x04, priv);

    dma_set_params(1, 0xffffffff);

    if (dev->id == 0x03) {
-        sio_write(0, 0xa0, 0x08, p);
-        sio_write(0, 0xa2, 0x00, p);
-        sio_write(0, 0xa4, 0x00, p);
-        sio_write(0, 0xa5, 0x00, p);
-        sio_write(0, 0xa6, 0x00, p);
-        sio_write(0, 0xa7, 0x00, p);
-        sio_write(0, 0xa8, 0x0f, p);
+        sio_write(0, 0xa0, 0x08, priv);
+        sio_write(0, 0xa2, 0x00, priv);
+        sio_write(0, 0xa4, 0x00, priv);
+        sio_write(0, 0xa5, 0x00, priv);
+        sio_write(0, 0xa6, 0x00, priv);
+        sio_write(0, 0xa7, 0x00, priv);
+        sio_write(0, 0xa8, 0x0f, priv);
    }
 }

 static void
-sio_close(void *p)
+sio_close(void *priv)
 {
-    sio_t *dev = (sio_t *) p;
+    sio_t *dev = (sio_t *) priv;

    free(dev);
 }
@@ -542,7 +549,9 @@ sio_init(const device_t *info)

    timer_add(&dev->timer, NULL, NULL, 0);

-    // device_add(&i8254_sec_device);
+#if 0
+    device_add(&i8254_sec_device);
+#endif

    return dev;
 }
--- a/src/chipset/neat.c
+++ b/src/chipset/neat.c
@@ -30,6 +30,7 @@
 #include <86box/device.h>
 #include <86box/io.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

 #define NEAT_DEBUG  0
@@ -200,7 +201,7 @@
 #define RB11_EMSLEN    0xe0 /*  EMS memory chunk size */
 #define RB11_EMSLEN_SH 5

-typedef struct {
+typedef struct emspage_t {
    int8_t        enabled; /* 1=ENABLED */
    char          pad;
    uint16_t      page;    /* selected page in EMS block */
@@ -209,18 +210,18 @@ typedef struct {
    mem_mapping_t mapping; /* mapping entry for page */
 } emspage_t;

-typedef struct {
+typedef struct neat_t {
    uint8_t regs[128]; /* all the CS8221 registers */
    uint8_t indx;      /* programmed index into registers */

    char pad;

-    uint16_t ems_base, /* configured base address */
-        ems_oldbase;
-    uint32_t ems_frame, /* configured frame address */
-        ems_oldframe;
-    uint16_t ems_size,          /* EMS size in KB */
-        ems_pages;              /* EMS size in pages */
+    uint16_t ems_base;          /* configured base address */
+    uint16_t ems_oldbase;
+    uint32_t ems_frame;         /* configured frame address */
+    uint32_t ems_oldframe;
+    uint16_t ems_size;          /* EMS size in KB */
+    uint16_t ems_pages;         /* EMS size in pages */
    emspage_t ems[EMS_MAXPAGE]; /* EMS page registers */
 } neat_t;

@@ -340,6 +341,8 @@ ems_write(uint16_t port, uint8_t val, void *priv)
            ems->page |= (val & 0x7f); /* add new bits */
            ems_recalc(dev, ems);
            break;
+        default:
+            break;
    }
 }

@@ -359,6 +362,8 @@ ems_read(uint16_t port, void *priv)
            if (dev->ems[vpage].enabled)
                ret |= 0x80;
            break;
+        default:
+            break;
    }

 #if NEAT_DEBUG > 1
@@ -372,12 +377,12 @@ ems_read(uint16_t port, void *priv)
 static void
 ems_init(neat_t *dev, int en)
 {
-    int i;
+    uint8_t j;

    /* Remove if needed. */
    if (!en) {
        if (dev->ems_base > 0)
-            for (i = 0; i < EMS_MAXPAGE; i++) {
+            for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
                /* Disable for now. */
                mem_mapping_disable(&dev->ems[i].mapping);

@@ -394,19 +399,19 @@ ems_init(neat_t *dev, int en)
    }

    /* Get configured I/O address. */
-    i             = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
-    dev->ems_base = 0x0208 + (0x10 * i);
+    j             = (dev->regs[REG_RB9] & RB9_BASE) >> RB9_BASE_SH;
+    dev->ems_base = 0x0208 + (0x10 * j);

    /* Get configured frame address. */
-    i              = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
-    dev->ems_frame = 0xC0000 + (EMS_PGSIZE * i);
+    j              = (dev->regs[REG_RB9] & RB9_FRAME) >> RB9_FRAME_SH;
+    dev->ems_frame = 0xC0000 + (EMS_PGSIZE * j);

    /*
     * For each supported page (we can have a maximum of 4),
     * create, initialize and disable the mappings, and set
     * up the I/O control handler.
     */
-    for (i = 0; i < EMS_MAXPAGE; i++) {
+    for (uint8_t i = 0; i < EMS_MAXPAGE; i++) {
        /* Create and initialize a page mapping. */
        mem_mapping_add(&dev->ems[i].mapping,
                        dev->ems_frame + (EMS_PGSIZE * i), EMS_PGSIZE,
@@ -608,6 +613,8 @@ neat_write(uint16_t port, uint8_t val, void *priv)
                        case 7: /* 7 MB */
                            dev->ems_size = i << 10;
                            break;
+                        default:
+                            break;
                    }
                    dev->ems_pages = (dev->ems_size << 10) / EMS_PGSIZE;
                    if (dev->regs[REG_RB7] & RB7_EMSEN) {
@@ -622,6 +629,8 @@ neat_write(uint16_t port, uint8_t val, void *priv)
                    break;
            }
            break;
+        default:
+            break;
    }
 }

@@ -660,17 +669,17 @@ neat_close(void *priv)
 }

 static void *
-neat_init(const device_t *info)
+neat_init(UNUSED(const device_t *info))
 {
    neat_t *dev;
-    int     i;
+    uint8_t dram_mode = 0;

    /* Create an instance. */
    dev = (neat_t *) malloc(sizeof(neat_t));
    memset(dev, 0x00, sizeof(neat_t));

    /* Initialize some of the registers to specific defaults. */
-    for (i = REG_RA0; i <= REG_RB11; i++) {
+    for (uint8_t i = REG_RA0; i <= REG_RB11; i++) {
        dev->indx = i;
        neat_write(0x0023, 0x00, dev);
    }
@@ -682,7 +691,6 @@ neat_init(const device_t *info)
     * TODO: We might also want to set 'valid' waitstate
     *       bits, based on our cpu speed.
     */
-    i = 0;
    switch (mem_size) {
        case 512: /* 512KB */
            /* 256K, 0, 0, 0 */
@@ -690,7 +698,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
-            i = 2;
+            dram_mode = 2;
            break;

        case 640: /* 640KB */
@@ -699,7 +707,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
            dev->regs[REG_RB8] &= ~RB8_BANKS;                /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH);  /* NONE */
-            i = 4;
+            dram_mode = 4;
            break;

        case 1024: /* 1MB */
@@ -708,7 +716,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
-            i = 5;
+            dram_mode = 5;
            break;

        case 1536: /* 1.5MB */
@@ -717,7 +725,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
-            i = 7;
+            dram_mode = 7;
            break;

        case 1664: /* 1.64MB */
@@ -726,7 +734,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
            dev->regs[REG_RB8] |= RB8_BANKS;                 /* two banks */
            dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH);  /* 256K */
-            i = 10;
+            dram_mode = 10;
            break;

        case 2048: /* 2MB */
@@ -737,14 +745,14 @@ neat_init(const device_t *info)
            dev->regs[REG_RB8] |= RB8_BANKS;                /* two banks */
            dev->regs[REG_RB8] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] |= RB8_4WAY;                 /* 4way intl */
-            i = 11;
+            dram_mode = 11;
 #else
            /* 1M, 0, 0, 0 */
            dev->regs[REG_RB6] &= ~RB6_BANKS;               /* one bank */
            dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH);   /* 1M */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
-            i = 3;
+            dram_mode = 3;
 #endif
            break;

@@ -754,7 +762,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH);   /* 1M */
-            i = 8;
+            dram_mode = 8;
            break;

        case 4096: /* 4MB */
@@ -763,7 +771,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH);   /* 1M */
            dev->regs[REG_RB8] &= ~RB8_BANKS;               /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_NONE << RTYPE_SH); /* NONE */
-            i = 6;
+            dram_mode = 6;
            break;

        case 4224: /* 4.64MB */
@@ -772,7 +780,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_MIXED << RTYPE_SH); /* mixed */
            dev->regs[REG_RB8] |= RB8_BANKS;                 /* two banks */
            dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH);    /* 1M */
-            i = 12;
+            dram_mode = 12;
            break;

        case 5120: /* 5MB */
@@ -781,7 +789,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_256K << RTYPE_SH); /* 256K */
            dev->regs[REG_RB8] |= RB8_BANKS;                /* two banks */
            dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH);   /* 1M */
-            i = 13;
+            dram_mode = 13;
            break;

        case 6144: /* 6MB */
@@ -790,7 +798,7 @@ neat_init(const device_t *info)
            dev->regs[REG_RB6] |= (RTYPE_1M << RTYPE_SH); /* 1M */
            dev->regs[REG_RB8] &= ~RB8_BANKS;             /* one bank */
            dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
-            i = 9;
+            dram_mode = 9;
            break;

        case 8192: /* 8MB */
@@ -800,13 +808,13 @@ neat_init(const device_t *info)
            dev->regs[REG_RB8] |= RB8_BANKS;              /* two banks */
            dev->regs[REG_RB8] |= (RTYPE_1M << RTYPE_SH); /* 1M */
            dev->regs[REG_RB8] |= RB8_4WAY;               /* 4way intl */
-            i = 14;
+            dram_mode = 14;
            break;

        default:
            neat_log("NEAT: **INVALID DRAM SIZE %iKB !**\n", mem_size);
    }
-    if (i > 0) {
+    if (dram_mode > 0) {
        neat_log("NEAT: using DRAM mode #%i (mem=%iKB)\n", i, mem_size);
    }

--- a/src/chipset/olivetti_eva.c
+++ b/src/chipset/olivetti_eva.c
@@ -32,9 +32,9 @@
 #include <86box/chipset.h>
 #include <86box/video.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>

-typedef struct
-{
+typedef struct olivetti_eva_t {
    uint8_t reg_065;
    uint8_t reg_067;
    uint8_t reg_069;
@@ -77,20 +77,24 @@ olivetti_eva_write(uint16_t addr, uint8_t val, void *priv)
             * Unfortunately, if triggered, the BIOS remapping function fails causing
             * a fatal error. Therefore, this code section is currently commented.
             */
-            // if (val & 1){
-            //     /*
-            //      * Set the register to 7 or above for the BIOS to trigger the
-            //      * memory remapping function if shadowing is active.
-            //      */
-            //     dev->reg_069 = 0x7;
-            // }
-            // if (val & 8) {
-            //     /*
-            //      * Activate shadowing for region e0000-fffff
-            //      */
-            //     mem_remap_top(256);
-            //     mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
-            // }
+#if 0
+            if (val & 1) {
+                /*
+                 * Set the register to 7 or above for the BIOS to trigger the
+                 * memory remapping function if shadowing is active.
+                 */
+                 dev->reg_069 = 0x7;
+            }
+            if (val & 8) {
+                /*
+                 * Activate shadowing for region e0000-fffff
+                 */
+                 mem_remap_top(256);
+                 mem_set_mem_state_both(0xa0000, 0x60000, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
+            }
+#endif
+            break;
+        default:
            break;
    }
 }
@@ -111,6 +115,8 @@ olivetti_eva_read(uint16_t addr, void *priv)
        case 0x069:
            ret = dev->reg_069;
            break;
+        default:
+            break;
    }
    olivetti_eva_log("Olivetti EVA Gate Array: Read %02x at %02x\n", ret, addr);
    return ret;
@@ -125,7 +131,7 @@ olivetti_eva_close(void *priv)
 }

 static void *
-olivetti_eva_init(const device_t *info)
+olivetti_eva_init(UNUSED(const device_t *info))
 {
    olivetti_eva_t *dev = (olivetti_eva_t *) malloc(sizeof(olivetti_eva_t));
    memset(dev, 0, sizeof(olivetti_eva_t));
--- a/src/chipset/opti283.c
+++ b/src/chipset/opti283.c
@@ -29,6 +29,7 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

 #ifdef ENABLE_OPTI283_LOG
@@ -49,15 +50,15 @@ opti283_log(const char *fmt, ...)
 #    define opti283_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint32_t phys, virt;
+typedef struct mem_remapping_t {
+    uint32_t phys;
+    uint32_t virt;
 } mem_remapping_t;

-typedef struct
-{
-    uint8_t index, shadow_high,
-        regs[256];
+typedef struct opti283_t {
+    uint8_t         index;
+    uint8_t         shadow_high;
+    uint8_t         regs[256];
    mem_remapping_t mem_remappings[2];
    mem_mapping_t   mem_mappings[2];
 } opti283_t;
@@ -234,8 +235,14 @@ opti283_write(uint16_t addr, uint8_t val, void *priv)
                    dev->regs[dev->index] = val;
                    opti283_shadow_recalc(dev);
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -260,7 +267,7 @@ opti283_close(void *priv)
 }

 static void *
-opti283_init(const device_t *info)
+opti283_init(UNUSED(const device_t *info))
 {
    opti283_t *dev = (opti283_t *) malloc(sizeof(opti283_t));
    memset(dev, 0x00, sizeof(opti283_t));
--- a/src/chipset/opti291.c
+++ b/src/chipset/opti291.c
@@ -28,6 +28,7 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

@@ -49,9 +50,9 @@ opti291_log(const char *fmt, ...)
 #    define opti291_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint8_t    index, regs[256];
+typedef struct opti291_t {
+    uint8_t    index;
+    uint8_t    regs[256];
    port_92_t *port_92;
 } opti291_t;

@@ -107,8 +108,14 @@ opti291_write(uint16_t addr, uint8_t val, void *priv)
                case 0x2c:
                    dev->regs[dev->index] = val;
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -129,7 +136,7 @@ opti291_close(void *priv)
 }

 static void *
-opti291_init(const device_t *info)
+opti291_init(UNUSED(const device_t *info))
 {
    opti291_t *dev = (opti291_t *) malloc(sizeof(opti291_t));
    memset(dev, 0, sizeof(opti291_t));
--- a/src/chipset/opti391.c
+++ b/src/chipset/opti391.c
@@ -27,6 +27,7 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

 #ifdef ENABLE_OPTI391_LOG
@@ -47,20 +48,19 @@ opti391_log(const char *fmt, ...)
 #    define opti391_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint32_t phys, virt;
+typedef struct mem_remapping_t {
+    uint32_t phys;
+    uint32_t virt;
 } mem_remapping_t;

-typedef struct
-{
-    uint8_t index, regs[256];
+typedef struct opti391_t {
+    uint8_t index;
+    uint8_t regs[256];
 } opti391_t;

 static void
 opti391_shadow_recalc(opti391_t *dev)
 {
-    uint32_t i;
    uint32_t base;
    uint8_t  sh_enable;
    uint8_t  sh_master;
@@ -78,7 +78,7 @@ opti391_shadow_recalc(opti391_t *dev)

    sh_write_internal = (dev->regs[0x26] & 0x40);
    /* D0000-EFFFF */
-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        base = 0xd0000 + (i << 14);
        if (base >= 0xe0000) {
            sh_master = (dev->regs[0x22] & 0x40);
@@ -108,7 +108,7 @@ opti391_shadow_recalc(opti391_t *dev)
    /* C0000-CFFFF */
    sh_master = !(dev->regs[0x26] & 0x10);
    sh_wp     = (dev->regs[0x26] & 0x20);
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base      = 0xc0000 + (i << 14);
        sh_enable = dev->regs[0x26] & (1 << i);

@@ -164,8 +164,14 @@ opti391_write(uint16_t addr, uint8_t val, void *priv)
                    dev->regs[dev->index] = val;
                    opti391_shadow_recalc(dev);
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -190,7 +196,7 @@ opti391_close(void *priv)
 }

 static void *
-opti391_init(const device_t *info)
+opti391_init(UNUSED(const device_t *info))
 {
    opti391_t *dev = (opti391_t *) malloc(sizeof(opti391_t));
    memset(dev, 0x00, sizeof(opti391_t));
--- a/src/chipset/opti495.c
+++ b/src/chipset/opti495.c
@@ -31,11 +31,10 @@
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t idx,
-        regs[256],
-        scratch[2];
+typedef struct opti495_t {
+    uint8_t idx;
+    uint8_t regs[256];
+    uint8_t scratch[2];
 } opti495_t;

 #ifdef ENABLE_OPTI495_LOG
@@ -60,7 +59,6 @@ static void
 opti495_recalc(opti495_t *dev)
 {
    uint32_t base;
-    uint32_t i;
    uint32_t shflags = 0;

    shadowbios       = 0;
@@ -78,7 +76,7 @@ opti495_recalc(opti495_t *dev)

    mem_set_mem_state_both(0xf0000, 0x10000, shflags);

-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        base = 0xd0000 + (i << 14);

        if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
@@ -95,7 +93,7 @@ opti495_recalc(opti495_t *dev)
        mem_set_mem_state_both(base, 0x4000, shflags);
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base = 0xc0000 + (i << 14);

        if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
@@ -141,6 +139,8 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
                    case 0x26:
                        opti495_recalc(dev);
                        break;
+                    default:
+                        break;
                }
            }
            break;
@@ -149,6 +149,8 @@ opti495_write(uint16_t addr, uint8_t val, void *priv)
        case 0xe2:
            dev->scratch[~addr & 0x01] = val;
            break;
+        default:
+            break;
    }
 }

@@ -172,6 +174,8 @@ opti495_read(uint16_t addr, void *priv)
        case 0xe2:
            ret = dev->scratch[~addr & 0x01];
            break;
+        default:
+            break;
    }

    return ret;
--- a/src/chipset/opti499.c
+++ b/src/chipset/opti499.c
@@ -29,12 +29,13 @@
 #include <86box/device.h>
 #include <86box/mem.h>
 #include <86box/port_92.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

-typedef struct
-{
+typedef struct opti499_t {
    uint8_t idx,
-        regs[256], scratch[2];
+    uint8_t regs[256];
+    uint8_t scratch[2];
 } opti499_t;

 #ifdef ENABLE_OPTI499_LOG
@@ -59,7 +60,6 @@ static void
 opti499_recalc(opti499_t *dev)
 {
    uint32_t base;
-    uint32_t i;
    uint32_t shflags = 0;

    shadowbios       = 0;
@@ -77,7 +77,7 @@ opti499_recalc(opti499_t *dev)

    mem_set_mem_state_both(0xf0000, 0x10000, shflags);

-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        base = 0xd0000 + (i << 14);

        if ((dev->regs[0x22] & ((base >= 0xe0000) ? 0x20 : 0x40)) && (dev->regs[0x23] & (1 << i))) {
@@ -93,7 +93,7 @@ opti499_recalc(opti499_t *dev)
        mem_set_mem_state_both(base, 0x4000, shflags);
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base = 0xc0000 + (i << 14);

        if ((dev->regs[0x26] & 0x10) && (dev->regs[0x26] & (1 << i))) {
@@ -154,6 +154,9 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
                    case 0x2d:
                        opti499_recalc(dev);
                        break;
+
+                    default:
+                        break;
                }
            }
            break;
@@ -162,6 +165,9 @@ opti499_write(uint16_t addr, uint8_t val, void *priv)
        case 0xe2:
            dev->scratch[~addr & 0x01] = val;
            break;
+
+        default:
+            break;
    }
 }

@@ -188,6 +194,9 @@ opti499_read(uint16_t addr, void *priv)
        case 0xe2:
            ret = dev->scratch[~addr & 0x01];
            break;
+
+        default:
+            break;
    }

    return ret;
@@ -230,7 +239,7 @@ opti499_close(void *priv)
 }

 static void *
-opti499_init(const device_t *info)
+opti499_init(UNUSED(const device_t *info))
 {
    opti499_t *dev = (opti499_t *) malloc(sizeof(opti499_t));
    memset(dev, 0, sizeof(opti499_t));
--- a/src/chipset/opti5x7.c
+++ b/src/chipset/opti5x7.c
@@ -32,10 +32,10 @@
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t idx, is_pci,
-        regs[16];
+typedef struct opti5x7_t {
+    uint8_t idx;
+    uint8_t is_pci;
+    uint8_t regs[16];
 } opti5x7_t;

 #ifdef ENABLE_OPTI5X7_LOG
@@ -84,7 +84,7 @@ opti5x7_shadow_map(int cur_reg, opti5x7_t *dev)
            mem_set_mem_state_both(0xf0000, 0x10000, ((dev->regs[6] & 4) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[6] & 8) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
        }
    } else {
-        for (int i = 0; i < 4; i++) {
+        for (uint8_t i = 0; i < 4; i++) {
            if (dev->is_pci)
                mem_set_mem_state_cpu_both(0xc0000 + ((cur_reg & 1) << 16) + (i << 14), 0x4000, ((dev->regs[cur_reg] & (1 << (2 * i))) ? MEM_READ_INTERNAL : MEM_READ_EXTANY) | ((dev->regs[cur_reg] & (2 << (2 * i))) ? MEM_WRITE_INTERNAL : MEM_WRITE_EXTANY));
            else
@@ -143,9 +143,13 @@ opti5x7_write(uint16_t addr, uint8_t val, void *priv)
                case 0x11: /* Master Cycle Control Register */
                    dev->regs[dev->idx] = val;
                    break;
+                default:
+                    break;
            }
            opti5x7_log("OPTi 5x7: dev->regs[%02x] = %02x\n", dev->idx, dev->regs[dev->idx]);
            break;
+        default:
+            break;
    }
 }

--- a/src/chipset/opti822.c
+++ b/src/chipset/opti822.c
@@ -33,6 +33,7 @@
 #include <86box/timer.h>
 #include <86box/pic.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc_ide.h>
 #include <86box/hdc.h>
@@ -40,10 +41,9 @@
 #include <86box/chipset.h>
 #include <86box/spd.h>

-typedef struct
-{
-    uint8_t irq_convert,
-        pci_regs[256];
+typedef struct opti822_t {
+    uint8_t irq_convert;
+    uint8_t pci_regs[256];
 } opti822_t;

 // #define ENABLE_OPTI822_LOG 1
@@ -107,7 +107,9 @@ opti822_update_irqs(opti822_t *dev, int set)
    int     irq_map[8] = { -1, 5, 9, 10, 11, 12, 14, 15 };
    pic_t  *temp_pic;

-    // dev->irq_convert = (dev->pci_regs[0x53] & 0x08);
+#if 0
+    dev->irq_convert = (dev->pci_regs[0x53] & 0x08);
+#endif
    dev->irq_convert = 1;

    for (uint8_t i = 0; i < 16; i++) {
@@ -325,6 +327,9 @@ opti822_pci_write(int func, int addr, uint8_t val, void *priv)
            }
            opti822_update_irqs(dev, 1);
            break;
+
+        default:
+            break;
    }
 }

@@ -383,7 +388,7 @@ opti822_close(void *p)
 }

 static void *
-opti822_init(const device_t *info)
+opti822_init(UNUSED(const device_t *info))
 {
    opti822_t *dev = (opti822_t *) malloc(sizeof(opti822_t));
    memset(dev, 0, sizeof(opti822_t));
--- a/src/chipset/opti895.c
+++ b/src/chipset/opti895.c
@@ -32,12 +32,12 @@
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t idx, forced_green,
-        is_pci,
-        regs[256],
-        scratch[2];
+typedef struct opti895_t {
+    uint8_t idx;
+    uint8_t forced_green;
+    uint8_t is_pci;
+    uint8_t regs[256];
+    uint8_t scratch[2];

    smram_t *smram;
 } opti895_t;
@@ -64,7 +64,6 @@ static void
 opti895_recalc(opti895_t *dev)
 {
    uint32_t base;
-    uint32_t i;
    uint32_t shflags = 0;

    shadowbios       = 0;
@@ -85,7 +84,7 @@ opti895_recalc(opti895_t *dev)
    else
        mem_set_mem_state_both(0xf0000, 0x10000, shflags);

-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        base = 0xd0000 + (i << 14);

        if (dev->regs[0x23] & (1 << i)) {
@@ -109,7 +108,7 @@ opti895_recalc(opti895_t *dev)
            mem_set_mem_state_both(base, 0x4000, shflags);
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base = 0xc0000 + (i << 14);

        if (dev->regs[0x26] & (1 << i)) {
@@ -185,6 +184,9 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
                            break;
                        }
                        break;
+
+                    default:
+                        break;
                }
            }
            break;
@@ -193,6 +195,9 @@ opti895_write(uint16_t addr, uint8_t val, void *priv)
        case 0xe2:
            dev->scratch[addr - 0xe1] = val;
            break;
+
+        default:
+            break;
    }
 }

@@ -218,6 +223,9 @@ opti895_read(uint16_t addr, void *priv)
        case 0xe2:
            ret = dev->scratch[addr - 0xe1];
            break;
+
+        default:
+            break;
    }

    return ret;
--- a/src/chipset/scamp.c
+++ b/src/chipset/scamp.c
@@ -31,6 +31,7 @@
 #include <86box/io.h>
 #include <86box/mem.h>
 #include <86box/nmi.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/chipset.h>

@@ -66,20 +67,21 @@ enum {
    BANK_4M_INTERLEAVED
 };

-typedef struct {
+typedef struct ram_struct_t {
    void *parent;
    int   bank;
 } ram_struct_t;

-typedef struct {
+typedef struct ems_struct_t {
    void *parent;
    int   segment;
 } ems_struct_t;

-typedef struct {
+typedef struct scamp_t {
    int     cfg_index;
    uint8_t cfg_regs[256];
-    int     cfg_enable, ram_config;
+    int     cfg_enable;
+    int     ram_config;

    int           ems_index;
    int           ems_autoinc;
@@ -91,21 +93,23 @@ typedef struct {
    ram_struct_t  ram_struct[2];
    ems_struct_t  ems_struct[20];

-    uint32_t ram_virt_base[2], ram_phys_base[2];
+    uint32_t ram_virt_base[2];
+    uint32_t ram_phys_base[2];
    uint32_t ram_mask[2];
-    int      row_virt_shift[2], row_phys_shift[2];
-    int      ram_interleaved[2], ibank_shift[2];
+    int      row_virt_shift[2];
+    int      row_phys_shift[2];
+    int      ram_interleaved[2];
+    int      ibank_shift[2];

    port_92_t *port_92;
 } scamp_t;

-static const struct
-{
+static const struct {
    int size_kb;
    int rammap;
    int bank[2];
 } ram_configs[] = {
-    {512,    0x0, { BANK_256K, BANK_NONE }                        },
+    {  512,  0x0, { BANK_256K, BANK_NONE }                        },
    { 1024,  0x1, { BANK_256K_INTERLEAVED, BANK_NONE }            },
    { 1536,  0x2, { BANK_256K_INTERLEAVED, BANK_256K }            },
    { 2048,  0x3, { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }},
@@ -118,12 +122,11 @@ static const struct
    { 16384, 0x9, { BANK_4M_INTERLEAVED, BANK_NONE }              },
 };

-static const struct
-{
+static const struct {
    int bank[2];
    int remapped;
 } rammap[16] = {
-    {{ BANK_256K, BANK_NONE },                          0},
+    { { BANK_256K, BANK_NONE },                         0},
    { { BANK_256K_INTERLEAVED, BANK_NONE },             0},
    { { BANK_256K_INTERLEAVED, BANK_256K },             0},
    { { BANK_256K_INTERLEAVED, BANK_256K_INTERLEAVED }, 0},
@@ -424,6 +427,9 @@ recalc_mappings(void *priv)
                    virt_base += (1 << 24);
                    dev->row_virt_shift[bank_nr] = 12;
                    break;
+
+                default:
+                    break;
            }
        } else {
            switch (rammap[cur_rammap].bank[bank_nr]) {
@@ -489,6 +495,9 @@ recalc_mappings(void *priv)
                    virt_base += (1 << 24);
                    dev->row_virt_shift[bank_nr] = 12;
                    break;
+
+                default:
+                    break;
            }
        }
        switch (rammap[cur_rammap].bank[bank_nr]) {
@@ -534,6 +543,9 @@ recalc_mappings(void *priv)
                                                ram_mirrored_interleaved_write, NULL, NULL);
                }
                break;
+
+            default:
+                break;
        }
    }
 }
@@ -584,7 +596,6 @@ scamp_ems_write(uint32_t addr, uint8_t val, void *priv)
 static void
 recalc_ems(scamp_t *dev)
 {
-    int            segment;
    const uint32_t ems_base[12] = {
        0xc0000, 0xc4000, 0xc8000, 0xcc000,
        0xd0000, 0xd4000, 0xd8000, 0xdc000,
@@ -593,7 +604,7 @@ recalc_ems(scamp_t *dev)
    uint32_t new_mappings[20];
    uint16_t ems_enable;

-    for (segment = 0; segment < 20; segment++)
+    for (int segment = 0; segment < 20; segment++)
        new_mappings[segment] = 0xa0000 + segment * 0x4000;

    if (dev->cfg_regs[CFG_EMSEN1] & EMSEN1_EMSENAB)
@@ -601,7 +612,7 @@ recalc_ems(scamp_t *dev)
    else
        ems_enable = 0;

-    for (segment = 0; segment < 12; segment++) {
+    for (int segment = 0; segment < 12; segment++) {
        if (ems_enable & (1 << segment)) {
            uint32_t phys_addr = dev->ems[segment] << 14;

@@ -613,7 +624,7 @@ recalc_ems(scamp_t *dev)
        }
    }

-    for (segment = 0; segment < 20; segment++) {
+    for (int segment = 0; segment < 20; segment++) {
        if (new_mappings[segment] != dev->mappings[segment]) {
            dev->mappings[segment] = new_mappings[segment];
            if (new_mappings[segment] < (mem_size * 1024)) {
@@ -644,6 +655,8 @@ shadow_control(uint32_t addr, uint32_t size, int state, int ems_enable)
            case 3:
                mem_set_mem_state(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
                break;
+            default:
+                break;
        }

    flushmmucache_nopc();
@@ -756,6 +769,8 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
                    case CFG_FEAXS:
                        shadow_recalc(dev);
                        break;
+                    default:
+                        break;
                }
            }
            break;
@@ -767,6 +782,9 @@ scamp_write(uint16_t addr, uint8_t val, void *priv)
                mem_a20_recalc();
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -809,6 +827,9 @@ scamp_read(uint16_t addr, void *priv)
            softresetx86();
            cpu_set_edx();
            break;
+
+        default:
+            break;
    }

    return ret;
@@ -823,10 +844,9 @@ scamp_close(void *priv)
 }

 static void *
-scamp_init(const device_t *info)
+scamp_init(UNUSED(const device_t *info))
 {
    uint32_t addr;
-    int      c;
    scamp_t *dev = (scamp_t *) malloc(sizeof(scamp_t));
    memset(dev, 0x00, sizeof(scamp_t));

@@ -847,7 +867,7 @@ scamp_init(const device_t *info)
    dev->ram_config = 0;

    /* Find best fit configuration for the requested memory size */
-    for (c = 0; c < NR_ELEMS(ram_configs); c++) {
+    for (uint8_t c = 0; c < NR_ELEMS(ram_configs); c++) {
        if (mem_size < ram_configs[c].size_kb)
            break;

@@ -863,7 +883,7 @@ scamp_init(const device_t *info)
    mem_mapping_set_exec(&ram_mid_mapping, ram + 0xf0000);

    addr = 0;
-    for (c = 0; c < 2; c++) {
+    for (uint8_t c = 0; c < 2; c++) {
        dev->ram_struct[c].parent = dev;
        dev->ram_struct[c].bank   = c;
        mem_mapping_add(&dev->ram_mapping[c], 0, 0,
@@ -924,12 +944,15 @@ scamp_init(const device_t *info)
                dev->ibank_shift[c]     = 23;
                dev->ram_interleaved[c] = 1;
                break;
+
+            default:
+                break;
        }
    }

    mem_set_mem_state(0xfe0000, 0x20000, MEM_READ_EXTANY | MEM_WRITE_EXTANY);

-    for (c = 0; c < 20; c++) {
+    for (uint8_t c = 0; c < 20; c++) {
        dev->ems_struct[c].parent  = dev;
        dev->ems_struct[c].segment = c;
        mem_mapping_add(&dev->ems_mappings[c],
--- a/src/chipset/scat.c
+++ b/src/chipset/scat.c
@@ -55,8 +55,9 @@
 #define SCATSX_HIGH_PERFORMANCE_REFRESH 0x63
 #define SCATSX_CAS_TIMING_FOR_DMA       0x64

-typedef struct {
-    uint8_t valid, pad;
+typedef struct ems_page_t {
+    uint8_t valid;
+    uint8_t pad;

    uint8_t regs_2x8;
    uint8_t regs_2x9;
@@ -75,7 +76,8 @@ typedef struct scat_t {

    int external_is_RAS;

-    ems_page_t null_page, page[32];
+    ems_page_t null_page;
+    ems_page_t page[32];

    mem_mapping_t low_mapping[32];
    mem_mapping_t remap_mapping[6];
@@ -931,9 +933,8 @@ static void
 memmap_state_update(scat_t *dev)
 {
    uint32_t addr;
-    int      i;

-    for (i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) {
+    for (uint8_t i = (((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? 0 : 16); i < 44; i++) {
        addr = get_addr(dev, 0x40000 + (i << 14), &dev->null_page);
        mem_mapping_set_exec(&dev->efff_mapping[i],
                             addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
@@ -947,37 +948,40 @@ memmap_state_update(scat_t *dev)
    mem_mapping_set_exec(&dev->low_mapping[1],
                         addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);

-    for (i = 2; i < 32; i++) {
+    for (uint8_t i = 2; i < 32; i++) {
        addr = get_addr(dev, i << 19, &dev->null_page);
        mem_mapping_set_exec(&dev->low_mapping[i],
                             addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
    }

    if ((dev->regs[SCAT_VERSION] & 0xf0) == 0) {
-        for (i = 0; i < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; i++)
-            mem_mapping_enable(&dev->low_mapping[i]);
+        uint8_t j = 0;

-        for (; i < 32; i++)
-            mem_mapping_disable(&dev->low_mapping[i]);
+        for (j = 0; j < max_map[(dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | ((dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40) >> 2)]; j++)
+            mem_mapping_enable(&dev->low_mapping[j]);

-        for (i = 24; i < 36; i++) {
+        for (; j < 32; j++)
+            mem_mapping_disable(&dev->low_mapping[j]);
+
+        for (j = 24; j < 36; j++) {
            if (((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) | (dev->regs[SCAT_EXTENDED_BOUNDARY] & 0x40)) < 4)
-                mem_mapping_disable(&dev->efff_mapping[i]);
+                mem_mapping_disable(&dev->efff_mapping[j]);
            else
-                mem_mapping_enable(&dev->efff_mapping[i]);
+                mem_mapping_enable(&dev->efff_mapping[j]);
        }
    } else {
-        for (i = 0; i < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; i++)
-            mem_mapping_enable(&dev->low_mapping[i]);
+        uint8_t j = 0;
+        for (j = 0; j < max_map_sx[dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f]; j++)
+            mem_mapping_enable(&dev->low_mapping[j]);

-        for (; i < 32; i++)
-            mem_mapping_disable(&dev->low_mapping[i]);
+        for (; j < 32; j++)
+            mem_mapping_disable(&dev->low_mapping[j]);

-        for (i = 24; i < 36; i++) {
+        for (j = 24; j < 36; j++) {
            if ((dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) < 2 || (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)
-                mem_mapping_disable(&dev->efff_mapping[i]);
+                mem_mapping_disable(&dev->efff_mapping[j]);
            else
-                mem_mapping_enable(&dev->efff_mapping[i]);
+                mem_mapping_enable(&dev->efff_mapping[j]);
        }
    }

@@ -985,21 +989,21 @@ memmap_state_update(scat_t *dev)
        if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) == 3) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) == 3)) {
            mem_mapping_disable(&dev->low_mapping[2]);

-            for (i = 0; i < 6; i++) {
+            for (uint8_t i = 0; i < 6; i++) {
                addr = get_addr(dev, 0x100000 + (i << 16), &dev->null_page);
                mem_mapping_set_exec(&dev->remap_mapping[i],
                                     addr < ((uint32_t) mem_size << 10) ? ram + addr : NULL);
                mem_mapping_enable(&dev->remap_mapping[i]);
            }
        } else {
-            for (i = 0; i < 6; i++)
+            for (uint8_t i = 0; i < 6; i++)
                mem_mapping_disable(&dev->remap_mapping[i]);

            if ((((dev->regs[SCAT_VERSION] & 0xf0) == 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x0f) > 4) || (((dev->regs[SCAT_VERSION] & 0xf0) != 0) && (dev->regs[SCAT_DRAM_CONFIGURATION] & 0x1f) > 3))
                mem_mapping_enable(&dev->low_mapping[2]);
        }
    } else {
-        for (i = 0; i < 6; i++)
+        for (uint8_t i = 0; i < 6; i++)
            mem_mapping_disable(&dev->remap_mapping[i]);

        mem_mapping_enable(&dev->low_mapping[2]);
@@ -1191,6 +1195,9 @@ scat_out(uint16_t port, uint8_t val, void *priv)
            if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
                dev->reg_2xA = ((dev->regs[SCAT_VERSION] & 0xf0) == 0) ? val : val & 0xc3;
            break;
+
+        default:
+            break;
    }
 }

@@ -1258,6 +1265,8 @@ scat_in(uint16_t port, void *priv)
            if ((dev->regs[SCAT_EMS_CONTROL] & 0x41) == (0x40 | ((port & 0x10) >> 4)))
                ret = dev->reg_2xA;
            break;
+        default:
+            break;
    }

    return ret;
@@ -1374,7 +1383,7 @@ static void *
 scat_init(const device_t *info)
 {
    scat_t  *dev;
-    uint32_t i;
+    uint32_t j;
    uint32_t k;
    int      sx;

@@ -1384,7 +1393,7 @@ scat_init(const device_t *info)

    sx = (dev->type == 32) ? 1 : 0;

-    for (i = 0; i < sizeof(dev->regs); i++)
+    for (uint32_t i = 0; i < sizeof(dev->regs); i++)
        dev->regs[i] = 0xff;

    if (sx) {
@@ -1445,7 +1454,7 @@ scat_init(const device_t *info)
                    mem_write_scatb, mem_write_scatw, mem_write_scatl,
                    ram + 0xf0000, MEM_MAPPING_INTERNAL, &dev->null_page);

-    for (i = 2; i < 32; i++) {
+    for (uint8_t i = 2; i < 32; i++) {
        mem_mapping_add(&dev->low_mapping[i], (i << 19), 0x80000,
                        mem_read_scatb, mem_read_scatw, mem_read_scatl,
                        mem_write_scatb, mem_write_scatw, mem_write_scatl,
@@ -1453,27 +1462,27 @@ scat_init(const device_t *info)
    }

    if (sx) {
-        i = 16;
+        j = 16;
        k = 0x40000;
    } else {
-        i = 0;
+        j = 0;
        k = (dev->regs[SCAT_VERSION] < 4) ? 0x40000 : 0x60000;
    }
    mem_mapping_set_addr(&dev->low_mapping[31], 0xf80000, k);

-    for (; i < 44; i++) {
-        mem_mapping_add(&dev->efff_mapping[i], 0x40000 + (i << 14), 0x4000,
+    for (; j < 44; j++) {
+        mem_mapping_add(&dev->efff_mapping[j], 0x40000 + (j << 14), 0x4000,
                        mem_read_scatb, mem_read_scatw, mem_read_scatl,
                        mem_write_scatb, mem_write_scatw, mem_write_scatl,
-                        mem_size > (256 + (i << 4)) ? ram + 0x40000 + (i << 14) : NULL,
+                        mem_size > (256 + (j << 4)) ? ram + 0x40000 + (j << 14) : NULL,
                        MEM_MAPPING_INTERNAL, &dev->null_page);

        if (sx)
-            mem_mapping_enable(&dev->efff_mapping[i]);
+            mem_mapping_enable(&dev->efff_mapping[j]);
    }

    if (sx) {
-        for (i = 24; i < 32; i++) {
+        for (uint8_t i = 24; i < 32; i++) {
            dev->page[i].valid    = 1;
            dev->page[i].regs_2x8 = 0xff;
            dev->page[i].regs_2x9 = 0x03;
@@ -1485,7 +1494,7 @@ scat_init(const device_t *info)
            mem_mapping_disable(&dev->ems_mapping[i]);
        }
    } else {
-        for (i = 0; i < 32; i++) {
+        for (uint8_t i = 0; i < 32; i++) {
            dev->page[i].valid    = 1;
            dev->page[i].regs_2x8 = 0xff;
            dev->page[i].regs_2x9 = 0x03;
@@ -1498,7 +1507,7 @@ scat_init(const device_t *info)
        }
    }

-    for (i = 0; i < 6; i++) {
+    for (uint8_t i = 0; i < 6; i++) {
        mem_mapping_add(&dev->remap_mapping[i], 0x100000 + (i << 16), 0x10000,
                        mem_read_scatb, mem_read_scatw, mem_read_scatl,
                        mem_write_scatb, mem_write_scatw, mem_write_scatl,
--- a/src/chipset/sis_5511.c
+++ b/src/chipset/sis_5511.c
@@ -32,6 +32,7 @@
 #include <86box/hdc_ide.h>
 #include <86box/hdc_ide_sff8038i.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/smram.h>

@@ -65,10 +66,13 @@ sis_5511_log(const char *fmt, ...)
 #endif

 typedef struct sis_5511_t {
-    uint8_t pci_conf[256], pci_conf_sb[2][256],
-        index, regs[16];
+    uint8_t pci_conf[256];
+    uint8_t pci_conf_sb[2][256];
+    uint8_t index;
+    uint8_t regs[16];

-    int nb_pci_slot, sb_pci_slot;
+    int nb_pci_slot;
+    int sb_pci_slot;

    sff8038i_t *ide_drive[2];
    smram_t    *smram;
@@ -121,6 +125,9 @@ sis_5511_smram_recalc(sis_5511_t *dev)
        case 2:
            smram_enable(dev->smram, 0x000e0000, 0x000b0000, 0x8000, dev->pci_conf[0x65] & 0x10, 1);
            break;
+
+        default:
+            break;
    }

    flushmmucache();
@@ -153,7 +160,7 @@ sis_5513_bm_handler(sis_5511_t *dev)
 }

 static void
-sis_5511_write(int func, int addr, uint8_t val, void *priv)
+sis_5511_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    sis_5511_t *dev = (sis_5511_t *) priv;

@@ -331,12 +338,15 @@ sis_5511_write(int func, int addr, uint8_t val, void *priv)
        case 0x93: /* 5512 General Purpose Register Index */
            dev->pci_conf[addr] = val;
            break;
+
+        default:
+            break;
    }
    sis_5511_log("SiS 5511: dev->pci_conf[%02x] = %02x POST: %02x\n", addr, dev->pci_conf[addr], inb(0x80));
 }

 static uint8_t
-sis_5511_read(int func, int addr, void *priv)
+sis_5511_read(UNUSED(int func), int addr, void *priv)
 {
    sis_5511_t *dev = (sis_5511_t *) priv;
    sis_5511_log("SiS 5511: dev->pci_conf[%02x] (%02x) POST %02x\n", addr, dev->pci_conf[addr], inb(0x80));
@@ -428,6 +438,9 @@ sis_5513_pci_to_isa_write(int addr, uint8_t val, sis_5511_t *dev)
        case 0x6a: /* GPIO Status Register */
            dev->pci_conf_sb[0][addr] &= val & 0x15;
            break;
+
+        default:
+            break;
    }
 }

@@ -514,6 +527,9 @@ sis_5513_ide_write(int addr, uint8_t val, sis_5511_t *dev)
        case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
            dev->pci_conf_sb[1][addr] = val;
            break;
+
+        default:
+            break;
    }
 }

@@ -528,6 +544,9 @@ sis_5513_write(int func, int addr, uint8_t val, void *priv)
        case 1:
            sis_5513_ide_write(addr, val, dev);
            break;
+
+        default:
+            break;
    }
    sis_5511_log("SiS 5513: dev->pci_conf[%02x][%02x] = %02x POST: %02x\n", func, addr, dev->pci_conf_sb[func][addr], inb(0x80));
 }
@@ -567,6 +586,9 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
                        case 2:
                            cpu_set_isa_pci_div(3);
                            break;
+
+                        default:
+                            break;
                    }
                    break;
                case 0x01:
@@ -587,9 +609,15 @@ sis_5513_isa_write(uint16_t addr, uint8_t val, void *priv)
                case 0x0b:
                    dev->regs[dev->index] = val;
                    break;
+
+                default:
+                    break;
            }
            sis_5511_log("SiS 5513-ISA: dev->regs[%02x] = %02x POST: %02x\n", dev->index + 0x50, dev->regs[dev->index], inb(0x80));
            break;
+
+        default:
+            break;
    }
 }

@@ -700,7 +728,7 @@ sis_5511_close(void *priv)
 }

 static void *
-sis_5511_init(const device_t *info)
+sis_5511_init(UNUSED(const device_t *info))
 {
    sis_5511_t *dev = (sis_5511_t *) malloc(sizeof(sis_5511_t));
    memset(dev, 0, sizeof(sis_5511_t));
--- a/src/chipset/sis_5571.c
+++ b/src/chipset/sis_5571.c
@@ -30,6 +30,7 @@
 #include <86box/mem.h>
 #include <86box/pci.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc_ide.h>
 #include <86box/hdc_ide_sff8038i.h>
@@ -74,9 +75,11 @@ sis_5571_log(const char *fmt, ...)
 #endif

 typedef struct sis_5571_t {
-    uint8_t pci_conf[256], pci_conf_sb[3][256];
+    uint8_t pci_conf[256];
+    uint8_t pci_conf_sb[3][256];

-    int nb_pci_slot, sb_pci_slot;
+    int nb_pci_slot;
+    int sb_pci_slot;

    port_92_t  *port_92;
    sff8038i_t *ide_drive[2];
@@ -117,6 +120,9 @@ sis_5571_smm_recalc(sis_5571_t *dev)
        case 0x03:
            smram_enable(dev->smram, 0xa0000, 0xa0000, 0x10000, (dev->pci_conf[0xa3] & 0x10), 1);
            break;
+
+        default:
+            break;
    }

    flushmmucache();
@@ -149,7 +155,7 @@ sis_5571_bm_handler(sis_5571_t *dev)
 }

 static void
-memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
+memory_pci_bridge_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    sis_5571_t *dev = (sis_5571_t *) priv;

@@ -324,12 +330,15 @@ memory_pci_bridge_write(int func, int addr, uint8_t val, void *priv)
            dev->pci_conf[addr] = val & 0xd0;
            sis_5571_smm_recalc(dev);
            break;
+
+        default:
+            break;
    }
    sis_5571_log("SiS5571: dev->pci_conf[%02x] = %02x\n", addr, val);
 }

 static uint8_t
-memory_pci_bridge_read(int func, int addr, void *priv)
+memory_pci_bridge_read(UNUSED(int func), int addr, void *priv)
 {
    sis_5571_t *dev = (sis_5571_t *) priv;
    sis_5571_log("SiS5571: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf[addr]);
@@ -375,6 +384,9 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
                        case 2:
                            cpu_set_isa_pci_div(3);
                            break;
+
+                        default:
+                            break;
                    }
                    break;

@@ -498,6 +510,9 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
                case 0x77: /* Monitor Standby Timer Reload And Monitor Standby State ExitControl */
                    dev->pci_conf_sb[0][addr] = val;
                    break;
+
+                default:
+                    break;
            }
            sis_5571_log("SiS5571-SB: dev->pci_conf[%02x] = %02x\n", addr, val);
            break;
@@ -577,6 +592,9 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
                case 0x4f: /* Prefetch Count of Secondary Channel (High Byte) */
                    dev->pci_conf_sb[1][addr] = val;
                    break;
+
+                default:
+                    break;
            }
            sis_5571_log("SiS5571-IDE: dev->pci_conf[%02x] = %02x\n", addr, val);
            break;
@@ -615,8 +633,14 @@ pci_isa_bridge_write(int func, int addr, uint8_t val, void *priv)
                case 0x3c: /* Interrupt Line */
                    dev->pci_conf_sb[2][addr] = val;
                    break;
+
+                default:
+                    break;
            }
            sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] = %02x\n", addr, val);
+
+        default:
+            break;
    }
 }

@@ -635,6 +659,7 @@ pci_isa_bridge_read(int func, int addr, void *priv)
        case 2:
            sis_5571_log("SiS5571-USB: dev->pci_conf[%02x] (%02x)\n", addr, dev->pci_conf_sb[2][addr]);
            return dev->pci_conf_sb[2][addr];
+
        default:
            return 0xff;
    }
@@ -654,6 +679,7 @@ sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
            case 0x08:
            case 0x0d:
                break;
+
            default:
                if (usb->irq_level)
                    picint(1 << dev->pci_conf_sb[0][0x68] & 0x0f);
@@ -670,7 +696,7 @@ sis_5571_usb_update_interrupt(usb_t* usb, void* priv)
 }

 static uint8_t
-sis_5571_usb_handle_smi(usb_t* usb, void* priv)
+sis_5571_usb_handle_smi(UNUSED(usb_t* usb), UNUSED(void* priv))
 {
    /* Left unimplemented for now. */
    return 1;
@@ -740,7 +766,7 @@ sis_5571_close(void *priv)
 }

 static void *
-sis_5571_init(const device_t *info)
+sis_5571_init(UNUSED(const device_t *info))
 {
    sis_5571_t *dev = (sis_5571_t *) malloc(sizeof(sis_5571_t));
    memset(dev, 0x00, sizeof(sis_5571_t));
--- a/src/chipset/sis_85c310.c
+++ b/src/chipset/sis_85c310.c
@@ -10,12 +10,13 @@
 #include <86box/io.h>
 #include <86box/device.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t cur_reg, tries,
-        regs[258];
+typedef struct rabbit_t {
+    uint8_t cur_reg;
+    uint8_t tries;
+    uint8_t regs[258];
 } rabbit_t;

 static void
@@ -64,6 +65,8 @@ rabbit_recalcmapping(rabbit_t *dev)
            /* 128K at 0E0000-0FFFFF */
            mem_set_mem_state(0x000e0000, 0x00020000, shflags);
            break;
+        default:
+            break;
    }

    flushmmucache();
@@ -89,6 +92,8 @@ rabbit_write(uint16_t addr, uint8_t val, void *priv)
            } else
                dev->regs[dev->cur_reg] = val;
            break;
+        default:
+            break;
    }
 }

@@ -106,6 +111,9 @@ rabbit_read(uint16_t addr, void *priv)
            } else
                ret = dev->regs[dev->cur_reg];
            break;
+
+        default:
+            break;
    }

    return ret;
@@ -120,7 +128,7 @@ rabbit_close(void *priv)
 }

 static void *
-rabbit_init(const device_t *info)
+rabbit_init(UNUSED(const device_t *info))
 {
    rabbit_t *dev = (rabbit_t *) malloc(sizeof(rabbit_t));
    memset(dev, 0, sizeof(rabbit_t));
--- a/src/chipset/sis_85c496.c
+++ b/src/chipset/sis_85c496.c
@@ -32,6 +32,7 @@
 #include <86box/dma.h>
 #include <86box/nvr.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc_ide.h>
 #include <86box/machine.h>
@@ -39,9 +40,10 @@
 #include <86box/spd.h>

 typedef struct sis_85c496_t {
-    uint8_t cur_reg, rmsmiblk_count,
-        regs[127],
-        pci_conf[256];
+    uint8_t    cur_reg;
+    uint8_t    rmsmiblk_count;
+    uint8_t    regs[127];
+    uint8_t    pci_conf[256];
    smram_t   *smram;
    pc_timer_t rmsmiblk_timer;
    port_92_t *port_92;
@@ -98,6 +100,8 @@ sis_85c497_isa_write(uint16_t port, uint8_t val, void *priv)
                dev->regs[dev->cur_reg] = val & 0xfc;
                dma_set_mask((val & 0x80) ? 0xffffffff : 0x00ffffff);
                break;
+            default:
+                break;
        }
 }

@@ -182,7 +186,7 @@ sis_85c496_ide_handler(sis_85c496_t *dev)

 /* 00 - 3F = PCI Configuration, 40 - 7F = 85C496, 80 - FF = 85C497 */
 static void
-sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
+sis_85c49x_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    sis_85c496_t *dev = (sis_85c496_t *) priv;
    uint8_t       old;
@@ -255,7 +259,9 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
        case 0x4d:
        case 0x4e:
        case 0x4f:
-            // dev->pci_conf[addr] = val;
+#if 0
+            dev->pci_conf[addr] = val;
+#endif
            spd_write_drbs(dev->pci_conf, 0x48, 0x4f, 1);
            break;
        case 0x50:
@@ -321,6 +327,8 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
                            host_base = 0x000e0000;
                            ram_base  = 0x000b0000;
                            break;
+                        default:
+                            break;
                    }

                    smram_enable(dev->smram, host_base, ram_base, size,
@@ -459,11 +467,14 @@ sis_85c49x_pci_write(int func, int addr, uint8_t val, void *priv)
            dev->pci_conf[addr] = val & 0x6e;
            nvr_bank_set(0, !!(val & 0x40), dev->nvr);
            break;
+
+        default:
+            break;
    }
 }

 static uint8_t
-sis_85c49x_pci_read(int func, int addr, void *priv)
+sis_85c49x_pci_read(UNUSED(int func), int addr, void *priv)
 {
    sis_85c496_t *dev = (sis_85c496_t *) priv;
    uint8_t       ret = dev->pci_conf[addr];
@@ -481,6 +492,9 @@ sis_85c49x_pci_read(int func, int addr, void *priv)
        case 0x83: /*Port 70h Mirror*/
            ret = inb(0x70);
            break;
+
+        default:
+            break;
    }

    sis_85c496_log("[%04X:%08X] PCI Read  %02X from %02X:%02X\n", CS, cpu_state.pc, ret, func, addr);
@@ -607,7 +621,9 @@ static void

    pci_add_card(PCI_ADD_NORTHBRIDGE, sis_85c49x_pci_read, sis_85c49x_pci_write, dev);

-    // sis_85c497_isa_reset(dev);
+#if 0
+    sis_85c497_isa_reset(dev);
+#endif

    dev->port_92 = device_add(&port_92_device);
    port_92_set_period(dev->port_92, 2ULL * TIMER_USEC);
--- a/src/chipset/sis_85c4xx.c
+++ b/src/chipset/sis_85c4xx.c
@@ -28,6 +28,7 @@
 #include <86box/timer.h>
 #include <86box/io.h>
 #include <86box/device.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/mem.h>
 #include <86box/smram.h>
@@ -35,14 +36,19 @@
 #include <86box/machine.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t cur_reg, tries,
-        reg_base, reg_last,
-        reg_00, is_471,
-        force_flush, shadowed,
-        smram_enabled, pad,
-        regs[39], scratch[2];
+typedef struct sis_85c4xx_t {
+    uint8_t    cur_reg;
+    uint8_t    tries;
+    uint8_t    reg_base;
+    uint8_t    reg_last;
+    uint8_t    reg_00;
+    uint8_t    is_471;
+    uint8_t    force_flush;
+    uint8_t    shadowed;
+    uint8_t    smram_enabled;
+    uint8_t    pad;
+    uint8_t    regs[39];
+    uint8_t    scratch[2];
    uint32_t   mem_state[8];
    smram_t   *smram;
    port_92_t *port_92;
@@ -124,7 +130,7 @@ sis_85c4xx_recalcmapping(sis_85c4xx_t *dev)
 }

 static void
-sis_85c4xx_sw_smi_out(uint16_t port, uint8_t val, void *priv)
+sis_85c4xx_sw_smi_out(UNUSED(uint16_t port), UNUSED(uint8_t val), void *priv)
 {
    sis_85c4xx_t *dev = (sis_85c4xx_t *) priv;

@@ -235,6 +241,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
                                port_92_add(dev->port_92);
                        }
                        break;
+                    default:
+                        break;
                }
            } else if ((dev->reg_base == 0x60) && (dev->cur_reg == 0x00))
                dev->reg_00 = val;
@@ -245,6 +253,8 @@ sis_85c4xx_out(uint16_t port, uint8_t val, void *priv)
        case 0xe2:
            dev->scratch[port - 0xe1] = val;
            return;
+        default:
+            break;
    }
 }

@@ -273,6 +283,10 @@ sis_85c4xx_in(uint16_t port, void *priv)
        case 0xe1:
        case 0xe2:
            ret = dev->scratch[port - 0xe1];
+            break;
+
+        default:
+            break;
    }

    return ret;
--- a/src/chipset/sis_85c50x.c
+++ b/src/chipset/sis_85c50x.c
@@ -31,6 +31,7 @@
 #include <86box/apm.h>
 #include <86box/machine.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/mem.h>
 #include <86box/smram.h>
 #include <86box/pci.h>
@@ -57,9 +58,10 @@ sis_85c50x_log(const char *fmt, ...)
 #endif

 typedef struct sis_85c50x_t {
-    uint8_t index,
-        pci_conf[256], pci_conf_sb[256],
-        regs[256];
+    uint8_t index;
+    uint8_t pci_conf[256];
+    uint8_t pci_conf_sb[256];
+    uint8_t regs[256];

    smram_t   *smram[2];
    port_92_t *port_92;
@@ -133,6 +135,8 @@ sis_85c50x_smm_recalc(sis_85c50x_t *dev)
            smram_enable(dev->smram[0], host_base, 0xb0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
            smram_enable(dev->smram[1], host_base ^ 0x00100000, 0xa0000, 0x8000, (dev->pci_conf[0x65] & 0x10), 1);
            break;
+        default:
+            break;
    }
 }

@@ -213,7 +217,10 @@ sis_85c50x_write(int func, int addr, uint8_t val, void *priv)
                dev->pci_conf[addr] = (val & 0x7f);
                break;
            case 0x69:
-                dev->pci_conf[addr] &= ~(val);
+                dev->pci_conf[addr] &= ~val;
+                break;
+
+            default:
                break;
        }
 }
@@ -267,6 +274,9 @@ sis_85c50x_sb_write(int func, int addr, uint8_t val, void *priv)
            case 0x4b: /* ISA Master/DMA Memory Cycle Control Register 4 */
                dev->pci_conf_sb[addr] = val;
                break;
+
+            default:
+                break;
        }
 }

@@ -314,8 +324,14 @@ sis_85c50x_isa_write(uint16_t addr, uint8_t val, void *priv)
                case 0x85:
                    outb(0x70, val);
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -336,6 +352,9 @@ sis_85c50x_isa_read(uint16_t addr, void *priv)
            else
                ret = dev->regs[dev->index];
            break;
+
+        default:
+            break;
    }

    sis_85c50x_log("85C503 ISA: [R] (%04X) = %02X\n", addr, ret);
@@ -401,7 +420,7 @@ sis_85c50x_close(void *priv)
 }

 static void *
-sis_85c50x_init(const device_t *info)
+sis_85c50x_init(UNUSED(const device_t *info))
 {
    sis_85c50x_t *dev = (sis_85c50x_t *) malloc(sizeof(sis_85c50x_t));
    memset(dev, 0x00, sizeof(sis_85c50x_t));
--- a/src/chipset/stpc.c
+++ b/src/chipset/stpc.c
@@ -30,6 +30,7 @@
 #include <86box/timer.h>
 #include <86box/pit.h>
 #include <86box/device.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/usb.h>
 #include <86box/hdc_ide.h>
@@ -248,6 +249,9 @@ stpc_nb_write(int func, int addr, uint8_t val, void *priv)
        case 0x52:
            val &= 0x70;
            break;
+
+        default:
+            break;
    }

    dev->pci_conf[0][addr] = val;
@@ -432,6 +436,9 @@ stpc_ide_write(int func, int addr, uint8_t val, void *priv)
                sff_bus_master_set_irq(0x00, dev->bm[1]);
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -489,6 +496,9 @@ stpc_isab_write(int func, int addr, uint8_t val, void *priv)
        case 0x05:
            val &= 0x01;
            break;
+
+        default:
+            break;
    }

    dev->pci_conf[1][addr] = val;
@@ -551,6 +561,8 @@ stpc_usb_write(int func, int addr, uint8_t val, void *priv)
            dev->pci_conf[3][addr] = val;
            ohci_update_mem_mapping(dev->usb, dev->pci_conf[3][0x11], dev->pci_conf[3][0x12], dev->pci_conf[3][0x13], 1);
            break;
+        default:
+            break;
    }

    dev->pci_conf[3][addr] = val;
@@ -720,6 +732,9 @@ stpc_reg_write(uint16_t addr, uint8_t val, void *priv)
                val &= 0xf1;
                stpc_serial_handlers(val);
                break;
+
+            default:
+                break;
        }

        dev->regs[dev->reg_offset] = val;
@@ -957,7 +972,7 @@ stpc_serial_close(void *priv)
 }

 static void *
-stpc_serial_init(const device_t *info)
+stpc_serial_init(UNUSED(const device_t *info))
 {
    stpc_log("STPC: serial_init()\n");

@@ -990,6 +1005,8 @@ stpc_lpt_handlers(stpc_lpt_t *dev, uint8_t val)
        case 0x3:
            lpt2_remove();
            break;
+        default:
+            break;
    }

    switch (new_addr) {
@@ -1068,7 +1085,7 @@ stpc_lpt_close(void *priv)
 }

 static void *
-stpc_lpt_init(const device_t *info)
+stpc_lpt_init(UNUSED(const device_t *info))
 {
    stpc_log("STPC: lpt_init()\n");

--- a/src/chipset/umc_8886.c
+++ b/src/chipset/umc_8886.c
@@ -121,10 +121,10 @@ umc_8886_log(const char *fmt, ...)
 #define SB_ID dev->sb_id

 typedef struct umc_8886_t {
-    uint8_t max_func,        /* Last function number */
-        pci_conf_sb[2][256]; /* PCI Registers */
-    uint16_t sb_id;          /* Southbridge Revision */
-    int      has_ide;        /* Check if Southbridge Revision is AF or F */
+    uint8_t max_func;            /* Last function number */
+    uint8_t pci_conf_sb[2][256]; /* PCI Registers */
+    uint16_t sb_id;              /* Southbridge Revision */
+    int      has_ide;            /* Check if Southbridge Revision is AF or F */
 } umc_8886_t;

 static void
@@ -212,6 +212,8 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
                            case 2:
                                cpu_set_isa_pci_div(2);
                                break;
+                            default:
+                                break;
                        }

                        break;
@@ -250,6 +252,9 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
                    case 0xa5 ... 0xa8:
                        dev->pci_conf_sb[func][addr] = val;
                        break;
+
+                    default:
+                        break;
                }
                break;

@@ -271,8 +276,13 @@ umc_8886_write(int func, int addr, uint8_t val, void *priv)
                    case 0x41:
                        dev->pci_conf_sb[func][addr] = val;
                        break;
+
+                    default:
+                        break;
                }
                break;
+            default:
+                break;
        }
 }

@@ -339,7 +349,7 @@ umc_8886_reset(void *priv)
        umc_8886_ide_handler(1);
    }

-    for (int i = 1; i < 5; i++) /* Disable all IRQ interrupts */
+    for (uint8_t i = 1; i < 5; i++) /* Disable all IRQ interrupts */
        pci_set_irq_routing(i, PCI_IRQ_DISABLED);

    cpu_set_isa_pci_div(3);
--- a/src/chipset/umc_hb4.c
+++ b/src/chipset/umc_hb4.c
@@ -106,6 +106,7 @@

 #include <86box/mem.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/smram.h>

@@ -142,9 +143,10 @@ hb4_log(const char *fmt, ...)
 #endif

 typedef struct hb4_t {
-    uint8_t shadow,
-        shadow_read, shadow_write,
-        pci_conf[256]; /* PCI Registers */
+    uint8_t  shadow;
+    uint8_t  shadow_read;
+    uint8_t  shadow_write;
+    uint8_t  pci_conf[256]; /* PCI Registers */
    int      mem_state[9];
    smram_t *smram[3]; /* SMRAM Handlers */
 } hb4_t;
@@ -261,7 +263,7 @@ hb4_smram(hb4_t *dev)
 }

 static void
-hb4_write(int func, int addr, uint8_t val, void *priv)
+hb4_write(UNUSED(int func), int addr, uint8_t val, void *priv)
 {
    hb4_t *dev = (hb4_t *) priv;

@@ -322,6 +324,9 @@ hb4_write(int func, int addr, uint8_t val, void *priv)
        case 0x61:
            dev->pci_conf[addr] = val;
            break;
+
+        default:
+            break;
    }
 }

@@ -383,7 +388,7 @@ hb4_close(void *priv)
 }

 static void *
-hb4_init(const device_t *info)
+hb4_init(UNUSED(const device_t *info))
 {
    hb4_t *dev = (hb4_t *) malloc(sizeof(hb4_t));
    memset(dev, 0, sizeof(hb4_t));
--- a/src/chipset/via_apollo.c
+++ b/src/chipset/via_apollo.c
@@ -69,6 +69,8 @@ apollo_map(uint32_t addr, uint32_t size, int state)
        case 3:
            mem_set_mem_state_both(addr, size, MEM_READ_INTERNAL | MEM_WRITE_INTERNAL);
            break;
+        default:
+            break;
    }

    flushmmucache_nopc();
@@ -392,8 +394,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
            smram_disable_all();
            if (dev->id >= VIA_691)
                switch (val & 0x03) {
-                    case 0x00:
                    default:
+                    case 0x00:
                        apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 1); /* SMM: Code DRAM, Data DRAM */
                        apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0); /* Non-SMM: Code PCI, Data PCI */
                        break;
@@ -412,8 +414,8 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
                }
            else if (dev->id >= VIA_597)
                switch (val & 0x03) {
-                    case 0x00:
                    default:
+                    case 0x00:
                        /* Disable SMI Address Redirection (default) */
                        apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 0);
                        apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 0);
@@ -458,6 +460,9 @@ via_apollo_host_bridge_write(int func, int addr, uint8_t val, void *priv)
                        apollo_smram_map(dev, 1, 0x000a0000, 0x00020000, 3);
                        apollo_smram_map(dev, 0, 0x000a0000, 0x00020000, 3);
                        break;
+
+                    default:
+                        break;
                }
            break;
        case 0x65:
@@ -673,6 +678,8 @@ via_apollo_read(int func, int addr, void *priv)
        case 0:
            ret = dev->pci_conf[addr];
            break;
+        default:
+            break;
    }

    return ret;
@@ -685,6 +692,8 @@ via_apollo_write(int func, int addr, uint8_t val, void *priv)
        case 0:
            via_apollo_host_bridge_write(func, addr, val, priv);
            break;
+        default:
+            break;
    }
 }

@@ -728,6 +737,9 @@ via_apollo_init(const device_t *info)
        case VIA_694:
            device_add(&via_mvp3_agp_device);
            break;
+
+        default:
+            break;
    }

    if (dev->id >= VIA_597)
--- a/src/chipset/via_pipc.c
+++ b/src/chipset/via_pipc.c
@@ -41,6 +41,7 @@
 #include <86box/ddma.h>
 #include <86box/pci.h>
 #include <86box/pic.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/hdc.h>
 #include <86box/hdc_ide.h>
@@ -109,22 +110,28 @@ enum {
 typedef struct {
    struct _pipc_ *dev;
    void          *trap;
-    uint32_t      *sts_reg, *en_reg, mask;
+    uint32_t      *sts_reg;
+    uint32_t      *en_reg;
+    uint32_t       mask;
 } pipc_io_trap_t;

 typedef struct _pipc_ {
    uint32_t local;
-    uint8_t  max_func, max_pcs;
+    uint8_t  max_func;
+    uint8_t  max_pcs;

-    uint8_t pci_isa_regs[256],
-        ide_regs[256],
-        usb_regs[2][256],
-        power_regs[256],
-        ac97_regs[2][256], fmnmi_regs[4], fmnmi_status;
+    uint8_t pci_isa_regs[256];
+    uint8_t ide_regs[256];
+    uint8_t usb_regs[2][256];
+    uint8_t power_regs[256];
+    uint8_t ac97_regs[2][256];
+    uint8_t fmnmi_regs[4];
+    uint8_t fmnmi_status;

    sff8038i_t    *bm[2];
    nvr_t         *nvr;
-    int            nvr_enabled, slot;
+    int            nvr_enabled;
+    int            slot;
    ddma_t        *ddma;
    smbus_piix4_t *smbus;
    usb_t         *usb[2];
@@ -132,9 +139,14 @@ typedef struct _pipc_ {
    acpi_t        *acpi;
    pipc_io_trap_t io_traps[TRAP_MAX];

-    void    *gameport, *ac97, *sio, *hwm;
+    void    *gameport;
+    void    *ac97;
+    void    *sio;
+    void    *hwm;
    sb_t    *sb;
-    uint16_t midigame_base, sb_base, fmnmi_base;
+    uint16_t midigame_base;
+    uint16_t sb_base;
+    uint16_t fmnmi_base;
 } pipc_t;

 #ifdef ENABLE_PIPC_LOG
@@ -162,7 +174,7 @@ static uint8_t pipc_read(int func, int addr, void *priv);
 static void    pipc_write(int func, int addr, uint8_t val, void *priv);

 static void
-pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
+pipc_io_trap_pact(UNUSED(int size), UNUSED(uint16_t addr), UNUSED(uint8_t write), UNUSED(uint8_t val), void *priv)
 {
    pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;

@@ -175,7 +187,7 @@ pipc_io_trap_pact(int size, uint16_t addr, uint8_t write, uint8_t val, void *pri
 }

 static void
-pipc_io_trap_glb(int size, uint16_t addr, uint8_t write, uint8_t val, void *priv)
+pipc_io_trap_glb(UNUSED(int size), UNUSED(uint16_t addr), uint8_t write, UNUSED(uint8_t val), void *priv)
 {
    pipc_io_trap_t *trap = (pipc_io_trap_t *) priv;

@@ -332,6 +344,8 @@ pipc_reset_hard(void *priv)
            case VIA_PIPC_8231:
                dev->usb_regs[i][0x08] = 0x1e;
                break;
+            default:
+                break;
        }

        dev->usb_regs[i][0x0a] = 0x03;
@@ -392,6 +406,9 @@ pipc_reset_hard(void *priv)
            case VIA_PIPC_686B:
                dev->power_regs[0x08] = 0x40;
                break;
+
+            default:
+                break;
        }
        if (dev->local == VIA_PIPC_686B)
            dev->power_regs[0x34] = 0x68;
@@ -453,6 +470,9 @@ pipc_reset_hard(void *priv)
                case VIA_PIPC_8231:
                    dev->ac97_regs[i][0x08] = (i == 0) ? 0x40 : 0x20;
                    break;
+
+                default:
+                    break;
            }

            if (i == 0) {
@@ -1567,36 +1587,36 @@ pipc_write(int func, int addr, uint8_t val, void *priv)
 }

 static void
-pipc_reset(void *p)
+pipc_reset(void *priv)
 {
-    pipc_t *dev     = (pipc_t *) p;
+    pipc_t *dev     = (pipc_t *) priv;
    uint8_t pm_func = dev->usb[1] ? 4 : 3;

-    pipc_write(pm_func, 0x41, 0x00, p);
-    pipc_write(pm_func, 0x48, 0x01, p);
-    pipc_write(pm_func, 0x49, 0x00, p);
+    pipc_write(pm_func, 0x41, 0x00, priv);
+    pipc_write(pm_func, 0x48, 0x01, priv);
+    pipc_write(pm_func, 0x49, 0x00, priv);

-    pipc_write(1, 0x04, 0x80, p);
-    pipc_write(1, 0x09, 0x85, p);
-    pipc_write(1, 0x10, 0xf1, p);
-    pipc_write(1, 0x11, 0x01, p);
-    pipc_write(1, 0x14, 0xf5, p);
-    pipc_write(1, 0x15, 0x03, p);
-    pipc_write(1, 0x18, 0x71, p);
-    pipc_write(1, 0x19, 0x01, p);
-    pipc_write(1, 0x1c, 0x75, p);
-    pipc_write(1, 0x1d, 0x03, p);
-    pipc_write(1, 0x20, 0x01, p);
-    pipc_write(1, 0x21, 0xcc, p);
+    pipc_write(1, 0x04, 0x80, priv);
+    pipc_write(1, 0x09, 0x85, priv);
+    pipc_write(1, 0x10, 0xf1, priv);
+    pipc_write(1, 0x11, 0x01, priv);
+    pipc_write(1, 0x14, 0xf5, priv);
+    pipc_write(1, 0x15, 0x03, priv);
+    pipc_write(1, 0x18, 0x71, priv);
+    pipc_write(1, 0x19, 0x01, priv);
+    pipc_write(1, 0x1c, 0x75, priv);
+    pipc_write(1, 0x1d, 0x03, priv);
+    pipc_write(1, 0x20, 0x01, priv);
+    pipc_write(1, 0x21, 0xcc, priv);
    if (dev->local <= VIA_PIPC_586B)
-        pipc_write(1, 0x40, 0x04, p);
+        pipc_write(1, 0x40, 0x04, priv);
    else
-        pipc_write(1, 0x40, 0x00, p);
+        pipc_write(1, 0x40, 0x00, priv);

    if (dev->local < VIA_PIPC_586B)
-        pipc_write(0, 0x44, 0x00, p);
+        pipc_write(0, 0x44, 0x00, priv);

-    pipc_write(0, 0x77, 0x00, p);
+    pipc_write(0, 0x77, 0x00, priv);
 }

 static void *
@@ -1682,13 +1702,13 @@ pipc_init(const device_t *info)
 }

 static void
-pipc_close(void *p)
+pipc_close(void *priv)
 {
-    pipc_t *dev = (pipc_t *) p;
+    pipc_t *dev = (pipc_t *) priv;

    pipc_log("PIPC: close()\n");

-    for (int i = 0; i < TRAP_MAX; i++)
+    for (uint8_t i = 0; i < TRAP_MAX; i++)
        io_trap_remove(dev->io_traps[i].trap);

    free(dev);
--- a/src/chipset/via_vt82c49x.c
+++ b/src/chipset/via_vt82c49x.c
@@ -35,13 +35,14 @@
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct
-{
-    uint8_t has_ide, index,
-        regs[256];
+typedef struct vt82c49x_t {
+    uint8_t has_ide;
+    uint8_t index;
+    uint8_t regs[256];

-    smram_t *smram_smm, *smram_low,
-        *smram_high;
+    smram_t *smram_smm;
+    smram_t *smram_low;
+    smram_t *smram_high;
 } vt82c49x_t;

 #ifdef ENABLE_VT82C49X_LOG
@@ -65,7 +66,6 @@ vt82c49x_log(const char *fmt, ...)
 static void
 vt82c49x_recalc(vt82c49x_t *dev)
 {
-    int      i;
    int      relocate;
    uint8_t  reg;
    uint8_t  bit;
@@ -78,7 +78,7 @@ vt82c49x_recalc(vt82c49x_t *dev)
    shadowbios       = 0;
    shadowbios_write = 0;

-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        base = 0xc0000 + (i << 14);
        reg  = 0x30 + (i >> 2);
        bit  = (i & 3) << 1;
@@ -123,7 +123,7 @@ vt82c49x_recalc(vt82c49x_t *dev)
        mem_set_mem_state_both(base, 0x4000, state);
    }

-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        base = 0xe0000 + (i << 15);
        bit  = 6 - (i & 2);

@@ -189,6 +189,8 @@ vt82c49x_recalc(vt82c49x_t *dev)
            if (!shadow_bitmap)
                mem_remap_top(384);
            break;
+        default:
+            break;
    }
 }

@@ -280,8 +282,14 @@ vt82c49x_write(uint16_t addr, uint8_t val, void *priv)
                                     (val & 0x40) ? "second" : "prim");
                    }
                    break;
+
+                default:
+                    break;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -303,6 +311,9 @@ vt82c49x_read(uint16_t addr, void *priv)
            else if (dev->index < 0x80)
                ret = dev->regs[dev->index];
            break;
+
+        default:
+            break;
    }

    return ret;
--- a/src/chipset/via_vt82c505.c
+++ b/src/chipset/via_vt82c505.c
@@ -26,6 +26,7 @@
 #include <86box/io.h>
 #include <86box/pic.h>
 #include <86box/pci.h>
+#include <86box/plat_unused.h>
 #include <86box/device.h>
 #include <86box/chipset.h>

@@ -116,6 +117,9 @@ vt82c505_write(int func, int addr, uint8_t val, void *priv)
        case 0x93:
            dev->pci_conf[addr] = val & 0xe0;
            break;
+
+        default:
+            break;
    }
 }

@@ -194,7 +198,7 @@ vt82c505_close(void *priv)
 }

 static void *
-vt82c505_init(const device_t *info)
+vt82c505_init(UNUSED(const device_t *info))
 {
    vt82c505_t *dev = (vt82c505_t *) malloc(sizeof(vt82c505_t));
    memset(dev, 0, sizeof(vt82c505_t));
--- a/src/chipset/vl82c480.c
+++ b/src/chipset/vl82c480.c
@@ -29,9 +29,9 @@
 #include <86box/port_92.h>
 #include <86box/chipset.h>

-typedef struct {
-    uint8_t idx,
-        regs[256];
+typedef struct vl82c480_t {
+    uint8_t idx;
+    uint8_t regs[256];
 } vl82c480_t;

 static int
@@ -40,8 +40,8 @@ vl82c480_shflags(uint8_t access)
    int ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;

    switch (access) {
-        case 0x00:
        default:
+        case 0x00:
            ret = MEM_READ_EXTANY | MEM_WRITE_EXTANY;
            break;
        case 0x01:
@@ -81,9 +81,9 @@ vl82c480_recalc(vl82c480_t *dev)
 }

 static void
-vl82c480_write(uint16_t addr, uint8_t val, void *p)
+vl82c480_write(uint16_t addr, uint8_t val, void *priv)
 {
-    vl82c480_t *dev = (vl82c480_t *) p;
+    vl82c480_t *dev = (vl82c480_t *) priv;

    switch (addr) {
        case 0xec:
@@ -121,17 +121,23 @@ vl82c480_write(uint16_t addr, uint8_t val, void *p)
            }
            break;

+/* TODO: This is actually Fast A20 disable. */
+#if 0
        case 0xee:
            if (mem_a20_alt)
                outb(0x92, inb(0x92) & ~2);
            break;
+#endif
+
+        default:
+            break;
    }
 }

 static uint8_t
-vl82c480_read(uint16_t addr, void *p)
+vl82c480_read(uint16_t addr, void *priv)
 {
-    vl82c480_t *dev = (vl82c480_t *) p;
+    vl82c480_t *dev = (vl82c480_t *) priv;
    uint8_t     ret = 0xff;

    switch (addr) {
@@ -143,24 +149,30 @@ vl82c480_read(uint16_t addr, void *p)
            ret = dev->regs[dev->idx];
            break;

+/* TODO: This is actually Fast A20 enable. */
+#if 0
        case 0xee:
            if (!mem_a20_alt)
                outb(0x92, inb(0x92) | 2);
            break;
+#endif

        case 0xef:
            softresetx86();
            cpu_set_edx();
            break;
+
+        default:
+            break;
    }

    return ret;
 }

 static void
-vl82c480_close(void *p)
+vl82c480_close(void *priv)
 {
-    vl82c480_t *dev = (vl82c480_t *) p;
+    vl82c480_t *dev = (vl82c480_t *) priv;

    free(dev);
 }
--- a/src/chipset/wd76c10.c
+++ b/src/chipset/wd76c10.c
@@ -37,6 +37,7 @@
 #include <86box/hdc_ide.h>
 #include <86box/lpt.h>
 #include <86box/mem.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/serial.h>
 #include <86box/chipset.h>
@@ -63,17 +64,33 @@ wd76c10_log(const char *fmt, ...)
 #    define wd76c10_log(fmt, ...)
 #endif

-typedef struct
-{
-    uint16_t lock_reg, oscillator_40mhz, cache_flush, ems_page_reg,
-        ems_page_reg_pointer, port_shadow, pmc_interrupt,
-        high_mem_protect_boundry, delay_line, diagnostic,
-        nmi_status, pmc_input, pmc_timer,
-        pmc_output, ems_control_low_address_boundry, shadow_ram,
-        split_addr, bank32staddr, bank10staddr,
-        non_page_mode_dram_timing, mem_control,
-        refresh_control, disk_chip_select, prog_chip_sel_addr,
-        bus_timing_power_down_ctl, clk_control;
+typedef struct wd76c10_t {
+    uint16_t lock_reg;
+    uint16_t oscillator_40mhz;
+    uint16_t cache_flush;
+    uint16_t ems_page_reg;
+    uint16_t ems_page_reg_pointer;
+    uint16_t port_shadow;
+    uint16_t pmc_interrupt;
+    uint16_t high_mem_protect_boundry;
+    uint16_t delay_line;
+    uint16_t diagnostic;
+    uint16_t nmi_status;
+    uint16_t pmc_input;
+    uint16_t pmc_timer;
+    uint16_t pmc_output;
+    uint16_t ems_control_low_address_boundry;
+    uint16_t shadow_ram;
+    uint16_t split_addr;
+    uint16_t bank32staddr;
+    uint16_t bank10staddr;
+    uint16_t non_page_mode_dram_timing;
+    uint16_t mem_control;
+    uint16_t refresh_control;
+    uint16_t disk_chip_select;
+    uint16_t prog_chip_sel_addr;
+    uint16_t bus_timing_power_down_ctl;
+    uint16_t clk_control;

    int lock;

@@ -100,6 +117,8 @@ wd76c10_refresh_control(wd76c10_t *dev)
        case 4:
            serial_setup(dev->uart[1], 0x2e8, 3);
            break;
+        default:
+            break;
    }

    serial_remove(dev->uart[0]);
@@ -117,6 +136,8 @@ wd76c10_refresh_control(wd76c10_t *dev)
        case 4:
            serial_setup(dev->uart[0], 0x2e8, 4);
            break;
+        default:
+            break;
    }

    lpt1_remove();
@@ -134,6 +155,9 @@ wd76c10_refresh_control(wd76c10_t *dev)
            lpt1_init(0x278);
            lpt1_irq(7);
            break;
+
+        default:
+            break;
    }
 }

@@ -153,6 +177,8 @@ wd76c10_split_addr(wd76c10_t *dev)
            if (((dev->shadow_ram >> 8) & 3) == 3)
                mem_remap_top(384);
            break;
+        default:
+            break;
    }
 }

@@ -187,6 +213,8 @@ wd76c10_shadow_recalc(wd76c10_t *dev)
        case 3:
            mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | MEM_WRITE_DISABLED);
            break;
+        default:
+            break;
    }

    switch ((dev->shadow_ram >> 8) & 3) {
@@ -203,6 +231,8 @@ wd76c10_shadow_recalc(wd76c10_t *dev)
        case 3:
            mem_set_mem_state_both(0x20000, 0x80000, MEM_READ_DISABLED | (!!(dev->shadow_ram & 0x1000) ? MEM_WRITE_DISABLED : MEM_WRITE_INTERNAL));
            break;
+        default:
+            break;
    }
 }

@@ -309,6 +339,9 @@ wd76c10_write(uint16_t addr, uint16_t val, void *priv)
                dev->cache_flush = val;
                flushmmucache();
                break;
+
+            default:
+                break;
        }
        wd76c10_log("WD76C10: dev->regs[%04x] = %04x\n", addr, val);
    }
@@ -326,6 +359,9 @@ wd76c10_write(uint16_t addr, uint16_t val, void *priv)
            dev->lock_reg = val & 0x00ff;
            LOCK          = !(val & 0x00da);
            break;
+
+        default:
+            break;
    }
 }

@@ -424,7 +460,7 @@ wd76c10_close(void *priv)
 }

 static void *
-wd76c10_init(const device_t *info)
+wd76c10_init(UNUSED(const device_t *info))
 {
    wd76c10_t *dev = (wd76c10_t *) malloc(sizeof(wd76c10_t));
    memset(dev, 0, sizeof(wd76c10_t));
--- a/src/config.c
+++ b/src/config.c
@@ -515,13 +515,8 @@ load_machine(void)

    cpu_use_dynarec = !!ini_section_get_int(cat, "cpu_use_dynarec", 0);
    fpu_softfloat = !!ini_section_get_int(cat, "fpu_softfloat", 0);
-    /*The IBM PS/2 model 70 type 4 BIOS does heavy tests to the FPU in 80-bit precision mode, requiring softfloat 
-      otherwise it would always throw error 12903 on POST, so always disable dynarec and enable softfloat for this
-      machine only.*/
-    if (!strcmp(machines[machine].internal_name, "ibmps2_m70_type4")) {
-        cpu_use_dynarec = 0;
+    if (machine_has_flags(machine, MACHINE_SOFTFLOAT_ONLY))
        fpu_softfloat = 1;
-    }

    p = ini_section_get_string(cat, "time_sync", NULL);
    if (p != NULL) {
@@ -898,11 +893,11 @@ load_ports(void)
        sprintf(temp, "serial%d_enabled", c + 1);
        com_ports[c].enabled = !!ini_section_get_int(cat, temp, (c >= 2) ? 0 : 1);

-        /*
+#if 0
                sprintf(temp, "serial%d_device", c + 1);
                p = (char *) ini_section_get_string(cat, temp, "none");
                com_ports[c].device = com_device_get_from_internal_name(p);
-        */
+#endif

        sprintf(temp, "serial%d_passthrough_enabled", c + 1);
        serial_passthrough_enabled[c] = !!ini_section_get_int(cat, temp, 0);
@@ -1008,9 +1003,11 @@ load_storage_controllers(void)
    ide_ter_enabled = !!ini_section_get_int(cat, "ide_ter", 0);
    ide_qua_enabled = !!ini_section_get_int(cat, "ide_qua", 0);

-    /* TODO: Re-enable by default after we actually have a proper machine flag for this. */
-    cassette_enable = !!ini_section_get_int(cat, "cassette_enabled", 0);
-    p               = ini_section_get_string(cat, "cassette_file", "");
+    if (machine_has_bus(machine, MACHINE_BUS_CASSETTE))
+        cassette_enable = !!ini_section_get_int(cat, "cassette_enabled", 0);
+    else
+        cassette_enable = 0;
+    p = ini_section_get_string(cat, "cassette_file", "");
    if (strlen(p) > 511)
        fatal("load_storage_controllers(): strlen(p) > 511\n");
    else
@@ -1078,8 +1075,8 @@ load_hard_disks(void)

        hdd[c].bus = hdd_string_to_bus(s, 0);
        switch (hdd[c].bus) {
-            case HDD_BUS_DISABLED:
            default:
+            case HDD_BUS_DISABLED:
                max_spt = max_hpc = max_tracks = 0;
                break;

@@ -1309,8 +1306,10 @@ load_floppy_drives(void)
        else
            strncpy(floppyfns[c], p, 511);

-        /* if (*wp != L'\0')
-            config_log("Floppy%d: %ls\n", c, floppyfns[c]); */
+#if 0
+        if (*wp != L'\0')
+            config_log("Floppy%d: %ls\n", c, floppyfns[c]);
+#endif
        sprintf(temp, "fdd_%02i_writeprot", c + 1);
        ui_writeprot[c] = !!ini_section_get_int(cat, temp, 0);
        ini_section_delete_var(cat, temp);
@@ -1375,8 +1374,10 @@ load_floppy_and_cdrom_drives(void)
        else
            strncpy(floppyfns[c], p, 511);

-        /* if (*wp != L'\0')
-            config_log("Floppy%d: %ls\n", c, floppyfns[c]); */
+#if 0
+        if (*wp != L'\0')
+            config_log("Floppy%d: %ls\n", c, floppyfns[c]);
+#endif
        sprintf(temp, "fdd_%02i_writeprot", c + 1);
        ui_writeprot[c] = !!ini_section_get_int(cat, temp, 0);
        sprintf(temp, "fdd_%02i_turbo", c + 1);
@@ -1971,8 +1972,7 @@ config_load(void)
        for (i = 0; i < ISAMEM_MAX; i++)
            isamem_type[i] = 0;

-        /* TODO: Re-enable by default when we have a proper machine flag for this. */
-        cassette_enable = 0;
+        cassette_enable = 1;
        memset(cassette_fname, 0x00, sizeof(cassette_fname));
        memcpy(cassette_mode, "load", strlen("load") + 1);
        cassette_pos          = 0;
@@ -2532,6 +2532,9 @@ save_network(void)
            case NET_TYPE_VDE:
                ini_section_set_string(cat, temp, "vde");
                break;
+
+            default:
+                break;
        }

        sprintf(temp, "net_%02i_host_device", c + 1);
@@ -2541,7 +2544,9 @@ save_network(void)
            else
                ini_section_set_string(cat, temp, net_cards_conf[c].host_dev_name);
        } else {
-            /* ini_section_set_string(cat, temp, "none"); */
+#if 0
+            ini_section_set_string(cat, temp, "none");
+#endif
            ini_section_delete_var(cat, temp);
        }

@@ -2572,7 +2577,7 @@ save_ports(void)
        else
            ini_section_set_int(cat, temp, com_ports[c].enabled);

-        /*
+#if 0
                        sprintf(temp, "serial%d_type", c + 1);
                        if (!com_ports[c].enabled))
                            ini_section_delete_var(cat, temp);
@@ -2585,7 +2590,7 @@ save_ports(void)
                        else
                            ini_section_set_string(cat, temp,
                              (char *) com_device_get_internal_name(com_ports[c].device));
-                */
+#endif

        sprintf(temp, "serial%d_passthrough_enabled", c + 1);
        if (serial_passthrough_enabled[c]) {
--- a/src/cpu/386_dynarec.c
+++ b/src/cpu/386_dynarec.c
@@ -431,7 +431,7 @@ exec386_dynarec_dyn(void)
            uint64_t mask = (uint64_t) 1 << ((phys_addr >> PAGE_MASK_SHIFT) & PAGE_MASK_MASK);
 #    ifdef USE_NEW_DYNAREC
            int      byte_offset = (phys_addr >> PAGE_BYTE_MASK_SHIFT) & PAGE_BYTE_MASK_OFFSET_MASK;
-            uint64_t byte_mask   = 1ull << (PAGE_BYTE_MASK_MASK & 0x3f);
+            uint64_t byte_mask   = 1ULL << (PAGE_BYTE_MASK_MASK & 0x3f);

            if ((page->code_present_mask & mask) || (page->byte_code_present_mask[byte_offset] & byte_mask))
 #    else
--- a/src/cpu/808x.c
+++ b/src/cpu/808x.c
--- a/src/cpu/cpu.c
+++ b/src/cpu/cpu.c
@@ -80,66 +80,147 @@ fpu_state_t fpu_state;
 uint32_t abrt_error;

 #ifdef USE_DYNAREC
-const OpFn *x86_dynarec_opcodes, *x86_dynarec_opcodes_0f,
-    *x86_dynarec_opcodes_d8_a16, *x86_dynarec_opcodes_d8_a32,
-    *x86_dynarec_opcodes_d9_a16, *x86_dynarec_opcodes_d9_a32,
-    *x86_dynarec_opcodes_da_a16, *x86_dynarec_opcodes_da_a32,
-    *x86_dynarec_opcodes_db_a16, *x86_dynarec_opcodes_db_a32,
-    *x86_dynarec_opcodes_dc_a16, *x86_dynarec_opcodes_dc_a32,
-    *x86_dynarec_opcodes_dd_a16, *x86_dynarec_opcodes_dd_a32,
-    *x86_dynarec_opcodes_de_a16, *x86_dynarec_opcodes_de_a32,
-    *x86_dynarec_opcodes_df_a16, *x86_dynarec_opcodes_df_a32,
-    *x86_dynarec_opcodes_REPE, *x86_dynarec_opcodes_REPNE,
-    *x86_dynarec_opcodes_3DNOW;
+const OpFn *x86_dynarec_opcodes;
+const OpFn *x86_dynarec_opcodes_0f;
+const OpFn *x86_dynarec_opcodes_d8_a16;
+const OpFn *x86_dynarec_opcodes_d8_a32;
+const OpFn *x86_dynarec_opcodes_d9_a16;
+const OpFn *x86_dynarec_opcodes_d9_a32;
+const OpFn *x86_dynarec_opcodes_da_a16;
+const OpFn *x86_dynarec_opcodes_da_a32;
+const OpFn *x86_dynarec_opcodes_db_a16;
+const OpFn *x86_dynarec_opcodes_db_a32;
+const OpFn *x86_dynarec_opcodes_dc_a16;
+const OpFn *x86_dynarec_opcodes_dc_a32;
+const OpFn *x86_dynarec_opcodes_dd_a16;
+const OpFn *x86_dynarec_opcodes_dd_a32;
+const OpFn *x86_dynarec_opcodes_de_a16;
+const OpFn *x86_dynarec_opcodes_de_a32;
+const OpFn *x86_dynarec_opcodes_df_a16;
+const OpFn *x86_dynarec_opcodes_df_a32;
+const OpFn *x86_dynarec_opcodes_REPE;
+const OpFn *x86_dynarec_opcodes_REPNE;
+const OpFn *x86_dynarec_opcodes_3DNOW;
 #endif

-const OpFn *x86_opcodes, *x86_opcodes_0f,
-    *x86_opcodes_d8_a16, *x86_opcodes_d8_a32,
-    *x86_opcodes_d9_a16, *x86_opcodes_d9_a32,
-    *x86_opcodes_da_a16, *x86_opcodes_da_a32,
-    *x86_opcodes_db_a16, *x86_opcodes_db_a32,
-    *x86_opcodes_dc_a16, *x86_opcodes_dc_a32,
-    *x86_opcodes_dd_a16, *x86_opcodes_dd_a32,
-    *x86_opcodes_de_a16, *x86_opcodes_de_a32,
-    *x86_opcodes_df_a16, *x86_opcodes_df_a32,
-    *x86_opcodes_REPE, *x86_opcodes_REPNE,
-    *x86_opcodes_3DNOW;
+const OpFn *x86_opcodes;
+const OpFn *x86_opcodes_0f;
+const OpFn *x86_opcodes_d8_a16;
+const OpFn *x86_opcodes_d8_a32;
+const OpFn *x86_opcodes_d9_a16;
+const OpFn *x86_opcodes_d9_a32;
+const OpFn *x86_opcodes_da_a16;
+const OpFn *x86_opcodes_da_a32;
+const OpFn *x86_opcodes_db_a16;
+const OpFn *x86_opcodes_db_a32;
+const OpFn *x86_opcodes_dc_a16;
+const OpFn *x86_opcodes_dc_a32;
+const OpFn *x86_opcodes_dd_a16;
+const OpFn *x86_opcodes_dd_a32;
+const OpFn *x86_opcodes_de_a16;
+const OpFn *x86_opcodes_de_a32;
+const OpFn *x86_opcodes_df_a16;
+const OpFn *x86_opcodes_df_a32;
+const OpFn *x86_opcodes_REPE;
+const OpFn *x86_opcodes_REPNE;
+const OpFn *x86_opcodes_3DNOW;

-uint16_t cpu_fast_off_count, cpu_fast_off_val;
+uint16_t cpu_fast_off_count;
+uint16_t cpu_fast_off_val;
 uint16_t temp_seg_data[4] = { 0, 0, 0, 0 };

-int isa_cycles, cpu_inited,
+int isa_cycles;
+int cpu_inited;

-    cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l,
-    cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles,
-    cpu_waitstates, cpu_cache_int_enabled, cpu_cache_ext_enabled,
-    cpu_isa_speed, cpu_pci_speed, cpu_isa_pci_div, cpu_agp_speed, cpu_alt_reset,
+int cpu_cycles_read;
+int cpu_cycles_read_l;
+int cpu_cycles_write;
+int cpu_cycles_write_l;
+int cpu_prefetch_cycles;
+int cpu_prefetch_width;
+int cpu_mem_prefetch_cycles;
+int cpu_rom_prefetch_cycles;
+int cpu_waitstates;
+int cpu_cache_int_enabled;
+int cpu_cache_ext_enabled;
+int cpu_isa_speed;
+int cpu_pci_speed;
+int cpu_isa_pci_div;
+int cpu_agp_speed;
+int cpu_alt_reset;

-    cpu_override, cpu_effective, cpu_multi, cpu_16bitbus, cpu_64bitbus,
-    cpu_cyrix_alignment, CPUID,
+int cpu_override;
+int cpu_effective;
+int cpu_multi;
+int cpu_16bitbus;
+int cpu_64bitbus;
+int cpu_cyrix_alignment;
+int CPUID;

-    is186, is_nec,
-    is286, is386, is6117, is486 = 1,
-                          cpu_isintel, cpu_iscyrix, hascache, isibm486, israpidcad, is_vpc,
-                          is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm, hasfpu,
+int is186;
+int is_nec;
+int is286;
+int is386;
+int is6117;
+int is486 = 1;
+int cpu_isintel;
+int cpu_iscyrix;
+int hascache;
+int isibm486;
+int israpidcad;
+int is_vpc;
+int is_am486;
+int is_am486dxl;
+int is_pentium;
+int is_k5;
+int is_k6;
+int is_p6;
+int is_cxsmm;
+int hasfpu;

-                          timing_rr, timing_mr, timing_mrl, timing_rm, timing_rml,
-                          timing_mm, timing_mml, timing_bt, timing_bnt,
-                          timing_int, timing_int_rm, timing_int_v86, timing_int_pm,
-                          timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm,
-                          timing_iret_pm_outer, timing_call_rm, timing_call_pm, timing_call_pm_gate,
-                          timing_call_pm_gate_inner, timing_retf_rm, timing_retf_pm, timing_retf_pm_outer,
-                          timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate, timing_misaligned;
-uint32_t cpu_features, cpu_fast_off_flags;
+int timing_rr;
+int timing_mr;
+int timing_mrl;
+int timing_rm;
+int timing_rml;
+int timing_mm;
+int timing_mml;
+int timing_bt;
+int timing_bnt;
+int timing_int;
+int timing_int_rm;
+int timing_int_v86;
+int timing_int_pm;
+int timing_int_pm_outer;
+int timing_iret_rm;
+int timing_iret_v86;
+int timing_iret_pm;
+int timing_iret_pm_outer;
+int timing_call_rm;
+int timing_call_pm;
+int timing_call_pm_gate;
+int timing_call_pm_gate_inner;
+int timing_retf_rm;
+int timing_retf_pm;
+int timing_retf_pm_outer;
+int timing_jmp_rm;
+int timing_jmp_pm;
+int timing_jmp_pm_gate;
+int timing_misaligned;
+
+uint32_t cpu_features;
+uint32_t cpu_fast_off_flags;

 uint32_t _tr[8]      = { 0, 0, 0, 0, 0, 0, 0, 0 };
 uint32_t cache_index = 0;
 uint8_t  _cache[2048];

-uint64_t cpu_CR4_mask, tsc = 0;
+uint64_t cpu_CR4_mask;
+uint64_t tsc = 0;
 uint64_t pmc[2] = { 0, 0 };

-double cpu_dmulti, cpu_busspeed;
+double cpu_dmulti;
+double cpu_busspeed;

 msr_t msr;

@@ -148,11 +229,18 @@ cyrix_t cyrix;
 cpu_family_t *cpu_f;
 CPU          *cpu_s;

-uint8_t do_translate = 0, do_translate2 = 0;
+uint8_t do_translate = 0;
+uint8_t do_translate2 = 0;

 void (*cpu_exec)(int cycs);

-static uint8_t ccr0, ccr1, ccr2, ccr3, ccr4, ccr5, ccr6;
+static uint8_t ccr0;
+static uint8_t ccr1;
+static uint8_t ccr2;
+static uint8_t ccr3;
+static uint8_t ccr4;
+static uint8_t ccr5;
+static uint8_t ccr6;

 void
 cpu_INVD(uint8_t wb)
@@ -231,7 +319,8 @@ cpu_is_eligible(const cpu_family_t *cpu_family, int cpu, int machine)
 {
    const machine_t *machine_s = &machines[machine];
    const CPU       *cpu_s     = &cpu_family->cpus[cpu];
-    uint32_t         packages, bus_speed;
+    uint32_t         packages;
+    uint32_t         bus_speed;
    uint8_t          i;
    double           multi;

@@ -1653,7 +1742,7 @@ cpu_current_pc(char *bufp)

    sprintf(bufp, "%04X:%04X", CS, cpu_state.pc);

-    return (bufp);
+    return bufp;
 }

 void
@@ -3258,7 +3347,7 @@ cpu_write(uint16_t addr, uint8_t val, void *priv)
                if (!(ccr3 & CCR3_SMI_LOCK) || in_smm) {
                    cyrix.arr[3].base = (cyrix.arr[3].base & ~0x0000f000) | ((val & 0xf0) << 8);
                    if ((val & 0xf) == 0xf)
-                        cyrix.arr[3].size = 1ull << 32; /* 4 GB */
+                        cyrix.arr[3].size = 1ULL << 32; /* 4 GB */
                    else if (val & 0xf)
                        cyrix.arr[3].size = 2048 << (val & 0xf);
                    else
@@ -3320,6 +3409,9 @@ cpu_read(uint16_t addr, void *priv)
                return cpu_s->cyrix_id & 0xff;
            case 0xff:
                return cpu_s->cyrix_id >> 8;
+
+            default:
+                break;
        }

        if ((cyrix_addr & 0xf0) == 0xc0)
--- a/src/cpu/cpu.h
+++ b/src/cpu/cpu.h
@@ -150,8 +150,10 @@ typedef struct {
    uint32_t    cpuid_model;
    uint16_t    cyrix_id;
    uint8_t     cpu_flags;
-    int8_t      mem_read_cycles, mem_write_cycles;
-    int8_t      cache_read_cycles, cache_write_cycles;
+    int8_t      mem_read_cycles;
+    int8_t      mem_write_cycles;
+    int8_t      cache_read_cycles;
+    int8_t      cache_write_cycles;
    int8_t      atclk_div;
 } CPU;

@@ -215,17 +217,19 @@ typedef union {
    uint32_t l;
    uint16_t w;
    struct {
-        uint8_t l,
-            h;
+        uint8_t l;
+        uint8_t h;
    } b;
 } x86reg;

 typedef struct {
    uint32_t base;
    uint32_t limit;
-    uint8_t  access, ar_high;
+    uint8_t  access;
+    uint8_t  ar_high;
    uint16_t seg;
-    uint32_t limit_low, limit_high;
+    uint32_t limit_low;
+    uint32_t limit_high;
    int      checked; /*Non-zero if selector is known to be valid*/
 } x86seg;

@@ -243,8 +247,9 @@ typedef union {

 typedef struct {
    /* IDT WinChip and WinChip 2 MSR's */
-    uint32_t tr1, tr12; /* 0x00000002, 0x0000000e */
-    uint32_t cesr;      /* 0x00000011 */
+    uint32_t tr1;  /* 0x00000002, 0x0000000e */
+    uint32_t tr12; /* 0x00000002, 0x0000000e */
+    uint32_t cesr; /* 0x00000011 */

    /* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
    uint64_t apic_base; /* 0x0000001b - Should the Pentium not also have this? */
@@ -259,8 +264,9 @@ typedef struct {
    uint64_t mtrr_cap;    /* 0x000000fe */

    /* IDT WinChip and WinChip 2 MSR's that are also on the VIA Cyrix III */
-    uint32_t fcr;        /* 0x00000107 (IDT), 0x00001107 (VIA) */
-    uint64_t fcr2, fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */
+    uint32_t fcr;  /* 0x00000107 (IDT), 0x00001107 (VIA) */
+    uint64_t fcr2; /* 0x00000108 (IDT), 0x00001108 (VIA) */
+    uint64_t fcr3; /* 0x00000108 (IDT), 0x00001108 (VIA) */

    /* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
    uint64_t ecx116;    /* 0x00000116 */
@@ -276,8 +282,9 @@ typedef struct {
    uint64_t mcg_ctl; /* 0x0000017b - Machine Check Architecture */

    /* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's */
-    uint64_t ecx186, ecx187; /* 0x00000186, 0x00000187 */
-    uint64_t ecx1e0;         /* 0x000001e0 */
+    uint64_t ecx186; /* 0x00000186, 0x00000187 */
+    uint64_t ecx187; /* 0x00000186, 0x00000187 */
+    uint64_t ecx1e0; /* 0x000001e0 */

    /* Pentium Pro, Pentium II Klamath, and Pentium II Deschutes MSR's that are also
       on the VIA Cyrix III */
@@ -325,7 +332,8 @@ typedef struct {
    uint64_t amd_epmr; /* 0xc0000086 */

    /* AMD K6-2C, K6-3, K6-2P, and K6-3P MSR's */
-    uint64_t amd_psor, amd_pfir; /* 0xc0000087, 0xc0000088 */
+    uint64_t amd_psor; /* 0xc0000087, 0xc0000088 */
+    uint64_t amd_pfir; /* 0xc0000087, 0xc0000088 */

    /* K6-3, K6-2P, and K6-3P MSR's */
    uint64_t amd_l2aar; /* 0xc0000089 */
@@ -345,33 +353,38 @@ typedef struct {
    uint32_t eaaddr;

    int      flags_op;
-    uint32_t flags_res,
-        flags_op1, flags_op2;
+    uint32_t flags_res;
+    uint32_t flags_op1;
+    uint32_t flags_op2;

-    uint32_t pc,
-        oldpc, op32;
+    uint32_t pc;
+    uint32_t oldpc;
+    uint32_t op32;

    int TOP;

    union {
        struct {
-            int8_t rm,
-                mod,
-                reg;
+            int8_t rm;
+            int8_t mod;
+            int8_t reg;
        } rm_mod_reg;
        int32_t rm_mod_reg_data;
    } rm_data;

-    uint8_t ssegs, ismmx,
-        abrt, _smi_line;
+    uint8_t ssegs;
+    uint8_t ismmx;
+    uint8_t abrt;
+    uint8_t _smi_line;

+    int _cycles;
 #ifdef FPU_CYCLES
-    int _cycles, _fpu_cycles, _in_smm;
-#else
-    int      _cycles, _in_smm;
+    int _fpu_cycles;
 #endif
+    int _in_smm;

-    uint16_t npxs, npxc;
+    uint16_t npxs;
+    uint16_t npxc;

    double ST[8];

@@ -380,26 +393,34 @@ typedef struct {
    MMX_REG MM[8];

 #ifdef USE_NEW_DYNAREC
-    uint32_t    old_fp_control, new_fp_control;
+    uint32_t old_fp_control;
+    uint32_t new_fp_control;
 #    if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86
-    uint16_t                                                                           old_fp_control2, new_fp_control2;
+    uint16_t old_fp_control2;
+    uint16_t new_fp_control2;
 #    endif
 #    if defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86 || defined __amd64__ || defined _M_X64
-    uint32_t                                                                                                                   trunc_fp_control;
+    uint32_t trunc_fp_control;
 #    endif
 #else
-    uint16_t old_npxc, new_npxc;
+    uint16_t old_npxc;
+    uint16_t new_npxc;
 #endif

-    x86seg seg_cs, seg_ds, seg_es, seg_ss,
-        seg_fs, seg_gs;
+    x86seg seg_cs;
+    x86seg seg_ds;
+    x86seg seg_es;
+    x86seg seg_ss;
+    x86seg seg_fs;
+    x86seg seg_gs;

    union {
        uint32_t l;
        uint16_t w;
    } CR0;

-    uint16_t flags, eflags;
+    uint16_t flags;
+    uint16_t eflags;

    uint32_t _smbase;
 } cpu_state_t;
@@ -415,13 +436,15 @@ typedef struct {
    uint16_t fds;
    floatx80 st_space[8];
    unsigned char tos;
-    unsigned char align1, align2, align3;
+    unsigned char align1;
+    unsigned char align2;
+    unsigned char align3;
 } fpu_state_t;

 #define in_smm   cpu_state._in_smm
 #define smi_line cpu_state._smi_line

-#define smbase   cpu_state._smbase
+#define smbase cpu_state._smbase

 /*The cpu_state.flags below must match in both cpu_cur_status and block->status for a block
  to be valid*/
@@ -508,7 +531,8 @@ extern int                        cpu_override;

 extern int    cpu_isintel;
 extern int    cpu_iscyrix;
-extern int    cpu_16bitbus, cpu_64bitbus;
+extern int    cpu_16bitbus;
+extern int    cpu_64bitbus;
 extern int    cpu_pci_speed;
 extern int    cpu_multi;
 extern double cpu_dmulti;
@@ -517,8 +541,19 @@ extern double cpu_busspeed;
 extern int    cpu_cyrix_alignment; /*Cyrix 5x86/6x86 only has data misalignment
                                     penalties when crossing 8-byte boundaries*/

-extern int is8086, is186, is286, is386, is6117, is486;
-extern int is_am486, is_am486dxl, is_pentium, is_k5, is_k6, is_p6, is_cxsmm;
+extern int is8086;
+extern int is186;
+extern int is286;
+extern int is386;
+extern int is6117;
+extern int is486;
+extern int is_am486;
+extern int is_am486dxl;
+extern int is_pentium;
+extern int is_k5;
+extern int is_k6;
+extern int is_p6;
+extern int is_cxsmm;
 extern int hascache;
 extern int isibm486;
 extern int is_nec;
@@ -536,7 +571,8 @@ extern int hasfpu;

 extern uint32_t cpu_features;

-extern int smi_latched, smm_in_hlt;
+extern int smi_latched;
+extern int smm_in_hlt;
 extern int smi_block;

 #ifdef USE_NEW_DYNAREC
@@ -552,12 +588,21 @@ extern int      cgate16;
 extern int      cpl_override;
 extern int      CPUID;
 extern uint64_t xt_cpu_multi;
-extern int      isa_cycles, cpu_inited;
-extern uint32_t oldds, oldss, olddslimit, oldsslimit, olddslimitw, oldsslimitw;
+extern int      isa_cycles;
+extern int      cpu_inited;
+extern uint32_t oldds;
+extern uint32_t oldss;
+extern uint32_t olddslimit;
+extern uint32_t oldsslimit;
+extern uint32_t olddslimitw;
+extern uint32_t oldsslimitw;
 extern uint32_t pccache;
 extern uint8_t *pccache2;

-extern double   bus_timing, isa_timing, pci_timing, agp_timing;
+extern double   bus_timing;
+extern double   isa_timing;
+extern double   pci_timing;
+extern double   agp_timing;
 extern uint64_t pmc[2];
 extern uint16_t temp_seg_data[4];
 extern uint16_t cs_msr;
@@ -565,13 +610,16 @@ extern uint32_t esp_msr;
 extern uint32_t eip_msr;

 /* For the AMD K6. */
-extern uint64_t amd_efer, star;
+extern uint64_t amd_efer;
+extern uint64_t star;

 #define FPU_CW_Reserved_Bits (0xe0c0)

-#define cr0                  cpu_state.CR0.l
-#define msw                  cpu_state.CR0.w
-extern uint32_t cr2, cr3, cr4;
+#define cr0     cpu_state.CR0.l
+#define msw     cpu_state.CR0.w
+extern uint32_t cr2;
+extern uint32_t cr3;
+extern uint32_t cr4;
 extern uint32_t dr[8];
 extern uint32_t _tr[8];
 extern uint32_t cache_index;
@@ -581,7 +629,10 @@ extern uint8_t  _cache[2048];
  _cs,_ds,_es,_ss are the segment structures
  CS,DS,ES,SS is the 16-bit data
  cs,ds,es,ss are defines to the bases*/
-extern x86seg gdt, ldt, idt, tr;
+extern x86seg gdt;
+extern x86seg ldt;
+extern x86seg idt;
+extern x86seg tr;
 extern x86seg _oldds;
 #define CS            cpu_state.seg_cs.seg
 #define DS            cpu_state.seg_ds.seg
@@ -598,37 +649,67 @@ extern x86seg _oldds;

 #define ISA_CYCLES(x) (x * isa_cycles)

-extern int cpu_cycles_read, cpu_cycles_read_l, cpu_cycles_write, cpu_cycles_write_l;
-extern int cpu_prefetch_cycles, cpu_prefetch_width, cpu_mem_prefetch_cycles, cpu_rom_prefetch_cycles;
+extern int cpu_cycles_read;
+extern int cpu_cycles_read_l;
+extern int cpu_cycles_write;
+extern int cpu_cycles_write_l;
+extern int cpu_prefetch_cycles;
+extern int cpu_prefetch_width;
+extern int cpu_mem_prefetch_cycles;
+extern int cpu_rom_prefetch_cycles;
 extern int cpu_waitstates;
-extern int cpu_cache_int_enabled, cpu_cache_ext_enabled;
-extern int cpu_isa_speed, cpu_pci_speed, cpu_agp_speed;
+extern int cpu_cache_int_enabled;
+extern int cpu_cache_ext_enabled;
+extern int cpu_isa_speed;
+extern int cpu_pci_speed;
+extern int cpu_agp_speed;

 extern int timing_rr;
-extern int timing_mr, timing_mrl;
-extern int timing_rm, timing_rml;
-extern int timing_mm, timing_mml;
-extern int timing_bt, timing_bnt;
-extern int timing_int, timing_int_rm, timing_int_v86, timing_int_pm;
-extern int timing_int_pm_outer, timing_iret_rm, timing_iret_v86, timing_iret_pm;
-extern int timing_iret_pm_outer, timing_call_rm, timing_call_pm;
-extern int timing_call_pm_gate, timing_call_pm_gate_inner;
-extern int timing_retf_rm, timing_retf_pm, timing_retf_pm_outer;
-extern int timing_jmp_rm, timing_jmp_pm, timing_jmp_pm_gate;
+extern int timing_mr;
+extern int timing_mrl;
+extern int timing_rm;
+extern int timing_rml;
+extern int timing_mm;
+extern int timing_mml;
+extern int timing_bt;
+extern int timing_bnt;
+extern int timing_int;
+extern int timing_int_rm;
+extern int timing_int_v86;
+extern int timing_int_pm;
+extern int timing_int_pm_outer;
+extern int timing_iret_rm;
+extern int timing_iret_v86;
+extern int timing_iret_pm;
+extern int timing_iret_pm_outer;
+extern int timing_call_rm;
+extern int timing_call_pm;
+extern int timing_call_pm_gate;
+extern int timing_call_pm_gate_inner;
+extern int timing_retf_rm;
+extern int timing_retf_pm;
+extern int timing_retf_pm_outer;
+extern int timing_jmp_rm;
+extern int timing_jmp_pm;
+extern int timing_jmp_pm_gate;
 extern int timing_misaligned;

-extern int      in_sys, unmask_a20_in_smm;
+extern int      in_sys;
+extern int      unmask_a20_in_smm;
 extern int      cycles_main;
 extern uint32_t old_rammask;

 #ifdef USE_ACYCS
 extern int acycs;
 #endif
-extern int pic_pending, is_vpc;
-extern int soft_reset_mask, alt_access;
+extern int pic_pending;
+extern int is_vpc;
+extern int soft_reset_mask;
+extern int alt_access;
 extern int cpu_end_block_after_ins;

-extern uint16_t cpu_fast_off_count, cpu_fast_off_val;
+extern uint16_t cpu_fast_off_count;
+extern uint16_t cpu_fast_off_val;
 extern uint32_t cpu_fast_off_flags;

 /* Functions. */
@@ -704,7 +785,8 @@ extern void x87_dumpregs(void);
 extern void x87_reset(void);
 #endif

-extern int  cpu_effective, cpu_alt_reset;
+extern int  cpu_effective;
+extern int  cpu_alt_reset;
 extern void cpu_dynamic_switch(int new_cpu);

 extern void cpu_ven_reset(void);
@@ -729,22 +811,23 @@ void cyrix_write_seg_descriptor(uint32_t addr, x86seg *seg);
 #define SMHR_VALID     (1 << 0)
 #define SMHR_ADDR_MASK (0xfffffffc)

-typedef struct
-{
-    struct
-    {
+typedef struct {
+    struct {
        uint32_t base;
        uint64_t size;
    } arr[8];
    uint32_t smhr;
 } cyrix_t;

-extern uint32_t addr64, addr64_2;
-extern uint32_t addr64a[8], addr64a_2[8];
+extern uint32_t addr64;
+extern uint32_t addr64_2;
+extern uint32_t addr64a[8];
+extern uint32_t addr64a_2[8];

 extern int soft_reset_pci;

-extern int reset_on_hlt, hlt_reset_pending;
+extern int reset_on_hlt;
+extern int hlt_reset_pending;

 extern cyrix_t cyrix;

@@ -752,7 +835,8 @@ extern uint8_t  use_custom_nmi_vector;
 extern uint32_t custom_nmi_vector;

 extern void (*cpu_exec)(int cycs);
-extern uint8_t do_translate, do_translate2;
+extern uint8_t do_translate;
+extern uint8_t do_translate2;

 extern void SF_FPU_reset(void);

--- a/src/ddma.c
+++ b/src/ddma.c
@@ -34,6 +34,7 @@
 #include <86box/pit.h>
 #include <86box/dma.h>
 #include <86box/ddma.h>
+#include <86box/plat_unused.h>

 #ifdef ENABLE_DDMA_LOG
 int ddma_do_log = ENABLE_DDMA_LOG;
@@ -54,9 +55,9 @@ ddma_log(const char *fmt, ...)
 #endif

 static uint8_t
-ddma_reg_read(uint16_t addr, void *p)
+ddma_reg_read(uint16_t addr, void *priv)
 {
-    ddma_channel_t *dev  = (ddma_channel_t *) p;
+    ddma_channel_t *dev  = (ddma_channel_t *) priv;
    uint8_t         ret  = 0xff;
    int             ch   = dev->channel;
    int             dmab = (ch >= 4) ? 0xc0 : 0x00;
@@ -80,15 +81,18 @@ ddma_reg_read(uint16_t addr, void *p)
        case 0x09:
            ret = inb(dmab + 0x08);
            break;
+
+        default:
+            break;
    }

    return ret;
 }

 static void
-ddma_reg_write(uint16_t addr, uint8_t val, void *p)
+ddma_reg_write(uint16_t addr, uint8_t val, void *priv)
 {
-    ddma_channel_t *dev          = (ddma_channel_t *) p;
+    ddma_channel_t *dev          = (ddma_channel_t *) priv;
    int             ch           = dev->channel;
    int             page_regs[4] = { 7, 3, 1, 2 };
    int             dmab = (ch >= 4) ? 0xc0 : 0x00;
@@ -138,6 +142,9 @@ ddma_reg_write(uint16_t addr, uint8_t val, void *p)
        case 0x0f:
            outb(dmab + 0x0a, (val << 2) | (ch & 3));
            break;
+
+        default:
+            break;
    }
 }

@@ -163,7 +170,7 @@ ddma_close(void *priv)
 }

 static void *
-ddma_init(const device_t *info)
+ddma_init(UNUSED(const device_t *info))
 {
    ddma_t *dev;

--- a/src/device.c
+++ b/src/device.c
@@ -88,46 +88,46 @@ device_init(void)
 }

 void
-device_set_context(device_context_t *c, const device_t *d, int inst)
+device_set_context(device_context_t *c, const device_t *dev, int inst)
 {
    void *sec;
    void *single_sec;

    memset(c, 0, sizeof(device_context_t));
-    c->dev      = d;
+    c->dev      = dev;
    c->instance = inst;
    if (inst) {
-        sprintf(c->name, "%s #%i", d->name, inst);
+        sprintf(c->name, "%s #%i", dev->name, inst);

        /* If this is the first instance and a numbered section is not present, but a non-numbered
           section of the same name is, rename the non-numbered section to numbered. */
        if (inst == 1) {
            sec        = config_find_section(c->name);
-            single_sec = config_find_section((char *) d->name);
+            single_sec = config_find_section((char *) dev->name);
            if ((sec == NULL) && (single_sec != NULL))
                config_rename_section(single_sec, c->name);
        }
    } else
-        sprintf(c->name, "%s", d->name);
+        sprintf(c->name, "%s", dev->name);
 }

 static void
-device_context_common(const device_t *d, int inst)
+device_context_common(const device_t *dev, int inst)
 {
    memcpy(&device_prev, &device_current, sizeof(device_context_t));
-    device_set_context(&device_current, d, inst);
+    device_set_context(&device_current, dev, inst);
 }

 void
-device_context(const device_t *d)
+device_context(const device_t *dev)
 {
-    device_context_common(d, 0);
+    device_context_common(dev, 0);
 }

 void
-device_context_inst(const device_t *d, int inst)
+device_context_inst(const device_t *dev, int inst)
 {
-    device_context_common(d, inst);
+    device_context_common(dev, inst);
 }

 void
@@ -137,13 +137,13 @@ device_context_restore(void)
 }

 static void *
-device_add_common(const device_t *d, const device_t *cd, void *p, void *params, int inst)
+device_add_common(const device_t *dev, const device_t *cd, void *p, void *params, int inst)
 {
    void *priv = NULL;
    int   c;

    for (c = 0; c < 256; c++) {
-        if (!inst && (devices[c] == (device_t *) d)) {
+        if (!inst && (devices[c] == (device_t *) dev)) {
            device_log("DEVICE: device already exists!\n");
            return (NULL);
        }
@@ -157,17 +157,17 @@ device_add_common(const device_t *d, const device_t *cd, void *p, void *params,

    /* Do this so that a chained device_add will not identify the same ID
       its master device is already trying to assign. */
-    devices[c] = (device_t *) d;
+    devices[c] = (device_t *) dev;

    if (p == NULL) {
        memcpy(&device_prev, &device_current, sizeof(device_context_t));
        device_set_context(&device_current, cd, inst);

-        if (d->init != NULL) {
-            priv = (d->flags & DEVICE_EXTPARAMS) ? d->init_ext(d, params) : d->init(d);
+        if (dev->init != NULL) {
+            priv = (dev->flags & DEVICE_EXTPARAMS) ? dev->init_ext(dev, params) : dev->init(dev);
            if (priv == NULL) {
-                if (d->name)
-                    device_log("DEVICE: device '%s' init failed\n", d->name);
+                if (dev->name)
+                    device_log("DEVICE: device '%s' init failed\n", dev->name);
                else
                    device_log("DEVICE: device init failed\n");

@@ -178,8 +178,8 @@ device_add_common(const device_t *d, const device_t *cd, void *p, void *params,
            }
        }

-        if (d->name)
-            device_log("DEVICE: device '%s' init successful\n", d->name);
+        if (dev->name)
+            device_log("DEVICE: device '%s' init successful\n", dev->name);
        else
            device_log("DEVICE: device init successful\n");

@@ -192,114 +192,114 @@ device_add_common(const device_t *d, const device_t *cd, void *p, void *params,
 }

 char *
-device_get_internal_name(const device_t *d)
+device_get_internal_name(const device_t *dev)
 {
-    if (d == NULL)
+    if (dev == NULL)
        return "";

-    return (char *) d->internal_name;
+    return (char *) dev->internal_name;
 }

 void *
-device_add(const device_t *d)
+device_add(const device_t *dev)
 {
-    return device_add_common(d, d, NULL, NULL, 0);
+    return device_add_common(dev, dev, NULL, NULL, 0);
 }

 void *
-device_add_parameters(const device_t *d, void *params)
+device_add_parameters(const device_t *dev, void *params)
 {
-    return device_add_common(d, d, NULL, params, 0);
+    return device_add_common(dev, dev, NULL, params, 0);
 }

 /* For devices that do not have an init function (internal video etc.) */
 void
-device_add_ex(const device_t *d, void *priv)
+device_add_ex(const device_t *dev, void *priv)
 {
-    device_add_common(d, d, priv, NULL, 0);
+    device_add_common(dev, dev, priv, NULL, 0);
 }

 void
-device_add_ex_parameters(const device_t *d, void *priv, void *params)
+device_add_ex_parameters(const device_t *dev, void *priv, void *params)
 {
-    device_add_common(d, d, priv, params, 0);
+    device_add_common(dev, dev, priv, params, 0);
 }

 void *
-device_add_inst(const device_t *d, int inst)
+device_add_inst(const device_t *dev, int inst)
 {
-    return device_add_common(d, d, NULL, NULL, inst);
+    return device_add_common(dev, dev, NULL, NULL, inst);
 }

 void *
-device_add_inst_parameters(const device_t *d, int inst, void *params)
+device_add_inst_parameters(const device_t *dev, int inst, void *params)
 {
-    return device_add_common(d, d, NULL, params, inst);
+    return device_add_common(dev, dev, NULL, params, inst);
 }

 /* For devices that do not have an init function (internal video etc.) */
 void
-device_add_inst_ex(const device_t *d, void *priv, int inst)
+device_add_inst_ex(const device_t *dev, void *priv, int inst)
 {
-    device_add_common(d, d, priv, NULL, inst);
+    device_add_common(dev, dev, priv, NULL, inst);
 }

 void
-device_add_inst_ex_parameters(const device_t *d, void *priv, int inst, void *params)
+device_add_inst_ex_parameters(const device_t *dev, void *priv, int inst, void *params)
 {
-    device_add_common(d, d, priv, params, inst);
+    device_add_common(dev, dev, priv, params, inst);
 }

 /* These eight are to add a device with another device's context - will be
   used to add machines' internal devices. */
 void *
-device_cadd(const device_t *d, const device_t *cd)
+device_cadd(const device_t *dev, const device_t *cd)
 {
-    return device_add_common(d, cd, NULL, NULL, 0);
+    return device_add_common(dev, cd, NULL, NULL, 0);
 }

 void *
-device_cadd_parameters(const device_t *d, const device_t *cd, void *params)
+device_cadd_parameters(const device_t *dev, const device_t *cd, void *params)
 {
-    return device_add_common(d, cd, NULL, params, 0);
+    return device_add_common(dev, cd, NULL, params, 0);
 }

 /* For devices that do not have an init function (internal video etc.) */
 void
-device_cadd_ex(const device_t *d, const device_t *cd, void *priv)
+device_cadd_ex(const device_t *dev, const device_t *cd, void *priv)
 {
-    device_add_common(d, cd, priv, NULL, 0);
+    device_add_common(dev, cd, priv, NULL, 0);
 }

 void
-device_cadd_ex_parameters(const device_t *d, const device_t *cd, void *priv, void *params)
+device_cadd_ex_parameters(const device_t *dev, const device_t *cd, void *priv, void *params)
 {
-    device_add_common(d, cd, priv, params, 0);
+    device_add_common(dev, cd, priv, params, 0);
 }

 void *
-device_cadd_inst(const device_t *d, const device_t *cd, int inst)
+device_cadd_inst(const device_t *dev, const device_t *cd, int inst)
 {
-    return device_add_common(d, cd, NULL, NULL, inst);
+    return device_add_common(dev, cd, NULL, NULL, inst);
 }

 void *
-device_cadd_inst_parameters(const device_t *d, const device_t *cd, int inst, void *params)
+device_cadd_inst_parameters(const device_t *dev, const device_t *cd, int inst, void *params)
 {
-    return device_add_common(d, cd, NULL, params, inst);
+    return device_add_common(dev, cd, NULL, params, inst);
 }

 /* For devices that do not have an init function (internal video etc.) */
 void
-device_cadd_inst_ex(const device_t *d, const device_t *cd, void *priv, int inst)
+device_cadd_inst_ex(const device_t *dev, const device_t *cd, void *priv, int inst)
 {
-    device_add_common(d, cd, priv, NULL, inst);
+    device_add_common(dev, cd, priv, NULL, inst);
 }

 void
-device_cadd_inst_ex_parameters(const device_t *d, const device_t *cd, void *priv, int inst, void *params)
+device_cadd_inst_ex_parameters(const device_t *dev, const device_t *cd, void *priv, int inst, void *params)
 {
-    device_add_common(d, cd, priv, params, inst);
+    device_add_common(dev, cd, priv, params, inst);
 }

 void
@@ -328,11 +328,11 @@ device_reset_all(uint32_t match_flags)
 }

 void *
-device_get_priv(const device_t *d)
+device_get_priv(const device_t *dev)
 {
    for (uint16_t c = 0; c < DEVICE_MAX; c++) {
        if (devices[c] != NULL) {
-            if (devices[c] == d)
+            if (devices[c] == dev)
                return (device_priv[c]);
        }
    }
@@ -341,15 +341,15 @@ device_get_priv(const device_t *d)
 }

 int
-device_available(const device_t *d)
+device_available(const device_t *dev)
 {
    device_config_t      *config = NULL;
    device_config_bios_t *bios   = NULL;
    int                   roms_present = 0;
    int                   i = 0;

-    if (d != NULL) {
-        config = (device_config_t *) d->config;
+    if (dev != NULL) {
+        config = (device_config_t *) dev->config;
        if (config != NULL) {
            while (config->type != -1) {
                if (config->type == CONFIG_BIOS) {
@@ -372,8 +372,8 @@ device_available(const device_t *d)
        }

        /* No CONFIG_BIOS field present, use the classic available(). */
-        if (d->available != NULL)
-            return (d->available());
+        if (dev->available != NULL)
+            return (dev->available());
        else
            return 1;
    }
@@ -383,13 +383,13 @@ device_available(const device_t *d)
 }

 const char *
-device_get_bios_file(const device_t *d, const char *internal_name, int file_no)
+device_get_bios_file(const device_t *dev, const char *internal_name, int file_no)
 {
    device_config_t      *config = NULL;
    device_config_bios_t *bios   = NULL;

-    if (d != NULL) {
-        config = (device_config_t *) d->config;
+    if (dev != NULL) {
+        config = (device_config_t *) dev->config;
        if (config != NULL) {
            while (config->type != -1) {
                if (config->type == CONFIG_BIOS) {
@@ -416,18 +416,18 @@ device_get_bios_file(const device_t *d, const char *internal_name, int file_no)
 }

 int
-device_has_config(const device_t *d)
+device_has_config(const device_t *dev)
 {
    int              c = 0;
    device_config_t *config;

-    if (d == NULL)
+    if (dev == NULL)
        return 0;

-    if (d->config == NULL)
+    if (dev->config == NULL)
        return 0;

-    config = (device_config_t *) d->config;
+    config = (device_config_t *) dev->config;

    while (config->type != -1) {
        if (config->type != CONFIG_MAC)
@@ -439,11 +439,11 @@ device_has_config(const device_t *d)
 }

 int
-device_poll(const device_t *d, int x, int y, int z, int b)
+device_poll(const device_t *dev, int x, int y, int z, int b)
 {
    for (uint16_t c = 0; c < DEVICE_MAX; c++) {
        if (devices[c] != NULL) {
-            if (devices[c] == d) {
+            if (devices[c] == dev) {
                if (devices[c]->poll)
                    return (devices[c]->poll(x, y, z, b, 0, 0, device_priv[c]));
            }
@@ -454,11 +454,11 @@ device_poll(const device_t *d, int x, int y, int z, int b)
 }

 void
-device_register_pci_slot(const device_t *d, int device, int type, int inta, int intb, int intc, int intd)
+device_register_pci_slot(const device_t *dev, int device, int type, int inta, int intb, int intc, int intd)
 {
    for (uint16_t c = 0; c < DEVICE_MAX; c++) {
        if (devices[c] != NULL) {
-            if (devices[c] == d) {
+            if (devices[c] == dev) {
                if (devices[c]->register_pci_slot)
                    devices[c]->register_pci_slot(device, type, inta, intb, intc, intd, device_priv[c]);
                return;
@@ -470,38 +470,38 @@ device_register_pci_slot(const device_t *d, int device, int type, int inta, int
 }

 void
-device_get_name(const device_t *d, int bus, char *name)
+device_get_name(const device_t *dev, int bus, char *name)
 {
    char *sbus = NULL;
    char *fbus;
    char *tname;
    char  pbus[8] = { 0 };

-    if (d == NULL)
+    if (dev == NULL)
        return;

    name[0] = 0x00;

    if (bus) {
-        if (d->flags & DEVICE_ISA)
-            sbus = (d->flags & DEVICE_AT) ? "ISA16" : "ISA";
-        else if (d->flags & DEVICE_CBUS)
+        if (dev->flags & DEVICE_ISA)
+            sbus = (dev->flags & DEVICE_AT) ? "ISA16" : "ISA";
+        else if (dev->flags & DEVICE_CBUS)
            sbus = "C-BUS";
-        else if (d->flags & DEVICE_MCA)
+        else if (dev->flags & DEVICE_MCA)
            sbus = "MCA";
-        else if (d->flags & DEVICE_EISA)
+        else if (dev->flags & DEVICE_EISA)
            sbus = "EISA";
-        else if (d->flags & DEVICE_VLB)
+        else if (dev->flags & DEVICE_VLB)
            sbus = "VLB";
-        else if (d->flags & DEVICE_PCI)
+        else if (dev->flags & DEVICE_PCI)
            sbus = "PCI";
-        else if (d->flags & DEVICE_AGP)
+        else if (dev->flags & DEVICE_AGP)
            sbus = "AGP";
-        else if (d->flags & DEVICE_AC97)
+        else if (dev->flags & DEVICE_AC97)
            sbus = "AMR";
-        else if (d->flags & DEVICE_COM)
+        else if (dev->flags & DEVICE_COM)
            sbus = "COM";
-        else if (d->flags & DEVICE_LPT)
+        else if (dev->flags & DEVICE_LPT)
            sbus = "LPT";

        if (sbus != NULL) {
@@ -515,7 +515,7 @@ device_get_name(const device_t *d, int bus, char *name)
                sbus = "ISA";
            else if (!strcmp(sbus, "COM") || !strcmp(sbus, "LPT")) {
                sbus = NULL;
-                strcat(name, d->name);
+                strcat(name, dev->name);
                return;
            }

@@ -525,17 +525,17 @@ device_get_name(const device_t *d, int bus, char *name)
            strcat(pbus, ")");

            /* Allocate the temporary device name string and set it to all zeroes. */
-            tname = (char *) malloc(strlen(d->name) + 1);
-            memset(tname, 0x00, strlen(d->name) + 1);
+            tname = (char *) malloc(strlen(dev->name) + 1);
+            memset(tname, 0x00, strlen(dev->name) + 1);

            /* First strip the bus string with parentheses. */
-            fbus = strstr(d->name, pbus);
-            if (fbus == d->name)
-                strcat(tname, d->name + strlen(pbus) + 1);
+            fbus = strstr(dev->name, pbus);
+            if (fbus == dev->name)
+                strcat(tname, dev->name + strlen(pbus) + 1);
            else if (fbus == NULL)
-                strcat(tname, d->name);
+                strcat(tname, dev->name);
            else {
-                strncat(tname, d->name, fbus - d->name - 1);
+                strncat(tname, dev->name, fbus - dev->name - 1);
                strcat(tname, fbus + strlen(pbus));
            }

@@ -556,9 +556,9 @@ device_get_name(const device_t *d, int bus, char *name)
            free(tname);
            tname = NULL;
        } else
-            strcat(name, d->name);
+            strcat(name, dev->name);
    } else
-        strcat(name, d->name);
+        strcat(name, dev->name);
 }

 void
@@ -771,7 +771,7 @@ device_is_valid(const device_t *device, int m)
    if ((device->flags & DEVICE_AGP) && !machine_has_bus(m, MACHINE_BUS_AGP))
        return 0;

-    if ((device->flags & DEVICE_PS2) && !machine_has_bus(m, MACHINE_BUS_PS2))
+    if ((device->flags & DEVICE_PS2) && !machine_has_bus(m, MACHINE_BUS_PS2_PORTS))
        return 0;

    if ((device->flags & DEVICE_AC97) && !machine_has_bus(m, MACHINE_BUS_AC97))
--- a/src/device/bugger.c
+++ b/src/device/bugger.c
@@ -266,7 +266,7 @@ bug_reset(void)

 /* Handle a WRITE operation to one of our registers. */
 static void
-bug_write(uint16_t port, uint8_t val, void *priv)
+bug_write(uint16_t port, uint8_t val, UNUSED(void *priv))
 {
    switch (port - BUGGER_ADDR) {
        case BUG_CTRL: /* control register */
@@ -284,12 +284,14 @@ bug_write(uint16_t port, uint8_t val, void *priv)
                bug_wdata(val);
            }
            break;
+        default:
+            break;
    }
 }

 /* Handle a READ operation from one of our registers. */
 static uint8_t
-bug_read(uint16_t port, void *priv)
+bug_read(uint16_t port, UNUSED(void *priv))
 {
    uint8_t ret = 0xff;

@@ -319,7 +321,7 @@ bug_read(uint16_t port, void *priv)

 /* Initialize the ISA BusBugger emulator. */
 static void *
-bug_init(const device_t *info)
+bug_init(UNUSED(const device_t *info))
 {
    bugger_log("%s, I/O=%04x\n", info->name, BUGGER_ADDR);

--- a/src/device/cartridge.c
+++ b/src/device/cartridge.c
@@ -29,8 +29,7 @@
 #include <86box/machine.h>
 #include <86box/cartridge.h>

-typedef struct
-{
+typedef struct cart_t {
    uint8_t *buf;
    uint32_t base;
 } cart_t;
@@ -68,7 +67,7 @@ cart_read(uint32_t addr, void *priv)
 }

 static void
-cart_load_error(int drive, char *fn)
+cart_load_error(int drive, UNUSED(char *fn))
 {
    cartridge_log("Cartridge: could not load '%s'\n", fn);
    memset(cart_fns[drive], 0, sizeof(cart_fns[drive]));
--- a/src/device/cassette.c
+++ b/src/device/cassette.c
@@ -544,7 +544,7 @@ pc_cas_set_out(pc_cassette_t *cas, unsigned char val)
 }

 void
-pc_cas_print_state(const pc_cassette_t *cas)
+pc_cas_print_state(UNUSED(const pc_cassette_t *cas))
 {
    cassette_log("%s %s %lu %s %lu\n", (cas->fname != NULL) ? cas->fname : "<none>", cas->pcm ? "pcm" : "cas", cas->srate, cas->save ? "save" : "load", cas->position);
 }
@@ -552,9 +552,8 @@ pc_cas_print_state(const pc_cassette_t *cas)
 static void
 pc_cas_clock_pcm(pc_cassette_t *cas, unsigned long cnt)
 {
-    unsigned long i;
-    unsigned long n;
-    int           v = 0;
+    uint64_t n;
+    int      v = 0;

    n = cas->srate * cnt + cas->clk_pcm;

@@ -567,11 +566,11 @@ pc_cas_clock_pcm(pc_cassette_t *cas, unsigned long cnt)
    }

    if (cas->save) {
-        for (i = 0; i < n; i++) {
+        for (uint64_t i = 0; i < n; i++) {
            pc_cas_write_smp(cas, cas->pcm_out_val);
        }
    } else {
-        for (i = 0; i < n; i++) {
+        for (uint64_t i = 0; i < n; i++) {
            v = pc_cas_read_smp(cas);
        }

@@ -642,7 +641,7 @@ pc_cas_advance(pc_cassette_t *cas)
 }

 static void
-cassette_close(void *p)
+cassette_close(UNUSED(void *priv))
 {
    if (cassette != NULL) {
        free(cassette);
@@ -664,7 +663,7 @@ cassette_callback(void *p)
 }

 static void *
-cassette_init(const device_t *info)
+cassette_init(UNUSED(const device_t *info))
 {
    cassette = NULL;

--- a/src/device/clock_ics9xxx.c
+++ b/src/device/clock_ics9xxx.c
@@ -26,6 +26,7 @@
 #include <86box/i2c.h>
 #include "cpu.h"
 #include <86box/clock.h>
+#include <86box/plat_unused.h>

 #ifdef ENABLE_ICS9xxx_LOG
 int ics9xxx_do_log = ENABLE_ICS9xxx_LOG;
@@ -51,26 +52,26 @@ ics9xxx_log(const char *fmt, ...)
    ,
 #define agp_div ram_mult /* temporarily saves space while neither field matters */

-typedef struct {
+typedef struct ics9xxx_frequency_t {
    uint16_t bus      : 15;
    uint8_t  ram_mult : 2; /* change to full float when this becomes useful */
    uint8_t  pci_div  : 3;
 } ics9xxx_frequency_t;

-typedef struct {
+typedef struct ics9xxx_model_t {
 #if defined(ENABLE_ICS9xxx_LOG) || defined(ENABLE_ICS9xxx_DETECT)
    const char *name; /* populated by macro */
 #endif
    uint8_t max_reg : 3;        /* largest register index */
    uint8_t regs[7];            /* default registers */
-    struct {                    /* for each hardware frequency select bit [FS0:FS4]: */
+    struct fs_regs {            /* for each hardware frequency select bit [FS0:FS4]: */
        uint8_t normal_reg : 3; /* which register (or -1) for non-inverted input (FSn) */
        uint8_t normal_bit : 3; /* which bit (0-7) for non-inverted input (FSn) */
        uint8_t inv_reg    : 3; /* which register (or -1) for inverted input (FSn#) */
        uint8_t inv_bit    : 3; /* which bit (0-7) for inverted input (FSn#) */
    } fs_regs[5];
    uint8_t normal_bits_fixed : 1; /* set to 1 if the non-inverted bits are straps (hardware select only) */
-    struct {                       /* hardware select bit, which should be cleared for hardware select (latched inputs), or set for programming */
+    struct hw_select {             /* hardware select bit, which should be cleared for hardware select (latched inputs), or set for programming */
        uint8_t normal_reg : 3;    /* which register (or -1) */
        uint8_t normal_bit : 3;    /* which bit (0-7) */
    } hw_select;
@@ -79,7 +80,7 @@ typedef struct {
    const ics9xxx_frequency_t *frequencies;     /* frequency table, if not using another model's table */
 } ics9xxx_model_t;

-typedef struct {
+typedef struct ics9xxx_t {
    uint8_t          model_idx;
    ics9xxx_model_t *model;
    device_t        *dyn_device;
@@ -941,7 +942,10 @@ ics9xxx_detect(ics9xxx_t *dev)
    if (!(dev->regs[detect_reg] & 0x40))
        pclog("Bit 3 of register %d is clear, probably in hardware select mode!\n", detect_reg);

-    uint8_t              i = 0, matches = 0, val, bitmask;
+    uint8_t              i = 0;
+    uint8_t              matches = 0;
+    uint8_t              val;
+    uint8_t              bitmask;
    ics9xxx_frequency_t *frequencies_ptr;
    uint32_t             delta;
    for (uint8_t j = 0; j < ICS9xxx_MAX; j++) {
@@ -983,7 +987,7 @@ ics9xxx_detect(ics9xxx_t *dev)
 #endif

 static uint8_t
-ics9xxx_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+ics9xxx_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    ics9xxx_t *dev = (ics9xxx_t *) priv;

@@ -995,7 +999,7 @@ ics9xxx_start(void *bus, uint8_t addr, uint8_t read, void *priv)
 }

 static uint8_t
-ics9xxx_read(void *bus, uint8_t addr, void *priv)
+ics9xxx_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    ics9xxx_t *dev = (ics9xxx_t *) priv;
    uint8_t    ret = 0xff;
@@ -1049,7 +1053,7 @@ ics9xxx_set(ics9xxx_t *dev, uint8_t val)
 }

 static uint8_t
-ics9xxx_write(void *bus, uint8_t addr, uint8_t data, void *priv)
+ics9xxx_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
 {
    ics9xxx_t *dev = (ics9xxx_t *) priv;

--- a/src/device/hasp.c
+++ b/src/device/hasp.c
@@ -52,9 +52,11 @@ enum {
    HASP_TYPE_SAVQUEST = 0
 };

-typedef struct {
-    const uint8_t *password, *prodinfo;
-    const uint8_t  password_size, prodinfo_size;
+typedef struct hasp_type_t {
+    const uint8_t *password;
+    const uint8_t *prodinfo;
+    const uint8_t  password_size;
+    const uint8_t  prodinfo_size;
 } hasp_type_t;

 typedef struct
@@ -62,8 +64,13 @@ typedef struct
    void              *lpt;
    const hasp_type_t *type;

-    int     index, state, passindex, passmode, prodindex;
-    uint8_t tmppass[0x29], status;
+    int     index;
+    int     state;
+    int     passindex;
+    int     passmode;
+    int     prodindex;
+    uint8_t tmppass[0x29];
+    uint8_t status;
 } hasp_t;

 static const hasp_type_t hasp_types[] = {
@@ -131,6 +138,8 @@ hasp_write_data(uint8_t val, void *priv)
                return;
            }
            break;
+        default:
+            break;
    }

    dev->status = 0;
@@ -163,6 +172,8 @@ hasp_write_data(uint8_t val, void *priv)
                       I guessed the implicit ones with a bit of trial and error */
                    dev->status = 0x20;
                    return;
+                default:
+                    break;
            }
        }

@@ -199,6 +210,8 @@ hasp_write_data(uint8_t val, void *priv)
                /* again, just the relevant bits instead of the true values */
                dev->status = 0x20;
                break;
+            default:
+                break;
        }
    } else if (dev->state == HASP_STATE_PASSWORD_END) {
        if (val & 1) {
--- a/src/device/hwm_gl518sm.c
+++ b/src/device/hwm_gl518sm.c
@@ -27,6 +27,8 @@
 #include <86box/io.h>
 #include <86box/i2c.h>
 #include <86box/hwm.h>
+#include <86box/plat_unused.h>
+

 #define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
 /* Formulas and factors derived from Linux's gl518sm.c driver. */
@@ -34,14 +36,16 @@
 #define GL518SM_VOLTAGE_TO_REG(v) ((uint8_t) round((v) / 19.0))
 #define GL518SM_VDD_TO_REG(v)     ((uint8_t) (((v) *4) / 95.0))

-typedef struct {
+typedef struct gl518sm_t {
    uint32_t      local;
    hwm_values_t *values;

    uint16_t regs[32];
    uint8_t  addr_register : 5;

-    uint8_t i2c_addr : 7, i2c_state : 2, i2c_enabled : 1;
+    uint8_t i2c_addr : 7;
+    uint8_t i2c_state : 2;
+    uint8_t i2c_enabled : 1;
 } gl518sm_t;

 static uint8_t  gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv);
@@ -85,7 +89,7 @@ gl518sm_remap(gl518sm_t *dev, uint8_t addr)
 }

 static uint8_t
-gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+gl518sm_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    gl518sm_t *dev = (gl518sm_t *) priv;

@@ -95,7 +99,7 @@ gl518sm_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
 }

 static uint8_t
-gl518sm_i2c_read(void *bus, uint8_t addr, void *priv)
+gl518sm_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    gl518sm_t *dev  = (gl518sm_t *) priv;
    uint16_t   read = gl518sm_read(dev, dev->addr_register);
@@ -159,7 +163,7 @@ gl518sm_read(gl518sm_t *dev, uint8_t reg)
 }

 static uint8_t
-gl518sm_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
+gl518sm_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
 {
    gl518sm_t *dev = (gl518sm_t *) priv;

--- a/src/device/hwm_lm75.c
+++ b/src/device/hwm_lm75.c
@@ -25,6 +25,7 @@
 #include <86box/device.h>
 #include <86box/i2c.h>
 #include <86box/hwm.h>
+#include <86box/plat_unused.h>

 #define LM75_TEMP_TO_REG(t) ((t) << 8)

@@ -47,7 +48,7 @@ lm75_log(const char *fmt, ...)
 #endif

 static uint8_t
-lm75_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+lm75_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    lm75_t *dev = (lm75_t *) priv;

@@ -74,7 +75,7 @@ lm75_read(lm75_t *dev, uint8_t reg)
 }

 static uint8_t
-lm75_i2c_read(void *bus, uint8_t addr, void *priv)
+lm75_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    lm75_t *dev = (lm75_t *) priv;
    uint8_t ret = 0;
@@ -103,6 +104,8 @@ lm75_i2c_read(void *bus, uint8_t addr, void *priv)
            case 0x3: /* Tos */
                ret = lm75_read(dev, (dev->i2c_state == 1) ? 0x5 : 0x6);
                break;
+            default:
+                break;
        }
    }

@@ -128,7 +131,7 @@ lm75_write(lm75_t *dev, uint8_t reg, uint8_t val)
 }

 static uint8_t
-lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
+lm75_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t data, void *priv)
 {
    lm75_t *dev = (lm75_t *) priv;

@@ -164,6 +167,9 @@ lm75_i2c_write(void *bus, uint8_t addr, uint8_t data, void *priv)
            case 0x3: /* Tos */
                lm75_write(dev, (dev->i2c_state == 1) ? 0x5 : 0x6, data);
                break;
+
+            default:
+                break;
        }
    }

--- a/src/device/hwm_lm78.c
+++ b/src/device/hwm_lm78.c
@@ -27,6 +27,7 @@
 #include <86box/timer.h>
 #include <86box/machine.h>
 #include <86box/nvr.h>
+#include <86box/plat_unused.h>
 #include "cpu.h"
 #include <86box/i2c.h>
 #include <86box/hwm.h>
@@ -48,7 +49,7 @@
 #define LM78_NEG_VOLTAGE(v, r)  (v * (604.0 / ((double) r)))                                /* negative voltage formula from the W83781D datasheet */
 #define LM78_NEG_VOLTAGE2(v, r) (((3600 + v) * (((double) r) / (((double) r) + 56.0))) - v) /* negative voltage formula from the W83782D datasheet */

-typedef struct {
+typedef struct lm78_t {
    uint32_t      local;
    hwm_values_t *values;
    device_t     *lm75[2];
@@ -56,10 +57,10 @@ typedef struct {

    uint8_t regs[256];
    union {
-        struct {
+        struct w83782d {
            uint8_t regs[2][16];
        } w83782d;
-        struct {
+        struct as99127f {
            uint8_t regs[3][128];

            uint8_t  nvram[1024], nvram_i2c_state : 2, nvram_updated : 1;
@@ -69,9 +70,12 @@ typedef struct {
            uint8_t security_i2c_state : 1, security_addr_register : 7;
        } as99127f;
    };
-    uint8_t addr_register, data_register;
+    uint8_t addr_register;
+    uint8_t data_register;

-    uint8_t i2c_addr : 7, i2c_state : 1, i2c_enabled : 1;
+    uint8_t i2c_addr : 7;
+    uint8_t i2c_state : 1;
+    uint8_t i2c_enabled : 1;
 } lm78_t;

 static void lm78_remap(lm78_t *dev, uint8_t addr);
@@ -114,7 +118,7 @@ lm78_nvram(lm78_t *dev, uint8_t save)
 }

 static uint8_t
-lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+lm78_nvram_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -124,7 +128,7 @@ lm78_nvram_start(void *bus, uint8_t addr, uint8_t read, void *priv)
 }

 static uint8_t
-lm78_nvram_read(void *bus, uint8_t addr, void *priv)
+lm78_nvram_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;
    uint8_t ret = 0xff;
@@ -158,7 +162,7 @@ lm78_nvram_read(void *bus, uint8_t addr, void *priv)
 }

 static uint8_t
-lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
+lm78_nvram_write(UNUSED(void *bus), uint8_t addr, uint8_t val, void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -195,7 +199,7 @@ lm78_nvram_write(void *bus, uint8_t addr, uint8_t val, void *priv)
 }

 static uint8_t
-lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+lm78_security_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -205,7 +209,7 @@ lm78_security_start(void *bus, uint8_t addr, uint8_t read, void *priv)
 }

 static uint8_t
-lm78_security_read(void *bus, uint8_t addr, void *priv)
+lm78_security_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -213,7 +217,7 @@ lm78_security_read(void *bus, uint8_t addr, void *priv)
 }

 static uint8_t
-lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
+lm78_security_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t val, void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -229,6 +233,8 @@ lm78_security_write(void *bus, uint8_t addr, uint8_t val, void *priv)
            case 0xe7:
                /* read-only registers */
                return 1;
+            default:
+                break;
        }

        dev->as99127f.regs[2][dev->as99127f.security_addr_register++] = val;
@@ -316,7 +322,7 @@ lm78_reset(void *priv)
 }

 static uint8_t
-lm78_i2c_start(void *bus, uint8_t addr, uint8_t read, void *priv)
+lm78_i2c_start(UNUSED(void *bus), UNUSED(uint8_t addr), UNUSED(uint8_t read), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -405,7 +411,7 @@ lm78_isa_read(uint16_t port, void *priv)
 }

 static uint8_t
-lm78_i2c_read(void *bus, uint8_t addr, void *priv)
+lm78_i2c_read(UNUSED(void *bus), UNUSED(uint8_t addr), void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -446,6 +452,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
            case 0x20:
                val &= 0x7f;
                break;
+            default:
+                break;
        }

        dev->as99127f.regs[0][reg] = val;
@@ -477,6 +485,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
                    case 0x5f:
                        /* read-only registers */
                        return 0;
+                    default:
+                        break;
                }

                dev->w83782d.regs[0][reg & 0x0f] = val;
@@ -497,6 +507,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
                    case 0x5f:
                        /* read-only registers */
                        return 0;
+                    default:
+                        break;
                }

                dev->w83782d.regs[1][reg & 0x0f] = val;
@@ -559,6 +571,8 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
            if (!(dev->local & LM78_WINBOND))
                return 0;
            break;
+        default:
+            break;
    }

    if ((reg >= 0x60) && (reg <= 0x94)) /* write auto-increment value RAM registers to their non-auto-increment locations */
@@ -613,6 +627,9 @@ lm78_write(lm78_t *dev, uint8_t reg, uint8_t val, uint8_t bank)
                    i2c_sethandler(i2c_smbus, (val & 0xf8) >> 1, 4, lm78_nvram_start, lm78_nvram_read, lm78_nvram_write, NULL, dev);
            }
            break;
+
+        default:
+            break;
    }

    return 1;
@@ -644,7 +661,7 @@ lm78_isa_write(uint16_t port, uint8_t val, void *priv)
 }

 static uint8_t
-lm78_i2c_write(void *bus, uint8_t addr, uint8_t val, void *priv)
+lm78_i2c_write(UNUSED(void *bus), UNUSED(uint8_t addr), uint8_t val, void *priv)
 {
    lm78_t *dev = (lm78_t *) priv;

@@ -694,13 +711,16 @@ lm78_as99127f_write(void *priv, uint8_t reg, uint8_t val)
                resetx86();
            }
            break;
+
+        default:
+            break;
    }

    return 1;
 }

 static void
-lm78_reset_timer(void *priv)
+lm78_reset_timer(UNUSED(void *priv))
 {
    pc_reset_hard();
 }
--- a/src/device/hwm_vt82c686.c
+++ b/src/device/hwm_vt82c686.c
@@ -25,6 +25,7 @@
 #include <86box/device.h>
 #include <86box/io.h>
 #include <86box/hwm.h>
+#include <86box/plat_unused.h>

 #define CLAMP(a, min, max) (((a) < (min)) ? (min) : (((a) > (max)) ? (max) : (a)))
 /* Formulas and factors derived from Linux's via686a.c driver. */
@@ -32,7 +33,7 @@
 #define VT82C686_TEMP_TO_REG(t)       (-1.160370e-10 * (t * t * t * t * t * t) + 3.193693e-08 * (t * t * t * t * t) - 1.464447e-06 * (t * t * t * t) - 2.525453e-04 * (t * t * t) + 1.424593e-02 * (t * t) + 2.148941e+00 * t + 7.275808e+01)
 #define VT82C686_VOLTAGE_TO_REG(v, f) CLAMP((((v) * (2.628 / (f))) - 120.5) / 25, 0, 255)

-typedef struct {
+typedef struct vt82c686_t {
    hwm_values_t *values;

    uint8_t  enable;
@@ -113,6 +114,9 @@ vt82c686_write(uint16_t port, uint8_t val, void *priv)
        case 0x48:
            val &= 0x7f;
            break;
+
+        default:
+            break;
    }

    dev->regs[reg] = val;
@@ -143,6 +147,9 @@ vt82c686_hwm_write(uint8_t addr, uint8_t val, void *priv)
        case 0x74:
            dev->enable = val & 0x01;
            break;
+
+        default:
+            break;
    }

    if (dev->enable && dev->io_base)
@@ -174,7 +181,7 @@ vt82c686_close(void *priv)
 }

 static void *
-vt82c686_init(const device_t *info)
+vt82c686_init(UNUSED(const device_t *info))
 {
    vt82c686_t *dev = (vt82c686_t *) malloc(sizeof(vt82c686_t));
    memset(dev, 0, sizeof(vt82c686_t));
--- a/src/device/i2c.c
+++ b/src/device/i2c.c
@@ -38,9 +38,10 @@ typedef struct _i2c_ {
    struct _i2c_ *prev, *next;
 } i2c_t;

-typedef struct {
+typedef struct i2c_bus_t {
    char  *name;
-    i2c_t *devices[NADDRS], *last[NADDRS];
+    i2c_t *devices[NADDRS];
+    i2c_t *last[NADDRS];
 } i2c_bus_t;

 void *i2c_smbus;
--- a/src/device/i2c_gpio.c
+++ b/src/device/i2c_gpio.c
@@ -24,11 +24,18 @@
 #include <86box/86box.h>
 #include <86box/i2c.h>

-typedef struct {
+typedef struct i2c_gpio_t {
    char   *bus_name;
    void   *i2c;
-    uint8_t prev_scl, prev_sda, slave_sda, started,
-        slave_addr_received, slave_addr, slave_read, pos, byte;
+    uint8_t prev_scl;
+    uint8_t prev_sda;
+    uint8_t slave_sda;
+    uint8_t started;
+    uint8_t slave_addr_received;
+    uint8_t slave_addr;
+    uint8_t slave_read;
+    uint8_t pos;
+    uint8_t byte;
 } i2c_gpio_t;

 #ifdef ENABLE_I2C_GPIO_LOG
@@ -136,6 +143,9 @@ i2c_gpio_set(void *dev_handle, uint8_t scl, uint8_t sda)
                    dev->slave_sda = !i2c_write(dev->i2c, dev->slave_addr, dev->byte);
                    i2c_gpio_log(2, "I2C GPIO %s: Write %02X %sACK\n", dev->bus_name, dev->byte, dev->slave_sda ? "N" : "");
                    break;
+                
+                default:
+                    break;
            }
        } else if (dev->pos == 9) {
            switch (dev->slave_read) {
--- a/src/device/ibm_5161.c
+++ b/src/device/ibm_5161.c
@@ -26,11 +26,11 @@
 #include <86box/pci.h>
 #include <86box/timer.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/port_92.h>
 #include <86box/machine.h>

-typedef struct
-{
+typedef struct ibm_5161_t {
    uint8_t regs[8];
 } ibm_5161_t;

@@ -76,21 +76,24 @@ ibm_5161_in(uint16_t port, void *priv)
                                            0 =On */
            ret = dev->regs[3] & 0x01;
            break;
+
+        default:
+            break;
    }

    return ret;
 }

 static void
-ibm_5161_close(void *p)
+ibm_5161_close(void *priv)
 {
-    ibm_5161_t *dev = (ibm_5161_t *) p;
+    ibm_5161_t *dev = (ibm_5161_t *) priv;

    free(dev);
 }

 static void *
-ibm_5161_init(const device_t *info)
+ibm_5161_init(UNUSED(const device_t *info))
 {
    ibm_5161_t *dev = (ibm_5161_t *) malloc(sizeof(ibm_5161_t));
    memset(dev, 0, sizeof(ibm_5161_t));
--- a/src/device/isamem.c
+++ b/src/device/isamem.c
@@ -112,7 +112,7 @@
 #define EXTRAM_HIGH            1
 #define EXTRAM_XMS             2

-typedef struct {
+typedef struct emsreg_t {
    int8_t        enabled; /* 1=ENABLED */
    uint8_t       page;    /* page# in EMS RAM */
    uint8_t       frame;   /* (varies with board) */
@@ -121,15 +121,15 @@ typedef struct {
    mem_mapping_t mapping; /* mapping entry for page */
 } emsreg_t;

-typedef struct {
+typedef struct ext_ram_t {
    uint32_t base;
    uint8_t *ptr;
 } ext_ram_t;

-typedef struct {
+typedef struct memdev_t {
    const char *name;
-    uint8_t     board : 6, /* board type */
-        reserved      : 2;
+    uint8_t     board    : 6; /* board type */
+    uint8_t     reserved : 2;

    uint8_t flags;
 #define FLAG_CONFIG 0x01 /* card is configured */
@@ -138,12 +138,12 @@ typedef struct {
 #define FLAG_EMS    0x40 /* card has EMS mode enabled */

    uint16_t total_size; /* configured size in KB */
-    uint32_t base_addr,  /* configured I/O address */
-        start_addr,      /* configured memory start */
-        frame_addr;      /* configured frame address */
+    uint32_t base_addr;  /* configured I/O address */
+    uint32_t start_addr; /* configured memory start */
+    uint32_t frame_addr; /* configured frame address */

-    uint16_t ems_size,  /* EMS size in KB */
-        ems_pages;      /* EMS size in pages */
+    uint16_t ems_size;  /* EMS size in KB */
+    uint16_t ems_pages; /* EMS size in pages */
    uint32_t ems_start; /* start of EMS in RAM */

    uint8_t *ram; /* allocated RAM buffer */
@@ -305,6 +305,9 @@ ems_read(uint16_t port, void *priv)

        case 0x0001: /* W/O */
            break;
+
+        default:
+            break;
    }

 #if ISAMEM_DEBUG
@@ -383,6 +386,9 @@ ems_write(uint16_t port, uint8_t val, void *priv)
            if (val)
                dev->flags |= FLAG_CONFIG;
            break;
+        
+        default:
+            break;
    }
 }

@@ -458,6 +464,9 @@ isamem_init(const device_t *info)
            if (!!device_get_config_int("speed"))
                dev->flags |= FLAG_FAST;
            break;
+
+        default:
+            break;
    }

    /* Fix up the memory start address. */
@@ -471,6 +480,7 @@ isamem_init(const device_t *info)
        isamem_log(", FAST");
    if (dev->flags & FLAG_WIDE)
        isamem_log(", 16BIT");
+
    isamem_log(")\n");

    /* Force (back to) 8-bit bus if needed. */
@@ -617,6 +627,7 @@ isamem_init(const device_t *info)
                   dev->base_addr, dev->ems_size, dev->ems_pages);
        if (dev->frame_addr > 0)
            isamem_log(", Frame=%05XH", dev->frame_addr);
+
        isamem_log("\n");

        /*
--- a/src/device/isapnp.c
+++ b/src/device/isapnp.c
@@ -26,6 +26,7 @@
 #include <86box/device.h>
 #include <86box/io.h>
 #include <86box/isapnp.h>
+#include <86box/plat_unused.h>

 #define CHECK_CURRENT_LD()                                  \
    if (!dev->current_ld) {                                 \
@@ -81,34 +82,48 @@ enum {
 typedef struct _isapnp_device_ {
    uint8_t                       number;
    uint8_t                       regs[256];
-    uint8_t                       mem_upperlimit, irq_types, io_16bit, io_len[8];
+    uint8_t                       mem_upperlimit;
+    uint8_t                       irq_types;
+    uint8_t                       io_16bit;
+    uint8_t                       io_len[8];
    const isapnp_device_config_t *defaults;

    struct _isapnp_device_ *next;
 } isapnp_device_t;

 typedef struct _isapnp_card_ {
-    uint8_t  enable, state, csn, id_checksum, serial_read, serial_read_pair, serial_read_pos, *rom;
-    uint16_t rom_pos, rom_size;
+    uint8_t  enable;
+    uint8_t  state;
+    uint8_t  csn;
+    uint8_t  id_checksum;
+    uint8_t  serial_read;
+    uint8_t  serial_read_pair;
+    uint8_t  serial_read_pos;
+    uint8_t *rom;
+    uint16_t rom_pos;
+    uint16_t rom_size;
    void    *priv;

    /* ISAPnP memory and I/O addresses are awkwardly big endian, so we populate this
       structure whenever something on some device changes, and pass it on instead. */
    isapnp_device_config_t config;
-    void (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv);
-    void (*csn_changed)(uint8_t csn, void *priv);
+    void    (*config_changed)(uint8_t ld, isapnp_device_config_t *config, void *priv);
+    void    (*csn_changed)(uint8_t csn, void *priv);
    uint8_t (*read_vendor_reg)(uint8_t ld, uint8_t reg, void *priv);
-    void (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv);
+    void    (*write_vendor_reg)(uint8_t ld, uint8_t reg, uint8_t val, void *priv);

    isapnp_device_t      *first_ld;
    struct _isapnp_card_ *next;
 } isapnp_card_t;

 typedef struct {
-    uint8_t  reg, key_pos : 5;
+    uint8_t  reg;
+    uint8_t  key_pos : 5;
    uint16_t read_data_addr;

-    isapnp_card_t   *first_card, *isolated_card, *current_ld_card;
+    isapnp_card_t   *first_card;
+    isapnp_card_t   *isolated_card;
+    isapnp_card_t   *current_ld_card;
    isapnp_device_t *current_ld;
 } isapnp_t;

@@ -121,36 +136,35 @@ isapnp_device_config_changed(isapnp_card_t *card, isapnp_device_t *ld)

    /* Populate config structure, performing endianness conversion as needed. */
    card->config.activate = ld->regs[0x30] & 0x01;
-    uint8_t i;
    uint8_t reg_base;
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        reg_base                 = 0x40 + (8 * i);
        card->config.mem[i].base = (ld->regs[reg_base] << 16) | (ld->regs[reg_base + 1] << 8);
        card->config.mem[i].size = (ld->regs[reg_base + 3] << 16) | (ld->regs[reg_base + 4] << 8);
        if (ld->regs[reg_base + 2] & 0x01) /* upper limit */
            card->config.mem[i].size -= card->config.mem[i].base;
    }
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        reg_base                   = (i == 0) ? 0x76 : (0x80 + (16 * i));
        card->config.mem32[i].base = (ld->regs[reg_base] << 24) | (ld->regs[reg_base + 1] << 16) | (ld->regs[reg_base + 2] << 8) | ld->regs[reg_base + 3];
        card->config.mem32[i].size = (ld->regs[reg_base + 5] << 24) | (ld->regs[reg_base + 6] << 16) | (ld->regs[reg_base + 7] << 8) | ld->regs[reg_base + 8];
        if (ld->regs[reg_base + 4] & 0x01) /* upper limit */
            card->config.mem32[i].size -= card->config.mem32[i].base;
    }
-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        reg_base = 0x60 + (2 * i);
        if (ld->regs[0x31] & 0x02)
            card->config.io[i].base = 0; /* let us handle I/O range check reads */
        else
            card->config.io[i].base = (ld->regs[reg_base] << 8) | ld->regs[reg_base + 1];
    }
-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        reg_base                  = 0x70 + (2 * i);
        card->config.irq[i].irq   = ld->regs[reg_base];
        card->config.irq[i].level = ld->regs[reg_base + 1] & 0x02;
        card->config.irq[i].type  = ld->regs[reg_base + 1] & 0x01;
    }
-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        reg_base                = 0x74 + i;
        card->config.dma[i].dma = ld->regs[reg_base];
    }
@@ -169,10 +183,9 @@ isapnp_reset_ld_config(isapnp_device_t *ld)

    /* Populate configuration registers. */
    ld->regs[0x30] = !!config->activate;
-    uint8_t  i;
    uint8_t reg_base;
    uint32_t size;
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        reg_base               = 0x40 + (8 * i);
        ld->regs[reg_base]     = config->mem[i].base >> 16;
        ld->regs[reg_base + 1] = config->mem[i].base >> 8;
@@ -182,7 +195,7 @@ isapnp_reset_ld_config(isapnp_device_t *ld)
        ld->regs[reg_base + 3] = size >> 16;
        ld->regs[reg_base + 4] = size >> 8;
    }
-    for (i = 0; i < 4; i++) {
+    for (uint8_t i = 0; i < 4; i++) {
        reg_base               = (i == 0) ? 0x76 : (0x80 + (16 * i));
        ld->regs[reg_base]     = config->mem32[i].base >> 24;
        ld->regs[reg_base + 1] = config->mem32[i].base >> 16;
@@ -196,17 +209,17 @@ isapnp_reset_ld_config(isapnp_device_t *ld)
        ld->regs[reg_base + 7] = size >> 8;
        ld->regs[reg_base + 8] = size;
    }
-    for (i = 0; i < 8; i++) {
+    for (uint8_t i = 0; i < 8; i++) {
        reg_base               = 0x60 + (2 * i);
        ld->regs[reg_base]     = config->io[i].base >> 8;
        ld->regs[reg_base + 1] = config->io[i].base;
    }
-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        reg_base               = 0x70 + (2 * i);
        ld->regs[reg_base]     = config->irq[i].irq;
        ld->regs[reg_base + 1] = (!!config->irq[i].level << 1) | !!config->irq[i].type;
    }
-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        reg_base           = 0x74 + i;
        ld->regs[reg_base] = config->dma[i].dma;
    }
@@ -221,15 +234,14 @@ isapnp_reset_ld_regs(isapnp_device_t *ld)
    ld->regs[0x74] = ld->regs[0x75] = ISAPNP_DMA_DISABLED;

    /* Set the upper limit bit on memory ranges which require it. */
-    uint8_t i;
-    for (i = 0; i < 4; i++)
+    for (uint8_t i = 0; i < 4; i++)
        ld->regs[0x42 + (8 * i)] |= !!(ld->mem_upperlimit & (1 << i));
    ld->regs[0x7a] |= !!(ld->mem_upperlimit & (1 << 4));
-    for (i = 1; i < 4; i++)
+    for (uint8_t i = 1; i < 4; i++)
        ld->regs[0x84 + (16 * i)] |= !!(ld->mem_upperlimit & (1 << (4 + i)));

    /* Set the default IRQ type bits. */
-    for (i = 0; i < 2; i++) {
+    for (uint8_t i = 0; i < 2; i++) {
        if (ld->irq_types & (0x1 << (4 * i)))
            ld->regs[0x70 + (2 * i)] = 0x02;
        else if (ld->irq_types & (0x2 << (4 * i)))
@@ -245,14 +257,14 @@ isapnp_reset_ld_regs(isapnp_device_t *ld)
 }

 static uint8_t
-isapnp_read_rangecheck(uint16_t addr, void *priv)
+isapnp_read_rangecheck(UNUSED(uint16_t addr), void *priv)
 {
    isapnp_device_t *dev = (isapnp_device_t *) priv;
    return (dev->regs[0x31] & 0x01) ? 0x55 : 0xaa;
 }

 static uint8_t
-isapnp_read_data(uint16_t addr, void *priv)
+isapnp_read_data(UNUSED(uint16_t addr), void *priv)
 {
    isapnp_t      *dev = (isapnp_t *) priv;
    uint8_t        ret = 0xff;
@@ -418,7 +430,7 @@ isapnp_set_read_data(uint16_t addr, isapnp_t *dev)
 }

 static void
-isapnp_write_addr(uint16_t addr, uint8_t val, void *priv)
+isapnp_write_addr(UNUSED(uint16_t addr), uint8_t val, void *priv)
 {
    isapnp_t      *dev  = (isapnp_t *) priv;
    isapnp_card_t *card = dev->first_card;
@@ -449,7 +461,7 @@ isapnp_write_addr(uint16_t addr, uint8_t val, void *priv)
 }

 static void
-isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
+isapnp_write_data(UNUSED(uint16_t addr), uint8_t val, void *priv)
 {
    isapnp_t        *dev = (isapnp_t *) priv;
    isapnp_card_t   *card;
@@ -681,6 +693,9 @@ isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
                            val |= 0x02;

                        break;
+
+                    default:
+                        break;
                }

                dev->current_ld->regs[dev->reg] = val;
@@ -691,7 +706,7 @@ isapnp_write_data(uint16_t addr, uint8_t val, void *priv)
 }

 static void *
-isapnp_init(const device_t *info)
+isapnp_init(UNUSED(const device_t *info))
 {
    isapnp_t *dev = (isapnp_t *) malloc(sizeof(isapnp_t));
    memset(dev, 0, sizeof(isapnp_t));
@@ -862,6 +877,9 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
                default:
                    isapnp_log("ISAPnP: >%s%s Large resource %02X (length %d)\n", ldn ? ">" : "", in_df ? ">" : "", res, (card->rom[i + 2] << 8) | card->rom[i + 1]);
                    break;
+#else
+                default:
+                    break;
 #endif
            }

@@ -1022,11 +1040,11 @@ isapnp_update_card_rom(void *priv, uint8_t *rom, uint16_t rom_size)
                    card->rom_size = i + 2;
                    break;

-#ifdef ENABLE_ISAPNP_LOG
                default:
+#ifdef ENABLE_ISAPNP_LOG
                    isapnp_log("ISAPnP: >%s%s Small resource %02X (length %d)\n", ldn ? ">" : "", in_df ? ">" : "", res, card->rom[i] & 0x07);
-                    break;
 #endif
+                    break;
            }

            i++; /* header */
--- a/src/device/isartc.c
+++ b/src/device/isartc.c
@@ -90,7 +90,7 @@

 #define ISARTC_DEBUG  0

-typedef struct {
+typedef struct rtcdev_t {
    const char *name;  /* board name */
    uint8_t     board; /* board type */

@@ -103,18 +103,18 @@ typedef struct {
    uint32_t base_addr; /* configured I/O address */

    /* Fields for the specific driver. */
-    void (*f_wr)(uint16_t, uint8_t, void *);
+    void    (*f_wr)(uint16_t, uint8_t, void *);
    uint8_t (*f_rd)(uint16_t, void *);
-    int8_t year; /* register for YEAR value */
-    char   pad[3];
+    int8_t    year; /* register for YEAR value */
+    char      pad[3];

    nvr_t nvr; /* RTC/NVR */
 } rtcdev_t;

 /************************************************************************
- *                                    *
- *            Driver for the NatSemi MM58167 chip.        *
- *                                    *
+ *                                                                      *
+ *            Driver for the NatSemi MM58167 chip.                      *
+ *                                                                      *
 ************************************************************************/
 #define MM67_REGS 32

@@ -427,7 +427,6 @@ mm67_write(uint16_t port, uint8_t val, void *priv)
 {
    rtcdev_t *dev = (rtcdev_t *) priv;
    int       reg = port - dev->base_addr;
-    int       i;

 #if ISARTC_DEBUG
    isartc_log("ISARTC: write(%04x, %02x)\n", port - dev->base_addr, val);
@@ -452,7 +451,7 @@ mm67_write(uint16_t port, uint8_t val, void *priv)

        case MM67_RSTRAM:
            if (val == 0xff) {
-                for (i = MM67_AL_MSEC; i <= MM67_AL_MON; i++)
+                for (uint8_t i = MM67_AL_MSEC; i <= MM67_AL_MON; i++)
                    dev->nvr.regs[i] = RTC_BCD(0);
                dev->nvr.regs[MM67_DOW] = RTC_BCD(1);
                dev->nvr.regs[MM67_DOM] = RTC_BCD(1);
@@ -500,9 +499,9 @@ mm67_write(uint16_t port, uint8_t val, void *priv)
 }

 /************************************************************************
- *                                    *
- *            Generic code for all supported chips.        *
- *                                    *
+ *                                                                      *
+ *            Generic code for all supported chips.                     *
+ *                                                                      *
 ************************************************************************/

 /* Initialize the device for use. */
--- a/src/device/kbc_at.c
+++ b/src/device/kbc_at.c
@@ -29,6 +29,7 @@
 #include <86box/io.h>
 #include <86box/pic.h>
 #include <86box/pit.h>
+#include <86box/plat_unused.h>
 #include <86box/ppi.h>
 #include <86box/mem.h>
 #include <86box/device.h>
@@ -80,6 +81,7 @@
 #define KBC_VEN_ACER       0x20
 #define KBC_VEN_NCR        0x24
 #define KBC_VEN_ALI        0x28
+#define KBC_VEN_SIEMENS    0x2c
 #define KBC_VEN_MASK       0x3c

 #define FLAG_CLOCK         0x01
@@ -103,12 +105,27 @@ enum {
    STATE_SCAN_AUX         /* KBC is waiting for the auxiliary command response. */
 };

-typedef struct {
-    uint8_t state, command, command_phase, status,
-            wantdata, ib, ob, sc_or,
-            mem_addr, p1, p2, old_p2,
-            misc_flags, ami_flags, key_ctrl_queue_start, key_ctrl_queue_end,
-            val, channel, stat_hi, pending;
+typedef struct atkbc_t {
+    uint8_t state;
+    uint8_t command;
+    uint8_t command_phase;
+    uint8_t status;
+    uint8_t wantdata;
+    uint8_t ib;
+    uint8_t ob;
+    uint8_t sc_or;
+    uint8_t mem_addr;
+    uint8_t p1;
+    uint8_t p2;
+    uint8_t old_p2;
+    uint8_t misc_flags;
+    uint8_t ami_flags;
+    uint8_t key_ctrl_queue_start;
+    uint8_t key_ctrl_queue_end;
+    uint8_t val;
+    uint8_t channel;
+    uint8_t stat_hi;
+    uint8_t pending;

    uint8_t mem[0x100];

@@ -279,6 +296,8 @@ kbc_translate(atkbc_t *dev, uint8_t val)
        case 0x4d:
            t3100e_notify_set(0x0f);
            break; /* Right */
+        default:
+            break;
    }

    kbc_at_log("ATkbc: translate is %s, ", translate ? "on" : "off");
@@ -305,7 +324,7 @@ static void
 kbc_send_to_ob(atkbc_t *dev, uint8_t val, uint8_t channel, uint8_t stat_hi)
 {
    uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
-    int temp = (channel == 1) ? kbc_translate(dev, val) : val;
+    int temp = (channel == 1) ? kbc_translate(dev, val) : ((int) val);

    if (temp == -1)
        return;
@@ -399,10 +418,14 @@ kbc_scan_kbd_at(atkbc_t *dev)
                kbc_ibf_process(dev);
        /* AT mode. */
        } else {
-            // dev->t = dev->mem[0x28];
+#if 0
+            dev->t = dev->mem[0x28];
+#endif
            if (dev->mem[0x2e] != 0x00) {
-                // if (!(dev->t & 0x02))
-                    // return;
+#if 0
+                if (!(dev->t & 0x02))
+                    return;
+#endif
                dev->mem[0x2e] = 0x00;
            }
            dev->p2 &= 0xbf;
@@ -422,7 +445,8 @@ kbc_scan_kbd_at(atkbc_t *dev)
    }
 }

-static void    write_p2(atkbc_t *dev, uint8_t val);
+static void
+write_p2(atkbc_t *dev, uint8_t val);

 static void
 kbc_at_poll_at(atkbc_t *dev)
@@ -466,7 +490,9 @@ at_main_ibf:
            /* Keyboard controller command want to output a single byte. */
            kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
            kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
-            // dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
+#if 0
+            dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
+#endif
            dev->state = STATE_MAIN_IBF;
            dev->pending = 0;
            goto at_main_ibf;
@@ -608,7 +634,9 @@ ps2_main_ibf:
            /* Keyboard controller command want to output a single byte. */
            kbc_at_log("ATkbc: %02X coming from channel %i with high status %02X\n", dev->val, dev->channel, dev->stat_hi);
            kbc_send_to_ob(dev, dev->val, dev->channel, dev->stat_hi);
-            // dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
+#if 0
+            dev->state = (dev->pending == 2) ? STATE_KBC_AMI_OUT : STATE_MAIN_IBF;
+#endif
            dev->state = STATE_MAIN_IBF;
            dev->pending = 0;
            goto ps2_main_ibf;
@@ -720,6 +748,12 @@ write_p2(atkbc_t *dev, uint8_t val)
                flushmmucache();
                if (kbc_ven == KBC_VEN_ALI)
                    smbase = 0x00030000;
+                /* Yes, this is a hack, but until someone gets ahold of the real PCD-2L
+                   and can find out what they actually did to make it boot from FFFFF0
+                   correctly despite A20 being gated when the CPU is reset, this will
+                   have to do. */
+                else if (kbc_ven == KBC_VEN_SIEMENS)
+                    loadcs(0xF000);
            }
        }
    }
@@ -1004,7 +1038,7 @@ write60_ami(void *priv, uint8_t val)
    switch (dev->command) {
        /* 0x40 - 0x5F are aliases for 0x60-0x7F */
        case 0x40 ... 0x5f:
-            kbc_at_log("ATkbc: AMI - alias write to %08X\n", dev->command);
+            kbc_at_log("ATkbc: AMI - alias write to %02X\n", dev->command & 0x1f);
            dev->mem[(dev->command & 0x1f) + 0x20] = val;
            if (dev->command == 0x60)
                write_cmd(dev, val);
@@ -1041,6 +1075,9 @@ write60_ami(void *priv, uint8_t val)
                kbc_at_do_poll = kbc_at_poll_at;
            }
            return 0;
+
+        default:
+            break;
    }

    return 1;
@@ -1140,7 +1177,7 @@ write64_ami(void *priv, uint8_t val)
            break;

        case 0xaf: /* set extended controller RAM */
-            if (kbc_ven != KBC_VEN_ALI) {
+            if ((kbc_ven != KBC_VEN_SIEMENS) && (kbc_ven != KBC_VEN_ALI)) {
                kbc_at_log("ATkbc: set extended controller RAM\n");
                dev->wantdata      = 1;
                dev->state         = STATE_KBC_PARAM;
@@ -1244,13 +1281,49 @@ write64_ami(void *priv, uint8_t val)
        case 0xef: /* ??? - sent by AMI486 */
            kbc_at_log("ATkbc: ??? - sent by AMI486\n");
            return 0;
+
+        default:
+            break;
    }

    return write64_generic(dev, val);
 }

 static uint8_t
-write60_quadtel(void *priv, uint8_t val)
+write64_siemens(void *priv, uint8_t val)
+{
+    atkbc_t *dev     = (atkbc_t *) priv;
+
+    switch (val) {
+        case 0x92: /*Siemens Award - 92 sent by PCD-2L BIOS*/
+            kbc_at_log("Siemens Award - 92 sent by PCD-2L BIOS\n");
+            return 0;
+
+        case 0x94: /*Siemens Award - 94 sent by PCD-2L BIOS*/
+            kbc_at_log("Siemens Award - 94 sent by PCD-2L BIOS\n");
+            return 0;
+
+        case 0x9a: /*Siemens Award - 9A sent by PCD-2L BIOS*/
+            kbc_at_log("Siemens Award - 9A sent by PCD-2L BIOS\n");
+            return 0;
+
+        case 0x9c: /*Siemens Award - 9C sent by PCD-2L BIOS*/
+            kbc_at_log("Siemens Award - 9C sent by PCD-2L BIOS\n");
+            return 0;
+
+        case 0xa9: /*Siemens Award - A9 sent by PCD-2L BIOS*/
+            kbc_at_log("Siemens Award - A9 sent by PCD-2L BIOS\n");
+            return 0;
+
+        default:
+            break;
+    }
+
+    return write64_ami(dev, val);
+}
+
+static uint8_t
+write60_quadtel(void *priv, UNUSED(uint8_t val))
 {
    atkbc_t *dev = (atkbc_t *) priv;

@@ -1258,6 +1331,8 @@ write60_quadtel(void *priv, uint8_t val)
        case 0xcf: /*??? - sent by MegaPC BIOS*/
            kbc_at_log("ATkbc: ??? - sent by MegaPC BIOS\n");
            return 0;
+        default:
+            break;
    }

    return 1;
@@ -1280,6 +1355,9 @@ write64_olivetti(void *priv, uint8_t val)
            kbc_delay_to_ob(dev, (0x0c | (is386 ? 0x00 : 0x80)) & 0xdf, 0, 0x00);
            dev->p1 = ((dev->p1 + 1) & 3) | (dev->p1 & 0xfc);
            return 0;
+
+        default:
+            break;
    }

    return write64_generic(dev, val);
@@ -1300,6 +1378,9 @@ write64_quadtel(void *priv, uint8_t val)
            dev->wantdata  = 1;
            dev->state     = STATE_KBC_PARAM;
            return 0;
+
+        default:
+            break;
    }

    return write64_generic(dev, val);
@@ -1315,6 +1396,9 @@ write60_toshiba(void *priv, uint8_t val)
            kbc_at_log("ATkbc: T3100e - set color/mono switch\n");
            t3100e_mono_set(val);
            return 0;
+
+        default:
+            break;
    }

    return 1;
@@ -1405,6 +1489,9 @@ write64_toshiba(void *priv, uint8_t val)
            dev->p1 = (t3100e_mono_get() & 1) ? 0xff : 0xbf;
            kbc_delay_to_ob(dev, dev->p1, 0, 0x00);
            return 0;
+
+        default:
+            break;
    }

    return write64_generic(dev, val);
@@ -1682,13 +1769,15 @@ static void
 kbc_at_write(uint16_t port, uint8_t val, void *priv)
 {
    atkbc_t *dev = (atkbc_t *) priv;
+    uint8_t kbc_ven = dev->flags & KBC_VEN_MASK;
+    uint8_t fast_a20 = (kbc_ven != KBC_VEN_SIEMENS);

    kbc_at_log("ATkbc: [%04X:%08X] write(%04X) = %02X\n", CS, cpu_state.pc, port, val);

    switch (port) {
        case 0x60:
            dev->status &= ~STAT_CD;
-            if (dev->wantdata && (dev->command == 0xd1)) {
+            if (fast_a20 && dev->wantdata && (dev->command == 0xd1)) {
                kbc_at_log("ATkbc: write P2\n");

 #if 0
@@ -1718,7 +1807,7 @@ kbc_at_write(uint16_t port, uint8_t val, void *priv)

        case 0x64:
            dev->status |= STAT_CD;
-            if (val == 0xd1) {
+            if (fast_a20 && (val == 0xd1)) {
                kbc_at_log("ATkbc: write P2\n");
                dev->wantdata  = 1;
                dev->state     = STATE_KBC_PARAM;
@@ -1726,6 +1815,9 @@ kbc_at_write(uint16_t port, uint8_t val, void *priv)
                return;
            }
            break;
+
+        default:
+            break;
    }

    dev->ib = val;
@@ -1865,6 +1957,13 @@ kbc_at_init(const device_t *info)
    kbc_award_revision = 0x42;

    switch (dev->flags & KBC_VEN_MASK) {
+        case KBC_VEN_SIEMENS:
+            kbc_ami_revision = '8';
+            kbc_award_revision = 0x42;
+            dev->write60_ven = write60_ami;
+            dev->write64_ven = write64_siemens;
+            break;
+
        case KBC_VEN_ACER:
        case KBC_VEN_GENERIC:
        case KBC_VEN_NCR:
@@ -1922,6 +2021,9 @@ kbc_at_init(const device_t *info)
            dev->write60_ven = write60_toshiba;
            dev->write64_ven = write64_toshiba;
            break;
+
+        default:
+            break;
    }

    max_ports = ((dev->flags & KBC_TYPE_MASK) >= KBC_TYPE_PS2_1) ? 2 : 1;
@@ -1955,6 +2057,20 @@ const device_t keyboard_at_device = {
    .config        = NULL
 };

+const device_t keyboard_at_siemens_device = {
+    .name          = "PC/AT Keyboard",
+    .internal_name = "keyboard_at",
+    .flags         = DEVICE_KBC,
+    .local         = KBC_TYPE_ISA | KBC_VEN_SIEMENS,
+    .init          = kbc_at_init,
+    .close         = kbc_at_close,
+    .reset         = kbc_at_reset,
+    { .available = NULL },
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
+
 const device_t keyboard_at_ami_device = {
    .name          = "PC/AT Keyboard (AMI)",
    .internal_name = "keyboard_at_ami",
--- a/src/device/kbc_at_dev.c
+++ b/src/device/kbc_at_dev.c
@@ -169,6 +169,8 @@ kbc_at_dev_poll(void *priv)
            if (dev->cmd_queue_start == dev->cmd_queue_end)
                dev->state = DEV_STATE_EXECUTE_BAT;
            break;
+        default:
+            break;
    }
 }

--- a/src/device/keyboard.c
+++ b/src/device/keyboard.c
@@ -167,6 +167,9 @@ keyboard_input(int down, uint16_t scan)
                case 0x138: /* Right Alt */
                    shift |= 0x40;
                    break;
+
+                default:
+                    break;
            }
        } else {
            switch (scan & 0x1ff) {
@@ -197,13 +200,18 @@ keyboard_input(int down, uint16_t scan)
                case 0x046:
                    scroll_lock ^= 1;
                    break;
+
+                default:
+                    break;
            }
        }
    }

    /* NOTE: Shouldn't this be some sort of bit shift? An array of 8 unsigned 64-bit integers
             should be enough. */
-    /* recv_key[scan >> 6] |= ((uint64_t) down << ((uint64_t) scan & 0x3fLL)); */
+#if 0
+    recv_key[scan >> 6] |= ((uint64_t) down << ((uint64_t) scan & 0x3fLL));
+#endif

    /* pclog("Received scan code: %03X (%s)\n", scan & 0x1ff, down ? "down" : "up"); */
    recv_key[scan & 0x1ff] = down;
--- a/src/device/keyboard_at.c
+++ b/src/device/keyboard_at.c
@@ -67,7 +67,7 @@ uint8_t keyboard_set3_all_break;

 /* Global keyboard mode:
   Bits 0 - 1 = scan code set. */
-uint8_t        keyboard_mode = 0x02;
+uint8_t keyboard_mode = 0x02;

 static atkbc_dev_t *SavedKbd                        = NULL;

@@ -491,8 +491,8 @@ static void
 keyboard_at_set_scancode_set(void)
 {
    switch (keyboard_mode) {
-        case 0x01:
        default:
+        case 0x01:
            keyboard_set_table(scancode_set1);
            break;

--- a/src/device/keyboard_xt.c
+++ b/src/device/keyboard_xt.c
@@ -68,14 +68,18 @@
 #define KBD_TYPE_PRAVETZ  10
 #define KBD_TYPE_XTCLONE  11

-typedef struct {
+typedef struct xtkbd_t {
    int want_irq;
    int blocked;
    int tandy;

-    uint8_t pa, pb, pd, clock;
+    uint8_t pa;
+    uint8_t pb;
+    uint8_t pd;
+    uint8_t clock;
    uint8_t key_waiting;
-    uint8_t type, pravetz_flags;
+    uint8_t type;
+    uint8_t pravetz_flags;

    pc_timer_t send_delay_timer;
 } xtkbd_t;
@@ -454,6 +458,9 @@ kbd_adddata(uint16_t val)
                case 0x54: /* SysRQ => toggle window */
                    t1000_syskey(0x00, 0x00, 0x08);
                    break;
+
+                default:
+                    break;
            }
        } else
            t1000_syskey(0x04, 0x00, 0x00); /* Reset 'Fn' indicator */
@@ -578,6 +585,9 @@ kbd_write(uint16_t port, uint8_t val, void *priv)
                kbd->pravetz_flags = (kbd->pravetz_flags & ~(1 << bit)) | set;
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -686,6 +696,9 @@ kbd_read(uint16_t port, void *priv)
                ret = kbd->pravetz_flags;
            kbd_log("XTkbd: Port %02X in : %02X\n", port, ret);
            break;
+
+        default:
+            break;
    }

    return ret;
--- a/src/device/mouse.c
+++ b/src/device/mouse.c
@@ -30,8 +30,9 @@
 #include <86box/timer.h>
 #include <86box/gdbstub.h>
 #include <86box/mouse.h>
+#include <86box/plat_unused.h>

-typedef struct {
+typedef struct mouse_t {
    const device_t *device;
 } mouse_t;

@@ -152,7 +153,7 @@ mouse_close(void)
 }

 static void
-mouse_timer_poll(void *priv)
+mouse_timer_poll(UNUSED(void *priv))
 {
    /* Poll at 255 Hz, maximum supported by PS/2 mic. */
    timer_on_auto(&mouse_timer, 1000000.0 / sample_rate);
--- a/src/device/mouse_bus.c
+++ b/src/device/mouse_bus.c
@@ -80,6 +80,7 @@
 #include <86box/timer.h>
 #include <86box/device.h>
 #include <86box/mouse.h>
+#include <86box/plat_unused.h>
 #include <86box/random.h>

 #define IRQ_MASK ((1 << 5) >> dev->irq)
@@ -132,16 +133,26 @@ static const uint8_t periods[4] = { 30, 50, 100, 200 };

 /* Our mouse device. */
 typedef struct mouse {
-    uint8_t current_b, control_val,
-        config_val, sig_val,
-        command_val, pad;
+    uint8_t current_b;
+    uint8_t control_val;
+    uint8_t config_val;
+    uint8_t sig_val;
+    uint8_t command_val;
+    uint8_t pad;

-    int8_t current_x, current_y;
+    int8_t current_x;
+    int8_t current_y;

-    int base, irq, bn, flags,
-        mouse_delayed_dx, mouse_delayed_dy,
-        mouse_buttons, mouse_buttons_last,
-        toggle_counter, timer_enabled;
+    int base;
+    int irq;
+    int bn;
+    int flags;
+    int mouse_delayed_dx;
+    int mouse_delayed_dy;
+    int mouse_buttons;
+    int mouse_buttons_last;
+    int toggle_counter;
+    int timer_enabled;

    double     period;
    pc_timer_t timer; /* mouse event timer */
@@ -216,6 +227,9 @@ lt_read(uint16_t port, void *priv)
            else
                return 0xff;
            break;
+
+        default:
+            break;
    }

    bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
@@ -249,6 +263,7 @@ ms_read(uint16_t port, void *priv)
                case INP_CTRL_COMMAND:
                    value = dev->control_val;
                    break;
+
                default:
                    bm_log("ERROR: Reading data port in unsupported mode 0x%02x\n", dev->control_val);
            }
@@ -263,6 +278,9 @@ ms_read(uint16_t port, void *priv)
        case INP_PORT_CONFIG:
            bm_log("ERROR: Unsupported read from port 0x%04x\n", port);
            break;
+
+        default:
+            break;
    }

    bm_log("DEBUG: read from address 0x%04x, value = 0x%02x\n", port, value);
@@ -355,6 +373,9 @@ lt_write(uint16_t port, uint8_t val, void *priv)
                    dev->control_val &= ~bit; /* Reset */
            }
            break;
+
+        default:
+            break;
    }
 }

@@ -380,6 +401,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
                case INP_CTRL_READ_Y:
                    dev->command_val = val & 0x07;
                    break;
+
                default:
                    bm_log("ERROR: Unsupported command written to port 0x%04x (value = 0x%02x)\n", port, val);
            }
@@ -429,6 +451,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
                            dev->control_val &= INP_PERIOD_MASK;
                            dev->control_val |= (val & ~INP_PERIOD_MASK);
                            return;
+
                        default:
                            bm_log("ERROR: Unsupported period written to port 0x%04x (value = 0x%02x)\n", port, val);
                    }
@@ -436,6 +459,7 @@ ms_write(uint16_t port, uint8_t val, void *priv)
                    dev->control_val = val;

                    break;
+
                default:
                    bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
            }
@@ -444,12 +468,15 @@ ms_write(uint16_t port, uint8_t val, void *priv)
        case INP_PORT_CONFIG:
            bm_log("ERROR: Unsupported write to port 0x%04x (value = 0x%02x)\n", port, val);
            break;
+
+        default:
+            break;
    }
 }

 /* The emulator calls us with an update on the host mouse device. */
 static int
-bm_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
+bm_poll(int x, int y, UNUSED(int z), int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
 {
    mouse_t *dev = (mouse_t *) priv;
    int xor ;
--- a/src/device/mouse_ps2.c
+++ b/src/device/mouse_ps2.c
@@ -23,6 +23,7 @@
 #include <86box/device.h>
 #include <86box/keyboard.h>
 #include <86box/mouse.h>
+#include <86box/plat_unused.h>

 enum {
    MODE_STREAM,
@@ -310,7 +311,7 @@ ps2_write(void *priv)
 }

 static int
-ps2_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
+ps2_poll(int x, int y, int z, int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
 {
    atkbc_dev_t *dev = (atkbc_dev_t *) priv;
    int packet_size = (dev->flags & FLAG_INTMODE) ? 4 : 3;
--- a/src/device/mouse_serial.c
+++ b/src/device/mouse_serial.c
@@ -26,6 +26,7 @@
 #include <86box/timer.h>
 #include <86box/serial.h>
 #include <86box/mouse.h>
+#include <86box/plat_unused.h>

 #define SERMOUSE_PORT 0 /* attach to Serial0 */

@@ -47,27 +48,40 @@ enum {
    REPORT_PHASE_TRANSMIT
 };

-typedef struct {
-    const char *name; /* name of this device */
-    int8_t      type, /* type of this device */
-        port;
-    uint8_t flags, but, /* device flags */
-        want_data,
-        status, format,
-        prompt, on_change,
-        id_len, id[255],
-        data_len, data[5];
-    int abs_x, abs_y,
-        rel_x, rel_y,
-        rel_z,
-        oldb, lastb;
+typedef struct mouse_t {
+    const char *name;  /* name of this device */
+    int8_t      type;  /* type of this device */
+    int8_t      port;
+    uint8_t     flags; /* device flags */
+    uint8_t     but; 
+    uint8_t     want_data;
+    uint8_t     status;
+    uint8_t     format;
+    uint8_t     prompt;
+    uint8_t     on_change;
+    uint8_t     id_len;
+    uint8_t     id[255];
+    uint8_t     data_len;
+    uint8_t     data[5];
+    int         abs_x;
+    int         abs_y;
+    int         rel_x;
+    int         rel_y;
+    int         rel_z;
+    int         oldb;
+    int         lastb;

-    int command_pos, command_phase,
-        report_pos, report_phase,
-        command_enabled, report_enabled;
-    double     transmit_period, report_period,
-               auto_period;
-    pc_timer_t command_timer, report_timer;
+    int        command_pos;
+    int        command_phase;
+    int        report_pos;
+    int        report_phase;
+    int        command_enabled;
+    int        report_enabled;
+    double     transmit_period;
+    double     report_period;
+    double     auto_period;
+    pc_timer_t command_timer;
+    pc_timer_t report_timer;

    serial_t *serial;
 } mouse_t;
@@ -138,8 +152,8 @@ sermouse_transmit_period(mouse_t *dev, int bps, int rps)
        case 5: /* MM Series format: 8 data, odd parity, 1 stop, 1 start */
            word_len = 11;
            break;
-        default:
        case 7: /* Microsoft-compatible format: 7 data, no parity, 1 stop, 1 start */
+        default:
            word_len = 9;
            break;
    }
@@ -158,7 +172,7 @@ sermouse_transmit_period(mouse_t *dev, int bps, int rps)

 /* Callback from serial driver: RTS was toggled. */
 static void
-sermouse_callback(struct serial_s *serial, void *priv)
+sermouse_callback(UNUSED(struct serial_s *serial), void *priv)
 {
    mouse_t *dev = (mouse_t *) priv;

@@ -332,6 +346,9 @@ sermouse_report(int x, int y, int z, int b, mouse_t *dev)
        case 7:
            len = sermouse_data_ms(dev, x, y, z, b);
            break;
+
+        default:
+            break;
    }

    dev->data_len = len;
@@ -527,7 +544,7 @@ sermouse_command_timer(void *priv)
 }

 static int
-sermouse_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
+sermouse_poll(int x, int y, int z, int b, UNUSED(double abs_x), UNUSED(double abs_y), void *priv)
 {
    mouse_t *dev = (mouse_t *) priv;

@@ -613,7 +630,7 @@ ltsermouse_switch_baud_rate(mouse_t *dev, int phase)
 }

 static void
-ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
+ltsermouse_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
 {
    mouse_t *dev = (mouse_t *) priv;

@@ -644,6 +661,8 @@ ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
                }
                ltsermouse_switch_baud_rate(dev, PHASE_BAUD_RATE);
                break;
+            default:
+                break;
        }
    else
        switch (data) {
@@ -728,11 +747,14 @@ ltsermouse_write(struct serial_s *serial, void *priv, uint8_t data)
            case 0x6B:
                ltsermouse_command_phase(dev, PHASE_BUTTONS);
                break;
+
+            default:
+                break;
        }
 }

 static void
-ltsermouse_transmit_period(serial_t *serial, void *priv, double transmit_period)
+ltsermouse_transmit_period(UNUSED(serial_t *serial), void *priv, double transmit_period)
 {
    mouse_t *dev = (mouse_t *) priv;

@@ -796,8 +818,8 @@ sermouse_init(const device_t *info)
        dev->id_len    = 1;
        dev->id[0]     = 'M';
        switch (dev->but) {
-            case 2:
            default:
+            case 2:
                dev->type = info->local ? MOUSE_TYPE_LOGITECH : MOUSE_TYPE_MICROSOFT;
                break;
            case 3:
@@ -846,7 +868,7 @@ sermouse_init(const device_t *info)
    mouse_set_buttons((dev->flags & FLAG_3BTN) ? 3 : 2);

    /* Return our private data to the I/O layer. */
-    return (dev);
+    return dev;
 }

 static const device_config_t mssermouse_config[] = {
--- a/src/device/mouse_wacom_tablet.c
+++ b/src/device/mouse_wacom_tablet.c
@@ -66,37 +66,49 @@ static const uint32_t wacom_resolution_values[4] = {
    1270
 };

-typedef struct {
+typedef struct mouse_wacom_t {
    const char *name; /* name of this device */
-    int8_t      type, /* type of this device */
-        port;
-    uint8_t flags, but, /* device flags */
-        status, bits,
-        data_rec[0x200];
-    int abs_x, abs_y,
-        rel_x, rel_y,
-        oldb, b;
+    int8_t      type; /* type of this device */
+    int8_t      port;
+    uint8_t     flags; /* device flags */
+    uint8_t     but;
+    uint8_t     status;
+    uint8_t     bits;
+    uint8_t     data_rec[0x200];
+    int         abs_x;
+    int         abs_y;
+    int         rel_x;
+    int         rel_y;
+    int         oldb;
+    int         b;

    Fifo8 data;

-    int data_rec_pos, mode, interval;
-    int increment, suppressed_increment;
+    int data_rec_pos;
+    int mode;
+    int interval;
+    int increment;
+    int suppressed_increment;
    int transmission_stopped;
    int reset;
-    int transmit_id, transmit_id_pending;
+    int transmit_id;
+    int transmit_id_pending;
    int pressure_mode;
-    int suppressed, measurement;
+    int suppressed;
+    int measurement;
    int remote_req;
    
-    uint32_t x_res, y_res;
-    const wacom_tablet_id* tablet_type;
+    uint32_t               x_res;
+    uint32_t               y_res;
+    const wacom_tablet_id *tablet_type;

-    int last_abs_x, last_abs_y; /* Suppressed/Increment Mode. */
+    int last_abs_x; /* Suppressed/Increment Mode. */
+    int last_abs_y; /* Suppressed/Increment Mode. */
    union {
        uint32_t settings; /* Settings DWORD */
        /* We don't target any architectures except x86/x64/ARM32/ARM64.
           (The ABIs for those are explicit in little-endian bit ordering) */
-        struct {
+        struct settings_bits {
            uint8_t remote_mode            : 1;
            uint8_t bitpad_two_cursor_data : 1;
            uint8_t mm961_orientation      : 1;
@@ -128,7 +140,8 @@ typedef struct {
    };

    double     transmit_period;
-    double     old_tsc, reset_tsc;
+    double     old_tsc;
+    double     reset_tsc;
    pc_timer_t report_timer;

    serial_t *serial;
@@ -197,6 +210,9 @@ wacom_process_settings_dword(mouse_wacom_t *wacom, uint32_t dword)
        case 3:
            wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
            break;
+
+        default:
+            break;
    }

    mouse_mode = !wacom->settings_bits.coord_sys;
@@ -245,7 +261,7 @@ wacom_reset_artpad(mouse_wacom_t *wacom)
 }

 static void
-wacom_callback(struct serial_s *serial, void *priv)
+wacom_callback(UNUSED(struct serial_s *serial), void *priv)
 {
    mouse_wacom_t *wacom = (mouse_wacom_t *) priv;

@@ -265,13 +281,16 @@ wacom_callback(struct serial_s *serial, void *priv)
        case 3:
            wacom->transmit_period = wacom_transmit_period(wacom, 19200, -1);
            break;
+
+        default:
+            break;
    }
    timer_stop(&wacom->report_timer);
    timer_on_auto(&wacom->report_timer, wacom->transmit_period);
 }

 static void
-wacom_write(struct serial_s *serial, void *priv, uint8_t data)
+wacom_write(UNUSED(struct serial_s *serial), void *priv, uint8_t data)
 {
    mouse_wacom_t *wacom           = (mouse_wacom_t *) priv;
    static int     special_command = 0;
@@ -295,6 +314,8 @@ wacom_write(struct serial_s *serial, void *priv, uint8_t data)
                    wacom->data_rec[wacom->data_rec_pos++] = data;
                    break;
                }
+            default:
+                break;
        }
        special_command = 0;
        return;
@@ -403,7 +424,7 @@ wacom_write(struct serial_s *serial, void *priv, uint8_t data)
 }

 static int
-wacom_poll(int x, int y, int z, int b, double abs_x, double abs_y, void *priv)
+wacom_poll(int x, int y, UNUSED(int z), int b, double abs_x, double abs_y, void *priv)
 {
    mouse_wacom_t *wacom = (mouse_wacom_t *) priv;

@@ -563,8 +584,8 @@ wacom_report_timer(void *priv)
            return;

        switch (wacom->mode) {
-            case WACOM_MODE_STREAM:
            default:
+            case WACOM_MODE_STREAM:
                break;

            case WACOM_MODE_POINT:
--- a/src/device/pci_bridge.c
+++ b/src/device/pci_bridge.c
@@ -47,10 +47,10 @@
 #define AGP_BRIDGE_VIA(x)      (((x) >> 16) == 0x1106)
 #define AGP_BRIDGE(x)          ((x) >= AGP_BRIDGE_ALI_M5243)

-typedef struct
-{
+typedef struct pci_bridge_t {
    uint32_t local;
-    uint8_t  type, ctl;
+    uint8_t  type;
+    uint8_t  ctl;

    uint8_t regs[256];
    uint8_t bus_index;
@@ -352,6 +352,9 @@ pci_bridge_write(int func, int addr, uint8_t val, void *priv)
                    return;
            }
            break;
+
+        default:
+            break;
    }

    dev->regs[addr] = val;
@@ -434,6 +437,9 @@ pci_bridge_reset(void *priv)
            dev->regs[0x06] = 0x20;
            dev->regs[0x07] = 0x02;
            break;
+
+        default:
+            break;
    }

    /* class */
@@ -477,7 +483,6 @@ pci_bridge_init(const device_t *info)
    uint8_t interrupt_count;
    uint8_t interrupt_mask;
    uint8_t slot_count;
-    uint8_t i;

    pci_bridge_t *dev = (pci_bridge_t *) malloc(sizeof(pci_bridge_t));
    memset(dev, 0, sizeof(pci_bridge_t));
@@ -493,7 +498,7 @@ pci_bridge_init(const device_t *info)
    interrupt_count = sizeof(interrupts);
    interrupt_mask  = interrupt_count - 1;
    if (dev->slot < 32) {
-        for (i = 0; i < interrupt_count; i++)
+        for (uint8_t i = 0; i < interrupt_count; i++)
            interrupts[i] = pci_get_int(dev->slot, PCI_INTA + i);
    }
    pci_bridge_log("PCI Bridge %d: upstream bus %02X slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, (dev->slot >> 5) & 0xff, dev->slot & 31, interrupts[0], interrupts[1], interrupts[2], interrupts[3]);
@@ -503,7 +508,7 @@ pci_bridge_init(const device_t *info)
    else
        slot_count = 1; /* AGP bridges always have 1 slot */

-    for (i = 0; i < slot_count; i++) {
+    for (uint8_t i = 0; i < slot_count; i++) {
        /* Interrupts for bridge slots are assigned in round-robin: ABCD, BCDA, CDAB and so on. */
        pci_bridge_log("PCI Bridge %d: downstream slot %02X interrupts %02X %02X %02X %02X\n", dev->bus_index, i, interrupts[i & interrupt_mask], interrupts[(i + 1) & interrupt_mask], interrupts[(i + 2) & interrupt_mask], interrupts[(i + 3) & interrupt_mask]);
        pci_register_bus_slot(dev->bus_index, i, AGP_BRIDGE(dev->local) ? PCI_CARD_AGP : PCI_CARD_NORMAL,
--- a/src/device/phoenix_486_jumper.c
+++ b/src/device/phoenix_486_jumper.c
@@ -1,148 +1,149 @@
-/*
- * 86Box    A hypervisor and IBM PC system emulator that specializes in
- *          running old operating systems and software designed for IBM
- *          PC systems and compatibles from 1981 through fairly recent
- *          system designs based on the PCI bus.
- *
- *          This file is part of the 86Box distribution.
- *
- *          Implementation of the Phoenix 486 Jumper Readout
- *
- *
- *
- * Authors: Tiseno100
- *
- *          Copyright 2020 Tiseno100
- */
-
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <wchar.h>
-#define HAVE_STDARG_H
-#include <86box/86box.h>
-#include "cpu.h"
-#include <86box/timer.h>
-#include <86box/io.h>
-#include <86box/device.h>
-#include <86box/chipset.h>
-
-/*
-    Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
-    Bit 6 = Graphics card: 1 = standalone, 0 = on-board;
-    Bit 5 = ???? (if 1, siren and hangs);
-    Bit 4 = ????;
-    Bit 3 = ????;
-    Bit 2 = ????;
-    Bit 1 = ????;
-    Bit 0 = ????.
-*/
-
-typedef struct
-{
-    uint8_t type, jumper;
-} phoenix_486_jumper_t;
-
-#ifdef ENABLE_PHOENIX_486_JUMPER_LOG
-int phoenix_486_jumper_do_log = ENABLE_PHOENIX_486_JUMPER_LOG;
-
-static void
-phoenix_486_jumper_log(const char *fmt, ...)
-{
-    va_list ap;
-
-    if (phoenix_486_jumper_do_log) {
-        va_start(ap, fmt);
-        pclog_ex(fmt, ap);
-        va_end(ap);
-    }
-}
-#else
-#    define phoenix_486_jumper_log(fmt, ...)
-#endif
-
-static void
-phoenix_486_jumper_write(uint16_t addr, uint8_t val, void *priv)
-{
-    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
-    phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
-    if (dev->type == 1)
-        dev->jumper = val & 0xbf;
-    else
-        dev->jumper = val;
-}
-
-static uint8_t
-phoenix_486_jumper_read(uint16_t addr, void *priv)
-{
-    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
-    phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);
-    return dev->jumper;
-}
-
-static void
-phoenix_486_jumper_reset(void *priv)
-{
-    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
-
-    if (dev->type == 1)
-        dev->jumper = 0x00;
-    else {
-        dev->jumper = 0x9f;
-        if (gfxcard[0] != 0x01)
-            dev->jumper |= 0x40;
-    }
-}
-
-static void
-phoenix_486_jumper_close(void *priv)
-{
-    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
-
-    free(dev);
-}
-
-static void *
-phoenix_486_jumper_init(const device_t *info)
-{
-    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) malloc(sizeof(phoenix_486_jumper_t));
-    memset(dev, 0, sizeof(phoenix_486_jumper_t));
-
-    dev->type = info->local;
-
-    phoenix_486_jumper_reset(dev);
-
-    io_sethandler(0x0078, 0x0001, phoenix_486_jumper_read, NULL, NULL, phoenix_486_jumper_write, NULL, NULL, dev);
-
-    return dev;
-}
-
-const device_t phoenix_486_jumper_device = {
-    .name          = "Phoenix 486 Jumper Readout",
-    .internal_name = "phoenix_486_jumper",
-    .flags         = 0,
-    .local         = 0,
-    .init          = phoenix_486_jumper_init,
-    .close         = phoenix_486_jumper_close,
-    .reset         = phoenix_486_jumper_reset,
-    { .available = NULL },
-    .speed_changed = NULL,
-    .force_redraw  = NULL,
-    .config        = NULL
-};
-
-const device_t phoenix_486_jumper_pci_device = {
-    .name          = "Phoenix 486 Jumper Readout (PCI machines)",
-    .internal_name = "phoenix_486_jumper_pci",
-    .flags         = 0,
-    .local         = 1,
-    .init          = phoenix_486_jumper_init,
-    .close         = phoenix_486_jumper_close,
-    .reset         = phoenix_486_jumper_reset,
-    { .available = NULL },
-    .speed_changed = NULL,
-    .force_redraw  = NULL,
-    .config        = NULL
-};
+/*
+ * 86Box    A hypervisor and IBM PC system emulator that specializes in
+ *          running old operating systems and software designed for IBM
+ *          PC systems and compatibles from 1981 through fairly recent
+ *          system designs based on the PCI bus.
+ *
+ *          This file is part of the 86Box distribution.
+ *
+ *          Implementation of the Phoenix 486 Jumper Readout
+ *
+ *
+ *
+ * Authors: Tiseno100
+ *
+ *          Copyright 2020 Tiseno100
+ */
+
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <wchar.h>
+#define HAVE_STDARG_H
+#include <86box/86box.h>
+#include "cpu.h"
+#include <86box/timer.h>
+#include <86box/io.h>
+#include <86box/device.h>
+#include <86box/chipset.h>
+#include <86box/plat_unused.h>
+
+/*
+    Bit 7 = Super I/O chip: 1 = enabled, 0 = disabled;
+    Bit 6 = Graphics card: 1 = standalone, 0 = on-board;
+    Bit 5 = ???? (if 1, siren and hangs);
+    Bit 4 = ????;
+    Bit 3 = ????;
+    Bit 2 = ????;
+    Bit 1 = ????;
+    Bit 0 = ????.
+*/
+
+typedef struct phoenix_486_jumper_t {
+    uint8_t type;
+    uint8_t jumper;
+} phoenix_486_jumper_t;
+
+#ifdef ENABLE_PHOENIX_486_JUMPER_LOG
+int phoenix_486_jumper_do_log = ENABLE_PHOENIX_486_JUMPER_LOG;
+
+static void
+phoenix_486_jumper_log(const char *fmt, ...)
+{
+    va_list ap;
+
+    if (phoenix_486_jumper_do_log) {
+        va_start(ap, fmt);
+        pclog_ex(fmt, ap);
+        va_end(ap);
+    }
+}
+#else
+#    define phoenix_486_jumper_log(fmt, ...)
+#endif
+
+static void
+phoenix_486_jumper_write(UNUSED(uint16_t addr), uint8_t val, void *priv)
+{
+    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
+    phoenix_486_jumper_log("Phoenix 486 Jumper: Write %02x\n", val);
+    if (dev->type == 1)
+        dev->jumper = val & 0xbf;
+    else
+        dev->jumper = val;
+}
+
+static uint8_t
+phoenix_486_jumper_read(UNUSED(uint16_t addr), void *priv)
+{
+    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
+    phoenix_486_jumper_log("Phoenix 486 Jumper: Read %02x\n", dev->jumper);
+    return dev->jumper;
+}
+
+static void
+phoenix_486_jumper_reset(void *priv)
+{
+    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
+
+    if (dev->type == 1)
+        dev->jumper = 0x00;
+    else {
+        dev->jumper = 0x9f;
+        if (gfxcard[0] != 0x01)
+            dev->jumper |= 0x40;
+    }
+}
+
+static void
+phoenix_486_jumper_close(void *priv)
+{
+    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) priv;
+
+    free(dev);
+}
+
+static void *
+phoenix_486_jumper_init(const device_t *info)
+{
+    phoenix_486_jumper_t *dev = (phoenix_486_jumper_t *) malloc(sizeof(phoenix_486_jumper_t));
+    memset(dev, 0, sizeof(phoenix_486_jumper_t));
+
+    dev->type = info->local;
+
+    phoenix_486_jumper_reset(dev);
+
+    io_sethandler(0x0078, 0x0001, phoenix_486_jumper_read, NULL, NULL, phoenix_486_jumper_write, NULL, NULL, dev);
+
+    return dev;
+}
+
+const device_t phoenix_486_jumper_device = {
+    .name          = "Phoenix 486 Jumper Readout",
+    .internal_name = "phoenix_486_jumper",
+    .flags         = 0,
+    .local         = 0,
+    .init          = phoenix_486_jumper_init,
+    .close         = phoenix_486_jumper_close,
+    .reset         = phoenix_486_jumper_reset,
+    { .available = NULL },
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
+
+const device_t phoenix_486_jumper_pci_device = {
+    .name          = "Phoenix 486 Jumper Readout (PCI machines)",
+    .internal_name = "phoenix_486_jumper_pci",
+    .flags         = 0,
+    .local         = 1,
+    .init          = phoenix_486_jumper_init,
+    .close         = phoenix_486_jumper_close,
+    .reset         = phoenix_486_jumper_reset,
+    { .available = NULL },
+    .speed_changed = NULL,
+    .force_redraw  = NULL,
+    .config        = NULL
+};
--- a/src/device/postcard.c
+++ b/src/device/postcard.c
@@ -86,7 +86,7 @@ postcard_reset(void)
 }

 static void
-postcard_write(uint16_t port, uint8_t val, void *priv)
+postcard_write(UNUSED(uint16_t port), uint8_t val, UNUSED(void *priv))
 {
    if (postcard_written && (val == postcard_code))
        return;
@@ -100,7 +100,7 @@ postcard_write(uint16_t port, uint8_t val, void *priv)
 }

 static void *
-postcard_init(const device_t *info)
+postcard_init(UNUSED(const device_t *info))
 {
    postcard_reset();

--- a/Show More
+++ b/Show More