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Merge remote-tracking branch 'upstream/master' into feature/mtrr

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This commit is contained in:
Jasmine Iwanek
2022-12-02 14:38:31 -05:00
parent 4fedabe749 910265d670
commit d067b38e75
8 changed files with 17 additions and 11 deletions
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11
src/cpu/cpu.c
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@@ -61,6 +61,7 @@ enum {
CPUID_AMDSEP = (1 << 10),
CPUID_SEP = (1 << 11),
CPUID_MTRR = (1 << 12),
CPUID_PGE = (1 << 13),
CPUID_MCA = (1 << 14),
CPUID_CMOV = (1 << 15),
CPUID_MMX = (1 << 23),
@@ -1177,7 +1178,9 @@ cpu_set(void)
if ((cpu_s->cpu_type == CPU_K6_2P) || (cpu_s->cpu_type == CPU_K6_3P)) {
x86_opcodes_3DNOW = ops_3DNOWE;
#ifdef USE_DYNAREC
x86_dynarec_opcodes_3DNOW = dynarec_ops_3DNOWE;
#endif
}
timing_rr = 1; /* register dest - register src */
@@ -1303,7 +1306,7 @@ cpu_set(void)
if (cpu_s->cpu_type >= CPU_PENTIUM2)
cpu_features |= CPU_FEATURE_MMX;
msr.fcr = (1 << 8) | (1 << 9) | (1 << 12) | (1 << 16) | (1 << 19) | (1 << 21);
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE;
cpu_CR4_mask = CR4_VME | CR4_PVI | CR4_TSD | CR4_DE | CR4_PSE | CR4_MCE | CR4_PAE | CR4_PCE | CR4_PGE;
if (cpu_s->cpu_type == CPU_PENTIUM2D)
cpu_CR4_mask |= CR4_OSFXSR;
@@ -1964,7 +1967,7 @@ cpu_CPUID(void)
} else if (EAX == 1) {
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
} else if (EAX == 2) {
EAX = 0x00000001;
EBX = ECX = 0;
@@ -1982,7 +1985,7 @@ cpu_CPUID(void)
} else if (EAX == 1) {
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_CMOV;
} else if (EAX == 2) {
EAX = 0x00000001;
EBX = ECX = 0;
@@ -2000,7 +2003,7 @@ cpu_CPUID(void)
} else if (EAX == 1) {
EAX = CPUID;
EBX = ECX = 0;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_MCA | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
EDX = CPUID_FPU | CPUID_VME | CPUID_PSE | CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CMPXCHG8B | CPUID_MMX | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_SEP | CPUID_FXSR | CPUID_CMOV;
} else if (EAX == 2) {
EAX = 0x00000001;
EBX = ECX = 0;

1
src/cpu/cpu.h
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@@ -195,6 +195,7 @@ typedef struct {
#define CR4_PVI (1 << 1)
#define CR4_PSE (1 << 4)
#define CR4_PAE (1 << 5)
#define CR4_PGE (1 << 7)
#define CPL ((cpu_state.seg_cs.access >> 5) & 3)

4
src/cpu/x86_ops_mov_ctrl.h
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@@ -148,7 +148,7 @@ opMOV_CRx_r_a16(uint32_t fetchdat)
break;
case 4:
if (cpu_has_feature(CPU_FEATURE_CR4)) {
if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE)
if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & (CR4_PAE | CR4_PGE))
flushmmucache();
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;
@@ -205,7 +205,7 @@ opMOV_CRx_r_a32(uint32_t fetchdat)
break;
case 4:
if (cpu_has_feature(CPU_FEATURE_CR4)) {
if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & CR4_PAE)
if (((cpu_state.regs[cpu_rm].l ^ cr4) & cpu_CR4_mask) & (CR4_PAE | CR4_PGE))
flushmmucache();
cr4 = cpu_state.regs[cpu_rm].l & cpu_CR4_mask;
break;

3
src/disk/hdc_ide.c
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@@ -1150,6 +1150,9 @@ ide_atapi_packet_write(ide_t *ide, uint32_t val, int length)
bufferw = (uint16_t *) bufferb;
bufferl = (uint32_t *) bufferb;
if (dev->packet_status == PHASE_DATA_IN)
return;
switch (length) {
case 1:
bufferb[dev->pos] = val & 0xff;

2
src/network/net_wd8003.c
View File

@@ -548,7 +548,7 @@ wd_mca_write(int port, uint8_t val, void *priv)
dev->base_address = (dev->pos_regs[2] & 0xfe) << 4;
dev->ram_addr = (dev->pos_regs[3] & 0xfc) << 12;
dev->irq = irq[dev->pos_regs[5] & 0x02];
dev->irq = irq[dev->pos_regs[5] & 0x03];
/* Initialize the device if fully configured. */
/* Register (new) I/O handler. */

2
src/scsi/scsi_aha154x.c
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@@ -519,7 +519,7 @@ aha_mca_write(int port, uint8_t val, void *priv)
/* Get the new assigned I/O base address. */
dev->Base = (dev->pos_regs[3] & 7) << 8;
dev->Base |= ((dev->pos_regs[3] & 0xc0) ? 0x34 : 0x30);
dev->Base |= ((dev->pos_regs[3] & 0x40) ? 0x34 : 0x30);
/* Save the new IRQ and DMA channel values. */
dev->Irq = (dev->pos_regs[4] & 0x07) + 8;

2
src/scsi/scsi_x54x.c
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@@ -1402,7 +1402,7 @@ x54x_reset(x54x_t *dev)
clear_irq(dev);
if (dev->flags & X54X_INT_GEOM_WRITABLE)
dev->Geometry = 0x80;
dev->Geometry = 0x90;
else
dev->Geometry = 0x00;
dev->callback_phase = 0;

3
src/sound/snd_optimc.c
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@@ -312,9 +312,8 @@ optimc_reg_read(uint16_t addr, void *p)
case 1: /* MC2 */
case 3: /* MC4 */
case 4: /* MC5 */
temp = optimc->regs[addr - 0xF8D];
case 5: /* MC6 */
temp = optimc->regs[5];
temp = optimc->regs[addr - 0xF8D];
break;
case 2: /* MC3 */
temp = (optimc->regs[2] & ~0x3) | 0x2;