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synced 2026-02-23 09:58:19 -07:00
Fix compile due to svga changes Improve RMA code which is one of the oldest pieces of code in the entire emulation.
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@@ -908,7 +908,7 @@ extern const device_config_t nv3t_config[]; // Confi
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// These are nvidia, licensed from weitek (25-63)
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#define NV3_CRTC_REGISTER_RPC0 0x19 // 7:5 - [10:8] of CRTC. 4:0 - [20:16] of 21-bit display buffer address
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#define NV3_CRTC_REGISTER_RPC1 0x1A // What does this mean?
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#define NV3_CRTC_REGISTER_RPC1 0x1A // bit7=hsync enabled, bit6=vsync enabled, bit4="compatible text", bit2=large screen, bit1=6bit palette width (>1280)
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#define NV3_CRTC_REGISTER_READ_BANK 0x1D
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#define NV3_CRTC_REGISTER_WRITE_BANK 0x1E
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#define NV3_CRTC_REGISTER_FORMAT 0x25
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@@ -921,8 +921,8 @@ extern const device_config_t nv3t_config[]; // Confi
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#define NV3_CRTC_REGISTER_HEB 0x2D // HRS most significant bit
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#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high
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#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable)
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#define NV3_CRTC_REGISTER_CURSOR_ADDR0 0x30 // Cursor high 21:16
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#define NV3_CRTC_REGISTER_CURSOR_ADDR1 0x31 // Cursor low (1:0 = enable) 15:11
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#define NV3_CRTC_REGISTER_PIXELMODE_VGA 0x00 // vga textmode
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#define NV3_CRTC_REGISTER_PIXELMODE_8BPP 0x01
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@@ -1413,7 +1413,7 @@ typedef struct nv3_ptimer_s
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} nv3_ptimer_t;
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// Object name is just a uint32_t identifier it doesn't need a struct
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// This is howt he cotnext is represented in ramin
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// This is how the context is represented in ramin
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// IN PGRAPH IT IS DIFFERENT! ONLY 5 BITS FOR THE CLASS ID! WHY?
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typedef struct nv3_ramin_context_s
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{
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@@ -192,7 +192,6 @@ add_library(vid OBJECT
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# Generic
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vid_bochs_vbe.c
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)
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if(G100)
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@@ -585,7 +585,7 @@ void nv3_recalc_timings(svga_t* svga)
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nv3_t* nv3 = (nv3_t*)svga->priv;
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uint32_t pixel_mode = svga->crtc[NV3_CRTC_REGISTER_PIXELMODE] & 0x03;
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svga->ma_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16;
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svga->memaddr_latch += (svga->crtc[NV3_CRTC_REGISTER_RPC0] & 0x1F) << 16;
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/* Turn off override if we are in VGA mode */
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svga->override = !(pixel_mode == NV3_CRTC_REGISTER_PIXELMODE_VGA);
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@@ -164,13 +164,8 @@ uint8_t nv3_pbus_rma_read(uint16_t addr)
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ret = nv3_mmio_read8(real_final_address, NULL);
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else
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{
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// ABOVE CODE IS TEMPORARY UNTIL PNVM EXISTS!!!!!
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// would svga->fast work?
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nv3->nvbase.svga.chain4 = true;
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nv3->nvbase.svga.packed_chain4 = true;
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ret = svga_read_linear((real_final_address - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), &nv3->nvbase.svga);
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nv3->nvbase.svga.chain4 = false;
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nv3->nvbase.svga.packed_chain4 = false;
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/* Do we need to read RAMIN here? */
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ret = nv3->nvbase.svga.vram[real_final_address - NV3_MMIO_SIZE] & (nv3->nvbase.svga.vram_max - 1);
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}
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// log current location for vbios RE
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@@ -246,11 +241,8 @@ void nv3_pbus_rma_write(uint16_t addr, uint8_t val)
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nv3_mmio_write32(nv3->pbus.rma.addr, nv3->pbus.rma.data, NULL);
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else // failsafe code, i don't think you will ever write outside of VRAM?
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{
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nv3->nvbase.svga.chain4 = true;
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nv3->nvbase.svga.packed_chain4 = true;
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svga_writel_linear((nv3->pbus.rma.addr - NV3_MMIO_SIZE) & (nv3->nvbase.svga.vram_max - 1), nv3->pbus.rma.data, &nv3->nvbase.svga);
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nv3->nvbase.svga.chain4 = false;
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nv3->nvbase.svga.packed_chain4 = false;
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uint32_t* vram_32 = (uint32_t*)nv3->nvbase.svga.vram;
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vram_32[(nv3->pbus.rma.addr - NV3_MMIO_SIZE) >> 2] = nv3->pbus.rma.data;
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}
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@@ -202,7 +202,7 @@ void nv3_pfifo_interrupt(uint32_t id, bool fire_now)
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/*
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RAMIN access arbitration functions
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Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) (RAMAU?)
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Arbitrates reads and writes to RAMFC (unused dma context storage), RAMRO (invalid object submission location), RAMHT (hashtable for graphics objectstorage) unused audio memory (RAMAU?)
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and generic RAMIN
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Takes a pointer to a result integer. This is because we need to check its result in our normal write function.
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