1. The PAS SCSI controller driver mamv1.sys dislikes having bits 0-6 set when a transfer has completed, take account from this, fixes mamv1.sys incomplete CD transfers (bits 0-6 get re-enabled when the transfer is ongoing).
2. I now understand why the T128 doesn't have a block count register, it does the block count manually from the SCSI layer directly, this fixes Pseudo-DMA transfers when using, e.g.: CD transfers using a sector size of 2340 bytes.
1. The DX/DY coordinates for BitBLT are now signed again, fixes 8514/A cursor issues.
2. Made the busy/data available processor statuses more like the ATI one for more stability and no stalls, fixes Windows 3.x and IBM OS/2 1.x (possibly later ones too) that use the built-in 8514/A driver.
3. Made the mode switching clearer (through a note) regarding the shadow sets, this should make every program happy, I hope.
4. In the Mach32 series only, a first load of the CRT sets also initializes the GE offsets if the corresponding bit is set, fixes Mach8/32 mode tests in their eeprom and demoai with hdiload from ATI/IBM.
1. Use proper identification to what chips use what.
2. Apply some mode switch fixes to the ATI 8514/A Ultra and make 1024x768 87Hz interlaced the default mode if htotal is 0 and on ati8514_init.
3. Add the undocumented ports to the ATI 8514/A Ultra add-on as well.
1. Implemented the FIFO test data to pass some tests of the Mach8 POST ROM and tests (not complete yet).
2. Overhauled the mode switches again, but this time with way less hacks and more on manual instructions.
3. Use a function pointer to determine if the Mach8 type used is a VGA combo or add-on.
4. Mach32 mode tests are no longer incorrectly green (was caused by improper pixtrans parts).
5. Implemented overscan color to the Mach32 as well as the CRT offset.
6. And fixed a PCI LFB GPF issue with the Mach32 2.3 drivers on Win3.1x.
7. Implemented memory boundary for both the Mach32 SVGA and its accelerator.
8. Added undocumented ports used by the FIFO (such as ports 0x8AEE and 0xEAEE).
9. Plus resetting the device right a la s3.
10. Temporarily switched the bus type of the Mach8 to 8-bit in both MCA and ISA variants.
