1. The S3 968-based Diamond Stealth 64 Video VRAM, using a 14mhz reference clock, now has its RGB528 fixed Pixel PLL reference divider set to its default value (0x07) per manual and reference clock. Fixes wrong refresh rates on said cards and others.
2. Added the ICS2494-324 clock generator to the ET4000AX. Fixes wrong refresh rates on this one too.
1. In the STG code, separated the STG1703 without its built-in clock as 1702 while keeping the one with the clock as 1703.
2. Added the ICS2494AN-324 clock generator used by the et4000w32 series.
3. Return 0x98 as the ID of the ATT498 ramdac.
4. Corrected the pixel clocks of the IBM RGB528 while keeping its current compatibility and exactness of the refresh rates of its clocks.
5. Added a variable reference clock of the SDAC/GenDAC for future use.
6. The clocks of the TVP3026 have been implemented for a while. Some corrections have been made (plus color key r/w).
7. Mach64 enhanced mode doesn't use scrollcache (bits 0-3 of attrregs 0x13), fixes some pixels being off (mainly in win3.1x)
8. Reorganized the cirrus 54xx built-in clock for proper refresh rates.
9. Proper reorganization of the et4000w32 series of chipsets and their cards supporting them, from cursor to clocks to ramdacs plus a 24bpp acceleration fix for the w32p series (about pixels being processed in bitblt).
10. Removed the PCI videomagic card as its bios doesn't have the PCIR header while making sure the plain ISA/VLB w32 and ISA only w32i (now named Axis Microdevice) support 2mb of vram properly.
11. Added the Hercules Dynamite VL Pro based on the w32i chip (and VLB).
12. Initialize the et4000w32 cards with misc bit 0 set as well as crtc31 bit 6 for rs2 connection to the ramdac.
13. Refactored the S3 Pre-ViRGE code to have proper refresh rates and clocks and added the 805I as a member of the chips (ID 0xa8).
14. Replaced the S3 805I Elsa Winner 1000 ISA bios with a more supported one for our code using the SDAC.
15. Added proper 24bpp acceleration to the Visionx68 chips.
16. Fixed wrong colors in the 911/924 15/16bpp acceleration when used for the first time.
17. Match the ViRGE mapping to the pre-ViRGE one per manual/datasheet.
18. Correct as best as possible the TGUI9400 clocks.
The rework resolves around implementing the clock multiplier and multiplexing rate of the bt485 ramdac alongside existing additional flags for eventual fixes (like cr31 bit 1) as well as the true color bypass (for 16-bit and true color modes). These, together, allow proper rendering of the generic VESA S3 drivers alongside non-VESA ELSA OEM drivers on various guests.
1. Rewritten Sierra SC1502x RAMDAC code to match the manual, allowing proper BPP selection on cards which use it.
2. Added a reference clock variable for cards which have a different default one (ELSA cards namely) on the ICD2061 code.
3. Reorganized RAMDAC selection in the S3 code.
4. Added more ELSA Winner cards based on the 928 chip (ELSA Winner 2000 ISA, 1000 VLB and 1000 PCI based on 928PCI).
5. The horizontal override is now also enabled for ELSA Winner 1000 (928 VLB and PCI) cards with 32bpp set, to avoid wrong horizontal displays.
6. LFB in PCI mode doesn't have the same limitations as on VLB or ISA.
7. Added more hdisp adjustments for the Elsa cards.
8. Mono patterns are now more correct in ROPBLT acceleration (command 14), fixes blackness in some instances of Win95 (matching the 968 manual).
9. Minor cleanup on the accel registers.
1.Move the 93cxx EEPROM implementation to the mem directory since it's used by cards which are not nics (e.g.: DC390 SCSI and S3 ELSA cards).
2. DC390 specific: remove the implementation used there and use the generic one from mem (used to be on the network directory) as well as fixing bus reset when interrupts are related.
3. S3: when the 64k size is selected in the LFB, use the SVGA 64k mapping as LFB (0xA0000).
1. If a card uses the icd2061a clock, so be it in a better way.
2. Vertical display fixes for heights greater than 1024 pixels, e.g.: 1600x1200 on the ELSA 96x cards.
3. Misc fixes (ROPBLT).
4. 0x3ca and 0x3cb in read mode are actually different from writes.
1. Correct the clock chip of the S3 928 (Metheus Premier 928) to use a ics2494 one (a board picture shows the CH9294, a clone of the ics2494/av9194).
2. Correct the 8bpp and high color refresh rates of the Metheus Premier 928 when either bt48x x2 clock multiplier is enabled or when hitting high color.
1. If the VGA mapping is for a 0xA0000 map for a length of 0x10000, then disable XGA mode (this is independent of the XGA extended mode aperture mode 1 which is XGA's own 0xA0000 mapping).
2. Remove text mode ctrl-alt-del hack.
3. Fixed cursor x coordinate in the Trio32 using 15bpp/16bpp modes.
1. Pixtrans on port 0xb2e8 is not available on 864/964 and up (including the trio64) due to color compare taking its place, fixes some graphical glitches in WinXP.
2. The DOS s3id utility identifies the 80x chips correctly, either it's 801 ISA or 805 VLB, but not 805 ISA even if they share the same id, but since it's an ISA card, identify the Elsa Winner 1000 805 ISA as a 801 card.
1. Actually mostly workarounds to make it render normally without a hitch (I hope) using the Diamond Stealth VRAM 911-based 15bpp driver.
2. Updated logs.
1. See above, as best as possible, but manuals would be helpful.
2. Reverted the ramdac of the 924 to the sierra one because of a bug that triggers 24bpp mode when it shouldn't.
SVGA related:
If CRTC1/HDISP is odd (if bit 0 is set), then make it even accordingly, else leave it as is. Should fix some display skews.
S3 related:
Remove old code references (can still be accessed through history if one needs it).
8514/A compatible related:
Proper use of the htotal and hdisp timings.
S3:
1. Cleaned up the Short Stroke command processing.
2. Proceed calculating the error term only when it's equal or greater than the line length (Draw Line, Command 1 and also applies to Short Strokes, Command 0).
8514/A compatibles:
1. Reworked the polygon draw type A processing.
2. As with the S3, reworked the way error term is handled in the processing, and on Command 5 (Draw Polygon Boundary Line).
1. Initialize Multifunction indexes 0x0D and 0x0E properly, should fix inverted colors on S3 OS/2 Warp drivers.
2. Make the remaining Vision868/968 only ports handle the 32-bit toggling properly.
3. Cleanups
Cirrus 5436/46 and 5480.
Finally fixed the Solaris 2.6 font issue, was a dword swap one with color expansion.
S3.
1. Make 868/968 ignore horizontal skew, ergo horizontal override until a proper solution is found regarding hardware tests.
2. Fixed a minor mix issue with S3 911/924 Win3.1 drivers in 8bpp mode.
1. Simplified 4bpp rendering mode.
2. Implement CRTC31 bit 0 functionality which enables/disables the vendor banks. Fixes Diamond Stealth 64 964 VRAM (VLB/PCI) detection on NT 3.1 (and possibly other cards) while keeping NT 3.1 347.1's full screen Command Prompt test normal without garbage using the 911/924 chips.
8514/A/Mach8/32:
Reworked the acceleration a bit as well as the mode switches from VGA to ATI/8514/A mode and viceversa based on the documentation. Fixes the Linux GUI fonts using the Mach32 driver (possibly Mach8 too) and other anomalies (still needs more work on the acceleration though).
PVGA:
Minor fixes to the banking.
S3-based (Pre-ViRGE):
1. Made the chip class use its own banking so that the Enhanced Mode mapping (equivalent to 64K-based A0000) is taken into account (per bit 3 of CRTC31, which forces the mapping to be 64K A0000, regardless of the GDCREG6 bits). Fixes NT 3.1 347.1's S3 driver.
2. Initial rework on 15bpp/16bpp accelerated mode of the 911/924 chips (currently not 100% bug free, I need help with this chips).
XGA-1/2:
Get rid of the linear endian reverse variable hack used by OS/2 and, instead, use the already declared ones more wisely, fixes OS/2 2.1 reversed fonts and keeps everything else working as it should.
Misc:
Added the BT481 RAMDAC for future card use.
1. Actually fix the remaining pinkish/reddish stuff in 32bpp modes properly (for real, especially OS/2 and possibly other stuff).
2. The Compare accel stuff is more sanitized.
3. When the BitBLT DY coordinates are negative, don't draw the pixels. This fixes some software cursor issues with OS/2's S3 3.03.xx drivers.
4. Reset the FIFO when the card is reset.
5. Indentation fixes (to be improved further however).
6. Implement bit 5 functionality of 0xBEE8 index 0xE (MULT_MISC) (and currently only in the Rectangle Fill command). This fixes missing text on I-O Data Vision968 specific drivers for Windows 3.10 Japanese (PC/AT compatible)
7. Moved the Streams engine out of the FIFO (like the ViRGE) as well as making all CRTC's of the Trio64V2 writable and SEQREGs from 0x10 onwards to make sure the Streams engine works properly.
8. Added a missing break from the RAMDAC read stuff.
9. Remove a leftover of PCem.
