[beken-72xx] Fix BK7231S 1.0.5 bootloader compatibility
This commit is contained in:
Kuba Szczodrzyński
@@ -97,6 +97,16 @@ env.Append(
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],
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)
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srcs_core = []
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srcs_fixups = []
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# Fix for BK7231T's bootloader compatibility
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if board.get("build.bkboot_version") == "1.0.5-bk7231s":
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env.Append(CPPDEFINES=[("CFG_SUPPORT_BOOTLOADER", "1")])
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srcs_fixups.append("+<boot_handlers_105_bk7231s.S>")
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else:
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srcs_core.append("+<driver/entry/boot_handlers.S>")
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# Sources - from framework-beken-bdk/beken378/beken_src.mk
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env.AddLibrary(
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name="bdk_core",
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@@ -106,15 +116,11 @@ env.AddLibrary(
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"+<app/ate_app.c>",
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"+<app/config/param_config.c>",
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"+<demo/*.c>",
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"+<driver/driver.c>",
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"+<driver/entry/arch_main.c>",
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"+<driver/entry/boot_handlers.S>",
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"+<driver/entry/boot_vectors.S>",
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"+<driver/intc/intc.c>",
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"+<func/func.c>",
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"+<func/wlan_ui/bk_peripheral_test.c>",
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"+<func/wlan_ui/wlan_cli.c>",
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"+<func/wlan_ui/wlan_ui.c>",
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*srcs_core,
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],
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includes=[
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"+<app>",
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@@ -128,6 +134,17 @@ env.AddLibrary(
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],
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)
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# Sources - parent family fixups
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env.AddLibrary(
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name="${FAMILY_PARENT_CODE}_fixups",
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base_dir="$PARENT_DIR/fixups",
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srcs=[
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"+<arch_main.c>",
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"+<intc.c>",
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*srcs_fixups,
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],
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)
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# Sources - app module
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env.AddLibrary(
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name="bdk_app",
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@@ -153,6 +170,7 @@ env.AddLibrary(
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name="bdk_driver",
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base_dir=DRIVER_DIR,
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srcs=[
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"+<driver.c>",
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"+<calendar/*.c>",
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"+<common/*.c>",
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"+<dma/*.c>",
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@@ -208,6 +226,7 @@ env.AddLibrary(
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name="bdk_func",
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base_dir=FUNC_DIR,
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srcs=[
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"+<func.c>",
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"+<airkiss/*.c>",
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"+<base64/*.c>",
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"+<ble_wifi_exchange/*.c>",
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104
platform/beken-72xx/fixups/arch_main.c
Normal file
104
platform/beken-72xx/fixups/arch_main.c
Normal file
@@ -0,0 +1,104 @@
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/**
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****************************************************************************************
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*
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* @file arch_main.c
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*
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* @brief Main loop of the application.
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*
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* Copyright (C) Beken Corp 2011-2020
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*
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****************************************************************************************
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*/
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#include "app.h"
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#include "ate_app.h"
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#include "driver_pub.h"
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#include "func_pub.h"
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#include "include.h"
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#include "start_type_pub.h"
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beken_semaphore_t extended_app_sema = NULL;
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uint32_t extended_app_stack_size = 2048;
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extern void user_main_entry(void);
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#if CFG_SUPPORT_BOOTLOADER
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void entry_set_world_flag(void) {
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*(volatile uint32_t *)0x00400000 = 1;
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}
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#endif // CFG_SUPPORT_BOOTLOADER
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void extended_app_launch_over(void) {
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OSStatus ret;
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ret = rtos_set_semaphore(&extended_app_sema);
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(void)ret;
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}
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void extended_app_waiting_for_launch(void) {
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OSStatus ret;
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ret = rtos_get_semaphore(&extended_app_sema, BEKEN_WAIT_FOREVER);
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ASSERT(kNoErr == ret);
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(void)ret;
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}
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static void extended_app_task_handler(void *arg) {
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func_init_extended();
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if (get_ate_mode_state()) {
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ate_start();
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} else {
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app_start();
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}
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extended_app_launch_over();
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rtos_delete_thread(NULL);
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}
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void extended_app_init(void) {
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OSStatus ret;
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ret = rtos_init_semaphore(&extended_app_sema, 1);
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ASSERT(kNoErr == ret);
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}
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void extended_app_uninit(void) {
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OSStatus ret;
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ret = rtos_deinit_semaphore(&extended_app_sema);
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ASSERT(kNoErr == ret);
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}
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void extended_app_launch(void) {
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OSStatus ret;
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ret = rtos_create_thread(
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NULL,
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THD_EXTENDED_APP_PRIORITY,
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"extended_app",
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(beken_thread_function_t)extended_app_task_handler,
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extended_app_stack_size,
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(beken_thread_arg_t)0
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);
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ASSERT(kNoErr == ret);
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}
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void entry_main(void) {
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// check GPIO0 and start ATE app
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ate_app_init();
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// compatibility with BK7231S_1.0.5
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#if CFG_SUPPORT_BOOTLOADER
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entry_set_world_flag();
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#endif
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// read reboot cause into bk_misc_get_start_type()
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bk_misc_init_start_type();
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// clear driver registration arrays
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driver_init();
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// reboot the board if start_type == RESET_SOURCE_CRASH_PER_XAT0
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bk_misc_check_start_type();
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// init flash and intc
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func_init_basic();
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// init semaphore for extended_app_launch
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extended_app_init();
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// run task with init_app_thread
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user_main_entry();
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// run task with extended_app_task_handler
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extended_app_launch();
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// start FreeRTOS
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#if (CFG_OS_FREERTOS)
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vTaskStartScheduler();
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#endif
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}
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499
platform/beken-72xx/fixups/boot_handlers_105_bk7231s.S
Normal file
499
platform/beken-72xx/fixups/boot_handlers_105_bk7231s.S
Normal file
@@ -0,0 +1,499 @@
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/**
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****************************************************************************************
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*
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* @file boot_handlers.s
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*
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* @brief ARM Exception Vector handler functions.
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*
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* Copyright (C) RivieraWaves 2011-2016
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*
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****************************************************************************************
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*/
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.globl entry_main
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.globl intc_irq
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.globl intc_fiq
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.globl boot_reset
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.globl boot_swi
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.globl boot_undefined
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.globl boot_pabort
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.globl boot_dabort
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.globl boot_reserved
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.globl irq_handler
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.globl fiq_handler
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.globl vPortStartFirstTask
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.globl do_irq
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.globl do_fiq
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.globl do_swi
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.globl do_undefined
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.globl do_pabort
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.globl do_dabort
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.globl do_reserved
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.globl bk_trap_udef
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.globl bk_trap_pabt
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.globl bk_trap_dabt
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.globl bk_trap_resv
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#include "sys_config.h"
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/* ========================================================================
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* Macros
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* ======================================================================== */
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#define _FIQ_STACK_SIZE_ 0x7F0
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#define _IRQ_STACK_SIZE_ 0xFF0
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#define _SVC_STACK_SIZE_ 0x3F0
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#define _SYS_STACK_SIZE_ 0x3F0
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#define _UND_STACK_SIZE_ 0x010
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#define _ABT_STACK_SIZE_ 0x010
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#define BOOT_MODE_MASK 0x1F
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#define BOOT_MODE_USR 0x10
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#define BOOT_MODE_FIQ 0x11
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#define BOOT_MODE_IRQ 0x12
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#define BOOT_MODE_SVC 0x13
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#define BOOT_MODE_ABT 0x17
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#define BOOT_MODE_UND 0x1B
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#define BOOT_MODE_SYS 0x1F
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#define BOOT_FIQ_IRQ_MASK 0xC0
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#define BOOT_IRQ_MASK 0x80
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#define BOOT_COLOR_UNUSED 0xAAAAAAAA //Pattern to fill UNUSED stack
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#define BOOT_COLOR_SVC 0xBBBBBBBB //Pattern to fill SVC stack
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#define BOOT_COLOR_IRQ 0xCCCCCCCC //Pattern to fill IRQ stack
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#define BOOT_COLOR_FIQ 0xDDDDDDDD //Pattern to fill FIQ stack
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#define BOOT_COLOR_SYS 0xEEEEEEEE //Pattern to fill SYS stack
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/* ========================================================================
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Context save and restore macro definitions
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* ======================================================================== */
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/* ========================================================================*/
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.macro portSAVE_CONTEXT
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//Push R0 as we are going to use the register.
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STMDB SP!, {R0}
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MRS R0, spsr
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AND R0, R0, #0x1F
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CMP R0, #0x1F
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BNE 10f
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//Set R0 to point to the task stack pointer.
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STMDB SP, {SP}^
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NOP
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SUB SP, SP, #4
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LDMIA SP!, {R0}
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//Push the return address onto the stack.
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STMDB R0!, {LR}
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//Now we have saved LR we can use it instead of R0.
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MOV LR, R0
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//Pop R0 so we can save it onto the system mode stack.
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LDMIA SP!, {R0}
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//Push all the system mode registers onto the task stack.
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STMDB LR, {R0-R14}^
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NOP
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NOP
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SUB LR, LR, #60
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//Push the SPSR onto the task stack.
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MRS R0, SPSR
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STMDB LR!, {R0}
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LDR R0, =ulCriticalNesting
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LDR R0, [R0]
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STMDB LR!, {R0}
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//Store the new top of stack for the task.
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LDR R0, =pxCurrentTCB
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LDR R0, [R0]
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STR LR, [R0]
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B 11f
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10:
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LDMIA SP!, {R0}
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STMDB r13!, {r0-r12,r14}
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NOP
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NOP
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LDR R0, =ulCriticalNesting
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LDR R0, [R0]
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STMDB r13!, {R0}
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LDR R0, =pxCurrentTCB
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LDR R0, [R0]
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STMDB r13!, {R0}
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SUB r13, r13, #8
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11:
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MOV R0, R0
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.endm
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/* ========================================================================*/
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.macro portRESTORE_CONTEXT
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MRS R0, spsr
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AND R0, R0, #0x1F
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CMP R0, #0x1F
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BNE 20f
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//Set the LR to the task stack.
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LDR R0, =pxCurrentTCB
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LDR R0, [R0]
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LDR LR, [R0]
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//The critical nesting depth is the first item on the stack.
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//Load it into the ulCriticalNesting variable.
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LDR R0, =ulCriticalNesting
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LDMFD LR!, {R1}
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STR R1, [R0]
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//Get the SPSR from the stack.
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LDMFD LR!, {R0}
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MSR SPSR_cxsf, R0
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//Restore all system mode registers for the task.
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LDMFD LR, {R0-R14}^
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NOP
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NOP
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//Restore the return address.
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LDR LR, [LR, #+60]
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//And return - correcting the offset in the LR to obtain the
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//correct address.
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SUBS PC, LR, #4
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20:
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ADD r13, r13, #0x8
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LDR R0, =pxCurrentTCB
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LDMFD r13!, {R1}
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STR R1, [R0]
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LDR R0, =ulCriticalNesting
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LDMFD r13!, {R1}
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STR R1, [R0]
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LDMIA r13!, {r0-r12,r14}
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NOP
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NOP
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SUBS pc, r14, #0x4
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.endm
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/* ========================================================================*/
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.macro firstRESTORE_CONTEXT
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//Set the LR to the task stack.
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LDR R0, =pxCurrentTCB
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LDR R0, [R0]
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LDR LR, [R0]
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//The critical nesting depth is the first item on the stack.
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//Load it into the ulCriticalNesting variable.
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LDR R0, =ulCriticalNesting
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LDMFD LR!, {R1}
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STR R1, [R0]
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//Get the SPSR from the stack.
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LDMFD LR!, {R0}
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MSR SPSR_cxsf, R0
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//Restore all system mode registers for the task.
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LDMFD LR, {R0-R14}^
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NOP
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NOP
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//Restore the return address.
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LDR LR, [LR, #+60]
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//And return - correcting the offset in the LR to obtain the
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//correct address.
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SUBS PC, LR, #4
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.endm
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/* ========================================================================
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* Macro for switching ARM mode
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*/
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.macro BOOT_CHANGE_MODE, mode, mode_mask
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MRS R0, CPSR
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BIC R0, R0, #\mode_mask
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ORR R0, R0, #\mode
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MSR CPSR_c, R0
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.endm
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/* ========================================================================
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* Macro for setting the stack
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*/
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.macro BOOT_SET_STACK, stackStart, stackLen, color
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LDR R0, \stackStart
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LDR R1, \stackLen
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ADD R1, R1, R0
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MOV SP, R1 //Set stack pointer
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LDR R2, =\color
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3:
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CMP R0, R1 //End of stack?
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STRLT R2, [r0] //Colorize stack word
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ADDLT R0, R0, #4
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BLT 3b //branch to previous local label
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.endm
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.section .data
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.align 3
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.global und_stack_start
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und_stack_start:
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.space _UND_STACK_SIZE_
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.align 3
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.global abt_stack_start
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abt_stack_start:
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.space _ABT_STACK_SIZE_
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.align 3
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.global fiq_stack_start
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fiq_stack_start:
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.space _FIQ_STACK_SIZE_
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.align 3
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.global irq_stack_start
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irq_stack_start:
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.space _IRQ_STACK_SIZE_
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.align 3
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.global sys_stack_start
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sys_stack_start:
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.space _SYS_STACK_SIZE_
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.align 3
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.global svc_stack_start
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svc_stack_start:
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.space _SVC_STACK_SIZE_
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||||
/* ========================================================================
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||||
* Functions
|
||||
* ========================================================================
|
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* Function to handle reset vector
|
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*/
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.globl boot_reset
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.section ".boot", "ax"
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|
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boot_reset:
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//Disable IRQ and FIQ before starting anything
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MRS R0, CPSR
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ORR R0, R0, #0xC0
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MSR CPSR_c, R0
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//Setup all stacks //Note: Abt and Usr mode are not used
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BOOT_CHANGE_MODE BOOT_MODE_SYS BOOT_MODE_MASK
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BOOT_SET_STACK boot_stack_base_SYS boot_stack_len_SYS BOOT_COLOR_SYS
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BOOT_CHANGE_MODE BOOT_MODE_ABT BOOT_MODE_MASK
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BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
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BOOT_CHANGE_MODE BOOT_MODE_UND BOOT_MODE_MASK
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BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
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BOOT_CHANGE_MODE BOOT_MODE_IRQ BOOT_MODE_MASK
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BOOT_SET_STACK boot_stack_base_IRQ boot_stack_len_IRQ BOOT_COLOR_IRQ
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||||
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BOOT_CHANGE_MODE BOOT_MODE_FIQ BOOT_MODE_MASK
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BOOT_SET_STACK boot_stack_base_FIQ boot_stack_len_FIQ BOOT_COLOR_FIQ
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|
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//Clear FIQ banked registers while in FIQ mode
|
||||
MOV R8, #0
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MOV R9, #0
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MOV R10, #0
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||||
MOV R11, #0
|
||||
MOV R12, #0
|
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|
||||
BOOT_CHANGE_MODE BOOT_MODE_SVC BOOT_MODE_MASK
|
||||
BOOT_SET_STACK boot_stack_base_SVC boot_stack_len_SVC BOOT_COLOR_SVC
|
||||
|
||||
/*Stay in Supervisor Mode
|
||||
copy data from binary to ram*/
|
||||
BL _sysboot_copy_data_to_ram
|
||||
|
||||
/*Init the BSS section*/
|
||||
BL _sysboot_zi_init
|
||||
|
||||
//==================
|
||||
//Clear Registers
|
||||
MOV R0, #0
|
||||
MOV R1, #0
|
||||
MOV R2, #0
|
||||
MOV R3, #0
|
||||
MOV R4, #0
|
||||
MOV R5, #0
|
||||
MOV R6, #0
|
||||
MOV R7, #0
|
||||
MOV R8, #0
|
||||
MOV R9, #0
|
||||
MOV R10, #0
|
||||
MOV R11, #0
|
||||
MOV R12, #0
|
||||
|
||||
/* start main entry*/
|
||||
B entry_main
|
||||
B .
|
||||
|
||||
/* ========================================================================
|
||||
* Globals
|
||||
* ======================================================================== */
|
||||
boot_stack_base_UNUSED:
|
||||
.word und_stack_start
|
||||
|
||||
boot_stack_len_UNUSED:
|
||||
.word _UND_STACK_SIZE_
|
||||
|
||||
boot_stack_base_IRQ:
|
||||
.word irq_stack_start
|
||||
|
||||
boot_stack_len_IRQ:
|
||||
.word _IRQ_STACK_SIZE_
|
||||
|
||||
boot_stack_base_SVC:
|
||||
.word svc_stack_start
|
||||
|
||||
boot_stack_len_SVC:
|
||||
.word _SVC_STACK_SIZE_
|
||||
|
||||
boot_stack_base_FIQ:
|
||||
.word fiq_stack_start
|
||||
|
||||
boot_stack_len_FIQ:
|
||||
.word _FIQ_STACK_SIZE_
|
||||
|
||||
boot_stack_base_SYS:
|
||||
.word sys_stack_start
|
||||
|
||||
boot_stack_len_SYS:
|
||||
.word _SYS_STACK_SIZE_
|
||||
|
||||
/*FUNCTION: _sysboot_copy_data_to_ram*/
|
||||
/*DESCRIPTION: copy main stack code from FLASH/ROM to SRAM*/
|
||||
_sysboot_copy_data_to_ram:
|
||||
LDR R0, =_data_flash_begin
|
||||
LDR R1, =_data_ram_begin
|
||||
LDR R2, =_data_ram_end
|
||||
|
||||
4: CMP R1, R2
|
||||
LDRLO R4, [R0], #4
|
||||
STRLO R4, [R1], #4
|
||||
BLO 4b
|
||||
BX LR
|
||||
|
||||
/*FUNCTION: _sysboot_zi_init*/
|
||||
/*DESCRIPTION: Initialise Zero-Init Data Segment*/
|
||||
_sysboot_zi_init:
|
||||
LDR R0, =_bss_start
|
||||
LDR R1, =_bss_end
|
||||
|
||||
MOV R3, R1
|
||||
MOV R4, R0
|
||||
MOV R2, #0
|
||||
5: CMP R4, R3
|
||||
STRLO R2, [R4], #4
|
||||
BLO 5b
|
||||
BX LR
|
||||
|
||||
#if (CFG_SOC_NAME == SOC_BK7231N)
|
||||
/*FUNCTION: _sysboot_copy_code_to_itcm*/
|
||||
/*DESCRIPTION: copy itcm code from FLASH/ROM to SRAM*/
|
||||
_sysboot_copy_code_to_itcm:
|
||||
LDR R0, =_itcmcode_flash_begin
|
||||
LDR R1, =_itcmcode_ram_begin
|
||||
LDR R2, =_itcmcode_ram_end
|
||||
|
||||
6: CMP R1, R2
|
||||
LDRLO R4, [R0], #4
|
||||
STRLO R4, [R1], #4
|
||||
BLO 6b
|
||||
BX LR
|
||||
|
||||
/*FUNCTION: _sysboot_sdbss_init*/
|
||||
/*DESCRIPTION: Initialise Zero-Init Data Segment of TCM */
|
||||
_sysboot_tcmbss_init:
|
||||
LDR R0, =_tcmbss_start
|
||||
LDR R1, =_tcmbss_end
|
||||
|
||||
MOV R3, R1
|
||||
MOV R4, R0
|
||||
MOV R2, #0
|
||||
8: CMP R4, R3
|
||||
STRLO R2, [R4], #4
|
||||
BLO 8b
|
||||
BX LR
|
||||
#endif
|
||||
|
||||
.align 5
|
||||
boot_undefined:
|
||||
B boot_undefined
|
||||
|
||||
.align 5
|
||||
boot_swi:
|
||||
B vPortYieldProcessor
|
||||
|
||||
.align 5
|
||||
boot_pabort:
|
||||
B boot_pabort
|
||||
|
||||
.align 5
|
||||
boot_dabort:
|
||||
B boot_dabort
|
||||
|
||||
.align 5
|
||||
boot_reserved:
|
||||
B boot_reserved
|
||||
|
||||
.align 5
|
||||
irq_handler:
|
||||
portSAVE_CONTEXT
|
||||
LDR R0, =intc_irq
|
||||
MOV LR, PC
|
||||
BX R0
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
.align 5
|
||||
fiq_handler:
|
||||
portSAVE_CONTEXT
|
||||
LDR R0, =intc_fiq
|
||||
MOV LR, PC
|
||||
BX R0
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
/*Starting the first task is just a matter of restoring the context that*/
|
||||
/*was created by pxPortInitialiseStack().*/
|
||||
vPortStartFirstTask:
|
||||
firstRESTORE_CONTEXT
|
||||
|
||||
/*Manual context switch function. This is the SWI hander.*/
|
||||
vPortYieldProcessor:
|
||||
#if (0 == CFG_SUPPORT_BOOTLOADER)
|
||||
ADD LR, LR, #4 //Add 4 to the LR to make the LR appear exactly
|
||||
//as if the context was saved during and IRQ
|
||||
//handler.
|
||||
#endif // CFG_SUPPORT_BOOTLOADER
|
||||
|
||||
portSAVE_CONTEXT //Save the context of the current task...
|
||||
|
||||
LDR R0, =vTaskSwitchContext
|
||||
MOV LR, PC
|
||||
BX R0
|
||||
|
||||
portRESTORE_CONTEXT //Restore the context of the selected task.
|
||||
|
||||
.code 32
|
||||
.global WFI
|
||||
.type WFI,%function
|
||||
WFI:
|
||||
MOV R0, #0
|
||||
MCR p15, 0, R0, c7, c0, 4
|
||||
BX LR
|
||||
/*EOF*/
|
||||
420
platform/beken-72xx/fixups/intc.c
Normal file
420
platform/beken-72xx/fixups/intc.c
Normal file
@@ -0,0 +1,420 @@
|
||||
/**
|
||||
****************************************************************************************
|
||||
*
|
||||
* @file intc.c
|
||||
*
|
||||
* @brief Definition of the Interrupt Controller (INTCTRL) API.
|
||||
*
|
||||
* Copyright (C) RivieraWaves 2011-2016
|
||||
*
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
* INCLUDE FILES
|
||||
****************************************************************************************
|
||||
*/
|
||||
#include "compiler.h"
|
||||
#include "intc.h"
|
||||
#include "intc_pub.h"
|
||||
|
||||
#include "include.h"
|
||||
#include "arm_arch.h"
|
||||
#include "drv_model_pub.h"
|
||||
#include "icu_pub.h"
|
||||
#include "mem_pub.h"
|
||||
#include "uart_pub.h"
|
||||
#include "power_save_pub.h"
|
||||
#include "start_type_pub.h"
|
||||
|
||||
ISR_T _isrs[INTC_MAX_COUNT] = {{{0, 0}},};
|
||||
static UINT32 isrs_mask = 0;
|
||||
static ISR_LIST_T isr_hdr = {{&isr_hdr.isr, &isr_hdr.isr},};
|
||||
|
||||
void intc_hdl_entry(UINT32 int_status)
|
||||
{
|
||||
UINT32 i;
|
||||
ISR_T *f;
|
||||
UINT32 status;
|
||||
LIST_HEADER_T *n;
|
||||
LIST_HEADER_T *pos;
|
||||
|
||||
status = int_status & isrs_mask;
|
||||
INTC_PRT("intc:%x:%x\r\n", int_status, status);
|
||||
|
||||
#if CFG_USE_STA_PS
|
||||
power_save_dtim_wake(status);
|
||||
#endif
|
||||
|
||||
list_for_each_safe(pos, n, &isr_hdr.isr)
|
||||
{
|
||||
f = list_entry(pos, ISR_T, list);
|
||||
i = f->int_num;
|
||||
|
||||
if ((BIT(i) & status))
|
||||
{
|
||||
f->isr_func();
|
||||
status &= ~(BIT(i));
|
||||
}
|
||||
|
||||
if(0 == status)
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void intc_service_register(UINT8 int_num, UINT8 int_pri, FUNCPTR isr)
|
||||
{
|
||||
LIST_HEADER_T *pos, *n;
|
||||
ISR_T *tmp_ptr, *cur_ptr;
|
||||
ISR_T buf_ele;
|
||||
|
||||
GLOBAL_INT_DECLARATION();
|
||||
|
||||
buf_ele = _isrs[int_num];
|
||||
cur_ptr = &_isrs[int_num];
|
||||
cur_ptr->isr_func = isr;
|
||||
cur_ptr->int_num = int_num;
|
||||
cur_ptr->pri = int_pri;
|
||||
|
||||
INTC_PRT("reg_isr:%d:%d:%p\r\n", int_num, int_pri, isr);
|
||||
|
||||
GLOBAL_INT_DISABLE();
|
||||
if (list_empty(&isr_hdr.isr))
|
||||
{
|
||||
list_add_head(&cur_ptr->list, &isr_hdr.isr);
|
||||
goto ok;
|
||||
}
|
||||
|
||||
/* Insert the ISR to the function list, this list is sorted by priority number */
|
||||
list_for_each_safe(pos, n, &isr_hdr.isr)
|
||||
{
|
||||
tmp_ptr = list_entry(pos, ISR_T, list);
|
||||
|
||||
if (int_pri < tmp_ptr->pri)
|
||||
{
|
||||
/* add entry at the head of the queue */
|
||||
list_add_tail(&cur_ptr->list, &tmp_ptr->list);
|
||||
|
||||
INTC_PRT("reg_isr_o1\r\n");
|
||||
|
||||
goto ok;
|
||||
}
|
||||
else if (int_pri == tmp_ptr->pri)
|
||||
{
|
||||
INTC_PRT("reg_isr_error\r\n");
|
||||
goto error;
|
||||
}
|
||||
}
|
||||
|
||||
list_add_tail(&cur_ptr->list, &isr_hdr.isr);
|
||||
INTC_PRT("reg_isr_o2\r\n");
|
||||
|
||||
ok:
|
||||
isrs_mask |= BIT(int_num);
|
||||
GLOBAL_INT_RESTORE();
|
||||
|
||||
return;
|
||||
|
||||
error:
|
||||
/* something wrong */
|
||||
_isrs[int_num] = buf_ele;
|
||||
GLOBAL_INT_RESTORE();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void intc_service_change_handler(UINT8 int_num, FUNCPTR isr)
|
||||
{
|
||||
LIST_HEADER_T *pos, *n;
|
||||
ISR_T *tmp_ptr, *cur_ptr;
|
||||
ISR_T buf_ele;
|
||||
UINT8 int_pri;
|
||||
|
||||
GLOBAL_INT_DECLARATION();
|
||||
|
||||
buf_ele = _isrs[int_num];
|
||||
cur_ptr = &_isrs[int_num];
|
||||
int_pri = cur_ptr->pri;
|
||||
|
||||
if(!cur_ptr->isr_func)
|
||||
return;
|
||||
|
||||
INTC_PRT("reg_isr:%d:%d:%p\r\n", int_num, int_pri, isr);
|
||||
|
||||
GLOBAL_INT_DISABLE();
|
||||
if (list_empty(&isr_hdr.isr))
|
||||
{
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* Insert the ISR to the function list, this list is sorted by priority number */
|
||||
list_for_each_safe(pos, n, &isr_hdr.isr)
|
||||
{
|
||||
tmp_ptr = list_entry(pos, ISR_T, list);
|
||||
|
||||
if (int_pri == tmp_ptr->pri)
|
||||
{
|
||||
buf_ele.isr_func = isr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
exit:
|
||||
/* something wrong */
|
||||
_isrs[int_num] = buf_ele;
|
||||
GLOBAL_INT_RESTORE();
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* FUNCTION DEFINITIONS
|
||||
****************************************************************************************
|
||||
*/
|
||||
void intc_spurious(void)
|
||||
{
|
||||
ASSERT(0);
|
||||
}
|
||||
|
||||
void intc_enable(int index)
|
||||
{
|
||||
UINT32 param;
|
||||
|
||||
param = (1UL << index);
|
||||
sddev_control(ICU_DEV_NAME, CMD_ICU_INT_ENABLE, ¶m);
|
||||
}
|
||||
|
||||
void intc_disable(int index)
|
||||
{
|
||||
UINT32 param;
|
||||
|
||||
param = (1UL << index);
|
||||
sddev_control(ICU_DEV_NAME, CMD_ICU_INT_DISABLE, ¶m);
|
||||
}
|
||||
|
||||
void rf_ps_wakeup_isr_idle_int_cb(void)
|
||||
{
|
||||
#if ( CONFIG_APP_MP3PLAYER == 1 )
|
||||
UINT32 irq_status;
|
||||
|
||||
irq_status = sddev_control(ICU_DEV_NAME, CMD_GET_INTR_STATUS, 0);
|
||||
|
||||
if(irq_status & 1<<IRQ_I2S_PCM)
|
||||
{
|
||||
irq_status &= 1<<IRQ_I2S_PCM;
|
||||
i2s_isr();
|
||||
sddev_control(ICU_DEV_NAME, CMD_CLR_INTR_STATUS, &irq_status);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void intc_irq(void)
|
||||
{
|
||||
UINT32 irq_status;
|
||||
|
||||
irq_status = icu_ctrl(CMD_GET_INTR_STATUS, 0);
|
||||
irq_status = irq_status & 0xFFFF;
|
||||
if(0 == irq_status)
|
||||
{
|
||||
#if (! CFG_USE_STA_PS)
|
||||
os_printf("irq:dead\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
icu_ctrl(CMD_CLR_INTR_STATUS, &irq_status);
|
||||
|
||||
intc_hdl_entry(irq_status);
|
||||
}
|
||||
|
||||
void intc_fiq(void)
|
||||
{
|
||||
UINT32 fiq_status;
|
||||
|
||||
fiq_status = icu_ctrl(CMD_GET_INTR_STATUS, 0);
|
||||
fiq_status = fiq_status & 0xFFFF0000;
|
||||
icu_ctrl(CMD_CLR_INTR_STATUS, &fiq_status);
|
||||
|
||||
intc_hdl_entry(fiq_status);
|
||||
}
|
||||
|
||||
#if (CFG_SUPPORT_ALIOS)
|
||||
void deafult_swi(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
void intc_init(void)
|
||||
{
|
||||
UINT32 param;
|
||||
|
||||
#if !CFG_SUPPORT_BOOTLOADER
|
||||
*((volatile uint32_t *)0x400000) = (uint32_t)&do_irq;
|
||||
*((volatile uint32_t *)0x400004) = (uint32_t)&do_fiq;
|
||||
*((volatile uint32_t *)0x400008) = (uint32_t)&do_swi;
|
||||
*((volatile uint32_t *)0x40000c) = (uint32_t)&do_undefined;
|
||||
*((volatile uint32_t *)0x400010) = (uint32_t)&do_pabort;
|
||||
*((volatile uint32_t *)0x400014) = (uint32_t)&do_dabort;
|
||||
*((volatile uint32_t *)0x400018) = (uint32_t)&do_reserved;
|
||||
#endif
|
||||
intc_enable(FIQ_MAC_GENERAL);
|
||||
intc_enable(FIQ_MAC_PROT_TRIGGER);
|
||||
|
||||
intc_enable(FIQ_MAC_TX_TRIGGER);
|
||||
intc_enable(FIQ_MAC_RX_TRIGGER);
|
||||
|
||||
intc_enable(FIQ_MAC_TX_RX_MISC);
|
||||
intc_enable(FIQ_MAC_TX_RX_TIMER);
|
||||
|
||||
intc_enable(FIQ_MODEM);
|
||||
|
||||
param = GINTR_FIQ_BIT | GINTR_IRQ_BIT;
|
||||
sddev_control(ICU_DEV_NAME, CMD_ICU_GLOBAL_INT_ENABLE, ¶m);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void intc_deinit(void)
|
||||
{
|
||||
UINT32 param;
|
||||
|
||||
for( int i = 0; i<=FIQ_DPLL_UNLOCK; i++)
|
||||
{
|
||||
intc_disable(i);
|
||||
}
|
||||
|
||||
param = GINTR_FIQ_BIT | GINTR_IRQ_BIT;
|
||||
sddev_control(ICU_DEV_NAME, CMD_ICU_GLOBAL_INT_DISABLE, ¶m);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
void bk_cpu_shutdown(void)
|
||||
{
|
||||
GLOBAL_INT_DECLARATION();
|
||||
|
||||
os_printf("shutdown...\n");
|
||||
|
||||
GLOBAL_INT_DISABLE();
|
||||
while(1);
|
||||
GLOBAL_INT_RESTORE();
|
||||
}
|
||||
|
||||
void bk_show_register (struct arm_registers *regs)
|
||||
{
|
||||
os_printf("Current regs:\n");
|
||||
os_printf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
|
||||
regs->r0, regs->r1, regs->r2, regs->r3);
|
||||
os_printf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n",
|
||||
regs->r4, regs->r5, regs->r6, regs->r7);
|
||||
os_printf("r08:0x%08x r09:0x%08x r10:0x%08x\n",
|
||||
regs->r8, regs->r9, regs->r10);
|
||||
os_printf("fp :0x%08x ip :0x%08x\n",
|
||||
regs->fp, regs->ip);
|
||||
os_printf("sp :0x%08x lr :0x%08x pc :0x%08x\n",
|
||||
regs->sp, regs->lr, regs->pc);
|
||||
os_printf("SPSR:0x%08x\n", regs->spsr);
|
||||
os_printf("CPSR:0x%08x\n", regs->cpsr);
|
||||
|
||||
int i;
|
||||
const unsigned int *reg1;
|
||||
|
||||
os_printf("\nseparate regs:\n");
|
||||
|
||||
reg1 = (const unsigned int *)0x400024;
|
||||
os_printf("SYS:cpsr r8-r14\n");
|
||||
for(i=0;i<0x20>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("IRQ:cpsr spsr r8-r14\n");
|
||||
reg1 = (const unsigned int *)0x400044;
|
||||
for(i=0;i<0x24>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("FIR:cpsr spsr r8-r14\n");
|
||||
reg1 = (const unsigned int *)0x400068;
|
||||
for(i=0;i<0x24>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("ABT:cpsr spsr r8-r14\n");
|
||||
reg1 = (const unsigned int *)0x40008c;
|
||||
for(i=0;i<0x24>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("UND:cpsr spsr r8-r14\n");
|
||||
reg1 = (const unsigned int *)0x4000b0;
|
||||
for(i=0;i<0x24>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("SVC:cpsr spsr r8-r14\n");
|
||||
reg1 = (const unsigned int *)0x4000d4;
|
||||
for(i=0;i<0x24>>2;i++)
|
||||
{
|
||||
os_printf("0x%08x\n",*(reg1 + i));
|
||||
}
|
||||
|
||||
os_printf("\r\n");
|
||||
|
||||
}
|
||||
|
||||
void bk_trap_udef(struct arm_registers *regs)
|
||||
{
|
||||
#if (CFG_SOC_NAME == SOC_BK7231N)
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_UNDEFINED_VALUE & 0xffff);
|
||||
#else
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_UNDEFINED_VALUE;
|
||||
#endif
|
||||
os_printf("undefined instruction\n");
|
||||
bk_show_register(regs);
|
||||
bk_cpu_shutdown();
|
||||
}
|
||||
|
||||
void bk_trap_pabt(struct arm_registers *regs)
|
||||
{
|
||||
#if (CFG_SOC_NAME == SOC_BK7231N)
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_PREFETCH_ABORT_VALUE & 0xffff);
|
||||
#else
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_PREFETCH_ABORT_VALUE;
|
||||
#endif
|
||||
os_printf("prefetch abort\n");
|
||||
bk_show_register(regs);
|
||||
bk_cpu_shutdown();
|
||||
}
|
||||
|
||||
void bk_trap_dabt(struct arm_registers *regs)
|
||||
{
|
||||
#if (CFG_SOC_NAME == SOC_BK7231N)
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_DATA_ABORT_VALUE & 0xffff);
|
||||
#else
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_DATA_ABORT_VALUE;
|
||||
#endif
|
||||
os_printf("data abort\n");
|
||||
bk_show_register(regs);
|
||||
bk_cpu_shutdown();
|
||||
}
|
||||
|
||||
void bk_trap_resv(struct arm_registers *regs)
|
||||
{
|
||||
#if (CFG_SOC_NAME == SOC_BK7231N)
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)(CRASH_UNUSED_VALUE & 0xffff);
|
||||
#else
|
||||
*((volatile uint32_t *)START_TYPE_ADDR) = (uint32_t)CRASH_UNUSED_VALUE;
|
||||
#endif
|
||||
os_printf("not used\n");
|
||||
bk_show_register(regs);
|
||||
bk_cpu_shutdown();
|
||||
}
|
||||
|
||||
/// @}
|
||||
Reference in New Issue
Block a user