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remove some oboslete code
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@@ -213,10 +213,6 @@ void nv3_mmio_write32(uint32_t addr, uint32_t val, void* priv)
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}
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nv3_mmio_arbitrate_write(addr, val);
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// This may get around the riva shredding its own cache
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//nv3_pfifo_cache0_pull();
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//nv3_pfifo_cache1_pull();
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}
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// PCI stuff
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@@ -103,9 +103,6 @@ uint32_t nv3_mmio_arbitrate_read(uint32_t address)
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ret = nv3_vram_read(address);
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else if (address >= NV3_USER_START && address <= NV3_USER_END)
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ret = nv3_user_read(address);
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// RAMIN is handled by a separate memory mapping in PCI BAR1
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//else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END)
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//ret = nv3_ramin_arbitrate_read(address); // RAMHT, RAMFC, RAMRO etc dettermined by nv3_ramin_* function
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else
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{
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nv_log("MMIO read arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x [returning 0x00]\n", address);
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@@ -167,8 +164,7 @@ void nv3_mmio_arbitrate_write(uint32_t address, uint32_t value)
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nv3_vram_write(address, value);
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else if (address >= NV3_USER_START && address <= NV3_USER_END)
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nv3_user_write(address, value);
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else if (address >= NV3_RAMIN_START && address <= NV3_RAMIN_END)
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nv3_ramin_arbitrate_write(address, value); // RAMHT, RAMFC, RAMRO etc is determined by the nv3_ramin_* functions
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//RAMIN is its own thing
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else
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{
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nv_log("MMIO write arbitration failed, INVALID address NOT mapped to any GPU subsystem 0x%08x\n", address);
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